Amruta Patilpatilamruta375@gmail.com, +91-9620

2827 60Bangalore-560102, Karnataka

Career Objective

To be a globally skilled engineer and to present my finest to the company I serve.

Core Competency

Knowledge of ASIC flowKnowledge of Physical design (PD), Floor planning, placement, routing, APR, (P&R), DRC Knowledge of DFT Static Timing Analysis (STA), Timing closure, OCV, Logical drc fixing.Tools used: Synopsys ICC, Primetime (PT), Questasim, scripting language: tcl,perlHDL language: VerilogAutoCAD Electrical (AutoCAD 2012)

Education Details

Education Institute Board Percentage

Year

Adv. Diploma in ASIC Design

RV-VLSI Design Centre, Bengaluru

Appearing 2017

BE (Electrical Engineering)

Sharad Institute of Technology, Ichalkaranji.

Shivaji University, Kolhapur, Maharastra

61% 2014

PUC/12th DKASC, Ichalkaranji Maharastra Board HSC, Pune.

59% 2010

SSLC/10th The New High school, Ichakar11anji

Maharastra Board SSC, Pune.

68% 2008

Domain Specific ProjectI. RV-VLSI Design Center, BangalorePhysical Design Trainee Engineer Oct-2016 to Oct-2016Static Timing analysis using Synopsys PrimetimeDescription

Generating timing constraints and reporting analyzing all timing path groups in Synopsys Primetime tool and listing solutions to fix existing violations for given block having multiple clocks.

ToolsSynopsys Primetime

Challenges

Analyzing timing for Latch to DFF and DFF to Latch timingConstraining and analyzing multicycle paths from fast to slow and slow to fast clocks. Analyzing design based on CRPR and OCV.

II. RV-VLSI Design Center, BangalorePhysical Design Trainee Engineer Nov-2016 to Jan-2017Block level physical design of Torpedo subsystemDescription

Worked on block level Torpedo physical design implementation having 32 macros and 43K instances. Performing physical design related task for 180nm technology involves design setup, floorplaning, power routing, std cell placement, cts, routing, DRC fixing etc.

Tools

Synopsys IC Compiler

Challenges

In floor plan there was space from core ring to macro, where standard cells were placed and resulted into floating pins.Maintaining IR drop to 5% of supply voltage by increasing or decreasing the number of metal streams.Found global route congestion during placement and was resolved by rearranging macros.

After CTS many violations were fixed by setting proper timing constraints. DRC fixing, Antenna violation.

B.E / B.Tech Academic ProjectSharad Institute of Technology Collage of Engg. IchalkaranjiInvestigation of performance of induction motor by using advanced package-LABVIEW Description

Formulations are proposed to calculate different parameters of induction motor. These are used to guide the LABVIEW modeling. By using interface, performance of the motor under different loading conditions can be validated before it is sold out.

ToolsLABVIEW/ Microcontroller kit, Single phase induction motor

ChallengesEstimation of real time torque, output power, slip frequency using LABVIEW.

Achievements Won 1st prize in a national level project competition, held in Dange College, Ashta (Maharashtra) on

29th March 2014; the event was sponsored by IDBI Bank Won 2nd prize in a national level project competition organized by Bharat Forge and Rajarambapu

Institute of Technology (RIT), Islampur (Maharashtra) on 28th and 29th March 2014

Personal Details

Full Name : Amruta Raju PatilDate of Birth : 1ST March 1993

Marital Status : MarriedLanguages Known : English, Hindi and MarathiContact Nos. : +91-9620282760

Address : HSR Layout, Bangalore. Hobbies : Listening music, swimming