Year 4

No . 4

March 2015

State Key Lab of Analog and Mixed-Signal VLSI (SKL AMS-VLSI)

Newsletter

Motto: “Locally, from (World) Quality towards (National) Quantity”

座右銘:立足本土、人才培養, 以世界級質量創建國家級規模

2014 Milestones

Events

SKL AMS-VLSI awarded "Excellence in INNOVATION" by Business Awards of Macau on Nov-2014

At Macao Science and Technology Awards presented this year, SKL AMS-VLSI won two 2nd and one 3rd prizes in

the Technological Invention Award category. Also, Tech-nology Development Award was granted to 3 PhD stu-

dents and 1 Master Student from SKL AMS-VLSI

President Xi Jinping visited UM, and listened to the report of SKL (AMSV-VLSI) research achievements. President Xi mentioned that was happy to see the self-developed state-of-the-art leading chips and encouraged our team to con-

tribute further to China high-level strategy policy of "Leading by Innovation" - as quoted by online Chinese Media.

Co-Funded by Macao Science and Technology Development Fund (FDCT)

State-of-the-Art Chips - Designed and Tested in 2014 (9 chips)

High efficient 5GHz ADC (65nm)

ISSCC 2015

Four PhD students and one assistant professor from the University of Macau (UM) State Key Laboratory of Analog and Mixed-Signal VLSI (AMS-VLSI Lab) and Faculty of Science and Technology attended the Institute of Electrical and Electronics Engineer’s (IEEE) 62nd International Solid-State Circuits Conference (ISSCC) in February 2015, which is considered the ‘Chip Olympics’, the most competitive conference in the field of chip design.

The 6 papers from UM were "A 5.5mW 6b 5GS/s 4-times Interleaved 3b/cycle SAR ADC in 65nm CMOS", "A Multi-Step Multi-Sample µNMR Relaxometer Using Inside-Magnet Digital Microfluidics and a Butterfly-Coil-Input CMOS Transceiver", "A 12b 180MS/s 0.068mm2 Full-Calibration-Integrated Pipelined-SAR ADC", "A 123-Phase DC-DC Converter-Ring with Fast-DVS for Microprocessors", "A 0.028mm2 11mW Single-Mixing Blocker-Tolerant Receiver

with Double-RF N-Path Filtering, S11 Centering, +13dBm OB-IIP3 and 1.5-to-2.9dB NF", and "A 2-/3-Phase Fully-Integrated Switched-Capacitor DC-DC Converter in Bulk-CMOS for Energy-Efficient Digital Circuits With 14% Effi-ciency Improvement". There included 2 Pre-Doctoral Achievement Awards and 2 Student Research Previews.

A 123-Phase DC-DC Converter-Ring with Fast-DVS for Microprocessors (65nm)

A VCO-based Switched-Capacitor DC-DC Converter with Segment Frequency Modulation Control for Fast Recovery (65nm)

UM’s 1st book in

Power Electronics

US Patents granted in 2014 1. C. Shi, M. K. Law and A. Bermak, “Method and Apparatus for Energy Harvesting using CMOS Sensor”, US

Patent, US8629386 B2, Jan. 14, 2014.

2. Chi-Hang Chan, Yan Zhu, U-Fat Chio, Sai-Weng Sin, Seng-Pan U and Martins, R.P., "Comparator and Calibration Thereof", US Patent, US8829942 B2, Sept. 9, 2014.

UM PhD graduates to join the world’s No 1 mobile chip maker and Asia’s largest

fabless IC design company

Four PhD graduates from SKL AMS-VLSI recently passed their oral defenses, with external exa-miners unanimously praising their works for

reaching world-class standards. The 4 new doc-tors are Un Ka-Fai, Yan Zushu, Lin Zhicheng, and Lin Fujian. Two of them have received job contracts from Qualcomm in the United States, which is the world’s No 1 mobile chip maker. One has joined Mediatek in Singapore, which is Asia’s largest fabless IC design company and ranks No 4 in the world. The last has decided to stay at UM as a post-doctoral researcher.

Supply Modulated Micro-stimulator with Energy Recycling (180nm)

µNMR Transceiver for Chemical/Biological Diagnosis and Ultra-low Power Wavelet Shrinkage ECG Processor (180nm)

Single Chip Solar Energy Harvesting IC (180nm)

Optogenetic Frontend IC and Nested-Current-Mirror Amplifier (180nm)

Ultra-high Area Efficient and Low-Power Wireless Receiver (65nm)

Ch.1 Ch.2

CLK Gen.

1st-stage

2nd-stage

430μm

340μm

Output Buffers

900MS/s 11b ADC (65nm)

Wireless Chips

Integrated Power Chips DCSP Chips

BME (Biomedical Engineering) Chips

Motivation

Verification

Architecture

System Implementation

An 11b 900 MS/s Time-Interleaved Sub-ranging Pipelined-SAR ADC [Best Paper Award]

Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui P. Martins

The highly Time-Interleaved(TI) SAR ADC with timing-calibration obtains the best power effi-ciency for the GHz speed goal, which removes the power and accuracy trade-off in the clock generator. However, the calibration sensitivity is limited by the type of input signal or the other non-idealities among sub-SAR ADCs such as reference noise, offset and gain mismatches. The skew calibration achieves better than 63dB SFDR in a TI-SAR ADC with GHz sampling rate and 10b resolution, while the calibration power from offset, gain and timing occupies near 50% total ADC power. This paper presents an 11b TI-sub-ranging pipelined-SAR ADC that achieves a maximum 1.1GS/s sampling rate with com-petitive power-efficiency as compared with the timing-calibrated TI-SAR ADCs. We propose the optimization Based on ADC’s sampling front-end for better SFDR by using the proposed channel-selection-embedded bootstrap rather than timing-calibration.

In ESSCIRC 2014 Selected works from each research line

From Data Conversion and Signal Processing research line

System Implementation

0 0.1 0.2 0.3 0.4 0.5

-100

0

Normalized Frequency (fin / fs)(decimate by 25)

Po

wer

(d

B)

HD2HD3

Gain Mismatches

0 0.1 0.2 0.3 0.4 0.5

SNR = 51.7 dB, SNDR = 51.5 dB,

SFDR = 65.9 dB, THD = -64.3 dB

-100

0

Po

wer

(d

B)

HD2

fs=900MS/s, fin=11MHz

fs=900MS/s, fin=431MHz

HD5 HD8HD4

offset Mismatches

HD3 HD8

offset MismatchesSkew/Gain Mismatches

Normalized Frequency (fin / fs)(decimate by 25)

SN

DR

& S

FD

R (

dB

)

Input frequency (MHz) @fs=900MS/s

10 100 200 300 400 50050

52

54

56

58

60

62

64

66

68

70

SNDR

SNRSFDR

CLK Jitter 650fs

Verification

Technology (nm)

Resolution (bit)

Sampling Rate (MS/s)

Supply Voltage (V)

SNDR @DC (dB)

FoM @DC (fJ/conv.step)

Power (mW)

Architecture

65

10

0.8

51

0.18

19

N/A

Pipeline

[8]

VLSI’13

TI-SAR

65

10

1

53.5

0.1/0.1

19.8

0.78

[2]

ISSCC’14

1 1.2

Area (mm2)

65

11

0.9

57.6

28

15.5

0.66/1.5

TI-Pipelined-SAR

1.2/1.2

This Work

SNDR @Nyq. (dB)

Input Swing (Vp-p)

DNL/INL (LSB)

FoM @Nyq. (fJ/conv.step)

N/A 1.8 1.2

4851.2 51.5

0.15

51 53

5662 71

Calibration (on-chip) Offset No Offset

11

1.1

56.2

32

18

0.69/1.6

1.2/1.3

1.2

50.7

58

TI-SAR

40

10

1.62

51

N/A

71

0.83

[1]

ISSCC’14

1.1

1

48

150

210

Offset, gain,

time

SFDR @Nyq. (dB) 62 60 N/A 65.9 64

TI-SAR

65

10

2.8

53.5

0.7/1.8

44.6

1.7

[3]

JSSCC’13

1

N/A

51.2

56

78

Offset, time

55

Require Timing Correction Yes Yes Yes No No

Vdd

Vin

Channel Selection Embedded (CSE)

Bootstrap Circuit

Φ1(Φ2)

ΦP1(ΦP2)

M1

M2

M3

Bootstraped

switch

A1(A2)

VB1(B2)

Φs(Φs)

ΦM

M4Vdd

CSE

Bootstrap

6 Sub-S/H channels

Vin DAC

A1

CF

Φ1,1

CSE

Bootstrap

A2

DAC

DAC

DAC

DAC

DAC

CF

2 Main S/H

channels

Φ1,2

Φ1,3

Φ2,1

Φ2,2

Φ2,3

ΦM

Φ1

Φ2

Motivation

Verification

Architecture

System Implementation

Energy Optimized Sub-threshold VLSI Logic Family with Unbalanced

Pull-up/down Network and Inverse-Narrow-Width Techniques

Ming-Zhong Li, Chio-In Ieong, Man-Kay Law, Pui-In Mak, Mang-I Vai, Sio-Hang Pun and Rui P. Martins

Ultra-low-energy biomedical applications have urged the development of a sub-threshold VLSI logic family in standard CMOS. Instead of the traditionally preferred balanced pull-up (PU) and pull-down (PD) network approach in logic cell design, this work proposes an unbalanced pull-up/down network together with an inverse-narrow-width technique to improve the operating speed of the individual logic cell. Effective logical efforts save both power and die area in the pro-cess of device sizing and topology optimization. Three experimental 14-tap 8-bit finite impulse response (FIR) filters optimized for ultra-low-voltage operation were fabricated in 0.18-μm CMOS. Measurements show that the optimized 0.45-V and 0.6-V libraries achieve minimum en-ergy operations at 100 kHz, with a Figure-of-Merit (FoM) of 0.365 (at 0.31 V) and 0.4632 (at 0.39 V), respectively. They correspond to 35.96% and 18.74% improvements, and the overall performances are well comparable with the state-of-the-art.

In TVLSI 2015

0%

10%

20%

30%

103 104 105 106 107

10-16

10-19

10-18

10-17

Diff

eren

ce in

pow

er-d

elay

pro

duct

Frequency (Hz)

Pow

er-d

elay

pro

duct

(J)

40%10-15

with balancingw/o balancingdifference

Operating

frequency limit

(unbalanced)

PMOS Width (mm)0.2 0.4 0.6 0.8 1 1.2 1.4

0.8

1.6

2.4

3.2

4.0

Nor

mal

ized

Pow

er-d

elay

pro

duct WNMOS = 0.88 mm

WNMOS = 0.22 mmWNMOS = 0.44 mmWNMOS = 0.66 mm

Power-delay product of an inverter (FO4 loading) with balanced (P/N ratio = 5/1) and unbalanced (P/N ratio = 2/1) PU/PD network vs. operating frequen-cy at 0.3 V (left); Normalized power-delay product of a FO4 inverter at vari-

ous NMOS/PMOS widths at 0.3 V (right).

Transistor Length (mm)

NM

OS

VT (

V)

PM

OS

VT (

V)

-0.49

-0.41

0 0.5 1 1.5 2 2.5

Minimum

NMOS VT

Minimum

PMOS |VT|

0.42

0.5

0.42

Transistor Width (mm)

-0.5

-0.460.5

0.1 0.5 0.9 1.3 1.7 2.1 2.5

Minimum

NMOS VT

@ 220 nm

Minimum PMOS

|VT| interval @

400 – 590 nm

NM

OS

VT (

V)

PM

OS

VT (

V)

INW

NMOS/PMOS VT vs. transistor length (left); Transistor width (right) at VDD = 0.3 V.

0.45 V liberty

file (.lib)

based FIR

0.2 mm

0.265 mm0.3 V liberty

file (.lib)

based FIR

0.35 mm

0.33 mm

0.6 V liberty

file (.lib)

based FIR0.25

mm

0.196 mm

Die micrographs of the 0.18-µm sub-threshold FIR test chips using the 0.3V, 0.45V and 0.6V liberty file.

Power Supply Voltage (V)

No

rmal

ized

En

erg

y/C

ycle

0

0.2

0.6

1.0

0.25 0.35 0.45 0.55

0.32V

0.34V

0.44V

Circuit with 0.30-V .lib

Circuit with 0.60-V .libCircuit with 0.45-V .lib

Power Supply Voltage (V)

No

rmal

ized

En

erg

y/C

ycle

0

0.2

0.6

1.0

0.25 0.35 0.45 0.55

0.28V

0.31V

0.39V

Circuit with 0.30-V .lib

Circuit with 0.60-V .libCircuit with 0.45-V .lib

Die micrographs of the 0.18-µm sub-threshold FIR test chips using the 0.3V, 0.45V and 0.6V liberty file.

Die micrographs of the 0.18-µm sub-threshold FIR test chips using the 0.3V, 0.45V and 0.6V liberty file.

Nu

mb

er o

f C

hip

s

Energy/Cycle (pJ)

2

3

1

0

4

0 0.41 0.45 0.49 0.53 0.57 0.63

σ = 0.0543 pJ

μ = 0.4995 pJ

Nu

mb

er o

f C

hip

s

Energy/Cycle (pJ)

2

3

1

0

5

0 0.33 0.37 0.41 0.45 0.49 0.60

σ = 0.0678 pJ

μ = 0.3829 pJ4

0.53

From Biomedical IC research line

(Accepted in 2014)

Motivation

Result II

Architecture

Result I

Natural Discharge after Pulse and Cooperative Electrodes to

Enhance Droplet Velocity in Digital Microfluidics

Tianlan Chen, Cheng Dong, Jie Gao, Yanwei Jia, Pui-In Mak, Mang-I Vai, and Rui P. Martins

Digital Microfluidics (DMF) is a promising tech-nology for biological/chemical micro-reactions due to its distinct droplet manageability via elec-tronic automation, but the limited velocity of droplet transportation has hindered DMF from utilization in high throughput applications. In this paper, by adaptively fitting the actuation voltages to the dynamic motions of droplet movement under real-time feedback monitoring, two control-engaged electrode-driving tech-niques: Natural Discharge after Pulse (NDAP) and Cooperative Electrodes (CE) are proposed. They together lead to, for the first time, en-hanced droplet velocity with lower root mean square voltage value.

In American Institute of Physics – Advances 2014

Sketches of four possible electrode-driving schemes for droplet movements over two electrodes: (a) Natural Discharge after Pulse (NDAP): The high-voltage (HV) period lasts shorter, while the low-voltage (LV) under natural discharge lasts longer with short pulse recharging periodically. (b) DC signal. (c) NDAP with cooperative electrodes (CE) overlaps the charging time of neighboring electrodes. (d) DC plus CE driving. (e) Droplet moving toward two target electrodes and location of the two thresholds on the first target electrode. The electrode was grounded when the charging was done in all schemes.

(a) Velocity comparison of NDAP signals with different and DC. NDAP with 13-ms to 100-ms has average velocities higher than DC signal. (b) Video frames of a droplet actuated by NDAP and DC crossing 2 electrodes (Multimedia view). Video was captured by a high speed camera (Nikon V2), which has a maximum frame rate up to 1200 frames/second (resolution 320 x 120 pixels). A LED light was set in the same frame to light on when the electrode was being charged. Individual frames extracted from the videos were analyzed by the image processing software Image J to obtain the vdroplet.

Comparison between the proposed (NDAP + CE and high-speed feedback) and classical (DC) schemes for droplet movements in a long run of 3 s: (a) Droplet successfully moved across 12 electrodes when it was controlled by the proposed scheme. The path of the droplet’s center had been shortened at electrode No. 6 by CE, which charged electrode No. 7 before the droplet reached electrode No. 6, resulting in an upward move of droplet in advance. The whole droplet transportation was recorded in video (Multimedia view). (b) Droplet failed to complete movement in 3 s due to its lower speed. The moving path was close to the right angle at the two corners. The whole droplet transportation was recorded in video (Multimedia view). (c) Instanta-neous velocity of the droplet moving across the electrodes. As expected, droplet controlled by the proposed scheme moved across electrode No. 6-7-8 using a much shorter time than that of the classical procedure.

From Multidisciplinary Research Area

(a)

Vo

ltag

e

uα

Time

Vo

ltag

e

Time

uα

0tthc tths

0tthc tths

uα

uβ

0

HV period

tα

tβ

tths

tα’

uα

0tths

uβ’

uβ

uβ’

LV period (c)

(b) (d)1st

2nd

ths

thc

(e)

NDAP

NDAP + CE DC + CE

DC

2nd electrode1st electrode

Motivation

Result

Architecture I

Architecture II

NMR-DMF: A Modular Nuclear Magnetic Resonance–Digital

Microfluidics System for Biological Assays

Ka-Meng Lei, Pui-In Mak, Man-Kay Law, and Rui P. Martins

We present a modular nuclear magnetic reso-nance–digital microfluidics (NMR-DMF) system as a portable diagnostic platform for miniaturized biological assays. With increasing numbers of combination be-tween designed probes and a specific target, NMR becomes an accurate and rapid assay tool capable of detecting particular kinds of proteins, DNAs, bacteria and cells with a customized probe quantitatively. Traditional sample operation (e.g., manipulation and mixing) relied heavily on human efforts. We herein propose a modular NMR-DMF system to allow electronic automation of multi-step reac-tion-screening protocols.

In Royal Society of Chemistry - Analyst 2014

The overall schematics and operations of the NMR-DMF system. (a) The placement of the DMF chip, magnet, RF coil and PCB board in 3D view. Bene-fit from the plane-parallel magnetic field generated by the figure-8 shaped coil, the NMR system can be effectively integrated into the DMF system; (b) Sche-matics of the NMR Electronics. The transmitter which is formed by the digital logics such as flip flops is used to excite the hydrogen atom. On the receiver part, the capacitor together with the RF-coil (fabricated figure-8 shaped coil) forms a LC tank to provide passive gain enhancing of the system’s sensitivity. The signal is then amplified and down converted to fIF (intermediate frequency) and fed to the external filters and oscilloscope; (c) The filtered results from the PCB are captured by the oscilloscope for easier demonstration purpose. Waveforms are then analysed and the spin-spin relaxation time (T2) is fitted by the algorithm written in MATLAB; (d) The photograph of the DMF chip and structure of the DMF platform. The droplets are squeezed between the top and bottom planes and surrounded by silicone oil; (e) The detection mechanism of the NMR-DMF system. The target-specific magnetic nanoparticles, which act as probes, are placed on the sensing site initially (in purple). The samples at other electrodes (in cyan) will be transported to the sensing site and mixed with the probes to perform NMR assays automatically by applying voltage on corre-sponding electrodes. Without the target, the probes stay monodispersed and will have a longer T2. Otherwise, the target and probes will form clusters by forming bonds between each other and the T2 will be decreased.

(a) Plot of unit magnetic field in y-direction of the 14-turn figure-8 shaped coil along z-axis. The magnetic field is stronger on the coil surface (1.8 mT) and starts to decrease above the coil. Inset shows the photograph of the 14-turn figure-8 shaped coil; (b) The magnetic flux lines of the simulated 14-turn figure-8 shaped coil. The magnetic fluxes are still pointing in the z-direction at the centres of each coil. However, between the two coils, the magnetic flux is pointing in the y-direction, generating plane-parallel magnetic flux. (c) Plane-parallel magnetic flux density map of the 14-turn figure-8 shaped coil at z = 0.6 mm (depth of the ITO glass). The sensing region, which is defined as the area have a plane-parallel magnetic flux density larger than 50% its peak value (1.43 mT) is located between the centers of two coils and has a shape of circle with diameter around 4.2 mm.

(a) Illustration of droplets mixing. The droplets at electrode no. 1 (samples) and no. 8 (probe) were driven to electrode no.7 and mixed together. (b) The NMR assay results from the mixed droplets. Biotinylated magnetic nanopar-ticles acted as a probe. If the samples do not contain avidin, the nanoparti-cles will stay monodispersed and a longer T2 will be obtained (181.5 ms). If avidin is with the samples, avidin and biotin will combine to form rigid bond and clusters will be presented. In consequence, T2 will be decreased by the perturbation of the magnetic nanoparticle clusters (86.13 ms). This shows that the system is capable of detecting the existence of protein in the sam-ples in a fully-automated way.

From Multidisciplinary Research Area

Motivation

Verification

Architecture

System Implementation

A 0.5V 1.15mW 0.2mm2 Sub-GHz ZigBee Receiver Supporting

433/860/915/960MHz ISM Bands with Zero External Components [ISSCC 2014 Highlight]

Zhicheng Lin, Pui-In Mak and Rui P. Martins

The rapid proliferation of Internet of Things has urged the development of ultra-low-power (ULP) radios at the lowest possible cost, while being universal for worldwide markets. This work is a single-0.5V ULP receiver for sub-GHz ZigBee (IEEE 802.15.4c/d) products. With 1.15mW of power and 0.2mm2 of area, the receiver shows 8.1-dB NF and –20.5dBm IIP3 over the 433/860/915/960MHz ISM bands apt for China, Europe, North America and Ja-pan, respectively, with zero external compo-nent.

In ISSCC 2014 and JSSC 2014

From Wireless IC research line

Motivation

Verification

Architecture

System Implementation

Inspired by The Square of Vatican City, a fully-integrated step-down switched-capacitor DC-DC converter-ring with 100+ phases is designed with a fast-DVS (dynamic volt-age scaling) feature for the microprocessor in portable/wearable devices. Switched-capacitor power converters (SCPCs) are pre-ferred for full integration because the capacitor density has increased significantly in nm processes. Multiphase architecture for ripple reduction can be easily built into the SCPC with little power and area overheads. This symmetrical ring-shaped converter surrounds its load in the square and supplies the on-chip power grid, such that a good quality power supply can be easily accessed at any point of the chip edges. There are 30 phases on the top edge and 31 phases on each of the other 3 edges, making 123 phases in total. The phase number and unit cell dimensions of this architecture can easily be modified to fit the floor plan of the load. By using the proposed VDD-controlled oscillator (VDDCO) the frequency of which is controlled by varying its supply voltage, a hitherto unexplored feature of the multiphase DC-DC architecture is exposed: the control-loop unity gain frequency (UGF) could be designed to be higher than the switching frequency.

A 123-Phase DC-DC Converter-Ring with Fast-DVS for

Microprocessors

Yan Lu, Junmin Jiang, Wing-Hung Ki, C. Patrick Yue, Sai-Weng Sin, Seng-Pan U, and Rui P. Martins

In ISSCC 2015

For the conventional PFM topology that uses a centralized current-starved (CS) voltage-controlled oscillator (VCO) and distributed clock phases, the upper limit on phase number is due to the matching of phases and routings; and its domi-nant pole is usually set at the VCTL node. For the proposed topology, the error amplifier (EA) with NMOS source follower buffer stage drives the VDDCO which is distributed and localized to every phase that makes it free of matching and routing problems. Now, VDDC is a low-impedance node and the associated pole is located at high frequencies; and the output pole becomes the dominant pole and the bandwidth is extended.

From Integrated Power research line

(Accepted in 2014)

A/D Converter Circuit and Architecture Design for High-speed

Data Communication by

Prof. Boris MURMANN, Stanford University, USA

Biosensors - Playing at the Crossroads of Engineering and the Sciences

by

Dr. M. Jamal Deen FRSC, McMaster University, Canada

Distinguished Lectures on Microelectronics and Biomedical Engineering

Events and Visits

Visit by Mr. Ma Chi Ngai Frederico, President of FDCT

Dr. Jun Yin received the B.Sc. and the M.Sc. degrees in Microelectronics from Peking University, Beijing, China, in 2004 and 2007,

respectively, and the Ph.D. degree in Electronic and Computer Engineering (ECE) from Hong Kong University of Science and Technol-

ogy (HKUST), Hong Kong, China, in 2013.

Research Interests: CMOS RF and mm-Wave integrated circuits for wireless communication and wireless sensing systems.

Dr. Yan Lu received the B.Eng. and M.Sc. degrees in Microelectronic Engineering from South China University of Technology, Guang-

zhou, China, in 2006 and 2009, respectively; and the Ph.D. degree in Electronic and Computer Engineering from the Hong Kong Uni-

versity of Science and Technology, Hong Kong, China, in 2013. He was a Visiting Scholar at University of Twente, the Netherlands, in

2013 for four months.

Research interests: Wireless power transfer systems, fully-integrated DC-DC converters, low-dropout regulators and RF energy har-

vesting.

Two New Academics Joined SKL AMS-VLSI

IEEE Solid-State Circuits Society 2014 Distinguished Lecture Workshop -

Macau by Prof. Jan Van der Spiegel, University of Pennsylvania, Prof. Tzi

-Dar Chiueh, National Taiwan University, Prof. Howard Luong, HKUST

2-Day Workshop on Integrated Power and Energy in Semiconductor

by Prof. LEO LORENZ, IEEE Fellow, Member of German National Academy

of Sciences, President of European Center of Power Electronics (ECPE)

Visit by Prof. Bai Chun Li, President of Chinese

Academy of Sciences

SCI Journals – 20 Papers

▓ Hugo Horta, R. P. Martins, "The start-up, evolution and impact of a research group in a university developing its knowledge base", Tertiary Education and Management, Taylor & Francis, vol. 20, No.4, pp. 280-293, Dec. 2014

▓ Zhicheng Lin, Pui-In Mak, R. P. Martins, "A Sub-GHz Multi-ISM-Band ZigBee Receiver Using Function-Reuse and Gain-Boosted N-Path Techniques for IoT Applications", IEEE Journal of Solid-State Circuits, vol. 49, Issue 12, pp. 2990 - 3004, Dec. 2014

▓ Fujian Lin, Pui-In Mak, R. P. Martins, "An RF-to-BB-Current-Reuse Wideband Receiver with Parallel N-Path Active/Passive Mixers and a Single-MOS Pole-Zero LPF", IEEE Journal of Solid-State Circuits, vol. 49, Nov. 2014

▓ D. G. Chen, F. Tang, M. K. Law, X. Zhong and A. Bermak, "A 64-fJ/step 9-bit SAR ADC Array with Forward Error Correction and mixed-signal CDS for CMOS Image Sensors," IEEE Transactions on Circuits and Systems-I, vol. 61, issue 11, pp. 3085-3093, Nov. 2014

▓ Md.Tawfiq Amin, Pui-In Mak and R. P. Martins, "A 0.137-mm2 9-GHz Hybrid Class-B/C QVCO with Output Buffering in 65-nm CMOS," IEEE Microwave and Wireless Components Letters, vol. 24, pp. 716-718, Oct. 2014

▓ Zhicheng Lin, Pui-In Mak, R. P. Martins, "Analysis and Modeling of a Gain-Boosted N-Path Switched-Capacitor Bandpass Filter", IEEE Transactions on Circuits and Systems – I, vol. 9, pp. 2560-2568, Sept. 2014

▓ NingYi Dai, Chi-Seng Lam, WenChen Zhang, “Multifunctional voltage source inverter for renewable energy integration and power quality conditioning”, The Scientific World Journal, vol. 2014, Aug. 2014

▓ K. M. Lei, P. I. Mak, M. K. Law and R. P. Martins, “NMR-DMF: A Modular Nuclear Magnetic Resonance-Digital Microfluidics System for Biological Assays,” RSC Analyst, 2014, 139, 6204-6213, Aug. 2014

▓ Zhicheng Lin, Pui-In Mak, R. P. Martins, "A 0.14-mm2, 1.4-mW, 59.4 dB-SFDR, 2.4-GHz ZigBee/WPAN Receiver Exploiting a Split-LNTA + 50% LO Topology in 65-nm CMOS", IEEE Transactions on Microwave Theory and Techniques, vol. 62, pp. 1525-1534 , Jul. 2014

▓ Zhicheng Lin, Pui-In Mak, R. P. Martins, "A 2.4-GHz ZigBee Receiver Exploiting an RF-to-BB-Current-Reuse Blixer + Hybrid Filter Topology in 65-nm CMOS", IEEE Journal of Solid-State Circuits, vol. 49, pp. 1333-1344, Jun. 2014

▓ Pui-In Mak, Miao Liu, Yaohua Zhao, R. P. Martins, "Enhancing the Performances of Recycling Folded Cascode OpAmp in Nanoscale CMOS through Voltage Supply Doubling and Design for Reliability", Wiley International Journal of Circuit Theory and Appli-cations, vol. 42, pp. 605-619, Jun. 2014

▓ Yan Lu, Wing-Hung Ki, “A 13.56 MHz CMOS Active Rectifier with Switched-Offset and Compensated Biasing for Biomedical Wireless Power Transfer Systems”, IEEE Transactions on Biomedical Circuits and Systems, vol. 8, pp.334-344, Jun. 2014

▓ C. H. Chen, S. H. Pun, P. U. Mak, M. I. Vai, A. Klug, et al., "Circuit Models and Experimental Noise Measurements of Micropipette Amplifiers for Extracellular Neural Recordings from Live Animals," BioMed Research International, vol. 2014, p. 14, Jun. 2014

▓ Chi-Seng Lam, Man-Chung Wong, Wai-Hei Choi, Xiao-Xi Cui, Hong-Ming Mei, Jian-Zheng Liu, “Design and Performance of an adaptive low dc voltage controlled LC-hybrid active power filter with a neutral inductor in three-phase four-wire power systems”, IEEE Transactions on Industrial Electronics, vol. 61, no. 6, pp. 2635-2647, Jun. 2014

▓ D. G. Chen, F. Tang, M. K. Law and A. Bermak, “A 12 pJ/pixel Analog-to-Information Converter based 816 x 640 Pixel CMOS Image Sensor”, IEEE Journal of Solid-State Circuits, vol. 49, issue 5, pp. 1210-1222, May 2014

▓ Ning-Yi Dai, Man-Chung Wong, Keng-Weng Lao, Chi-Kong Wong, “Modelling and control of a railway power conditioner in co-phase traction power system under partial compensation”, IET Power Electronics, vol. 7, no. 5, pp. 1044 - 1054, May 2014

▓ Tianlan Chen, Cheng Dong, Jie Gao, Yanwei Jia, Pui-In Mak, Mang-I Vai and R. P. Martins, “Natural Discharge after Pulse and Coop-erative Electrodes to Enhance Droplet Velocity in Digital Microfluidics,” AIP Advances, Apr. 2014

▓ Fujian Lin, Pui-In Mak, R. P. Martins, "A Sine-LO Square-Law Harmonic-Rejection Mixer – Theory, Implementation and Application", IEEE Transactions on Microwave Theory and Techniques, vol. 62, pp. 313-322, Feb. 2014

▓ B. Wang, M. K. Law, A. Bermak and H. C. Luong, “A Passive RFID Tag Embedded Temperature Sensor With Improved Process Spreads Immunity for a -30oC to 60oC Sensing Range”, IEEE Transactions on Circuits and Systems I, pp. 337 – 346, Feb. 2014

▓ Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P. Martins, F. Maloberti, "Split-SAR ADCs: Improved Linearity With Power and Speed Optimization," IEEE Transactions on Very Large Scale Integration Systems, vol.22, no.2, pp.372,383, Feb. 2014

Conferences – 23 Papers Major solid-state circuits conferences

International Solid-State Circuits Conference (ISSCC) 2014, San Francisco, CA, USA, Feb. 2014 ▓ “A 0.0013mm2 3.6µW Nested-Current-Mirror Single-Stage Amplifier Driving 0.15-to-15nF Capacitive Loads with >62° Phase Margin”

[Pre-Doctoral Achievement Award] ▓ "An RF-to-BB current-reuse wideband receiver with parallel N-path active/passive mixers and a single-MOS pole-zero LPF" ▓ "A 0.5V 1.15mW 0.2mm2 Sub-GHz ZigBee receiver supporting 433/860/915/960MHz ISM bands with zero external components" ▓ "Circuit Techniques for Switched-Capacitor Filters" [Student Research Preview]

European Solid-State Circuits Conference (ESSCIRC) 2014, Venice, Italy, Sept. 2014 ▓ “An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC” [Best Paper Award]

Other conferences:

APPEEC 2014, Hong Kong, China, Dec. 2014 ▓ “An adaptive hysteresis band PWM control for hybrid active power filters in fixed frequency” ISIC 2014, Singapore, Dec. 2014 ▓ “A 0.3-V 37.5-nW 1.5~6.5-Input-Range Supply Voltage Tolerant Capacitive Sensor Readout”

BMEiCON 2014, Fukuoka, Japan, Nov. 2014 ▓ “Investigation on Error Performance for Galvanic-type Intra-body Communication with Experiment”

APCCAS 2014, Okinawa, Japan, Nov. 2014 ▓ “A Low-Dropout Regulator with Power Supply Rejection Improvement by Bandwidth-Zero Tracking” ▓ “Analysis of Two-Phase on-Chip Step-Down Switched Capacitor Power Converter” ▓ “Co-Design of a Low-Noise Receiver Front-End and its Exciting-Sensing Coil for Portable NMR-Screening of Chemical/Biological Droplets” ▓ “A 104μW EMI-Resisting Bandgap Voltage Reference Achieving –20dB PSRR, and 5% DC Shift under a 4dBm EMI Level”

Lab-on-a-Chip Asia 2014, Singapore, Nov. 2014 ▓ “Time-Regulated Actuation Signal for Enhancement of Droplet Transportation in Digital Microfluidics” ▓ “Electrical Actuation on Digital Microfluidics with a Ta2O5 Insulating Layer: a Comparison Study”

GCBME 2014 & APCMBE 2014, Tainan, Taiwan, Oct. 2014 ▓ “Initial Design of the Capacitive Micromachined Ultrasonic Transducers (CMUT) with Helmholtz Resonance Aperture”

ECCE 2014, Pittsburgh, PA, USA, Sept. 2014 ▓ “Hybrid railway power conditioner with partial compensation for rating optimization”

IC-TEMS 2014, ZhuHai, GuangDong, China, Jul. 2014 ▓ “The Fabrication and Application of a Robust and Intelligent Digital Microfluidics” ICIEA 2014, Hangzhou, China, Jun. 2014 ▓ “Modeling of novel single flow zinc-nickel battery for energy storage system” ISCAS 2014, Melbourne, Australia, Jun. 2014 ▓ “A High Voltage Zero-Static Current Voltage Scaling ADC Interface Circuit for Micro-Stimulator” ▓ “Micropower Two-Stage Amplifier Employing Recycling Current-Buffer Miller Compensation”

EDSSC 2014, Chengdu, China, Jun. 2014 ▓ “A 26.3 dBm 2.5 to 6 GHz Wideband Class-D Switched-Capacitor Power Amplifier with 40% Peak PAE ” ICBME 2013, Singapore, Dec. 2013 ▓ “Effect of Transmitter and Receiver Electrodes Configurations on the Capacitive Intrabody Communication Channel from 100 kHz to 100 MHz” ▓ ”Channel Modeling and Simulation for Galvanic Coupling Intra-body Communication”

State Key Laboratory of Analog and Mixed-Signal VLSI / UM

http://www.amsv.umac.mo