AN 899: Reducing Compile Time with Fast Preservation - Intel...Quartus Prime Pro Edition allows you to preserve satisfactory compilation results for FPGA periphery or core logic design

AN 899: Reducing Compile Time withFast Preservation

Updated for Intel® Quartus® Prime Design Suite: 19.3

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Contents

1. AN 899: Reducing Compile Time with Fast Preservation................................................. 31.1. Tutorial Design Overview........................................................................................ 41.2. Downloading Tutorial Design Files............................................................................ 51.3. Module 1: Analyze the Non-Partitioned Design...........................................................6

1.3.1. Step 1: Compile the Flat Design...................................................................61.3.2. Step 2: Identify Timing-Critical Design Blocks................................................71.3.3. Step 3: View Design Assistant Results.......................................................... 9

1.4. Module 2: Preserve Timing-Closed Design Partitions................................................. 111.4.1. Step 1: Create Design Partitions................................................................ 111.4.2. Step 2: Floorplan the Design Partitions....................................................... 131.4.3. Step 3: Preserve the Timing-Closed Root Partition........................................ 14

1.5. Module 3: Optimize with Fast Preservation.............................................................. 151.5.1. Step 1: Create a Project Revision............................................................... 151.5.2. Step 2: Enable Fast Preservation................................................................161.5.3. Step 3: Import the Root Partition............................................................... 161.5.4. Step 4: Optimize the Reserved Core Partitions............................................. 171.5.5. Step 5: View Fast Preservation Results........................................................17

1.6. AN 899: Reducing Compile Time with Fast Preservation Revision History..................... 19

Contents

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1. AN 899: Reducing Compile Time with Fast PreservationThis tutorial demonstrates how to use the fast preservation feature, along with designpartitions, to reduce the overall compile time for a design. The Fast Preserve optionsimplifies the logic of a preserved partition during compilation to only the interfacelogic between the partition boundary and the rest of the design, thereby reducing thecompilation time required for that partition.

Figure 1. Preserve Timing Closed Partitions to Reduce Compile Times

A

B C

D E F

Root Partition(Preserved)

Partition BCore Partition F

Partition Preserves Satisfactory Results

Compiler Fully Processes Non-Preserved partitions

Intel® Quartus® Prime Pro Edition allows you to preserve satisfactory compilationresults for FPGA periphery or core logic design blocks, and then reuse the placementand routing of those blocks in subsequent compilations. You assign the hierarchicalinstance as a design partition, which you can then preserve and reuse followingsuccessful compilation.

Design Setup Requirements

The use of fast preservation requires one or more reserved core partitions, and apreserved .qdb functioning as the root partition. This design partitioning is similar tothat required for the device periphery reuse or partial reconfiguration (PR)implementation flow. This tutorial includes a design example to demonstrate thissetup.

Related Information

• Intel Quartus Prime Pro Edition User Guide: Block-Based Design

• Intel Quartus Prime Pro Edition User Guide: Partial Reconfiguration

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1.1. Tutorial Design Overview

This tutorial includes a prepared design example to demonstrate use of fastpreservation. You can download the design example to follow along with the tutorialsteps in the Intel Quartus Prime Pro Edition software, as Downloading Tutorial DesignFiles on page 5 describes.

The example top-level design instantiates a PLL that generates a 550 MHz fast clock(CLK1), and a 100 MHz slow clock (CLK2). The top-level design also instantiates 4blinking LED modules that drive LED[3:0] every 2, 4, 8, and 16 seconds, respectively.

Figure 2. Incremental Block-Based Compilation Tutorial Design Example

u_big_partition1_top

u_blinking_led_i1

iopll_inst

clock

top

data_in

u_blinking_led_i2

u_blinking_led_i3

u_blinking_led_i4

32bCounter

32bComparator

32bCounter

32bComparator

Async FIFO

32bCounter

32bComparator

32bCounter

32bComparator

Async FIFO

64bCounter

64bComparator

32bCounter

32bComparator

Async FIFO

64bCounter

64bComparator

32bCounter

32bComparator

Async FIFO

>CLK1

> CLK2

> CLK2

> CLK2

>CLK2

>CLK1>CLK2

>CLK1>CLK2

>CLK1>CLK2

2s 2s

LED[0]

LED[1]

LED[2]

LED[3]

LED[7]LED[6]LED[5]LED[4]data_out

16sCLK2 -> 100 MHzCLK1 -> 550 MHz

16s

8s8s

4s4s

OpenCores*Design

Instances

D DA A

> CLK1 > CLK2> CLK1 > CLK1 > CLK2

D

D

D

D

> CLK1 > CLK2> CLK1 > CLK1B

A

> CLK2

BB

A

B

A

B

A

B

D A

B> CLK1 > CLK2> CLK1 > CLK1

> CLK2> CLK2

D A

B> CLK1 > CLK2> CLK1 > CLK1

> CLK2> CLK2

To increase the design size in the Intel FPGA, the design example also instantiates 20duplicate instances of an OpenCores* design.(1)

(1) Reed Solomon Decoder OpenCores project, Varkon Semiconductors, 2010.

1. AN 899: Reducing Compile Time with Fast Preservation

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The duplicate OpenCores design instances have the following characteristics:

• The design implements each instance in parallel.

• I/O wrapper logic is present to reduce the number of I/O pins that the largerdesign requires.

• No timing-critical paths exist between the instances and the wrapper logic.

1.2. Downloading Tutorial Design Files

1. Download and extract the tutorial design files at:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an899_fast_preservation_tutorial_files_193.zip

2. View the extracted tutorial design file directory structure.

Figure 3. Tutorial Directory Structure

an899_fast_preservation_tutorial_files_193

tutorial_flat–non-partitioned project directory and output

tutorial_impl–partitioned project with Fast Preserve

tutorial_base–partitioned project working directory

golden_rtl–corrected RTL that replaces RTL in tutorial_impl

Table 1. Tutorial Design Files

File Name Description

top.sv Top-level file that instantiates iopll, big_partition1_top, blinking_led_2s,blinking_led_4s, blinking_led_8s, and blinking_led_16s. Also includes logic todrive LED[4:7] as a single, shifting bit.

top.qpf Intel Quartus Prime project file that stores project name and revisions.

top.qsf Intel Quartus Prime settings file containing project assignments and settings.

big_partition1_top.v Design file that instantiates 20 instances of an OpenCores design.

blinking_led_2s.sv Logic to drive LED[0] every two seconds.

blinking_led_4s.sv Logic to drive LED[1] every four seconds.

blinking_led_8s.sv Logic to drive LED[2] every eight seconds.

blinking_led_16s.sv Logic to drive LED[3] every 16 seconds.

blinking_led.sdc A Synopsys Design Constraints file that defines the 50 MHz input reference clock.

iopll.ip The IOPLL Intel FPGA IP instantiated in top. The IP uses a 50 MHz reference clockfrequency, and generates 100 MHz and 550 MHz clocks.

tx_dcfifo.ip The dual clock FIFO Intel FPGA IP instantiated in blinking_led_2s, blinking_led_4s,blinking_led_8s, and blinking_led_16s instances. Has a write clock of 550 MHz andread clock of 100 MHz.

report_timing.tcl A tcl script with Timing Analyzer commands to generate summary of paths reports withleast positive or worst slack in each partition, and commands to report timing for two nodesin the partitions that meet timing.


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1.3. Module 1: Analyze the Non-Partitioned Design

Follow the steps in this tutorial module to analyze the non-partitioned design todetermine appropriate locations for design partitions.

Process Description

Use of the Fast Preserve option requires that you partition your design, similar to thesetup for partial reconfiguration. You first analyze the non-partitioned design todetermine which blocks have satisfactory performance, and which blocks requirefurther optimization. The Intel Quartus Prime Design Assistant helps you to identifyareas for further optimization.

After partitioning the design, you preserve the partitions and enable Fast Preserve tofocus compilation time on the non-optimized partitions.

Tutorial Files

The tutorial_flat directory contains the files for this tutorial module.

Tutorial Steps

This tutorial module includes the following steps:

• Step 1: Compile the Flat Design on page 6

• Step 2: Identify Timing-Critical Design Blocks on page 7

• Step 3: View Design Assistant Results on page 9

1.3.1. Step 1: Compile the Flat Design

Follow these steps to compile the flat (non-partitioned) design:

1. In the Intel Quartus Prime Pro Edition software, click File ➤ Open Project andopen the /tutorial_flat/top.qpf project file.

2. To compile the flat design, click Compile Design on the Compilation Dashboard.The flat compilation can require 40 minutes or more, depending on your system.

Figure 4. Compilation Dashboard

3. To view the compile time in the Compilation Report, click the Flow Elapsed Timereport. Fast Preserve can reduce this compilation time significantly.


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Figure 5. Flow Elapsed Time Report

Fast Preserve Off ≈ 49 min

1.3.2. Step 2: Identify Timing-Critical Design Blocks

Follow these steps to identify the timing-critical design blocks in the Intel QuartusPrime Timing Analyzer:

1. To open the Timing Analyzer, click Tools ➤ Timing Analyzer.

2. In the Timing Analyzer, on the Tasks pane, double-click Update Timing Netlistto load the final timing netlist generated during the compilation.

Figure 6. Timing Analyzer Tasks Pane

3. To run the report_timing.tcl script to identify any failing paths in the timing-critical design blocks, type the following command in the Console window. If notalready visible, click View ➤ Console in the Timing Analyzer to display theConsole. The script runs commands to identify any failing paths.

source report_timing.tcl

The tcl script runs the report_timing command, capturing timing for the top100 paths with the worst slack. The script is also preconfigured to capture timingbetween specific nodes for some of the design blocks. You analyze timing for thesenodes later in this tutorial.


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Figure 7. Timing Analyzer Report Folders

Require Furtheroptimization

Table 2. Timing Analysis Reports that report_timing.tcl Generates

Timing Analysis Folder Generated For Timing Reports Show

inst_big u_big_partition1_top

Analysis of top 100 paths with worst slack

inst_i1 u_blinking_led_i1




inst_big_path1 u_big_partition1_top

Analysis of timing between specific nodesinst_i1_path1 u_blinking_led_i1

inst_i2_path1 u_blinking_led_i2

4. In the inst_big folder, right-click the Slow 900 mV 100C Model report, and thenclick Generate in All Corners. Repeat this step for the inst_i1, inst_i2,inst_i3, and inst_i4 folders.

5. View the Multi Corner Summary report that generates under each folder in theReport pane. Reports in red text in the inst_i3 and inst_i4 folders indicatetiming-critical design blocks with failing paths.

6. Open the Multi Corner Summary report in the inst_i3 folder. Check the valuesin the From Node and To Node fields. Analysis indicates that the failing paths inu_blinking_led_i3 are in the 64-bit counter. This counter counts the numberof cycles equivalent to 8s, where each cycle is of 1.818 ns.


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Figure 8. Multi Corner Summary for u_blinking_led_i3

Note: Placement and routing results can vary by processor, OS, and softwareversion.

7. Open the Multi Corner Summary report in the inst_i4 folder. Check the valuesin the From Node and To Node fields. Analysis indicates that the failing paths inu_blinking_led_i4 are in the 64-bit counter. This counter counts the numberof cycles equivalent to 16s, where each cycle is of 1.818 ns.

Figure 9. Multi Corner Summary for u_blinking_led_i4

The timing analysis identifies u_blinking_led_i3 and u_blinking_led_i4 astiming-critical design blocks for optimization.

1.3.3. Step 3: View Design Assistant Results

The Intel Quartus Prime Design Assistant can run automatically during various stagesof compilation to report any violations against a standard set of Intel FPGA-recommended design rules. You can analyze Design Assistant results to determinewhere you can further optimize the design. For this tutorial module, specific Hyper-Retiming Design Assistant rules are enabled in the Compiler settings.

Follow these steps to run Design Assistant:

1. To view Design Assistant settings, click Assignments ➤ Settings ➤ DesignAssistant Rule Settings. Design Assistant settings show that Design Assistant isenabled automatically during compilation, and that rule HRR-10101Asynchronous Clears is enabled. HRR-10101 identifies asynchronous clearsignals that prevent retiming of paths that could increase design performance.


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Figure 10. Design Assistant Settings

2. Under the Synthesis folder of the Compilation Report, expand the DesignAssistant (Elaborated) folder. Design Assistant reports that the design containsasynchronous clears that limit retiming.

Figure 11. Design Assistant Report

Module 2: Preserve Timing-Closed Design Partitions on page 11 describes how topreserve the design partitions that don't require further optimization, allowing youto focus the Compiler's effort on areas requiring further optimization.


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1.4. Module 2: Preserve Timing-Closed Design Partitions

Follow the steps in this tutorial module to define and preserve the timing-closedpartitions in your design.

Process Description

Design partitioning the design allows you to preserve individual logic blocks in yourdesign. After partitioning the design, you can preserve the partitions for blocks thatmeet timing, and focus optimization on the other design blocks.

In this tutorial module, you preserve and reuse the root partition, which is thepartition that includes the device periphery.

Figure 12. Root Partition Reuse Example

Reserved CorePartition(shell)

RootPartition Export

Root Partition

ReusedRoot

Partition

Reserved CorePartition

Tutorial Files

The tutorial_base directory contains the files for this tutorial module.

Tutorial Steps


• Step 1: Create Design Partitions on page 11

• Step 2: Floorplan the Design Partitions on page 13

• Step 3: Preserve the Timing-Closed Root Partition on page 14

1.4.1. Step 1: Create Design Partitions

To export and reuse the root partition, first create reserved core partitions for thefailing u_blinking_led_i3 and u_blinking_led_i4 blocks that require furtheroptimization.

1. In the Intel Quartus Prime Pro Edition software, click File ➤ Open Project andopen the /tutorial_base/top.qpf project file.

2. Click Processing ➤ Start ➤ Start Analysis & Elaboration.

3. In the Project Navigator, expand the u_blinking_led_top instance in theHierarchy tab.


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4. Right-click the u_blinking_led_i3 instance, point to Design Partition, andselect the Reserved Core partition Type. A design partition icon appears next toeach instance you assign.

Figure 13. Create Design Partitions

5. Repeat step 4 to create a partition for the u_blinking_led_i4 instance. You willexport the remaining instances as part of the root partition.

6. If the Design Partitions Window is not already open, click Assignments ➤ DesignPartitions Window. The Design Partitions Window lists the partitions you define,along with the root partition (|) the Compiler automatically creates for eachproject.

Figure 14. Design Partitions Window

(2)

(2) You can rearrange columns in Design Partitions Window to match the layout in this tutorial.


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1.4.2. Step 2: Floorplan the Design Partitions

You must define a core-only, reserved, fixed routing region to reserve core resourcesin the project for the reserved core partition. Ensure that the exclusive placementregion size is large enough to contain all core logic in the reserved core partition.Follow these steps to define a core-only, reserved, fixed routing region to reserve coreresources in for non-periphery development:

1. In the Design Partitions Window, right-click the blinking_led_8s instance in theProject Navigator and click Logic Lock Region ➤ Create New Logic LockRegion.

Figure 15. Create Logic Lock Region

2. To modify the region properties, click Assignments ➤ Logic Lock RegionsWindow.

3. In the Origin column, specify X165_Y113.

4. Change the Width to 14, and the Height to 34.

5. Enable the Reserved and Core-Only options.

6. Click the Routing Region cell. The Logic Lock Routing Region Settings dialogbox appears.

7. Specify Fixed with expansion with Expansion Length of 1 for the RoutingType. The actual size and location are arbitrary for this tutorial. However, you canview and adjust the Logic Lock Region shape in the Chip Planner.

8. Repeat steps 1 through 7 to define the following Logic Lock region for theblinking_led_16s instance:

Figure 16. Logic Lock Regions


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• Origin—X165_Y149

• Width—14

• Height—34

• Reserved—On

• Core Only—On

• Expansion Length—Fixed with expansion 1

This floorplanning ensures that the ref_clock_in meets timing because theplacement location is not too far from output pins.

Figure 17. Logic Lock Region Placement

1.4.3. Step 3: Preserve the Timing-Closed Root Partition

Follow these steps to preserve and export the timing-closed root partition.

1. Click Assignments ➤ Design Partitions Window.

2. For the root_partition row, specify root_partition.qdb as the Post FinalExport File.


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Figure 18. Post Final Export File

3. To compile the design and export the partition, click Compile Design on theCompilation Dashboard.

1.5. Module 3: Optimize with Fast Preservation

Follow the steps in this tutorial module to enable the Fast Preserve option duringdesign optimization.

Process Description

You can create a separate revision of your project that reuses the preserved rootpartition during optimization of the other partitions. When you enable the FastPreserve option, the Compiler reduces the logic of the imported partition to only theinterface logic between the partition boundary and the rest of the design, therebyreducing the compilation time the partition requires.

In this tutorial module, you reuse the root partition, which is the partition thatincludes the device periphery.

Tutorial Files

The tutorial_impl directory contains the files for this tutorial module.

Tutorial Steps


• Step 1: Create a Project Revision on page 15

• Step 2: Enable Fast Preservation on page 16

• Step 3: Import the Root Partition on page 16

• Step 4: Optimize the Reserved Core Partitions on page 17

• Step 5: View Fast Preservation Results on page 17

1.5.1. Step 1: Create a Project Revision

Follow these steps to create a new project revision for import of the preservedpartition:

1. From the tutorial_base directory, copy the following files into thetutorial_impl directory:


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• top.qsf—to include the partition and Logic Lock settings in the new revisionof the project.

• root_partition.qdb—to apply the final snapshot .qdb as the root partitionof the new revision.

2. In top.qsf, remove the following line:

set_instance_assignment -name EXPORT_PARTITION_SNAPSHOT_FINAL \ root_partition.qdb -to | -entity top

3. Save top.qsf.

1.5.2. Step 2: Enable Fast Preservation

Follow these steps to enable the Fast Preserve option before running compilation.

1. Click Assignments ➤ Settings ➤ Compiler Settings ➤ Incremental Compile.

2. Turn on the Fast Preserve option.

Figure 19. Fast Preserve Option

3. Click OK.

Alternatively, you can enable Fast Preserve by specifying the following assignment inthe project .qsf:

set_global_assignment -name FAST_PRESERVE AUTO

1.5.3. Step 3: Import the Root Partition

Follow these steps to import the root partition to the project and run compilation withFast Preserve.

1. If the Design Partitions Window is not already open, click Assignments ➤ DesignPartitions Window. The Design Partitions Window lists the blinking_led_8sand blinking_led_16s partitions that you create in Step 1: Create DesignPartitions on page 11.

2. In the root_partition row, select root_partition.qdb as the PartitionDatabase File. root_partition.qdb is now the source for the root partition ofthis project.

Figure 20. Import the Root Partition


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1.5.4. Step 4: Optimize the Reserved Core Partitions

Next, you optimize the RTL of the blinking_led_8s and blinking_led_16sreserved core partitions.

1. Update the RTL for blinking_led_8s and blinking_led_16s to correct thetiming violations and asynchronous reset.

Note: To accelerate this step, you can simply copy the blinking_led_8s.sv andblinking_led_16s.sv from the golden_rtl directory, and paste thefiles into the tutorial_impl directory, overwriting the existing files.

2. Click Compile Design on the Compilation Dashboard. The Compilation Dashboarddisplays the time spent in each module of the Compiler and the total compilationtime.

Figure 21. Fast Preserve Compilation Flow Time

1.5.5. Step 5: View Fast Preservation Results

Follow these steps to view the Fast Preserve compilation time savings. With FastPreserve enabled the Compiler reduces the logic of the imported partition to onlyinterface logic, thereby significantly reducing the compilation time the partitionrequires.


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1. To view the compile time in the Compilation Report, click the Flow Elapsed Timereport. The report shows time savings in each module of the Compiler.

Figure 22. Compile Time Comparison

Fast Preserve On ≈ 16 min

Flat Compile ≈ 49 min

2. Under the Synthesis folder, view the Design Assistant (Elaborated) report. AllAsynchronous Clear rule violations are resolved.

Figure 23. Design Assistant Results

Optimized Partition Results

Non-Optimized Partition Results

3. To view the Timing Analyzer results, click Tools ➤ Timing Analyzer.


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4. On the Tasks pane, double-click Update Timing Netlist.

5. Under Reports, open the Slack folder.

6. Double-click Report Setup Summary. The design meets all setup timingrequirements.

Figure 24. Timing Analysis Results

This tutorial shows that use of Fast Preserve during design optimization can shortenoverall compile times, and preserve predictable, satisfactory results through designiterations.

1.6. AN 899: Reducing Compile Time with Fast PreservationRevision History

This document has the following revision history:

Document Version Intel QuartusPrime Version

Changes

2019.11.06 19.3.0 • First public release.


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AN 899: Reducing Compile Time with Fast PreservationContents1. AN 899: Reducing Compile Time with Fast Preservation1.1. Tutorial Design Overview1.2. Downloading Tutorial Design Files1.3. Module 1: Analyze the Non-Partitioned Design1.3.1. Step 1: Compile the Flat Design1.3.2. Step 2: Identify Timing-Critical Design Blocks1.3.3. Step 3: View Design Assistant Results

1.4. Module 2: Preserve Timing-Closed Design Partitions1.4.1. Step 1: Create Design Partitions1.4.2. Step 2: Floorplan the Design Partitions1.4.3. Step 3: Preserve the Timing-Closed Root Partition

1.5. Module 3: Optimize with Fast Preservation1.5.1. Step 1: Create a Project Revision1.5.2. Step 2: Enable Fast Preservation1.5.3. Step 3: Import the Root Partition1.5.4. Step 4: Optimize the Reserved Core Partitions1.5.5. Step 5: View Fast Preservation Results

1.6. AN 899: Reducing Compile Time with Fast Preservation Revision History

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AN 899: Reducing Compile Time with Fast Preservation - Intel...Quartus Prime Pro Edition allows you to preserve satisfactory compilation results for FPGA periphery or core logic design