An Affordable Solution That Bridges the Gap Between

Firmware and RTL Implementations

Alicia Strang, Robert C. Carden IV, Pei Suen

Marvell Semiconductor, Inc. CA

Two for the Price of One

Overview

• Unified System Architecture for pre-silicon firmware development and rapid system integration

• Simulation and Emulation Flow: RTL Verification andSystem Integration

• Steps to Build This System

• Result and Conclusions

System Architecture

• Architecture for firmware development and rapid system integration.– Simulation test bench that can generate test scripts for

FPGA environment

– IP RTL integration into ARM SOCs

– Firmware development (IROM)

– FPGA environment to run test scripts generated by simulation

System Architecture

knob

Test Code

seed

RTL design IP 2 RTL design IP nRTL design IP 1

ARM cortexUART DDR SRAM

Diagnostic LED

JTAG/DAP

…

XML

Unified System Architecture

AHB/APB

Parallel System Phases (1)

• Simulation Phase: Use Test IROM to test RTL and testbench

– SoC system platform for simulation using modern constrained random and event driven verification methodologies

– SystemVerilog code sends commands to the test IROM (embedded firmware) that executes on an ARM processor that is being simulated

Parallel System Phases (2)

• Emulation Phase: Both Production and Test IROM

– Replace the SystemVerilog code with a script that is executed on a PC that sends commands to the firmware running on an ARM processor within the FPGA environment.

– Same PC program can execute these scripts against a board containing the actual chips.

Flow: RTL Verification and System Integration

Traditional flow

Architecture RTL Design RTL Verification FirmwareDevelopment

SystemIntegration

CustomerIntegration

Unified System Architecture developer’s platform flow

Architecture RTL Design RTL Verification

FirmwareDevelopment

SystemIntegration

CustomerIntegration

Firmware Development

• Using firmware driven tests brings true accuracy and performance to the front end of the design cycle.

• Firmware is tested and debugged on RTL design IP before the design is fabricated.

• Seamlessly run firmware with RTL models without sacrificing speed or accuracy.

Flow: RTL Verification and System Integrations

Test EROM

and

Test IROM

Custom EROM

Production IROM

Design IPs and

Hardware RTL

Constrained Random Tests and reference model

Tests Vectorsand Golden ResultSimulation

Environment FPGA

SimulationEmulation (Board)

Chip

Steps to Build This System

• Generate firmware image from test firmware code

• Synthesize firmware image together with RTL for FPGA and program FPGA PROM

• Connect to PC host through serial port

• Execute script to send commands through the serial port to the firmware

• Process results from each command

Steps to Build This system (continued)

• Run processor at FPGA speed (16 MHz)

• Identify problems to be reproduced in simulation

• Debug RTL and tweak firmware performance

• Debug EROM written by customer

• Execute script on post-silicon chip and process results

Debugging and Performance Analyse the Systems.

WaveformGraphic presentation

Result and Conclusions

• By using Unified System Architecture we reduced our wasted time and removed the need for separate system simulation and emulation testbenches.

• This not only greatly reduces the amount of duplicated work but also bridges the critical gap between firmware and RTL implementations – two for the price of one.

Future Work

• Add ability to generate random sequences of activities within the tests that are to be run on the FPGA

• Add ability to run failed test in simulation once identified on FPGA