952 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 6, JUNE 1994

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16

An Analytical Quasi-Saturation Model

. I I I I

- IRF540 I I

Considering Heat Flow for a DMOS Device C. M. Liu, J. B. Kuo, Senior Member, IEEE, and Y. P. Wu

Abstract- This paper reports an analytical quasi-saturation model considering heat flow for a DMOS device. As verified by the PISCES results, the analytical model, which considers heat flow provides a good prediction of the much worse quasi- saturation behavior due to the elevated lattice temperature. This is a result of the limited heat sinking capability of the thermal contact node. Based on the analysis, for a DMOS device operating with a contact thermal resistance Of less than lo4 K/W, the drain current at quasi-saturation is found acceptable with a lattice temperature below 350 K.

I. INTRODUCTION OWER semiconductor devices usually operate at a high P voltage and a large current. As a result, the thermal effect

[I] due to nonisothermal heat flow [2] on the performance of a power device must be studied. In fact, due to the limited heat sinking capability of the thermal contact node [3], [4], the lattice temperature of a power device is usually much higher than the ambient temperature. As a result, the thermal effect on the performance of a power device must be studied. For a DMOS device, thermal effects are particularly important for considering the quasi-saturation [5] since it occurs at a biasing condition with a high voltage and a high current. Although recent analytical models of the quasi-saturation behavior have been reported [5]-[8], the thermal effects were not included. How the thermal resistance of a contact node [4], [9] affects the drain current characteristics at quasi-saturation is worth investigation.

Fig. 1 shows the drain current ( I D ) versus the gate-to- source voltage ( V ~ S ) characteristics of a typical DMOS device (IRF540 [ 40101) measured by imposing various supply voltages with a duration of 80 ,us and 1 ms on the gate. The device is biased at a drain-to-source voltage of 5 V and 15 V. For the longer pulse (1 ms) case, the DMOS device can be regarded as working at an elevated lattice temperature owing to the limited heat sinking capability of the packaging of the device [ l 11, [ 121. For the shorter pulse (80 ps) case, the device is operating under a condition where the thermal effect is negligible [lo]. As shown in the figure, in the pre-quasi-saturation region, the difference in the drain current for the two cases with and without considering thermal effects is negligible. However, in the quasi-saturation region, for a longer voitage pulse (1 ms) applied at the gate, the current at quasi-saturation [5] as

Manuscript received August 12, 1993; revised October 18,1993. The review of this paper was arranged by Associate Editor Y . Nisbi. This work was supported by ROC National Science Council Contract Numbers 82-0404- EOO2-267 and 288.

The authors are with the Department of Electrical Engineering, National Taiwan University, Taipei 106-17, Taiwan, ROC.

IEEE Log Number 940 1 13 1.

0 2 6 8 10 I2 14 16

vGS (v) Fig. 1. The measured Zo versus VGS characteristics of a DMOS device (IRF540) biased at VDS = 15 V, 5 V with a stress time of 80 ps and 1 ms.

shown in solid circles is smaller than that for a shorter voltage pulse (80 ,us). Therefore, the thermal effect lowers the drain current of a DMOS device at quasi-saturation.

In this paper, an analysis of the quasi-saturation behavior considering the elevated lattice temperature in terms of the thermal resistance of the contact node for a DMOS device is described. It will be shown that considering the limited heat sinking capability of the contact node, the drain current at quasi-saturation is smaller &d less VDS dependent as a result of the elevated lattice temperature. In addition, a closed-form thermal effect model is derived to provide a good explanation of DMOS thermal effect quasi-saturation behavior. In the following sections, the quasi-saturation behavior considering thermal effect is described first, followed by derivation of the quasi-saturation model considering heat flow, and comparison with simulation results and discussion.

11. THE THERMAL EFFECT ON QUASI-SATURATION Fig. 2 shows the DMOS device [8] used in this study.

It has the following characteristics. Under the gate oxide, a lateral channel of 1.3 pm with a peak doping density of 3 x 1017 cm-3 is formed by double-diffused technology. Below the lateral channel, an n-epi layer of 11 pm with a doping concentration of 1 x 1015 c ~ - ~ ( N D ) is used to sustain a high voltage. An N + polysilicon gate with an oxide thickness of 500 A has been used. In order to simplify the analysis, only half of the device is studied. The distance from the right edge of the lateral channel to the right end of Qe device cross section is 5 pm (LD) . A thermal resistance of lo5 K/W has been assumed at the drain contact.

Fig. 3 shows the simulated ID versus VGS characteristics of the DMOS device biased at VDS = 10 V to 40 V based on the

0018-9383/94$04,OO 0 1994 IEEE

LIU et al.: AN ANALYTICAL QUASI-SATURATION MODEL CONSIDERING HEAT FLOW 953

l L j

I l l L e

VD

Fig. 2. The DMOS device cross section under study. The substrate doping density is 10l5 cmP3. The gate oxide thickness is 500 A. A thermal resistance of lo5 K/W has been assumed at the drain contact.

TABLE I THE DRAIN CURRENT ( I D ) AND THE AVERAGE LAITICE TEMPERATURE (TL) OF THE DMOS AT QUASI-SATURATION WITH VDS = 1ov - 40 V

I.DS(V) 10 2 0 30 40 I D ( N P m ) 6 . 4 4 ~ IO-’ 7 . 0 5 ~ lo-’ 7 . 2 2 ~ IO-’ 7 . 2 6 ~ io-’ TL (K) 366 445 523 598

results from PISCES [ 131 with and without including the heat flow equation. When including the heat flow equation [2], the drain current at quasi-saturation becomes smaller compared to that without the heat flow equation. In addition, when including the heat flow equation, the drain current is less sensitive to the drain voltage as compared to that without including it. Fig. 4 shows the 2D electron concentration contours in the DMOS device biased at VDS = 30 V from 5 x 1014 cm-3 to 1.5 x l O I 5 cm-3 at an interval of 10O.l cm-3 with and without including the thermal effects. From this figure, the electron conduction channel exists from the source contact at upper left via the lateral channel region beneath the gate and the substiate drift region to the drain contact at bottom. As reported in the previous paper [8], the substrate channel region can be divided into two regions-the upper rectangular region ( -L3 < y < 0) and the trapezoidal region (0 < y < L e ) as shown in Fig. 2. As reported earlier [8], the width of the conduction channel in substrate varies as a function of V i s [5]. Before quasi-saturation, the conduction channel widens as VGS increases. After quasi-saturation, the width of the conduction channel reaches a maximum value and stays fixed regardless of VGS. From these figures, with and without including the thermal effects, the conduction channel is found similar in the substrate region.

Fig. 5 shows the 2D lattice temperature contours in the DMOS device biased at VDS = 10 V - 40 V and VGS = 20 V with an ambient temperature of 300 K. From these figures, for a higher drain voltage, the intemal lattice temperature is higher. For a drain voltage from 10 V to 40 V, the lattice temperature varies from 359 K to 570 K. For each case, the variation of the lattice temperature in the substrate conduction channel region is small. The elevated lattice temperature is due to the limited heat sinking capability from the drain contact region, which is assumed to have a thermal resistance of lo5

----. THERMAL

:: 0 2 4 6 8 IO 12 14 16 18 M

Fig. 3. The I D versus VGS characteristics of the DMOS device biased at VDS = 10 V-40 V based on the PISCES results with and without including thermal effects.

NONTHERMAL THERMAL 0

0 v,. 4v

0

YI

0

0

v,, I 5v 0 v,, I 5v

0

Lo

0

0

0 0 0 0

V,, I 6V V,, = 6V

Y) YI

0 0

0 0

0 0

0 v,, E 20v v,, = 2ov

0 Lo

0 0

0 0

0.0 5.0 10.0 0.0 5.0 10.0

Fig. 4. 2 D electron concentration contours in the DMOS device biased at Vjs = 30 V from 5 x lo i4 ~ m - ~ t o 1.5 x lo1’ cm-3 at an interval of 10’

K/W. Table I shows the summary of the drain current and the average lattice temperature of the DMOS device, biased at quasi-saturation with VDS = 10 V - 40 V, with a thermal resistance of lo5 K/W at the drain contact node. From this table, the lattice temperature increases by two-thirds despite the fact that the drain current changes by only 12% for VDS changes from 10 V to 40 V at quasi-saturation.

Fig. 6 shows the electric field distribution in the vertical substrate direction at the right side of the DMOS device biased at onset of quasi-saturation for VDS = 10 V - 40 V with and without including thermal effects. As shown in this figure, with and without including thermal effect, the electric field in the vertical direction of the DMOS biased at quasi-saturation is similar. Fig. 7 shows the electrostatic potential distribution in

cm-3 with and without including thermal effects.

954 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 6. JUNE 1994

b= ,20v

9

9 s 0.0 5.0 10.0

I 40v

Fig. 5. The 2D lattice temperature contours in the DMOS device biased at VDS = 10 V-40 V and VGS = 20 V with an ambient temperature of 300 K.

- NOMnERMA __----- ----___

DISTANCE (pm)

Fig. 6. The electric field distribution in the vertical substrate direction at the right side of the DMOS device biased at onset of quasi-saturation for VDS = 10 V - 40 V with and without including thermal effects.

" I I

z 4 I:

I

S 5.5 6 b.3 7 75 8 DISTANCE (pm)

the lateral channel beneath the gate oxide in the DMOS device Fig. 7. The electrostatic potential distribution in the lateral channel direction

biased at vDs = 30 with ';ld without including thermal effect. At quasi-saturation, the voltage drop throughout the

beheath the gate oxide in he DMOS device biased at VDS = 30 V with and without including thermal effects.

lateral 'Ompared to vDs for both with and without including thermal effects. As shown in the figure, the nonthermal lines at VGS = 4 V and 5 V are close with each

is Integrating (2) from the top of the substrate conduction channel ( y = - L j ) to the ( L e ) , one obtains:

other since the device does not operate at quasi-saturation,

traveling at a saturated velocity since the lateral electric field is high [SI.

where the electrons in the lateral channel under the gate are -E (Y )dY (3)

where A(y) is the cross section of the conduction channel. From the thermal resistance of the drain contact, one obtains: ITI. DERIVAnoN OF THE LAmCE TEMPERATURE

In the DMOS structure as shown in Fig. 2, the following heat flow equation has been used:

(4)

J" = -V (XVT). (1)

Along the current conduction path in the device, the lateral channel region beneath the gate has been neglected due to its negligible voltage drop as compared to VDS at quasi-sahration. In order to simplify the analysis, only the substrate conduction

simplified as

where T2 is the lattice temperature at the drain contact, T3 is the ambient temperature. LT is the width of the drain thermal contact. w is depth of the device. R~ is the of the drain contact. considering the thermal resistance at the top of the substrate conduction channel, one obtains:

( 5 )

where TI is the lattice temperature at the top of the substrate conduction channel. R, is the average thermal resistance of

By dividing the substrate conduction channel region into the upper rectangular region and the lower trapezoidal region as shown in Fig. 2, the channel width can be modeled [8]. As a

channel region is considered, where the heat flow equation is

A- = - J(Y)E(Y)

where X is the thermal conductivity of the substrate [14], [15].

dT - T2 - Tl X-ly=-L3 - -

dY LTWR, d2T

(2) dY2

the Substrate RS = ii:g 5 X lo3 K/w). (A = 1.547 W/K cm, at 300 K; 0.641 W/K cm at 600 K). y is in the substrate direction. E(y) is the electric field. J(y) i s current density. T(y) is the lattice temperature in Kelvin.

LIU et al.: AN ANALYTICAL QUASI-SATURATION MODEL CONSIDERING HEAT FLOW 955

result, the right side of (3) becomes:

From (13) in the previous paper [8], in the upper rectangular region, the electric field is

Q €si

E ( Y ) = --(n(O) - N D ) ~ - Lj < p < 0. (7)

From (22) in the previous paper [8], in the trapezoidal region,

Integrating (8) from y = O to location y(O < y < Le) , one obtains the electric field in the trapezoidal region:

From (7) and (9) the right side of (6) becomes:

From (4), (3, and (lo), one obtains:

Considering the thermal resistance at the drain contact, one obtains:

From (1 1) and (12), the lattice temperature at the top and the bottom of the substrate conduction channel can be uniquely determined:

Ti - T3 = I D ( R ~ V D ~ + R,VDS + SLTWR,). (13)

Equations (1 1 ) and (13) are the closed-form analytical model describing the lattice temperature of a DMOS device biased at quasi-saturation.

In order to verify the effectiveness of the lattice temperature model described above, the model results have been com- pared with the PISCES simulation results using the device

7w, 1 - PISCES RESULTS

650 1 -0- OUR MODEL

y MyJ .......................................................................................

2 ZY

v s=40v

2 550 . ............................... ii g 5w

......................... av

................ 350

DISTANCE (pn)

Fig. 8. device biased at \ b s = 10 V - 40 V and lks = 20 V.

The 1D lattice temperature distribution at the right side of the DMOS

TABLE U THE AVERAGE LATTICE TEMPERATURE ( T L ) , THE CORRESPONDING CRITICAL ELECTRIC FIELD (h’c ) , THE ELECTRON CORRESPONDING

SATURATED VELOCITY (\‘s), AND THE RELATED ELECTRIC FIELD AND DRIFT VELOCITY OF THE DMOS DEVICE

BASED AT QUASI-SATURATION WITH bD.5 = 1ov - 40 v v ~ s ( V ) zD(A/f” TL &(V/Cm) W,(Cm/S) E(O)(V/cm) W d (0)

(K) (cm/s) 10 6 . 4 4 ~ 1 0 - ~ 366 1.1 x lo4 9.2 X lo6 1.1 X l o4 6.6 X lo6 20 7 . 0 5 ~ 445 1.5 x lo4 8.4 x lo6 1.9 x l o4 6.5 x lo6

40 7 . 2 6 ~ 1 0 . ~ 598 2.4 x lo4 7 .3 x l o 6 3.6 x lo4 6.1 x l o 6 30 7.22x10-5 523 1.9 x 104 7,s x 106 2,s x 104 6.4 x 106

as described in the previous section. Fig. 8 shows the 1D lattice temperature distribution at the right side of the DMOS device biased at VDS = 10 V - 40 V and V& = 20 V using the analytical model and the PISCES simulation results. As shown in this figure, a good match can be observed. From this figure, the higher the VDS is, the higher the lattice temperature becomes.

Iv. DERIVATION OF THE QUASI-SATURATION CURRENT MODEL

The lattice temperature model of the DMOS device has been obtained in the previous section. In this section, the drain current model derived in the previous paper [8] will be linked to the lattice temperature model such that a closed-form model can be obtained.

For the DMOS device described in Fig. 2, the drain current at quasi-saturation is expressed as [8]

ID = n(O)qWLDvd(O) (14)

where vd(0) is the electron drift velocity considering the electric field dependent effect [16] at y = 0:

= & q 2 (15)

where E, is the critical electric field. 11, is the electron saturated velocity. Both E, and ‘U, are lattice temperature dependent as stated in the previous work [8]. The electron density and the electric field at y = 0 are:

956 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 6. JUNE 1994

N D L3

(17)

where the potential at the right end of the lateral channel has been assumed to be zero. c,i is the silicon permittivity. From (14)-(17), as shown in Table 11, the drain current and electric field and the electron saturation velocity at y = 0 for the DMOS device are also lattice temperature dependent. As shown in this table, for a higher lattice temperature at a larger VDS, the corresponding critical electric field is proportionally higher. On the other hand, the electron saturated velocity is slightly lower at a higher lattice temperature. For four VAss, the electric field at y = 0 is above the critical electric field. As a result, its drift velocity is close to the electron saturated velocity for each VDS.

Equation ( 15) is too complicated. In order to derive a closed- form formula for the drain current, an approximation formula for the lattice temperature dependent drift velocity with its references at 300 K and 600 K has been organized as shown below:

VD + ; 2 G L ;

I L . + L , + - f i : - L: -E(O) =

2 3 2Lj 1 2 L ~ L j

From (13), (14), (16), and (18), the drain current of a DMOS biased at quasi-saturation considering thermal effects has been obtained (see bottom of page). Equation (19) is the analytical model for the drain current of the DMOS device biased at quasi-saturation. Fig. 9 shows the ID versus VDS curve for the DMOS as shown in Fig. 2, biased at quasi-saturation with and without considering thermal effects, based on the analytical model and the PISCES simulation results. The thermal resistance of the drain contact is lo5 K/W. As shown in this figure, the model results show a good match with the PISCES results. The overestimation of the drain current based on the model results is due to the overestimation of the electron density at the top of the lattice (n(0)) as shown in (19). From (16), the voltage drop (Vch) in the lateral channel region [SI under the gate oxide has been neglected. As a result, n(0) (( 19)) has been overestimated. From (1 l), an overestimated I D leads to a higher lattice temperature as shown in Table 11.

V. DISCUSSION

The drain current of a DMOS device biased at quasi- saturation is dependent on the drain-to-source voltage. As discussed in the previous sections, without considering thermal effect, the higher the VDS is, the higher the drain current becomes at quasi-saturation. Considering thermal effect, the drain current at quasi-saturation is less sensitive to VDS. In fact, the thermal effect is due to the limited heat sinking capability of the contact thermal resistance. At quasi-saturation, the current level is the highest as compared to the pre-quasi- saturation operation case. As a result, at quasi-saturation, the

0 PISCES RESULTS ( NONTHERUIL ) PISCES RESULTS (THERMAL ) OUR YODEL ( NONTHERMAL ) OUR MODEL( THERMAL 1

Fig. 9. I D versus 1 % ~ curve for the DMOS as shown in Fig. 2, biased at quasi-saturation with and without considering thermal effects based on the analytical model and the PISCES simulation result.

thermal effect is the most serious. The effect of thermal resistance of the contact on the quasi-saturation is worth investigation. Fig 10(a) shows the maximum and the minimum lattice temperatures versus the thermal resistance of the drain contact for a VDS of 10 V - 40 V. Fig. 10(b) shows the drain current versus the thermal resistance of the drain contact of the DMOS device biased at quasi-saturation with VDS =10 - 40 V with and without considering the semiconductor thermal resistance (R,). For the drain contact with a high thermal resistance, the lattice temperature is high. In addition, with a high contact thermal resistance, the lattice temperature is very sensitive to VDS. For a thermal resistance of lo5 K/W at the contact, the lattice temperature can be as high as 600 K for the DMOS biased at quasi-saturation with VDS = 40 V. At such a high lattice temperature, the drain current at quasi-saturation may not be proportional to VDS any more. At a low thermal resistance such as lo3 K/W, the lattice temperature is slightly affected by VDS. As a result, the drain current at quasi-saturation is proportional to VDS as predicted before. Therefore, in order to have a DMOS device properly operable, the thermal effect needs to be suppressed-the thermal resistance of the thermal contact should be reduced. However, how good a thermal contact needs to be such that a DMOS can operate properly is important. From Fig. 10, as long as the thermal resistance of a thermal contact is smaller than lo3 K/W, the lattice temperature is only 50 K higher than room temperature in the DMOS biased at quasi-saturation for

As shown in Fig. 5, in the DMOS device, the location of the maximum lattice temperature (Tl) is at the top of the substrate and the location of the minimum one (T2) is at the drain contact. As shown in Fig. 10(a), the difference between the maximum lattice temperature and the minimum temperature varies depending on the thermal contact resis-

VDS i 40 V.

LIU et al.: AN ANALYTICAL QUASI-SATURATION MODEL CONSIDERING HEAT FLOW 951

- 30v \ I

11

’ t 61 I

10’ 10‘ IO’ ~t(Km.Wm)

(b) Fig. 10. (a) The maximum and minimum lattice temperatures versus the thermal resistance of the drain contact of the DMOS device biased at quasi-saturation with = 10 V- 40 V. (b) The drain current versus the thermal resistance of the drain contact of the DMOS device with and without considering the. semiconductor thermal resistance( Rs ) biased at quasi-saturation with V& = 10 V - 40 V.

tance (&). For a large thermal contact resistance, the lattice temperature distribution is more uniform due to the more influence of thermal contact resistance despite the fact that the overall lattice temperature is higher. On the other hand, for a smaller thermal contact resistance, the difference between the maximum temperature and the minimum temperature becomes larger due to the more importance of the lattice thermal resistance. As shown in Fig. 10(b), considering lattice thermal resistance (Rs # 0,Tl # T2) , the drain current becomes smaller, which can be explain using (19).

VI. CONCLUSION

In this paper, an analytical quasi-saturation model con- sidering heat flow for a DMOS device has been reported. As verified by the PISCES results, the analytical model considering heat flow provides a good prediction on the much worse quasi-saturation behavior due to the elevated lattice temperature as a result of the limited heat sinking capability of the thermal contact node. Based on the analysis, for a DMOS device operating with a contact thermal resistance of less than lo4 K/W, the drain current at quasi-saturation is acceptable with a lattice temperature below 350 K.

ACKNOWLEDGMENT The authors would like to thank Prof R. W. Dutton of

Stanford University for obtaining the PISCES license. The authors would also like to thank Mr. F. Shih of National Taiwan University for his help with measurements.

REFERENCES

A. Nakagawa and H. Ohashi, “A study of GTO tum-off failure mecha- nism,” IEEE Trans. Electron Devices, vol. ED-31, pp. 273-279, 1984. G. K. Wachutka, “Rigorous thermodynamic treatment of heat generation and conduction in semiconductor device modeling,” IEEE Trans. Camp.- Aided Design, vol. 9, pp. 1141-1 149, 1990. W. B. Joyce, “Thermal resistance of heat sinks with temperature- dependent conductivity,” Solid Stare Electron., vol. 18, pp. 321-322, 1975. A. Schutz, S. Selberherr, and H. W. Potzl, “Temperature distribution and power dissipation in MOSFETs,” Solid State Electron., vol. 27, no. 4, pp. 394-395, 1984. K. H. Lou, C. M. Liu, and J. B. Kuo, “Analysis of the quasi-saturation behavior considering the drain-to-source voltage and cell-spacing effects for a vertical DMOS power transistor,” Solid State Electron., Oct. 1992. K. H. Lou, C. M. Liu, and J. B. Kuo, “An analytical quasi-saturation model for vertical DMOS power transistor,” IEEE Trans. Electron Devices, Mar. 1993. C. M. Liu, K. H. Lou, and J. B. Kuo, “Two-dimensional analysis of low-temperature quasi-saturation behavior in a vertical DMOS power transistor operating at 77 K for derivation of a closed-form analytical model,” Int. Electron Devices and Materials Symp., Taipei, Nov. 1992. C. M. Liu, K. H. Lou, and J. B. Kuo, “77 K versus 300 K operation: the quasi-saturation behavior of DMOS device and its fully analytical model,” IEEE Trans. Electron Devices, Sept. 1993. I. Hirsch, E. Berman, and N. Haik, “Thermal resistance evaluation in 3-D thermal simulation of MOSFET transistors,” Solid State Electron., vol. 36, no. 1, pp. 106-108, 1993. HEXFET Databook: “Power MOSFET application and product data,” in International Rectifier, El Segundo, CA, 1985. A. A. Jaecklin and A. Marek, “Instantaneous temperature profiles inside semiconductor power devices: Part I,” IEEE Trans. Electron Devices,

V. C. Alwan, D. H. Navon, and L. I. Turgeon, “Time-dependent carrier flow in a transistor structure under nonisothermal conditions,” IEEE Trans. Electron Devices, vol. ED-24, pp. 1297-1304, 1977. M. R. Pinto, C. S. Rafferty, and R. W. Dutton, “PISCES 2: Poisson and continuity equation solver,” Tech. Rep., Stanford Univ., Sept. 1984. P. D. Maycock, ‘Thermal conductivity of silicon, germanium, 111-V compounds and II-V alloys,’’ Solid Stare Electron., vol. 10, pp. 161-168, 1967. C. J. Glassbrenner and G. A. Slack, “Thermal conductivity of silicon and germanium from 3 K to the melting point,” fhys . Rev., vol. 134. no. 4A, pp. A1058-Al069, 1964. D. M. Caughey and R. E. Thomas, “Carrier mobilities in silicon empirically related to doping and field,’’ froc. IEEE, vol. 55, pp.

vol. ED-21, pp. 50-53, 1974.

2 192-2 193. 1967.

Chung-Min Liu was bom in Kaoshiung, Taiwan, on July 15, 1969. He received the B.S. in electronic engineering from the National Chiao-Tung Univer- sity, Hsinchu. Taiwan, in 1991. Since then he has been studying for the Ph.D. in electrical engineering from the National Taiwan University. His research interests include the modeling of semiconductor power devices.

958 IEEE TRANSACTIONS ON ELEClRON DEVICES, VOL. 41. NO. 6, JUNE 1994

James B. Kuo (M'85SM'92) was born in Chang- Hwa, Taiwan, on October 16, 1956. He received the B.S.E.E. degree from the National Taiwan Univer- sity in 1977, the M.S.E.E. from the Ohio State Uni- versity, Columbus, OH, in 1978, and the Ph.D.E.E. from Stanford University, Stanford, CA, in 1985.

In 1987 he joined the National Taiwan Univer- sity's Department of Electrical Engineering, where he was promoted to Full Professor in 1990. He also founded the microelectronics lab for teaching and research in the design and analysis of VLSI devices

and circuits. His current research activities include simulation and modeling of BiCMOS devices and circuits operating at liquid nitrogen temperature and adaptive neural networks for pattem recognition applications. From 1985 to 1987, he was an Engineering Research Associate in the IC Lab at Stanford University, where he worked on BiCMOS devices. During 1980-1981, he was a Research Engineer working on CMOS single-chip FSK modem IC at Racal-Vadic Inc., in Sunnyvale, CA. During 1978-1979. he was an Electronic Engineer working on an adaptively equalized QAM modem at P e d Data Communication Corp., Rockville, MD. He has served as a technical reviewer for IEEE Transactions on Electron Devices and IEEE Transactions on Solid Srare Elecrronics. He has written over 165 published technical papers on BiCMOS devices/circuits and neural networks, including over 70 intemational joumal papers.

Dr. Kuo has served on technical committes of various conferences, in- cluding VPAD in Japan. he recently helped cooredinate the Symposium on Semiconductor Modeling and Simulation (SMS) in the Pacific Rim region. He is a member of Sigam Xi, and the Intemational Neural Network Society.

Yan-Pei Wu was born in Taiwan, ROC, in 1932. He received the B.S. degree from the National Taiwan University, the M.S. degree from the Na- tional Chiao-Tung University and the Ph.D. degree from the University of Washington, all in electrical engineering.

From 1957 to 1961, he was an Engineer with the Telecommunication Organization, Taiwan, ROC. in 1962, he joined the faculty of the Department of Electrical Engineering, National Taiwan University, where he is now Professor. His research interests

are circuit theory and power electronics. Dr. Wu is a member of the Institute of Electrical Engineers of the ROC.