656 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 62, NO. 7, JULY 2015

An Area- and Power-Efficient Iref CompensationTechnique for Voltage-Mode R− 2R DACs

Wenjuan Guo, Student Member, IEEE, Tsedeniya Abraham, Steven Chiang, Chintan Trehan,Masahiro Yoshioka, and Nan Sun, Member, IEEE

Abstract—Although segmented voltage-mode R − 2R digital-to-analog converters (DACs) have been widely used for high-precision DACs in static applications, its code-dependent referencecurrent induces a code-dependent IR drop through the referenceand ground wires, imposing a limitation on the linearity perfor-mance. To alleviate this problem, this brief proposes a simpleway to compute the reference current and compensate it via alow-resolution auxiliary DAC controlled by a computational block.A (4+12)-bit segmented voltage-mode R − 2R DAC with theproposed technique is designed and simulated in a 0.6-μm CMOSprocess. The SPICE simulation shows a six-time reduction of theintegral nonlinearity error from the code-dependent referencecurrent, greatly relaxing the requirement on the reference andground distribution paths design. Compared with the conven-tional way of adding high-quality reference and ground bufferson chip, the proposed technique is estimated to take up 1/3 areaand consume 1/5 power. With the scaling of the technology, theproposed technique becomes more competent, for 60% area comesfrom the purely digital computational block. Furthermore, formultichannel R − 2R DACs, the computational block can beshared among channels if time multiplexing is allowed.

Index Terms—Code-dependent, digital-to-analog converter(DAC), reference current, R − 2R.

I. INTRODUCTION

H IGH-RESOLUTION digital-to-analog converters(DACs) are widely used in industrial process-control

applications such as programmable logic controllers andtemperature controllers. In these applications, DAC is part ofa sensor/controller feedback system and used for controllingsuch objects as motors and cylinders based on the sensorsinputs. Therefore, dynamic performances such as spurious-freedynamic range and signal-to-noise-and-distortion ratio are notrequired, but we need high resolution and fast settling time tocontrol the objects accurately and fast [1], [2]. Additionally,small area, low power, and simple design are desirable as theyreduce the production cost.

Manuscript received October 22, 2014; revised December 16, 2014; acceptedFebruary 11, 2015. Date of publication February 24, 2015; date of currentversion June 25, 2015.This work was supported in part by the National ScienceFoundation under Grant ECCS-1254459. This brief was recommended byAssociate Editor E. Bonizzoni.

W. Guo and N. Sun are with the Department of Electrical and ComputerEngineering, The University of Texas at Austin, Austin, TX 78712 USA(e-mail: wjguo@utexas.edu; nansun@mail.utexas.edu).

T. Abraham, S. Chiang, C. Trehan, and M. Yoshioka are with Texas Instru-ments, Dallas, TX 75243 USA (e-mail: tsedeniya@ti.com; schiang@ti.com;ctrehan@ti.com; yoshioka@ti.com).

Color versions of one or more of the figures in this brief are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCSII.2015.2406351

With small device count and high resolution, the R− 2RDAC is well suited for these applications [1], [2]. It is typicallyused in one of two operation modes. The current mode exploitsthe current division along the R− 2R ladder, whereas thevoltage mode is based on the voltage division. For a current-mode R− 2R DAC, the major disadvantage is that it hasa code-dependent output impedance, making it necessary tocascade an op-amp at the R− 2R output. However, the code-dependent output impedance still induces many problems in theop-amp, such as stability and dynamic offset [3]. In contrast,the voltage-mode R− 2R has a constant output impedance,thereby avoiding all the aforementioned issues. Nevertheless,the voltage-mode R− 2R DAC has a disadvantage that itsreference impedance is code dependent. A code-dependentreference impedance induces a code-dependent current fromthe reference to the ground. To keep low cost and provide moreflexibility to customers, the reference and ground tend to beprovided off chip. Considering the wire resistances before theexternal reference and ground reach the R− 2R ladder, thereexists a code-dependent IR drop on the reference and groundlines, leading to linearity degradation. This degradation willbecome a main source of integral nonlinearity (INL) error as thetarget resolution increases. Even if there is an on-chip bandgapreference, for multichannel high-precision DACs, the referenceand ground distribution path resistances still cannot be ignored.

To alleviate the problem, the conventional way is to adda reference buffer and a ground buffer close to the R− 2Rladder so that the wire resistances before the buffers will notaffect the precision of the reference and ground. However, itis area, power, and time consuming to design two low-noise,small-offset, and small-output-impedance buffers [2], [4]. Toavoid adding buffers, this brief proposes a simple backgroundreference current compensation technique. The technique uses alow-resolution auxiliary DAC (AUXDAC) that shares the samereference and ground with the main R− 2R DAC. The input tothe AUXDAC comes from a computational block. Based on theinput to the main R− 2R DAC, it computes the current valuewe need to maintain a constant reference current. This way, weonly get a fixed gain error rather than nonlinearity. The gainerror can be easily removed by adjusting the reference value.Compared with buffers, the proposed technique is area andpower efficient and has low design complexity. With the scalingof the technology, it will become more competent, for 60% areacomes from the computational block, which is digital. In addi-tion, for multichannel R− 2R DACs, the computational blockcan be shared among channels if time multiplexing is allowed.

1549-7747 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

GUO et al.: AREA- AND POWER-EFFICIENT Iref COMPENSATION TECHNIQUE FOR VOLTAGE-MODE R− 2R DACs 657

Fig. 1. (log2(M + 1) +N)-bit segmented voltage-mode R− 2R DAC.

Fig. 2. Voltage-mode R− 2R DAC equivalent model.

Although the nonlinearity error of an R− 2R DAC canbe also compensated via conventional calibration circuits [2]or predistortion blocks [5], they are based on measuring theoutput voltage error and, thus, need a prior knowledge aboutthe reference and ground distribution path resistances, whichcannot be properly controlled. Different from them, the pro-posed technique removes the nonlinearity error via compen-sating code-dependent reference current, which is independentof the path resistances. Furthermore, compared with [3], thisbrief proposes to divide the reference current in a segmentedvoltage-mode R− 2R DAC into least significant bit (LSB),most significant bit (MSB), and interactive portions, which notonly simplifies the reference current derivation but also makesthe computational block design much easier.

This brief is organized as follows. Section II proposes a sim-ple way to derive the reference current in a segmented voltage-mode R− 2R DAC. Section III models the wire resistances onthe reference and ground lines and demonstrates their effect onthe linearity. Section IV proposes the reference current compen-sation technique and its circuit implementation for a (4+12)-bitsegmented voltage-mode R− 2R DAC. Section V shows theSPICE simulation results in a 0.6-μm CMOS process. Finally,Section VI concludes this brief.

II. Iref DERIVATION

In high-precision R− 2R DACs, segmentation is commonlyused to relax the resistor matching requirement and ensurethe monotonic operation [6]. Fig. 1 shows the circuit diagramof a (log2(M + 1) +N)-bit segmented voltage-mode R− 2RDAC. The reference voltage Vref is divided along the resistornetwork. The MSB 2R legs are controlled by the thermometer-coded MSB inputs, i.e., t1, t2, . . . , tM , to connect to Vref or theground (Gnd), whereas the LSB 2R legs are controlled by thebinary-coded LSB inputs, i.e., b1, b2, . . . , bM . An equivalentmodel of the voltage-mode R− 2R DAC is shown in Fig. 2.As aforementioned, the output impedance Rout is constant,whereas the reference impedance Rref is code dependent, lead-ing to a code-dependent reference current Iref .

Fig. 3. Equivalent model of a (log2(M + 1) +N)-bit segmented voltage-mode R− 2R DAC. (a) When all MSB inputs are set to zero. (b) When allLSB inputs are set to zero.

Although [3] has already given a complete derivation ofIref , the extension from the binary model to the segmentedmodel is quite complicated and indirect. To make it easier toderive and understand, we propose to divide Iref into threeportions, i.e., ILSB induced by LSB, IMSB induced by MSB,and IINT induced by the interaction between LSB and MSB.By superposition, we have

Iref = ILSB + IMSB + IINT. (1)

To get ILSB, we set all MSB inputs to zero, and thus, MSBis equivalent to a single resistor 2R/M connected to Gnd, asshown in Fig. 3(a). Similar to the derivation of the binary modelin [3], we can derive ILSB as

ILSB = − Vref

3R(M + 1)

[N∑

x=1

bx2−M − (M + 1)22x+1

22x+1

+

N∑x=2

x−1∑y=1

bxby2−M + (M + 1)22y

2x+y

](2)

which is the same as the binary model in [3] when M is zero.For IMSB, we set all LSB inputs to zero so that LSB is

equivalent to a single resistor R connected to Gnd. Assumingthat t1, t2, . . . , tk are high and tk+1, tk+2, . . . , tM are low, theR− 2R DAC can be modeled as shown in Fig. 3(b). Therefore,we can easily derive IMSB as

IMSB =Vref

2R(M + 1)k(M + 1− k), k =

M∑y=1

ty. (3)

If bx and ty are both high, there will be interactions betweenLSB and MSB. Through simple derivation, it can be found thatthe current injected into Vref at ty due to bx and the currentinjected into Vref at bx due to ty are equal, whose detailedexpression is

IINTx,y= IINTy,x

= − Vref

2R(M + 1)2−x. (4)

Therefore, the total IINT is

IINT = − Vref

R(M + 1)

N∑x=1

M∑y=1

bxty2−x. (5)

Based on (1)–(5), Iref in an ideal (4+12)-bit segmentedvoltage-mode R− 2R DAC is computed, as shown in Fig. 4(a).Its compositions, i.e., ILSB, IMSB, and IINT, are further shown

658 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 62, NO. 7, JULY 2015

Fig. 4. Iref in an ideal (4+12)-bit segmented voltage-mode R− 2R DAC(Vref = 2.5 V and R = 40 kΩ). (a) Iref . (b) ILSB, IMSB, and IINT.

Fig. 5. Modeling of the wire resistances on the Vref and Gnd lines. (a) Single-channel R− 2R DAC. (b) Multichannel R− 2R DACs.

in Fig. 4(b). Here, ideal means ignoring the resistor mismatchand switch impedances.

III. NONLINEARITY PROBLEM

When the code-dependent Iref multiplies with the wire resis-tances on the Vref and Gnd lines, a nonlinearity problem occursat the DAC final output. Fig. 5 models the wire resistanceson the Vref and Gnd lines in the R− 2R DAC. In the realimplementation, a star connection is commonly adopted toconnect each 2R leg to Vref and Gnd. In a single-channelR− 2R DAC, the star connection starts from the Vref andGnd pads, as shown in Fig. 5(a). Therefore, Rcom includes thebonding wire resistances and the printed circuit board metaltrace resistances from the external reference/ground to the Vref

and Gnd pads. Here, we assume that Vref and Gnd have thesame Rcom to simplify the analysis, for it does not have anyeffect on the proposed technique. Rsep are the metal traceresistances from the Vref and Gnd pads to each 2R leg, whichcan be regarded as part of the mismatch of the 2R legs. For ahigh-resolution R− 2R DAC, calibration is usually necessaryto reduce the resistor mismatch. As long as the value of R is nottoo small, it is easy to make sure that Rsep adds little burden to

Fig. 6. INL and DNL results of an ideal (4+12)-bit segmented voltage-modeR− 2R DAC with (a) Rcom = 1Ω and (b) Rcom = 10 Ω (Vref = 2.5 V andR = 40 kΩ).

the existing calibration scheme. Therefore, our main problemfalls on Rcom. For multichannel R− 2R DACs sharing thesame Vref and Gnd pads, there are two-level Rcom, as shownin Fig. 5(b). The first-level Rcom1 is the same as the single-channel R− 2R DAC, and the second-level Rcom2 are themetal trace resistances from the Vref and Gnd pads to eachchannel Vref and Gnd pins. Both of them contribute to the code-dependent IR drop of Vref and Gnd, leading to a more seriousnonlinearity problem. Note that, even if there is an on-chipbandgap reference, multichannel R− 2R DACs still have thesecond-level Rcom2 from the bandgap reference to each channelR− 2R DAC Vref and Gnd pins.

Since Rcom is much smaller than R, the value of Iref isdetermined by R. Therefore, when R is fixed, INL and differ-ential nonlinearity (DNL) errors induced by the IR drop onthe Vref and Gnd lines are proportional to the value of Rcom.Fig. 6 shows the INL and DNL results of an ideal (4+12)-bit segmented voltage-mode R− 2R DAC with Rcom = 1 Ωand Rcom = 10 Ω, respectively. As can be seen, even 1-Ω wireresistance already gives an error of 1.7 LSB INL and 0.4 LSBDNL. When Rcom increases to 10 Ω, INL and DNL become tentimes worse. Therefore, it is necessary to develop an effectivesolution to address this issue.

IV. PROPOSED REFERENCE CURRENT COMPENSATION

TECHNIQUE

Different from the conventional way of adding Vref and Gndbuffers to reduce the effect of Rcom, a simple background ref-erence current compensation technique is proposed, as shownin Fig. 7. We use an AUXDAC to share the same Vref and Gndwith the main R− 2R DAC. The AUXDAC is controlled by acomputational block, which realizes a transfer function as

Iaux = Iconst − Iref (6)

where Iconst is the constant current through Rcom, and Iauxis the output as digital codes to control the AUXDAC. Toensure Iaux ≥ 0 and the smallest gain error, the best option forIconst is the maximum value of Iref . As long as the currentthrough Rcom is constant, we avoid the nonlinearity problem.This technique also applies to multichannel R− 2R DACs.Although multichannel R− 2R DACs have two-level Rcom, asshown in Fig. 5(b), if each channel R− 2R DAC has a constantIref , the current through Rcom of both levels will be code inde-pendent. Taking a (4+12)-bit segmented voltage-mode R− 2R

GUO et al.: AREA- AND POWER-EFFICIENT Iref COMPENSATION TECHNIQUE FOR VOLTAGE-MODE R− 2R DACs 659

Fig. 7. Proposed reference current compensation technique.

Fig. 8. Proposed architecture of the AUXDAC.

DAC as an example, the detailed circuit implementations ofthe AUXDAC and the computational block are discussed in thefollowing subsections.

A. AUXDAC

Fig. 8 shows the architecture of the AUXDAC. To avoid dif-ferent process–voltage–temperature variations, the AUXDACuses the same unit resistor as the main R− 2R DAC. di are thedigital control signals from the computational block. As shownin Fig. 4(a), the (4+12)-bit segmented voltage-mode R− 2RDAC has a Iref varying from 0 to 210 μA. To make the sizeof the AUXDAC reasonable, we use 16R in series for the lastbit, giving an LSB step of 4 μA. With this LSB step, a 6-bitAUXDAC is enough to cover the range of 210 μA. Since 6 bitis much more relaxed than the resistor mismatch requirementfor the main 16-bit R− 2R DAC, the mismatch between theAUXDAC and the main R− 2R DAC can be ignored.

B. Computational Block

To implement the computational block, it is important todecide the bit numbers of its input and output. The output bitnumber is decided by the resolution of the AUXDAC, which is6 bit. As derived in Section II, Iref contribution is not subjectto the rule of scaling down by 2 from MSB to LSB. Throwingaway any bit causes a big error in estimating Iref . Fig. 9 showsthe comparison of the calculated Iref when the input bit numberis reduced from 16 to 15. As can be seen, the estimation error ofIref reaches 21 μA after 1-bit reduction. As a result, the input bitnumber must be 16. Then, the straightforward implementation

Fig. 9. Comparison of the calculated Iref when the input bit number of thedigital block is reduced from 16 to 15.

TABLE IGATE COUNT OF THE COMPUTATIONAL BLOCK

of the computational block is to build a mapping table fromthe 16-bit input to the 6-bit output based on (6) and apply theQuine–McCluskey (QM) simplification method [7]. However,the QM method tries to explore all the input combinationsto find a minimized Boolean function, giving a result whosecomplexity exponentially increases with the input bit number.After synthesis, the gate count of the digital block is 127 470,which is too huge to integrate it with the R− 2R DAC.

Since the QM method is not effective for a 16-bit input,the alternative way is to implement the Iref model. Comparedwith the model in [3], the proposed model, including (1)–(5),not only simplifies the derivation but also makes the computa-tional block design much easier. With ILSB, IMSB, and IINT

implemented separately, the gate count of the computationalblock is reduced to 656 gates, which is a 194-time reductionfrom directly applying the QM method on the 16-bit input. Thesynthesis results are summarized in Table I.

V. SIMULATION RESULTS

With the proposed technique, a (4+12)-bit segmentedvoltage-mode R− 2R DAC is designed and simulated in a0.6-μm CMOS process. Thin-film resistors are used, and dy-namic element matching (DEM) is applied to the 4-bit MSB tomake sure that INL and DNL induced by random mismatch arewithin 0.5 LSB. Fig. 10 shows the SPICE simulation results ofIref , Iaux, and Iconst. As can be seen, the variation of Iconstis 16 μA rather than the resolution of the AUXDAC (4 μA).It is due to the switch impedances. To make sure the switchimpedances do not affect the transfer function of the R− 2Rladder, the switch impedances need to be scaled up with astep of 2 from the MSB to the LSB. Therefore, the switchimpedances become comparable with the value of R in the lastseveral bits, making an impact on Iref . Since Iaux is calculatedbased on the Iref model, if the Iref model is not precise, Iconstwill see more variations.

660 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 62, NO. 7, JULY 2015

Fig. 10. SPICE simulation results of Iref , Iaux, and Iconst in a (4+12)-bitsegmented voltage-mode R− 2R DAC.

Fig. 11. SPICE simulation results of after-compensation INL and DNL in a(4+12)-bit segmented voltage-mode R− 2R DAC with (a) Rcom = 1 Ω and(b) Rcom = 10 Ω (Vref = 2.5 V and R = 40 kΩ).

Fig. 11(a) shows the SPICE simulation results of after-compensation INL and DNL with Rcom = 1 Ω. Compared withFig. 6(a), INL is reduced by six times from 1.7 to 0.27 LSB.Note that the essence behind the six-time INL reduction is thatthe code-dependent current is compensated, which is not relatedto the value of Rcom when Rcom � R and does not affect theaccuracy of the Iref model. This point is also verified by com-paring Figs. 6(b) and 11(b). With Rcom = 10 Ω, INL decreasesfrom 16.6 to 2.6 LSB, which is also a six-time reduction.

To further validate the proposed technique’s effectiveness,a 3σ resistor mismatch and temperature drift are added inthe simulation, whose results are shown in Fig. 12. Since weapply DEM on the 4-bit MSB, it is very time consuming torun transient analysis for all 16-bit input codes. To reducesimulation time, only INL and DNL at 8-bit MSB codes aresimulated, which still makes sense for process variations mainlyaffecting MSB precision. As shown in Fig. 12, before currentcompensation, INL is 1.6 LSB dominated by Rcom = 1 Ω.After current compensation, INL is 0.4 LSB dominated byresistor mismatch. At 125◦C, the proposed technique still workswell with INL = 0.43 LSB.

The current compensation technique is estimated to take up0.08 mm2 and consume 0.06-mA average current. A Vref bufferand a Gnd buffer good enough for a 16-bit DAC are estimatedto have a 0.24-mm2 area with a 0.3-mA quiescent current in thesame process. Therefore, the proposed technique is estimatedto take up 1/3 area and consume 1/5 power of the Vref andGnd buffers. Furthermore, 60% area comes from the purelydigital computational block, which scales with the technology.For multichannel R− 2R DACs, the computational block canbe also shared among channels if time multiplexing is allowed.

Fig. 12. SPICE simulation results of INL and DNL in a (4+12)-bit segmentedvoltage-mode R− 2R DAC with 3σ resistor mismatch with Rcom = 1 Ω(Vref = 2.5 V and R = 40 kΩ). (a) Before current compensation at 27 ◦C.(b) After current compensation at 27◦C. (c) After current compensationat 125 ◦C.

VI. CONCLUSION

This brief has investigated the effect of the code-dependentreference current on the linearity of the voltage-mode R− 2RDAC. An area- and power-efficient background reference cur-rent compensation technique is proposed to resolve the issue,which consists of a low-resolution AUXDAC and a purely dig-ital computational block. Through dividing Iref in a segmentedvoltage-mode R− 2R DAC to IMSB, ILSB, and IINT, thisbrief not only simplifies the Iref derivation but also efficientlyimplements the computational block. The simulation results ofa (4+12)-bit segmented voltage-mode R− 2R DAC verify theproposed technique with six-time INL reduction. Comparedwith the Vref and Gnd buffers, the proposed technique is es-timated to take up 1/3 area and consume 1/5 power. Due to itssimplicity, the proposed technique can be easily redesigned indifferent processes. With 60% area coming from purely digitalcomputational block, it will also become more competent withtechnology scaling and multichannel DACs.

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