An ASIC Design methodology An ASIC Design methodology with Predictably Low Leakage, with Predictably Low Leakage,

using Leakage-immune Standard using Leakage-immune Standard CellsCells

Nikhil Jayakumar, Sunil P KhatriNikhil Jayakumar, Sunil P Khatri

ISLPED’03ISLPED’03

outlineoutline

IntroductionIntroduction Research about leakage power reductionResearch about leakage power reduction State assignment and leakage powerState assignment and leakage power Approach and design methodologyApproach and design methodology ResultResult ConclusionConclusion

IntroductionIntroduction

Importance of leakage currents controlImportance of leakage currents control Leakage current ILeakage current Idsds::

Voltage scaling and Voltage scaling and

threshold voltage scalingthreshold voltage scaling

)1()()(

0t

ds

t

offVTVgsV

v

V

nvds eeI

L

WI

DS

G

B

Leakage reductionLeakage reduction

Source biasingSource biasing Using body effect case VUsing body effect case Vtt ↑↑ but performance but performance ↓ ↓ Stack effectStack effect

Direct VDirect Vtt manipulation manipulation Dual VDual Vtt partition partition MTCMOSMTCMOS VTCMOSVTCMOS

Leakage reductionLeakage reduction

Source biasingSource biasing Using body effect case VUsing body effect case Vtt ↓↓buperformancebuperformance↑↑ Stack effectStack effect

Direct VDirect Vtt manipulation manipulation Dual VDual Vtt partition partition MTCMOSMTCMOS VTCMOSVTCMOS

State & voltage assignmentState & voltage assignment (DAC (DAC 03)03)

State dependence of a leakage currentState dependence of a leakage current

Find the best input vector for standby stateFind the best input vector for standby state

accuratly estimate Leakage of designsaccuratly estimate Leakage of designs

State & voltage assignmentState & voltage assignment (DAC (DAC 03)03)

State dependence of a leakage currentState dependence of a leakage current

State & voltage assignmentState & voltage assignment (DAC (DAC 03)03)

Without any state assignmentWithout any state assignment

0.31ns

0.36ns

9.6nA 4.7nA

State & voltage assignmentState & voltage assignment (DAC (DAC 03)03)

Optimal input state with Vt assignmentOptimal input state with Vt assignment

0.31ns

0.31ns

9.6nA 0.99nA

MTCMOS & state assignmentMTCMOS & state assignment

MTCMOS better than traditional standard MTCMOS better than traditional standard cells designcells design

Not support predictable leakage currentsNot support predictable leakage currents Two variants of standard cellTwo variants of standard cell

H variant for output “high”H variant for output “high” L variant for output “low”L variant for output “low”

MTCMOS & state assignmentMTCMOS & state assignment

L variant of 3-NAND

H variant of 3-NAND

Layout floorplan of HL gatesLayout floorplan of HL gates

Regular standard-cell

L variant of a standard-cell

H variant of a standard-cell

Design flowDesign flow

Traditional mapping using regular standard cells

Determine a set of primary input assignment

Simulate to find output of each gate

Replace each gate by its output value

Standard cell

library

ModifiedStandard

cell library

Place and route

Experimental resultsExperimental results

HL cell versus MT cell

Experimental resultsExperimental resultsHL/MT cells versus regular cells

Leakage/area/delay comparisonLeakage/area/delay comparison

Precisely estimate leakagePrecisely estimate leakage

Leakage/area/delay comparisonLeakage/area/delay comparison

Using exact timing analysis by run “sense” Using exact timing analysis by run “sense” in SISin SIS

HL 10% MT 12.5% delay overheadHL 10% MT 12.5% delay overhead

Leakage/area/delay comparisonLeakage/area/delay comparison

Using SE to P&RUsing SE to P&R

HL 11-21% overhead but 17% less than HL 11-21% overhead but 17% less than MTCMOSMTCMOS

ConclusionsConclusions

Low and predictable leakage valueLow and predictable leakage value

Better algo. To determine the best primary Better algo. To determine the best primary input vectorinput vector

Improve overheadImprove overhead