__An Automatic Testbench Generation Tool for a SystemC Functional Verification Methodology

8/13/2019 __An Automatic Testbench Generation Tool for a SystemC Functional Verification Methodology

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An Automatic Testbench Generation Tool for a SystemCFunctional Verification Methodology

Karina R. G. da SilvaUniversidade Federal de

Campina GrandeAprigio Veloso Avenue, 882,

BodocongoCampina Grande - PB

Brasil

KarinarochaQdee .ufcg.edu.br

Elmar U. K. MelcherUniversidade Federal de

Aprigio Veloso Avenue, 882,

Guido AraujoUniversidade Estadual de

Albert Einstein Avenue, 1251Campina Grande Campinas

Bodocongo Carnpinas - SPCampina Grande - PB Brasil

Brasil guidoQic.unicamp.hrelmarQdsc. ufcg.edu.br

ABSTRACT sian verification. Although they have some useful hardwareTh e advent of new 90nm/130nm VLSI technology and SoCdesign methodologies, has brought an explosive growth in

the complexity of modern electronic circuits. As a result,functional verification has become the major bottleneck inany design flow. New methods are required that allow foreasier, quicker an d more reus able verification. In this pa-per we propose an automatic verification methodology a pproach that enables fast, transaction-level, coverage-driven,self-checking and random-constra int functional verification.Our ap proach uses the SystemC Verification Library (SCV ),to synthesize a tool capable of automatically generating test-bench templates. A case study from a real MP3 design isused t o show the effectiveness of our approac h.

Categories and Subject Descr ip to r s : B.7.3 [IntegratedCircuits]: Reliability and Testing

G e n e r a l Terms: Verification.Keywords:SystemC, SCV, VeriSC, Brazilip, tool.

1. INTRODUCTIONThe most difficult challenge in the design of any system is

to make sur e tha t t he final implementation is free of imple-menta tion flaws [Z]. Th e goal of functional verification is toverify all functionalities of the design and to assure that itbehaves according to th e specification. To do this, one mustcreate the design environment, by means of a testbench,that is capable of generating input data, while monitoringthe design out put against t he ou tpu t of a given referencemodel. Verification can consume over 70 of th e overalldesign effort [l] and th us, tools th at can quickly create ef-ficient testbenchs are in great demand.

Some well established ha rdwa re description languages, likeVHDL and VERILOG, are sometimes also used to do de-

Permission to make digital or hard copies of all or part of this work forpersonal or dassrwm use is granted without fee provided h a t copies arenot made or distributed for profit or commercial advantage and that copiesbear this notice and the full citation on he first page. To opy otherwise, orepublish, IO posl on scwers or to redistribute to lists, requires prior specificpermission and/or a fee.SBCCI M, September 7-1 I, 2oM, Pemambuco, Brazil.Copyfight 2004 ACM 1-58113-947-0/C4/~9 .. 5.00.

- -programming constructs, they lack major functional veri-fication capabilities like constraine d randomization, func-tional coverage and transa ction recording. On the otherhand, programming languages like C, C++: and Java, al-low high-level abstraction constructs, but do not have themechanisms to account for parallelism and timing which arerequired for hardware description. In order to close thisgap, some specialized verification languages have been cre-ated like Verisity, OpenVe ra a nd the SysteniC Verification~Library (SCV).

Historicallv. several methodoloaies have been used for func-tional verification[7][8], but theylack generality and ease ofuse. There are currently (circa April 2004) no tools thatare complete and generic enough to solve this problem [ l ]For this reason, a lot of effo rt has been conce ntrated on theresearch of th is problem.

The methodology proposed in this paper creates a Sys-temC based object oriented environment to perform veri-

fication. Many reuse methodologies are based on object-orientation[6]. In [4] th e auth ors describe an approach th atuses constraint solving to generate input vectors through afinite stat e machine. T he machine produces all possible in-puts to a specific Device Under Verification ( DUV ). In [5] heauthor s propose a methodology and a tool to do transaction-based functional coverage. Most tools cover some aspect ofverification or are specific to some kind of DUV.

In this paper we propose a new methodology, that aut-matically creates a DUV-specific templa te testbench. Th emethodology intends to be generic and covers all kinds ofsync hrono us DUV. Our methodology is implemented inVeriSC, a tool that performs automatic testbench genera-tion. VeriSC uses SystemC and th e Syst emC Verification Li-brary(SCV) to create a random-constra int, coverage-driven,self-checking and transaction-b ased testbench temp late. A

case study from a real MP3 design is used to show the ef-fectiveness of our approach.

Th e remainder of th is paper is organized as follows. Insection 2 we explain the proposed methodology. Section3 describes the implementation from VeriSC. In section 4we show a functional verification application example (M P3design), followed by the conclusion in 5 .


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2. THE METHODOLOGYAn important problem in design verification is the need

to adapt the testbenc h to the DU V. With our methodology,the verification engineer can use the testbench generationtool to make such adaptation. Other inte resting aspect ofthi s methodology is that the Reference Model (RM) can bewritten in virtually a ny high-level language, making it sim-ple and easier to maintain. However, the method proposedcan not be applied to reference models written in a non-executable description (e.g. natu ral language).

Our methodology proposes to create a testbench com-posed of source, drive r, monitor, reference model and checkermodules as shown in Figurel. Input dat a is fed into theDUV and the RM, and the outputs of both are collectedto see if they are equivalent. The purpose of each moduleinside the functional verification methodology is explainednext subsections.

We have been created a tool that automatize the test-bench implementation. This tool follows th e methodologyshowed in this section.

2.1 VeriSCVeriSC implements the methodology proposed and aut*

matically crea tes a template testbenc h according to t he par-ticular characteristics of the DUV. It creates all testbenchmodules: source, driver, monitor, reference model, checkerand all FIFOs th at connect these modules. Th e tool is alsoresponsible for connecting the specific DUV. The templateis created automatically by analyzing the DUV input andoutput ports and the SystemC descriptions of the transac-tion level structures. The transaction level structu res mustcontain all information about the semantics of the relevantdata that are communicating with the DUV.

VeriSC offers enhanced productivity to verification engi-neers by reducing the design time spent in creating test-benches. Th e resulting testbench templates are compact,easy to under stand and g uaranteed t o compile and simulate

without run time errors or hang ups. The next subsectiondescribes VeriSC implementation details.

2.2 Automatic Template GenerationTh e VeriSC tool generates all templates of the testbench's

modules according to th e DUV. Signal handshake, func-tional coverage metrics and input value distributions mustbe implemented by the verification engineer.

For the sake of clarity a simple adder will be used as an

I/ interface in inputS t N d add-input

int a;int b:

);inline ostreama operator < (ostreamL os, wn st add-input& arg)(

os


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void POwhile 1)inputgtr = input_stimule.read();output j t r = new add_output();o u t p u t j l r - > s = inputgtr->a + inputgtr->b;

delete i n p u t g f r ;tp t_answerwnte(o lp l j l~) ;

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SC_MODULE(adderKsc_in ci nP inp utLa, input-b:SC_OU~ cints outpulLs:void add(X

'SC_CTOR(adder)(

outputLs= InputLa + input-b;

SC-METHOD(add);sensitive


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D e c o d i n g and :M P 3 I npu t : CRC Requantization :

St r e am

Figure 6: MP3 blocks schema

Furthermore, SCV permits transaction level programming,a methodology that enables a high-level abstraction, reuti-

lization and simulation speedup.It is well known that providing the design with random-

ized input data is a very good technique to test the func-tionality of the design [ l ] This comes from the fact thateven the rare input cases can be simulated with constrainedrandomization, leading to a verification coverage that is dif-ficult to obta in by using directly specified inputs. Moreover,in order to verify all sta tes of th e design it is required thatevery important functiouality has been tested durin g sim-ulation. To do this, a functional coverage mechanism isprovided that monitors the progress of the verif icat ion p r ~cess. Wi th func tional coverage monitoring one knows, atany moment, which percentage of a specified full coveragehas already been achieved.

4 APPLICATION EXAMPLEOur test case D U V is an MP3 decoder implementation,

which is part of the BrazilIP project[9]. Th e entire MP3decoder project was verified using VeriSC, see Figure 6 . Wehave choosen the window function to show the testhenchproduced by VeriSC.

The window function is responsible for generating audioda ta PCM) from subban d samples. Th e reference modelused is from the Lihmad library th at follows th e I S 0 stan-dard and is open source code with GPL licence.

The next subsection describes the MP3 functional verifi-cation steps and points out the most relevant design errorsfound by the testbench.

4.1 Verification of Window moduleThe Window function's environment has only two inter-

faces, an input and an outp ut interface. The source usesfloating point to provide random input d at a to t he module.Input da ta was generated as sets of data pairs with a preci-sion of up to the 9th decimal digit. Random input was cre-ated by using the SCV library's class SCV-CONSTRAINT,with S C V B A G .Handshake t o do th e interfaces driver-DUVand DUV-monitor was also implemented.

To make the comparison between the Reference Modelresults and DUV results at the Checker Module, the Root

Mean Square method (RMS), was used:

where n is th e samples number, x is the reference samplesand y is th e resulting samples of our module decodification.A function in the Checker was created t ha t permits t he com-parison between the module outputs . According IS 0 stan-

dards, the RMS must not be higher than g nrthermoreIxk ~ yk it must not be higher than Z - 1 4 . Through thisfunction we could verify if the window outputs were withinspecifications.

4.2 ResultsTh e verification found three majo r design errors tha t were

not found during the preliminary simulation which did not

use th e proposed methodology. Th e list of relevant mistak esis shown below:

1 In the Finite Sta te Machine (FSM): he reset sta te wasnot reinitializing th e nt[2][512] vector t o zero.

2 The first 15 output blocks caused errors when th e resetsignal is raised;

3 Th e module decoded correctly only stereophonic data,but was not capable t o decode monophonic da ta cor-rectly.

Notice that subtle design errors, like error 3 above, couldhardly be captured if only simulation or standard verifica-tion procedures were used.

By using the VeriSC tool th e three designers of the MP 3could considerably speedup the verification of the MP3 de-sign, cutting in half the design time. All errors have beencorrected. Verification was repeated a nd it could not findany more mistakes.

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5. CONCLUSIONVerification engineers must employ tools that allow them

t o do easier, quicker and more reliable functional verifica-tion.

In this paper, we propose a new methodology that allowstransaction-leve l, coverage-driven, self-checking and random-constr aint functional verification. We have shown a tool,based on SystemC and SCV, th at implements this method-ology. Furthe rmore we presented the verification of an M P3module and showed that, by using the VeriSC tool, the de-signers could capture very hard design errors, considerablyreducing the design time.

6. ADDITIONAL AUTHORSAdditional au thors:Valdiney Alves Pime nta ( Universidade

Estadual d e Campinas. Albert Einstein Avenue, 125. Camp-inas - SP, Brasil. Email: ra005055Qic.unicamp.br).

7. REFERENCES[1] BERGERON, J., Functional Verification o HDL

models, Kluwer Academic Publishe rs, Second

Edition, 2002.

System-on-a-chip Verification: Methodology 4Techniques, Kluwer Academic Publishe rs,February, 2001.

21 Rashinkar, P., Paterson, P., Singh, L.,

[3] Bhasker, J., A SystemC Primer, Star Galaxy

[4] FERRAN DI, F., RENDINI, M., SCIUTO, D.,Publishing, 2002.

Functional Verification f o r SystemC Descriptionsusing Constrai nt solving, Automa tion and Test inEurope Conference and Exhibition (DATEOZ),p.0704, Paris, March,2002.

[ ] REGIMBAL, S., LEMIRE, J.-F., SAVARIA, Y .BOIS, G., ABOULHAMID, M., BARON, A.,Automating Functional Covemge Analysis BasedOn An Executable Specification, Proc. of theInternational Workshop on System-on-Chip forReal-Time Applications, Calgary, June,2003.

[6] DRUCKER,L., SystemC Verification Libmryspeeds transaction-base d verification, D RIndustry Articles,EEdesign, EEtimes,Fehruary,2003.

[7] FOUR NIER , L., ARBETM AN, y., LEVINGER,M., Functio nal Verification Methodology forMicroprocessors Using the Genesys Test-ProgramGenemtor,Design, Automation and Test in Europe(DATE '99), p.434, Munich, March 09, 1999.

Functional Verification Methodology for PowerPC6 4 Microprocessor,33rd Design Auto mationConference, DAC 96, Las Vegas.

[ ] MONACO, J., HOLLOWAY, D., RAINA, R.,

[9] http://www.brazilip.org

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http://www.brazilip.org/http://www.brazilip.org/

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__An Automatic Testbench Generation Tool for a SystemC Functional Verification Methodology