An Inherently Linear Phase-Oversampling

Vector Modulator in 90-nm CMOS Richard Tseng

1, Hao Li

1,2, Dae Hyun Kwon

1, Ada S. Y. Poon

3, and Yun Chiu

1

1University of Illinois at Urbana-Champaign, 1308 W. Main St., Urbana, IL 61801 USA 2University of Science and Technology of China, Hefei, Anhui, China

3Stanford University, 350 Serra Mall, Stanford, CA 94305 USA

Abstract—A four-antenna vector modulator (VM) beamforming receiver in 90-nm CMOS operating between 2.4 and 4.9 GHz is presented. The VM is based on a phase-oversampling technique that allows the synthesis of inherently linear, high-resolution complex gains without complex variable gain amplifiers. It achieves 360°°°° phase shift programmability with 8-bit digital control, a measured < 4.2°°°° phase error at a back-off of 4 dB from the maximum gain setting, and a complex gain constellation with a mean error vector magnitude of < 2%. The monolithic beamformer also demonstrates an interference cancellation of > 24 dB for interferers impinging from different directions.

I. INTRODUCTION

Beamforming for power gain or interference cancellation in multi-antenna wireless systems enables the exploitation of spatial diversity and increased receiver dynamic range. Beamforming in the analog domain can be performed with vector modulators (VMs), and has been explored using complex RF variable gain amplifiers (RFVGAs) in Cartesian-combining architectures [1–4]. As supply voltages decrease due to CMOS scaling, a trend has emerged in which analog circuit-block complexity is gradually being transferred to the digital backend and/or to the architectural level. Phase oversampling and coarse quantization is one technique that allows the circuit complexity of RFVGAs to be shifted to the architectural level, thus linearizing the receive paths at no loss of complex gain accuracy.

In this paper, a CMOS beamforming IC fabricated in 90-nm CMOS based on phase oversampling and coarse quantization is demonstrated. The chip contains four down-conversion paths, all supplied from 1.2 V. The VM architecture utilizes no

RFVGAs and achieves a measured < 4.2° phase error at a back-off of 4 dB from the maximum gain, and a complex gain error vector magnitude (EVM) of 2% over all complex gain points. In an active interference cancellation test, the chip achieves > 24-dB cancellation of interferers, potentially relaxing the dynamic range requirements of subsequent baseband blocks.

II. VECTOR MODULATOR ARCHITECTURE

The presence of large blockers close to the received signal poses numerous challenges for beamformer designs. The use of nonlinear amplifying components after the low noise amplifier in the receive path may allow the blockers to desensitize the receiver or to corrupt a weak desired signal with inter-modulation products. If used in an interference cancellation application, the resolution of the VM complex gain should be proportional to the desired cancellation accuracy. For example, to cancel a large interferer with random arrival angle by 20 dB, gain control must be within approximately 10%, and phase

resolution must be within 5.7°. This degree of resolution is not needed when the receive paths are utilized mainly for power

gain or diversity. Thus to achieve accurate cancellation of large interferers in the analog domain, it is advantageous to have high complex gain resolution as well as high linearity.

A diagram of the implemented direct-conversion phase-oversampling VM architecture is shown in Fig. 1. Each VM consists of a transconductance (Gm) amplifier, a bank of 8 mixers, a bank of cross-coupled NMOS switches, and a set of I-channel and Q-channel transimpedance amplifiers (TIAs). Each mixer is driven by a separate LO phase, and phase-shifts the incoming signal during frequency translation. A complex gain is realized by choosing the correct sign bm for the output of each mixer and then summing across all mixers with the TIAs. The bm terms can be chosen through a brute force search or a

Σ∆ algorithm running in the digital domain [5]. In contrast to employing fine resolution RFVGAs in the signal paths, the exploitation of multiphase LO to establish the complex gain decouples the circuit complexity from the signal integrity of the receive paths. In addition, the use of passive mixers for phase shifting avoids any nonlinear amplification in the receive path, further enhancing the linearity of the receiver.

III. CIRCUIT IMPLEMENTATION

The circuit schematic of a single down-conversion path of the VM, highlighted in Fig. 1, is shown in Fig. 2. In each path, the received signal is converted to current through a resistively degenerated cascode Gm amplifier. The current is then split evenly between the passive mixers due to the uniform spacing

of the LO phases between 0° and 180°, and then split again between the I and Q TIAs at the outputs of the mixers. A spiral inductor is used at the Gm amplifier output to tune out the parasitic capacitances of the amplifier and the mixer bank. The Gm amplifier input is resistively matched to 50 Ω for simplicity.

A double-balanced passive mixer topology was chosen for

u1

u3

u4

VM

u2

TIA0˚

22.5˚

45˚

67.5˚

b0=±1

b2=±1

b3=±1 TIA

b4=±1

b5=±1

b6=±1

b7=±1

DigitalAlgorithm u

I

QLO Gen.

0˚22.5˚45˚67.5˚90˚112.5˚135˚157.5˚

b1=±1

Inset see Fig. 2

Fig. 1. Beamforming receiver with phase oversampling VMs.

the mixers due to its high achievable linearity. The high IIP2 of passive mixers is important for direct-conversion architectures such as this one. The lack of static power consumption in passive mixers is also notable, given the large number of mixers in the phase-oversampling architecture. Unfortunately, passive mixer topologies also suffer from isolation problems because the input and output of a passive mixer are shorted together for a portion of each LO cycle. In order to properly isolate the summing nodes of the two TIAs, resistors are placed at the outputs of the mixers. The isolation resistors increase the voltage swing at the mixer output nodes, potentially increasing the noise figure of the down-conversion path and possibly limiting the achievable linearity. Extra design care was taken to balance between these conflicting constraints in this prototype.

Signal combining between the different down-conversion paths is performed at baseband to keep each path simple and to minimize any potential coupling between them. To accomplish this, the I and Q TIAs, which also set the bias points for the passive mixers, sum together the outputs from all the mixers in the VM down-conversion paths. It is advantageous for the

sources and drains of the choppers in the passive mixers to be biased close to the ground to minimize the on-resistance. To accommodate this, PMOS differential inputs are used in the TIAs. The input differential pairs are biased with low overdrive voltages and resistive loads are also used in the first stage of the amplifier for a low flicker noise corner, which is found close to 100 kHz in simulation.

A block diagram of the multiphase LO generation circuit is shown in Fig. 3. A pseudo-differential delay-locked loop (DLL), shown in the inset of Fig. 3, splits a reference signal into 8 equally spaced phases. The 8 DLL outputs are buffered and sent into a resistive interpolation network, which averages out the phase errors from the DLL and outputs 16 phases. A two-level resistive interpolation is adapted from folding-and- interpolating ADCs for phase interpolation. The inputs to the interpolator are used to derive extra phases, and the original phases are then discarded, minimizing the amplitude-oriented phase errors between the LO signals [6]. The DLL and the interpolation network run at fLO/2 to maintain high phase accuracy and to save power. The interpolator outputs are edge-combined to produce 8 phases at fLO before being distributed to the mixer bank. All LO signals swing rail-to-rail to minimize the impact of transistor mismatch on LO phase accuracy and to decouple DLL cell delay from the magnitude of its output swing. A dynamic logic phase detector, adapted from [7], is used in the DLL to enable high speed operation and to avoid systematic phase offsets commonly associated with high-frequency bang-bang phase detectors.

RX1

DLLLOOu

t B

uf

1.6mm

1.2

mm

RX2

RX3 RX4

TIA

TIA

Ou

t B

uf Buf

Fig. 4. Chip micrograph (90-nm CMOS, core area 1.92 mm2).

IV. MEASUREMENT RESULTS

A test chip was implemented in a 1P8M 90-nm RF CMOS process, and the die photo is shown in Fig. 4. All pads are ESD protected, and all supply voltages are 1.2 V. This section summarizes the experimental results of the prototype.

A. IQ Imbalance

Figs. 5a and 5b show the measured IQ imbalance over gain and phase settings for one of the four down-converting VM channels. While the complex gain u scales proportionally to the gain setting, the gain mismatch and LO phase non-uniformity in the individual mixers are relatively constant, resulting in large IQ imbalance at a low gain setting (e.g., Au = 2.4 dB in Fig. 5). In contrast, the same mismatch affects the IQ balance much less significantly when the gain is large (e.g., Au = 15 dB in Fig. 5). IQ imbalance can degrade a receiver’s image rejection ratio (IRR), and the measured results of this prototype are shown in Fig. 5c. While receiver architectures such as Low-

LO+

BI+

BI-

BI+LO-

To I-TIA

To Q-Side Switch & TIA

LO-

VCMC

Vo+ Vo

-

Vi+ Vi

-

Vi-Vi

+

RF InputVoI

+

VoI-

Vo- Vo

+

Fig. 2. Single receive path (highlighted in Fig. 1 as well).

8 Phases at fLO/2

8 Phasesat fLO

16 Phasesat fLO/2

To PD, LO Buffers, etc

From PreviousCell

To Next Cell

0° 22.5° 45° 67.5° 180°

PD CP

0°+

180°-

Up

Down

ResetPD Delay

Cell

DLL Interpolator EdgeCombiner

LOBuffers

Fig. 3. LO generation circuit.

IF and Weaver require high IRR for sufficient image rejection, an IRR of 20 dB is typically acceptable for direct-conversion receivers because the image is itself the signal mirrored. In this prototype, a > 20-dB IRR is achieved except for the lowest gain setting shown in Fig. 5, which is still useful in interference cancellation scenarios since a large interferer needs to be simply removed instead of demodulated.

B. Complex Gain Performance

The measured complex gain constellation of one VM channel is shown in Fig. 6. Measured and ideal data points are shown as filled and empty circles, respectively. Effects of IQ imbalance are averaged out to avoid any potential misinterpretation of the gain accuracy. Most of the complex gain errors are caused by the static offsets in the LO phases (the

standard deviation of the LO phase offset was deduced to be

approximately 2.8° based on the measured IQ mismatch and complex gain errors). The high resolution of the constellation

results in a worst-case measured phase error of < 4.2° in gain setting, which includes both random and systematic errors (due to phase quantization), at a back-off of 4 dB from the maximum gain setting.

We define a metric for the complex gain accuracy, the EVM of the gain constellation, analogous to the EVM of the signal constellation used in communications:

2

2

| |EVM ,

| |

u u

u

− ′=∑∑

(1)

where u is the ideal complex gain, and u′ is the measured one. For the measured complex gain shown in Fig. 6, the overall EVM of the constellation is 2%, showing good adherence to the ideal constellation.

To further elaborate on the accuracy of the complex gain

and phase, u and u′ are decomposed into the amplitudes (Au)

and phases (θu):

( )

,

( ,)

u

u u

j

u

j

u u

u A e

u A A e

θ

θ θ+∆

=

′ = + ∆

(2)

where ∆Au and ∆θu are the gain and phase errors associated

with the measured gain u′. Fig. 7a shows the root-mean-square

error (RMSE) of u′ with respect to u, and Figs. 7b and 7c

show the relative amplitude and phase deviations of u′ from u

across different gain and phase settings, respectively. Though

the RMSE is constant as a function of the gain, the relative

gain/phase errors appear larger at small gain settings due to the

un-scaling nature of the LO offsets mentioned earlier.

-100 0 100-4

-2

0

2

4

6

8

Phase Setting (deg)

IQ A

mp

. M

ism

atc

h V

I/VQ

(d

B) A

u=2.4dB

Au=5.9dB

Au=10.9dB

Au=15dB

-100 0 100

-15

-10

-5

0

5

10

15

20

25

Phase Setting (deg)

IQ P

ha

se

Mis

ma

tch

(d

eg

)

Au=2.4dB

Au=5.9dB

Au=10.9dB

Au=15dB

-100 0 100

10

20

30

40

50

60

Phase Setting (deg)

Ima

ge

Re

jec

t R

ati

o (

dB

)

Au=2.4dB

Au=5.9dB

Au=10.9dB

Au=15dB

(a) (b) (c)

Fig. 5. Measured IQ imbalances: (a) amplitude, (b) phase, and (c) image-rejection ratio vs. the gain magnitude/phase settings of VM.

-6 -4 -2 0 2 4 6-6

-4

-2

0

2

4

6

Re

Im IdealMeasured

Fig. 6. Measured complex gain constellation of one VM.

0 2 4 60.6

0.8

1

1.2

1.4

1.6

Complex Gain Magnitude (|u|)

Co

mp

lex

Ga

in R

MS

E |

u-u

′′ ′′|/|

um

ax|

(%)

-100 0 100

-0.5

0

0.5

1

1.5

Phase Setting (deg)

(Au+

∆∆ ∆∆A

u)/

Au (

dB

)

Au=2.4dB

Au=5.9dB

Au=10.9dB

Au=15dB

-100 0 100

-4

-2

0

2

4

6

Phase Setting (deg)

∆∆ ∆∆ θθ θθ

(d

eg

)

Au=2.4dB

Au=5.9dB

Au=10.9dB

Au=15dB

(a) (b) (c)

Fig. 7. Measured complex gain errors: (a) RMS, (b) magnitude, and (c) phase vs. the gain magnitude/phase settings of VM.

C. System Level Measurements

The measured responses of the four-channel VM receiver in

phased-array mode (d = λ/2) set to broadside and when steered

to a 60° scan angle are shown in Figs. 8a and 8b, respectively. The typical measured peak-to-null ratio is > 20 dB. The accuracy of this measurement was limited by the gain/phase-shifting accuracies of the plug-in, off-chip attenuators/phase shifters used in the experiment.

Figs. 9a and 9b demonstrate the measured interference cancellation of the VMs. An OFDM signal at 4 GHz represents the desired signal and another one placed 20 MHz away represents an interferer in the neighboring channel. Both the OFDM signal and the interferer are phase-shifted with passive off-chip components before being input into the VMs of the down-converter to mimic the effect of an interferer arriving from a different direction than that of the desired signal. The complex gains of two down-conversion paths are then set to actively cancel the interferer. The baseband output with one down-conversion channel on is shown in Fig. 9a. In contrast, when two channels are on, the interferer at the output of the VM is attenuated by 35 dB and the desired signal boosted by 4 dB, as shown in Fig. 9b. A worst-case cancellation of > 24 dB was observed over all tests in this case.

Table I summarizes the experimental results of the prototype chip measured at 4 GHz, which is the frequency of maximum gain. The use of passive mixers results in a high IIP2. At the same time, the IIP3 is eventually limited by the extra signal swing at the passive mixers’ outputs due to the isolation resistors, as pointed out earlier.

V. CONCLUSION

An inherently linear, four-channel beamforming IC with high gain resolution based on phase oversampling and coarse quantization is demonstrated. Accurate phase shifting is enabled by the VM architecture, achieving measured results of

< 4.2° phase error at 4-dB gain back-off and > 24-dB interference cancellation without the use of fine resolution RFVGAs in the signal paths. The technique allows potentially more linear beamformers to be implemented in scaled CMOS without linear amplifying components.

ACKNOWLEDGMENTS

The authors would like to thank C2S2, A MARCO FCRP, for funding and DARPA TAPO for chip fabrication.

REFERENCES

[1] K. Koh and G. Rebeiz, “An X- and Ku-band 8-element phased-array receiver in 0.18-µm SiGe BiCMOS technology,” IEEE J. Solid-State

Circuits, vol. 43, no.6, pp. 1360-1371, Jun., 2008.

[2] T. Yu and G. Rebeiz, “A 22-24 GHz 4-element CMOS phased array with on-chip coupling characterization,” IEEE. J. Solid-State Circuits, vol. 43, no.9, pp.2134-2143, Sept., 2008.

[3] J. Paramesh, R. Bishop, K. Soumvanath, and D. J. Allstot, “A four-antenna receiver in 90-nm CMOS for beamforming and spatial diversity,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2515-2524, Dec. 2005.

[4] A. Afsahi, A. Behzad, S. Au, R. Roufoogaran, and J. Rael, “An area and power efficient Cartesian phase shifter + mixer circuit applied to WLAN system,” in IEEE Radio Frequency Integrated Circuits Symposium 2007, pp. 357, 260, Jun. 2007.

[5] R. Tseng, A. S. Y. Poon, and Y. Chiu, “A mixed-signal vector modulator for eigen-beamforming receivers,” IEEE Trans. Circuits Syst. II, Exp.

Briefs, vol. 55, no. 5, pp. 475-483, May 2008.

[6] P. Vorenkamp and R. Roovers, “A 12-b, 60-MSample/s cascaded folding and interpolating ADC,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp.1876-1886, Dec. 1997.

[7] H. Partovl and R. Talaga, Jr., “Phase frequency detector having reduced blind spot,” US Patent No. 5,963,059, Oct. 5, 1999.

0.2

0.4

0.6

0.8

1

30

210

60

240

90

270

120

300

150

330

180 0

Measured Data

Ideal

0.2

0.4

0.6

0.8

1

30

210

60

240

90

270

120

300

150

330

180 0

(a) (b)

Fig. 8. Measured antenna patterns for (a) broadside input and (b) at 60°

incident angle.

(a)

(b)

Fig. 9. Measured (a) signal and interferer at VM output with one receive

channel active and (b) interference cancellation with two channels active.

TABLE I. CMOS VECTOR MODULATORS

[2] [3] [4] This Work

Architecture Cartesian

Combining

Cartesian

Combining

Cartesian

Combining

Phase

Oversampling

RX Channels 4 4 2 4

Frequency 24 GHz 5 GHz 2.4 GHz 4 GHz

Max Gain 12 dB N/A 53 dB 15 dB

NF 7.5 dB N/A 4 dB 13 dB

IIP3 -12.5 dBm N/A -14 dBm 2 dBm

IIP2 N/A N/A N/A 45 dBm

Core Area 3.02 mm2 4.11 mm2 0.29 mm2 1.92 mm2

Supply Voltage 1.5 V 1.4 V 1.2 V 1.2 V

Technology 130 nm 90 nm 130 nm 90 nm

Interference

Cancellation

(2-Channel)

N/A > 20 dB N/A > 24 dB

Power 115 mW 140 mW 30 mW 166 mW