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An Introduction to FPGA and SOPC Development
Board
Yong Wang
Outline
• What are Programmable Logic Devices?• Architecture and Examples• Why FPGA? • Vendors and Devices• Development on Altera Device• Summary
Programmable Logic Devices
• Programmable digital integrated circuit
• Desired functionality is implemented by configuring on-chip logic blocks and interconnections
• Developers only care about the logic design but not the internal hard-wire connection ( softwarelize the hardware design)
ASIC vs. Programmable Logic Devices
ASIC (Application Specific
Integrated Circuit)Programmable Chips
Longer design cycle and costlier ECO (Engineering Change order)
Shorter design cycle and cheaper ECO
Faster performance Long delay
Lower cost if produced in high volume > 10,000 chips
Higher cost, good for medium to low volume products
Energy saving More power consumption
Type of Programmable Logic Devices
• PLA (Programmable Logic Array)
• CPLD (Complex Programmable Logic Device)
• FPGA (Field Programmable Gate Array)
PLD - Sum of Products
A B C
CBACBAf 1
CBABAf 2
AND plane
Programmable AND array followed by fixed fan-in OR gates
Programmable switch or fuse
PLD - Macrocell
Can implement combinational or sequential logic A B C
Flip-flop
SelectEnable
D Q
Clock
AND plane
MUX
1f
CPLD Structure
Integration of several PLD blocks with a programmable interconnect on a single chip
PLDBlockPLD
BlockPLD
BlockPLD
Block
Interconnection MatrixInterconnection Matrix
I/O B
lock
I/O B
lock
I/O B
lock
I/O B
lock
PLDBlockPLD
BlockPLD
BlockPLD
Block
I/O B
lock
I/O B
lock
I/O B
lock
I/O B
lock
• • •
Interconnection MatrixInterconnection Matrix
• • •
• • •
• • •
CPLD Example - Altera MAX7000
EPM7000 Series Block Diagram
CPLD Example - Altera MAX7000
EPM7000 Series Device Macrocell
FPGA - Generic Structure
FPGA building blocks:• Programmable logic blocks
Implement combinatorial and sequential logic
• Programmable interconnectWires to connect inputs and outputs to logic blocks
• Programmable I/O blocks Special logic blocks at the periphery of device for external connections
I/O
I/O
Logic block
Interconnection switches
I/O
I/O
Other FPGA Building Blocks
• Clock distribution
• Embedded memory blocks
• Special purpose blocks:– DSP blocks:
• Hardware multipliers, adders and registers
– Embedded microprocessors/microcontrollers– High-speed serial transceivers
FPGA – Basic Logic Element
• LUT to implement combinatorial logic• Register for sequential circuits• Additional logic (not shown):
– Carry logic for arithmetic functions– Expansion logic for functions requiring more than 4 inputs
LUTLUT
Out
Select
D Q
A
B
C
D
Clock
Look-Up Tables (LUT)• Look-up table with N-inputs can be used to implement
any combinatorial function of N inputs• LUT is programmed with the truth-table
LUTLUT
ABCD
Z
A
B
C
D
Z
Truth-table Gate implementation
LUT implementation
LUT Implementation
• Example: 3-input LUT• Based on multiplexers
(pass transistors)• LUT entries stored in
configuration memory cells
0/10/1
0/10/1
0/10/1
0/10/1
0/10/1
0/10/1
0/10/1
0/10/1
X1X2
X3
F
Configuration memorycells
Other FPGA Building Blocks
• Clock distribution
• Embedded memory blocks
• Special purpose blocks:– DSP blocks:
• Hardware multipliers, adders and registers
– Embedded microprocessors/microcontrollers– High-speed serial transceivers
Special Features
• Clock management– PLL,DLL– Eliminate clock skew between external clock
input and on-chip clock– Low-skew global clock distribution network
• Support for various interface standards• High-speed serial I/Os• Embedded processor cores• DSP blocks
Configuration Storage Elements
• Static Random Access Memory (SRAM)– Logical configuration is controlled by the state of
SRAM bits– FPGA needs to be configured at power-on by another
separated ROM
• Flash Erasable Programmable ROM (Flash)– – Logical configuration is implemented by floating-
gate transistors that can be turned off by injecting charge onto its gate. FPGA itself holds the program
– reprogrammable, even in-circuit
Example: Altera Stratix Series
Why FPGA?
• FPGA chips handle dense logic and memory elements offering very high logic capacity
• Uncommitted logic blocks are replicated in an FPGA with interconnects and I/O blocks
• Complete integrated design environment (IDE)• Easy to learn and use• Low cost of ownership
FPGA Vendors
• Altera• Xilinx
– Virtex-II/Virtex-4: Feature-packed high-performance SRAM-based FPGA
– Spartan 3: low-cost feature reduced version– CoolRunner: CPLDs
• Actel• Lattice• QuickLogic
• Programmable Logic Families– High & Medium Density FPGAs
• Stratix™ II, Stratix, APEX™ II, APEX 20K, & FLEX® 10K
– Low-Cost FPGAs• Cyclone™ & ACEX® 1K
– FPGAs with Clock Data Recovery• Stratix GX & Mercury™
– CPLDs• MAX® 7000 & MAX 3000
– Embedded Processor Solutions• Nios™, ExcaliburT™
– Configuration Devices• EPC
Introduction to Altera Devices
Nios: The processor in software
• a user-configurable, 16-bit instruction set architecture (ISA), general-purpose RISC embedded processor
• designers can use the SOPC (system-on-aprogrammable-chip) Builder system development tool to very easily create custom processor-based systems
What is available
• Altera Stratix Nios Development Board
• Altera UP2 Development Board
Altera Stratix Nios Development Board
Altera Stratix Nios Development Board
• Stratix EP1S10F780C6– 10,570 Logic Elements– 920 Kb on-chip memory
• Provide hardware platform for developing embedded system– Comes pre-programmed with a 32-bit Nios
processor reference design
Altera Staratix Nios Development Board
• 8 MB of flash Memory,1MB of static RAM, 16MB of SDRAM
• On-board Ethernet MAC/PHY device• Compact Flash connector hearder• Two RS-232 DB9 serial ports• 50MHz oscillator and zero-skew clock
distribution circuitry• Four push-button switches• Dual 7-segment LED display
Altera UP2 Development Board
Altera UP2 Development Board
• EPF10K70RC240-4 device
• EPM7128SLC-7 device
• One RS-232 serial port
• Four push-button switches
• Dual 7-segment LED display
• 25.175MHz oscillator
FPGA Design Flow
FPGA Design Flow
Synthesis• Translate Design into Device Specific Primitives• Optimization to Meet Required Area & Performance Constraints
Design Specification
Place & Route• Map Primitives to Specific Locations inside Target Technology with Reference to Area &• Performance Constraints• Specify Routing Resources to Be Used
Design Entry/RTL CodingBehavioral or Structural Description of Design
LE
MEM I/O
RTL Simulation• Functional Simulation• Verify Logic Model & Data Flow (No Timing Delays)
FPGA Design FlowTiming Analysis - Verify Performance Specifications Were Met - Static Timing Analysis
Gate Level Simulation - Timing Simulation - Verify Design Will Work in Target Technology
Program & Test- Program & Test Device on Board
tclk
Design Entry Methods
• Text-based– VHDL(Very High
Speed Integrated Circuit Hardware Description Language)
– Verilog HDL
Block Diagram
• Contents of a block can be any type of design unit
State Diagram
• “Bubble” diagram
• States
• Conditions
• Transitions
• Outputs
• Useful for developing control modules
Program Devices
• Once we verify our design, it should be downloaded to the FPGA devices
• Designs can be downloaded through parallel port in PC to the JTAG connector on board using download cables
• Designs can also be downloaded via the Internet to a target device
Introduction to Altera Design Software
• Software & Development Tools: – Quartus II
• Stratix II, Stratix, Stratix GX, Cyclone, APEX II, APEX 20K/E/C, Excalibur, & Mercury Devices
• FLEX 10K/A/E, ACEX 1K, FLEX 6000, MAX 7000S/AE/B, MAX 3000A Devices
– Quartus II Web Edition• Free Version • Not All Features & Devices Included
– MAX+PLUS® II• All FLEX, ACEX, & MAX Devices
Quartus II Development System
• Fully-Integrated Design Tool
• Multiple Design Entry Methods
• Logic Synthesis
• Place & Route
• Simulation
• Timing & Power Analysis
• Device Programming
More Features
• MegaWizard® & SOPC Builder Design Tools• LogicLock™ Optimization Tool• NativeLink® 3rd-Party EDA Tool Integration• Integrated Embedded Software Development• SignalTap® II & SignalProbe™ Debug Tools• Windows, Solaris, HPUX, & Linux Support• Node-Locked & Network Licensing Options• Revision Control Interface
Quartus II Operating Environment
Main Toolbar & Modes
To Reset Views: Tools Toolbars>Reset All;Restart Quartus II
Window & new file buttons
Compiler ReportFloorplansExecution Controls
Dynamic menus
Previous Project 1: VGA Driver
• 25Mhz clock (640 * 480)
• Horizontal, Vertical Sync
• RGB
Previous Project 2: DRIIVE Network
Figure 1: Hardware Organization
Summary
• Prerequisite– Electronics and circuits– Digital logic design– VHDL (VHSIC Hardware Description
Language)
• FPGA– Combine technologies in hardware & software– Benefits