* Department of Electronics and Information, Politecnico di MilanoPiazza Leonardo da Vinci, 32 - 20133 Milano, Italy

Tel. +39-0223993580 Fax +39-0223993413 E-mail: achille@elet.polimi.it

An Optical Subsystem for Peak-Cell-Rate Policingin ATM Networks

Lorenzo Ghioni, Guido Maier, Mario Martinelli, Achille Pattavina*

CoreCom, via Ampére, 30 - 20131 Milan, ItalyTel. +39-022369131, Fax. +39-0223691322E-mail: maier@corecom.polimi.it

Abstract

The traffic-parameter control (policing) is a very important function of the ATM protocol architecture.Policing is normally performed by a subsystem included in the ATM node which measures the trafficparameters and discards cells when the bounds established at the connection set-up are exceeded. In thiswork we present the design and simulation of a policing subsystem suited to be employed in a high-capacity all-optical ATM switching network. The subsystem is able to perform Peak Cell Rate (PCR)enforcement over the global traffic carried by an ATM network fiber link in an all-optical environment,without requiring any opto-electronic conversions of the controlled signals. The processingarchitecture relies on the Virtual Scheduling Algorithm (VSA), one of the most known and used policingalgorithm. The implementation proposed is based on the employment of Semiconductor OpticalAmplifiers (SOAs). The simulated physical behaviour of the subsystem has been obtained by means of asimple physical model of the SOA device. Simulations have been conducted considering a bit-rate of 2.5Gbit/s, though the subsystem is theoretically able to operate at higher speeds.

1. INTRODUCTION

In the next years the development of the present telecommunication services, along with thebirth of new unexpected services, will lead to a huge increase in the traffic offered to networksand particularly to optical networks. The increase in bandwidth demand will be accompanied bymore stringent requirements in Quality of Services (QoS) (especially for multimedia networkapplications) which the network will have to guarantee, with possibly a more complex definitionof the traffic parameters.

ATM seems nowadays the most promising technique to meet the future requirements. In factit can offer not only an efficient bandwidth dynamic sharing, which allows a high channelcapacity utilization, but it has been also designed specifically to facilitate the establishing andmanaging of QoS-guaranteed connections.

In the past ten years many studies have been developed to evaluate the employment of theoptical technology not only for transmission, but also to implement the processing required inhigh-speed ATM switching nodes. These studies led to the proposal and lab-testing of some all-optical ATM switching-node architectures [Rac95]. In most of these initiatives the greatestefforts have been concentrated on the node subsystems performing the cell switching andbuffering functions. Less interest has been devoted to the optical realization of other ATMprotocol functions by preferring sometimes temporary electronic solutions when needed in theimplementation of the optical switching node prototypes.

Traffic parameter control (or policing) is among the ATM protocol functions whose opticalimplementation has not been attempted yet. This important function belongs to the ATM Layerof the ATM protocol stack (Figure 1). The ATM technique is based on the statisticalmultiplexing of virtual connections; at the opening of a new connection the user must declare inadvance the traffic parameters that will characterize the connection. The network managingsystem can then decide if enough network resources are available for the new connection(connection-admission-control procedure). If the connection is accepted the network must

guarantee that the required traffic parameters are respected along the whole connection lifetime.To accomplish this duty the network must be able to eliminate traffic that for any event shouldexceed its traffic limits thus avoiding congestion events or the degradation of the QoS of thecompliant connections. The ATM policing function has been standardized as a part of the ATMprotocol stack both by ITU-T and ATM Forum recommendations, though many implementationand architectural aspects are left to the initiative of the manufacturers.

This work deals specifically with the control of the Peak Cell Rate (PCR) traffic parameter.The policing function regarding this parameter has been better defined in international standardsthan other traffic parameters, which are more complicated to control. Many algorithms havebeen proposed in literature to perform PCR control. We took as a reference the VirtualScheduling Algorithm (VSA), which has been also included in both ITU-T [Itu93] and ATMForum [Afo96] standards. As reported in [Itu93], the PCR policing can be performed at variouslevels of traffic aggregation: in the most complete version it is performed on ever single VirtualChannel Connection (VCC), while other simpler operation modes are possible, like for examplethe control at Virtual Path Connection (VPC) level.

A discussion on the electronic VLSI implementation of a policing subsystem based on VSA canbe found in [Jeo96]. Many products are also commercially available that perform PCR policing on155 and 622 Mbit/s links using CMOS technology. The subsystems operating at 155 Mbit/sexecute the control on a VCC basis, while at 622 Mbit/s only an aggregate-traffic control can beachieved.

In the design of the optical policer proposed in this paper we choose to perform PCR controlof the entire aggregate traffic travelling on an optical link, which can thus be considered as a

User PlaneControlPl

Management Plane

ATM Layer

ATM Adaptation Layer (AAL)

Higher Layers Higher Layers

Physical Layer

Control Plane User Plane Policing

Figure 1 - Policing function in the ATM layered architecture

P

P P

P

P

P PCR enforcingWAN node MAN node

Figure 2 - Possible locations of a PCR policer in an optical ATM network

single path connection. This choice simplifies the hardware and reduces the cost of the subsystem,though it limits its functionalities. In a possible future development where this subsystem shouldbe part of a full all-optical switching node this limitation would not be necessary anymore.However the realization of a PCR link control can per se be very useful. In

Figure 2, for example, possible locations of optical PCR policers in an optical ATM networkare represented. The PCR optical link policers are used at the interfaces between WANs andMANs to prevent traffic overloadings of the core network. They are also used to control highspeed optical links between different WANs.

The layout of this paper is as follows. After a brief description of the VSA, in section 2 we willillustrate the block schematic of the optical policer. In the subsequent section we will describe indetails the implementation proposed and the required optical components. In section 4 thesimulation results will be reported to allow a system behaviour evaluation. Some conclusions willbe discussed in the final section.

2. THE VIRTUAL SCHEDULING ALGORITHM AND ITS OPTICALIMPLEMENTATION

The Virtual Scheduling Algorithm has been included in ITU-T I.371 recommendation t oprovide a standard reference for traffic control in ATM networks. Its scheme is reported in Figure3. The Theoretical Arrival Time (TAT) indicates the time value after which a new cell can beaccepted; T represents the inverse of PCR (T=PCR-1), which is expressed in cells per second; τ isthe Cell Delay Variation (CDV) admitted on the connection.

Owing to the large availability of simple and reliable electronic components performing logicaland mathematical functions, the electronic implementation of the VSA can be directly derivedfrom the block scheme defining the VSA, as reported in ITU-T and ATM Forum documents[Itu93] [Afo96]. In the case of optical implementation analogous components are not availablethat perform the functions specified by the block scheme. However it is possible to build adifferent optical implementation of the VSA.

Let T be the inverse of the PCR value. The "classical" VSA description states that, uponreceiving a new cell, the policer computes the time elapsed since the last cell arrival; if this time issmaller than T, then the new cell is discarded. Therefore two cells belonging to the sameconnection can cross the link only if they are at least T seconds apart. As already stated in theintroduction, we assume the optical link to support just one connection. Therefore the opticalflow control device could be activated by the transit of a cell after which the optical link should be

Arrival of a cell at time ta

TAT < ta ?

TAT = ta

Yes

TAT>ta + τ ?Non-compliant cellYes

No

Compliant cellTAT = TAT + T

No

Figure 3 - Virtual Scheduling Algorithm

disabled for a time T.Based on the previous considerations a VSA policer could be designed according to the scheme

of Figure 4. The policer, which receives cells on the input link and transmits cells on the outputlink, includes four devices. The Cell Delineator (CD) generates the control signal needed to set thestate of the two gates, i.e. Gate Normally "Closed" (GNC) and Gate Normally "Open" (GNO).These gates have different behaviours: GNC is normally closed (it enables the signal transit),whereas GNO is normally open (it disables the signal transit). The Optical Processor (OP) has t ogenerate two distinct control signals so as to "cut" on the optical channel (using the control signalgiven by the CD and setting the states of GNC and GNO) a time window whose width enablesexactly the transit of a single cell which must cross the policer without being discarded.

An example of the policer operations is shown in Figure 5, which assumes that the system is inthe idle state when a new cell arrives (cell 1). The cell reaches port and hence the CellDelineator, which generates a control pulse aligned with the cell itself. As long as the cell istransmitted to port , the control pulse is sent to port and thus to the Optical Processor(Figure 5.a). The OP sets a logical high signal on port to change the GNO state whose durationis fixed and equal to the transmission time of one cell, thus enabling the transit of one cell onlythrough the policer (see Figure 5.b).

When the last bit of the cell has crossed port , the Optical Processor has to send a logical

Input link Output link

OP - OpticalProcessor

ExcessBits

Cell flow Control signal flow

CD - CellDelineator

Non-compliantcells

CD: Cell Delineator OP: Optical Processor

GNO: Gate Normally "Open"

GNC GNO

GNC: Gate Normally "Closed"

Figure 4 - Functional scheme of the VSA-based policer

GNO

OP

GNC

GNC

CDGNO

OP

GNCCD

GNO

OP

CDGNCGNO

OP

(c)

H1H2

H1

(a) (b)

H1H

(d)

1H2

CD

CD: Cell Delineator OP: Optical Processor GNO: Gate Normally "Open" GNC: Gate Normally "Closed"

Figure 5 - Dynamic behaviour of the proposed policer

high signal on port to prevent that other cells cross port before the due time T (Figure 5.c).This signal is generated along with the pulse transmitted onto port , but its duration is not fixedas it depends on the connection PCR.

A new cell (cell 2) reaches the policer when a logical high signal is still present on port . Asis shown in Figure 5.d, this prevents the cell to reach port and thus to modify the policer stateso determining the cell discard. If the logical level on port changes before cell 2 is completelyreceived and discarded, the cell tail would enter the system and access the Cell Delineator.However this cell portion would not be recognized as a valid cell. The absence of control signal onport implies that the cell tail received on port would be lost as it would find GNO in theopen state.

From the above description it follows that the Optical Processor is the main system blockwhose implementation will be discussed in detail in the next section, where the complete policerarchitecture will be shown. It is worth noting that the policer is completely asynchronous, as it isnot driven by an external clock. All the timing needed for a correct operation are derived fromthe incoming signal flow.

3. POLICER IMPLEMENTATION: OPTICAL PROCESSOR STRUCTURE

The block structure of the Optical Processor is shown in Figure 6 within the frame of theoverall policer.

The input to the policer is controlled by Gate 1 (G1), which is connected to port of the CellDelineator (CD), which feeds both port of Gate 2 (G2) and port of Coupler 1 (C1). C1divides the input control signal in two equal parts. One part is transmitted through port to ablock that delays the signal by a fixed amount T* (FD1). The output signal from this block feedsthe optical Flip-Flop 1 (FF1) both directly on port (set signal) and through a variable delay(VD) on port (reset signal). The other part of the output signal from C1 is transmitted throughport to another device, Coupler 3 (C3), so as to obtain the set (port ) and reset (port )signals defining the state of optical Flip-Flop 2 (FF2). These two signals are received TC secondsapart due to a fixed delay (FD2) connected to port of FF2.

As far as the behaviour of the system in Figure 5 is concerned, the key point is that allreceived cells can reach port of G2. When this occurs the control signal on port enables t ochange immediately the state of G2 (from open to closed) and, after a time T* from the cellarrival on port , also that of G1 (from closed to open). The state of G1 must be changed justafter it finishes transmitting the cell that originated the control signal on port . This meansthat T* must be equal to the transmission time (TC) of an ATM cell over the input optical link

C: Coupler G: Gate

Source

FD1T* C1

G1Network

openclose

VDTIC

G2CD

FF1S R

control

FF2S RC3

FD2TCOptical Proces sor

CD: Cell Delineator FD: Fixed Delay VD: Variable DelayFF: Flip-Flop

C2

Figure 6 - Block diagram of the Optical Processor and the proposed policer

T * = TC

G2 stays in the closed state as long as it is crossed by the cell. Therefore the reset signal onport is generated with a fixed delay equal to TC with respect to the set signal received on port

.Analogously the time TIC for which G1 must remain in the open state depends on the PCR

values associated to the connection over the link controlled by the policer according to

T TIC C= −1

PCRSince the PCR value is negotiated between the source and the network, TIC must be dynamically

changeable.The above description shows that the policer is able to control the PCR of an ATM cell flow

without requiring any cell delays. The policer makes it possible to discard cells that are offered t othe network without being spaced according to the contracted PCR value.

We discuss now the physical implementation of the proposed VSA-based policer.Gates and flip-flop with optical control can be conveniently built with devices based on

Semiconductor Optical Amplifiers (SOA). The Gates, both in the open and closed state, can bebuilt by inserting two SOAs in a Mach-Zender interferometer, according to the scheme in Figure7. In this case the control signal on port enables the control of the unbalancing of the twobranches of the interferometer and hence also of the device transfer function between input port

and output port . Employing two SOAs according to the scheme in Figure 7 allows us also t ocontrol the signal amplification when the gate is in the closed state.

The flip-flop Set-Reset device could be implemented using the architecture proposed in[Par98], whose scheme is reported in Figure 8. With respect to the implementation proposed in[Par98], here we can obtain features closer to an ATM environment by using a SOA-based gatewith normal closed state to perform functions of gate and amplification.

input output

SOA 2

control

50 %

50 %

50 %

50 %

SOA 1

Figure 7 - Diagram of an optically controlled optical gate

A

Set Output

ResetFC 2

FC 1

BPF

A: Amplifier FC: Fiber CouplerBPF: Band Pass Filter

Figure 8 - Diagram of the optical Set-Reset Flip-Flop [Par98]

Fixed delays can be obtained using an optical fiber with proper length. The variable delay canbe implemented by means of a Forward Delay Line [Pru93], whose scheme is given in Figure 9.The rationale of this solution is to approximate the required signal delay by the sum of severaldiscrete delays, each obtained by a fiber span that is properly selected through 2x2 switches. Inorder to determine M different amounts of delays the structure of Figure 9 must include log2Mcascaded stages in addition to an output stage. Given the minimum delay, Tmin, we can define atime-base delay TB = M⋅Tmin. The relations between the parameters Tmin, TB, M and Tmax areexpressed by the following equations system

TTB

M

TTB

TBM

Mii

M

min

max

log

=

= = ⋅ −

=

∑ 2

1

1

2(1)

Note that Tmin also represents the minimum delay increase given by this structure. Thenumber M of different delays we would like to have available depends on the granularity of thePCR values that can be handled by the policer. ITU-T has mentioned the need for the definitionof a PCR [Itu93], but has left its definition to further studies.

The Cell Delineator can be developed following the guidelines given in [Mai98]. In this casecell delineation is accomplished by comparing a code derived from the content of four adjacentbytes with the content of the fifth byte. The code is obtained using the algorithm that generatesthe cell Header Error Control (HEC), which is carried by the fifth byte of the ATM cell headerand codes the content of the four preceding bytes. Different solutions to generate the controlsignal needed in the policer could rely on the WDM or TDM transmission of a synchronizationsignal.

4. SIMULATION AND PERFORMANCE OF THE POLICER

Since gates and flip-flops are implemented using semiconductor optical amplifiers, we need amathematical model of a SOA to be used in the performance evaluation of the policer. The SOAmodel defined in [Agr89] has been employed as a starting point that has been suitably integratedso as to take into account the optical control of the amplifier state.

The mathematical model is based on two equations describing the system, that isdh

dG h P h

τ= − − ⋅ −ln( ) [exp( ) ]0 1

E P i h t iin= ⋅ − +exp[ ( ) ( ) ]12 01 α φ

where P represents the sum of input signal power (Pin) and output control signal power (Pc),G0 is the SOA signal peak gain, φ0 is the initial phase and α is the Linewidth Enhancement Factor,that is a parameter taking into account the refractive index change due to the presence of carriersinside the active region of the amplifier. Table 1 reports the range of the model parameters as

TB/2

Stage #1

TB/4 TB/M

Stage#log2M

C1 C2 Clo gM

1x2 2x22x2 2x1

Figure 9 - Diagram of a Forward Delay Line [Pru93]

specified in the technical literature and the specific values used in the simulation. Input (Pin) andcontrol (Pc) signal powers have been normalized with the saturation power (Psat), which is adevice parameter depending on the physical characteristics of the SOA. Typical values of Psatcited in [Agr89] and in other studies are on the order of a few milliWatt for a SOA with an activesection area of about 1 µm2.

We carried out some "virtual experiments" of our policer using the above mathematical modelof a SOA and the software package Simulink. Figure 10 shows the block diagram of the simulatedPCR policer, which appears a little different from the scheme given in Figure 6. Now three SOAsare used in the scheme, whose task is the amplification of signal in transit that has to be used ascontrol signal of the gates. Also the simulated scheme uses three gates, of which two in thenormal closed state and one in the normal open state. An ideal behaviour has been assumed forthe Cell Delineator, which has been modelled as a component generating a control pulse alignedwith the incoming ATM cell. This assumption has required the use of a second gate in the normalclosed state which does not modify in any way the operations of the real policer. The outputsignal from SOA 3 has not been divided by a coupler as the usage of SOA Gate 2 is not required byreal needs but only by modelling purposes. The Source block models the traffic source and theOutput block enables to store and analyze the output signal.

The simulations have been carried out on a cell-level basis: a rectangular signal with properamplitude and width represents the transmission of an ATM cell, so that the transmission of thesingle bits is not considered. The policer is assumed to operate on a 2.5 Gbit/s link, so that it takesTc = 169.6 ns to transmit an ATM cell. Different types of traffic sources have been considered t oevaluate the policer, including some sources offering traffic at a rate exceeding the contractedPCR.

The bit rate corresponding to the different multiplexing levels of the SDH hierarchy have beenconsidered as the PCR values to study in our simulations. Table 2 gives the bit rate, the cell rate,the time between two consecutive cell arrivals (T) and the idle time between consecutive cells(TIC) for the different PCR values that have been considered. PCR-n denotes a PCR value equal t othe transmission rate in a STM-n system.

The Fiber Delay Line structure needs to be properly dimentioned according to the minimumand maximum value of TIC reported in Table 2. The maximun delay value Tmax corresponds to theidle time between cells of a PCR-2 flow. The number of stages of the Fiber Delay Line is obtainedsolving Eq. 1 after Tmin has been chosen. If Tmin = 57.6 ns then only six stages (log2M = 5) are

Minimum value Maximum value Value used in simulationsG0 (dB) 20 25 20α 3 5 3τc (ns) 0.2 1 1

Table 1 - Parameter values utilized in simulations

VariableDelay

SOA 3

SOA 2

SOA GateClosed 2

ontro l

SOA GateClosed 1

Source

Output

HECCell Delineator

.9 2

Gain 6

.0 1

Gain 5 .9 2

ain 4

.0 1

ain 3

.5

ain 2

.5ain 1

.0 2

Gain

eset

e t

Flip-F lop 2

Reset

Set

Flip-Flop 1

SOA GateOpen

Tc 2

c 1

SOA 1

ontro l

ontro l

Figure 10 - Block diagram of the PCR policer

needed. In this case the attainable values of the controlled PCR approximate the target PCRvalues with a deviation less then 1%. If we reduce the minimum delay Tmin to 2 ns, the maximumapproximation incurred in controlling the PCR is less than 0.25% of the target PCR value buttwelve stages are required (log2M = 11).

The simulations let us evaluate the maximum load that the policer can handle given that atime Tr is needed to reset the policer to the initial conditions after a cell transit. It has been foundTr ≅ 3 ns, which is the combined result of the recovery time in the flip-flop and the gate switchingtime (e.g., from the open state to the closed state). The maximum load, ρMAX, is given by

ρMAXc

c r

T

T T=

+=

+≈169 6

169 6 30 982

..

.

Figure 11 shows both input and output signals in the case of a PCR-16 connection loaded at93% (ρ = 0.93), the source being compliant. We can notice that in spite of a constant input signalamplitude, a ripple appears in the output signal amplitude of the cell itself (Rcell - the cell doesnot have constant amplitude) and also on the amplitude of the following cells (Rcells - differentcells do not have the same amplitude). This fact is due to the non-ideality of the flip-flop controlpulses and also to the inherent feedback structure of the policer that implies a finite time neededto properly set the policer state.

Table 3 summarizes the input parameters used in our simulations. ρ denotes the load valuecontrolled by the policer and c the load value offered by the source. Values of c larger than ρ

Mbit/s Cells/s T (ns) TIC (ns)

PCR-2 155.52 366,793 2,726.3 2,556.7PCR-4 622.08 1,467,170 681.6 512PCR-6 933.12 2,200,755 454.4 284.8PCR-8 1,244.16 2,934,340 340.8 171.2PCR-12 1,866.24 4,401,510 227.2 57.6PCR-16 2,488.32 5,868,680 169.6 0

Table 2 - Connections parameters used for policer simulation

0 100

5 10-4

1 10-3

1.5 10-3

2 10-3

2.5 10-3

0 500 1000 1500 2000 2500 3000

Input signal

Nor

mal

ized

pow

er

Time (ns)

0 100

1 10-2

2 10-2

3 10-2

4 10-2

5 10-2

0 500 1000 1500 2000 2500 3000

Output signal

Nor

mal

ized

pow

er

Time (ns)

Figure 11 - Policer behaviour with a PCR-16 compliant source

denote cases with a non-compliant traffic source in which the policer is expected to perform celldiscarding. Table 3 reports also the ripple value observed in the different cases in addition to theExtinction Ratio (ER) of the input and output signal and the dimensioning of the variable delay.The ripples Rcell and Rcells are measured as the ratio between the maximum and minimum values ofthe amplitude of, respectively, the single cell or consecutive cells.

The obtained results show that the proposed optical device handles correctly both compliantand non-compliant traffic flows. Cells in excess of the contracted rate are actually discardedwithout needing any storage device. The ripple amplitude is rather limited and does not affect theoverall policer behaviour.

In order to show the independence of the policer from the source periodicity, a different casehas also been examined in which the input signal is no more periodic. Figure 12 shows the case inwhich the controlled rate is the PCR-4 value. The source is characterized by two states: itgenerates cells at a rate double than allowed in the on state, whereas is inactive in the off state. Asthe cell rate in the on state exceeds the admissible value, the policer correctly discard the cells inexcess. In this case the cell ripple is Rcell = 0.18 dB and the amplitude ripple on the following cellis Rcells=0.27 dB. As far as the extinction ratio is concerned, a value EROUT = 17.2 dB has beenfound given that ERIN = 20 dB.

ρ c Rcell(dB)

Rcells(dB)

ERIN(dB)

EROUT(dB)

Variable Delay(ns)

Reference

PCR-16 0.93 0.93 0.54 0.36 - - 8.57 Figure 110.8 0.8 0.31 0.18 20 52 38.20.8 0.9 0.15 0.24 20 19 38.20.8 0.93 0.17 0.31 20 19.8 38.2

PCR-12 1 1 0.18 0.29 20 43 53.41 1.1 0.26 0.13 20 20.2 53.4

PCR-8 1 1 0.42 0.25 20 50.2 1671 1.1 0.23 0.12 20 19.9 1671 1.5 0.15 0.22 20 19.5 167 Figure 13

PCR-6 1 1 0.36 0.33 20 49.2 280.61 1.1 0.14 0.11 20 20.1 280.61 1.5 0.21 0.21 20 20 280.61 2 0.36 0.15 20 26.3 280.6

PCR-4 1 1 0.57 0.21 20 53 507.81 1.5 0.19 0.08 20 40.3 507.81 2 0.54 0.29 20 29.7 507.81 3 0.24 0.08 20 22.8 507.8 Figure 14

PCR-2 1 1 0.2 0.14 20 43.8 2,552.51 2 0.2 0.06 20 45.7 2,552.51 3 0.18 0.07 20 36.1 2,552.51 5 0.18 0.03 20 29.5 2,552.5 Figure 15

Table 3 - Simulation results

0 100

5 10-4

1 10-3

1.5 10-3

2 10-3

2.5 10-3

0 500 1000 1500 2000 2500 3000

Input signal

Nor

mal

ized

pow

erTime (ns)

0 100

1 10-2

2 10-2

3 10-2

4 10-2

5 10-2

0 500 1000 1500 2000 2500 3000

Output signal

Nor

mal

ized

pow

er

Time (ns)

Figure 12 - Policer behaviour with a two state non-compliant source

0 100

5 10-4

1 10-3

1.5 10-3

2 10-3

2.5 10-3

0 500 1000 1500 2000

Input signal

Nor

mal

ized

pow

er

Time (ns)

0 100

1 10-2

2 10-2

3 10-2

4 10-2

5 10-2

0 500 1000 1500 2000

Output signal

Nor

mal

ized

pow

er

Time (ns)

Figure 13 - Policer behaviour with a PCR-8 connection (non-compliantsource r = 1 c = 1.5)

0 100

5 10-4

1 10-3

1.5 10-3

2 10-3

2.5 10-3

0 500 1000 1500 2000 2500 3000

Input signal

Nor

mal

ized

pow

erTime (ns)

0 100

1 10-2

2 10-2

3 10-2

4 10-2

5 10-2

0 500 1000 1500 2000 2500 3000

Output signal

Nor

mal

ized

pow

er

Time (ns)

Figure 14 - Policer behaviour with a PCR-4 connection (non-compliantsource ρ = 1 c = 3)

0 100

5 10-4

1 10-3

1.5 10-3

2 10-3

2.5 10-3

0 500 1000 1500 2000 2500 3000

Input signal

Nor

mal

ized

pow

er

Time (ns)

0 100

1 10-2

2 10-2

3 10-2

4 10-2

5 10-2

0 500 1000 1500 2000 2500 3000

Output signal

Nor

mal

ized

pow

er

Time (ns)

Figure 15 - Policer behaviour with a PCR-2 connection (non-compliantsource r = 1 c = 5)

5. CONCLUSIONS

We have defined in this paper an architecture able to perform optically the functions relatedto the control of the peak cell rate in optical ATM networks. The proposal takes into accountboth the traffic control requirement and the possible solutions depending on the available opticaltechnology, so as to better integrate transmission and control functions in the optical domain.

The proposed solution for the peak cell rate control of an ATM connection is based on thevirtual scheduling algorithm. The policer can operate on the cell flow generated by a source thatdoes not need to be periodic without requiring storage devices. This is made possible by the factthat all the operations to be performed upon a cell arrival can be done as long as the cell crossesthe optical device.

By means of a mathematical modelling of the optical components, the behaviour of theoverall system has been simulated in a configuration very close to the target physical device. Theobtained results show the feasibility of utilizing the proposed architecture to perform a PCRenforcement on 2.5 Gbit/s ATM links. The proposed policer implementation based on SOAsmeans that the architecture is actually feasible.

The simulations have indicated the maximum load that the policer can handle, which is largerthan 98% with a 2.5 Gbit/s link. The decision on the acceptance or discarding of a cell is taken ina time of about 3 ns, which is the time needed to evaluate the correctness of the fields included inthe cell header.

6. REFERENCES

[Afo96] ATM Forum, “ATM Traffic Management Specification Version 4.0”, April 1996,ftp://ftp.atmforum.com/pub/approved-specs/af-tm-0056.000.ps.

[Agr89] G. P. Agrawal, N. A. Olsson, “Self-Phase Modulation and Spectral Broadening of Optical Pulses inSemiconductor Laser Amplifiers”, Nov. 1989, IEEE Journal of Quantum Electronics, Vol. 25, No. 11, p. 2297-2306.

[Itu93] ITU-T Recommendation I.371, “Integrated Services Digital Network (ISDN) - Traffic Control and CongestionControl in B-ISDN”, 1993, Helsinki.

[Jeo96] M-Y Jeon, D-Y Kwak, H-S Park, “Implementation of a Peak Cell Rate policer using the Virtual SchedulingAlgorithm”, June 1996, Proc. of IEEE ICC ’96, DALLAS, TX, USA, p. 762-766.

[Mai98] G. Maier, P. Boffi, R. Melen, M. Martinelli, "Free-Space Architecture for an ATM Header Processing function",June 1998, Proc. of Optics in Computing '98, Bruge, Belgium, p. 127-129.

[Par98] P. Parolari, L. Marazzi, P. Boffi, M. Martinelli, "Programmable Optical Bistable", June 1998, Proc. of Optics inComputing '98, Bruge, Belgium, p. 383-385.

[Pru93] Paul R. Prucnal, “Optically Processed Self-Routing, Synchronization and Contention Resolution for 1-Dand 2-D Photonic Switching Architectures”, Feb. 1993, IEEE Journal of Quantum Electronics, Vol. 29, No. 2, p.600-612.

[Rac95] RACE II PROJECT 2039 ATM Optical Switching (ATMOS), “Final Report”, Dec. 1995, Original Paper.