AN OVERVIEW OF ADVANCED ELECTRONIC PACKAGING TECHNOLOGY.pdf

TECHNICAL REPORT: CVEL-07-001

AN OVERVIEW OF ADVANCED ELECTRONIC PACKAGING TECHNOLOGY

Hocheol Kwak and Dr. Todd Hubing

May 1, 2007

Clemson Vehicular Electronics Laboratory, CVEL-07-001 2

EXECUTIVE SUMMARY

This report reviews recent and future trends in electronic packaging of integrated circuits and systems. Various novel approaches such as system-in-package (SiP) and system-on-chip (SoC) technologies allow integrated devices to work together and communicate at very high speeds. The report concludes with a discussion of the critical issue of power bus decoupling in ultra high-speed designs.


TABLE OF CONTENTS

Overview of Electronic Packaging .................................................................. 4 1.1 Definition of Electronic Packaging

1.2 Function of Electronic Packaging

1.3 Packaging Hierarchy

1.4 Driving Forces of Packaging Technology

1.4.1 Electrical Packaging Design Consideration

1.4.2 Electrical Packaging Design Process

Electronic Packaging Technology Trends ..................................................... 14 1.5 Recent Trends in Advanced Electronic Packaging Industries

1.5.1 Trends on the Electronic Package based on Mobile Platform

1.5.2 Trends on the Electronic Packages based on High-Performance Platform

1.5.3 Trends on the CoC Technology in Japanese Industry

1.5.4 Trends on the IC Substrate Technology

1.6 Future of Electronic Packaging Technology

1.6.1 Future Design Issues of Electronic Packaging Structure

1.6.2 Future Concept of the Advanced Electronic Package

Critical Issues for Decoupling Capacitors ..................................................... 42 1.7 Electrical Characteristics of Capacitors

1.7.1 Low Inductance Path (ESL)

1.7.2 Controlled-ESR

1.7.3 Distributed Capacitor Model

1.8 Evolution of Capacitor Design Concepts

1.8.1 Discrete Capacitor (MLCC)

1.8.2 Embedded Thin Film Capacitor

1.8.3 Future Strategy of Decoupling Capacitor

References ......................................................................................................... 54


1. Overview of Microelectronic Packaging 1.1 Definition of Electronic Packaging

An electronic package is the portion of an electronic structure that protects an electronic/electrical element and its environment from each other. [1] Packaging is the bridge that interconnects the ICs and other components into a system-level board to form electronic products. An integration of many circuits or components on a single chip is defined as an integrated circuit (IC). ICs are classified by their material and composition, degree of integration, number of transistor elements, principles of operation, manufacturing method and device type. Table 1.1 indicates how ICs are classified by integration level.

Table 1.1 Advances in IC integration [2]

Integration Level

Numbers of Transistors

Equivalent Gates

Typical Functions of Systems

Typical Number I/Os

SSI 1-40 1-10 Single Circuit Function (e.g., Transistors) 14

MSI 40-400 10-100 Functional Network 24

LSI 400-4,500 100-1000 Hand Calculator or Digital Watch 48

VLSI 4,500-300,000 1,000-80,000 Microprocessor 64-300

ULSI Over 300,000 Over 80,000 Small computer on a chip 300+

GSI 1 Billion Over 100 Million Supercomputer 10,000+

An IC can be a single component such as a power amplifier or a power transistor or they can have many components such as a fully integrated microprocessor used in modern PCs and high performance servers and workstations. System-on-chip (SoC) is a concept where electrical optical, mechanical, chemical, and biological devices are integrated on a single chip. There are many types of ICs based on different applications as illustrated in Fig 1.1.

Fig. 1.1 Types of ICs based on different applications. [2]

Table 1.2 ITRS packaging requirements [2]

Year 2005 2008 2011 2014 Low Cost

Cost (Cents/pin) 0.29-0.66 0.25-0.57 0.22-0.49 0.19-0.42 Power (Watts) 2.4 2.5 2.6 2.7 I/O count 109-395 160-580 201-730 254-920 Performance (MHz) 100 125 125 150 High Performance

Cost (Cents/pin) 2.28 1.95 1.68 1.44 Power (Watts) 160 170 174 183 I/O count 3158 4437 6234 8758 Performance (GHz) 1000 1250 1500 1800

One section of the ITSR (International Technology Roadmap for Semiconductors) specifically defines the packaging requirements of ICs. The most demanding projections for some of the important parameters such as cost, power, I/O count, and operating frequency for low-cost and high performance product categories are shown in Table 1.2.

The combined science of ICs and packaging is referred to as packaged devices or IC packaging [2]. Examples of packaged device technology include the microprocessors in a typical


PC. The overlap of ICs and systems can be referred to as sub-products that perform a partial system function and typically dont involve extensive packaging. These sub or complete products depend heavily on the high integration of ICs without depending on packaging in order to meet a variety of product functions. In the progression of systems technology, this approach is predicted to evolve into system-on-chip (SoC).

System-on-board (SoB) consists of a number of packaged ICs and other components assembled onto a system-level board. A new paradigm called system-on-package (SoP), or system-in-package (SiP) is analogous to SoC, in that it is a single component, multi-function, multi-chip package providing all the needed system-level functions. These functions include analog, digital, optical, RF and MEMS. Both SoC and SoP are expected to play an important role in the future of electronic systems [2].

Fig. 1.2 Integration of IC, Packaging and System [2]

In general, IC packages can be classified into two categories, through-hole, and surface mount (as shown in Fig. 1.3) depending on the methodology used to attach the packages to the printed wiring board (PWB).


Fig. 1.3 Types of IC packages (a) Through-Hole (b) Surface Mount [6]

Dual-in-line packages (DIP) and pin grid arrays (PGA) are through-hole packages. The small outline (SO) package is the most widely used package in modern memory for low I/O applications because of its extremely low cost. The quad flat package (QFP) is an extension of the SO package with more I/O connections. Both the SO and QFP packages have leads attached to the printed wiring board (PWB).

In the late 1980s, packages with solder balls were developed as an alternative to packages with leads. Surface mount packages have the advantage of a higher packaging density on the board compared to through-hole packages. LCC (Leadless Chip Carrier) and PLCC (Plastic Leaded Chip Carrier) are leadless packages. Ball grid array (BGA) packages are another example of this technology.


1.2 Function of Electronic Packaging

IC packaging has three important parameters: [1] The amount of I/O which determines the pitch of the IC package as well as the wiring needs at the system level, the size of the IC which affects the reliability of the IC to package connection and the power which affects the heat dissipation properties of IC and system level packaging.

The functions of an IC package are to protect, power, and cool the microelectronic device and to provide an electrical and mechanical connection between the chip and the outside world. The package for an IC must provide a structure to physically support the chip, a physical housing to protect the chip from the environment, an adequate means of removing heat generated by the chip or system, electrical connections to allow signal and power access to and from the chip, and a wiring structure to provide an interconnection between the chips of an electronic system. These basic functions are illustrated in Fig. 1.4.

Fig. 1.4 Basic electronic package functions.

In addition to the four basic requirements listed above, an electronic package must be consistent with requirements for a high quality, reliable, serviceable, and economical product at its designed performance level.


1.3 Packaging Hierarchy

Typical electronic systems have several layers or levels of packaging, and each level of packaging has distinctive interconnection devices associated with it. The hierarchy of interconnection level can be divided is as follows:

Level 0: Gate-to-gate interconnections on a monolithic silicon chip Level 1: Single-chip package, MCM, chips Packaging of silicon chips into dual-in-line packages (DIPs), small outline (SO) ICs,

chip carriers, multichip packages and the chip level interconnects that join the chip to

the lead frames. Instead of lead frames, tape-automated bonding (TAB) or chip on-

board (COB) technologies can be utilized.

Level 2: Printed wiring board (PWB) or Printed Circuit Board (PCB) Printed conductor paths connect the leads of components to PCBs and to the electrical

edge connectors for off-the-board interconnection

Level 3: Backplane (Equipment Drawer) connections between PCBs. PCB-to-PCB interconnections or card-to-motherboard interconnections Level 4: Equipment rack connections between two subassemblies. A rack or frame hold several shelves of subassemblies that must be connected together

to make up a complete system.

Level 5: Connections between physically separate systems such as host computer to terminals, computer to printer, and so on.

Fig.1.5 Electronic Packaging Hierarchy [1]


1.4 Driving Forces of Packaging Technology

Historically, packaging has always been a substantial fraction of the price of an IC (10 to 50%). Cost and performance are the primary concerns in electronic packaging. In general, packaging costs are driven by the materials and fabrication requirements associated with the actual manufacturing and by the testing and rework associated with manufacturability. In the case of multi-chip packaging, manufacturing costs affected by the reliability of the IC chips, generally referred to as known good die. Performance is a function of electrical, thermal, and mechanical design constraints, material selection, and fabrication limitations.

1.4.1 Electrical Packaging Design Consideration

Fig.1.6 Electrical Design Procedure of Electronic Package [ 3]

Packages provide semiconductor ICs with signal and power distribution. The package helps to distribute signals between chips and to supply voltage and current to the circuits within a chip, as well as to other ICs in a system. As illustrated in Fig. 1.6, the electrical packaging designer has to consider the optimal signal and power distribution of the package structure.


Fig.1.7 Electrical Design Issues (Power and Signal Distribution) [2]

The electrical functions of a package are illustrated in Fig. 1.7. In this figure, the package provides the signal path from the driver circuit in one chip to the receiver circuits in other chips, the power supply and ground connection to the chips, and support connections between passive devices. The signal path in the package is composed of bonding structures that act as an interface between the chip and package, transmission lines on the substrate, and vias that provide vertical connections. Through the signal path, chips exchange data, address, clock, and control signals with each other. The package supplying the power to the chips needs to have sufficient charge storage capability to supply the necessary amount of current with negligible power supply voltage fluctuations. The parasitic inductance of the power distribution and the bonding structures in the package must be minimized to ensure that they do not degrade the power supply. The use of power plane structures in the package provides more capacitance and less inductance.

The package may also contain lumped passive circuit elements such as resistors, inductors and capacitors. The capacitors in the package can be used to supply charge to the power supply of the chip and to isolate the inductive parasitics of the bonding structures. Lumped chip capacitors that are currently mounted on the surface or at the bottom of the package may be replaced with embedded capacitors buried inside the multilayer package. The embedded resistors may be used to terminate signal lines to avoid signal reflections from the ends that cause unwanted high-frequency noise and signal propagation delays.


Fig. 1.8 Parasitics in the Electronic Package [4]

The primary technical challenge for electrical design is driven by the frequency spectrum of the signals. At low frequencies, signal and power paths are easily realized since the physical geometry of the interconnection has little effect. At higher frequencies (1 GHz and up), the realization of appropriate interconnections is more difficult. At high frequencies, interconnects are physically longer than the packets of energy routed along them, and their behavior depends on the properties of the materials and the electromagnetic fields that comprise the signal. Effects such as propagation delay, the characteristic impedance associated with interconnect configurations, and parasitic reactances determine the behavior of the signal. Hence, the degree of distortion of the signal and the time required for the signal to reach its destination are functions of the interconnect parameters as illustrated in Fig. 1.8. Since the frequency of the signal generally dictates the rate at which power is required by the chips, similar concerns apply to the power and ground paths as well.


1.4.2 Electrical Packaging Design Process

Electrical package design is the process that defines the electrical signal and power paths through the package in a way that meets the overall system requirements. Ultimately, the end result of the design process is the geometrical layout of interconnects and the specification of materials and their geometries needed to meet the system requirements. The electrical design procedure of the package starts with the determination of the electrical specifications for the package. Basically, these specifications are based on the system and chip performance.

Fig. 1.9 Electrical Packaging Design Process [2]

The package designer must have access to the various technologies supported by a set of ground rules and material properties. From physical parameters such as minimum line width (w), spacing(s), thickness (t), dielectric thickness (d), dielectric constant (r) and conductivity (); the electrical parameters for the interconnections such as resistance (R), inductance (L), capacitance (C) and conductance (G) are extracted using electromagnetic modeling tools. These parameters are used to build the interconnection models in a circuit simulator such as SPICE.

2. Trends in Electronic Packaging Technology An emerging trend in electronic packaging technology is the convergent system or a

system that is characterized by the integration of diverse product functions into one package or product. [5]


Fig.2.1 Trend to convergent and miniaturized electronic and bio-electronic systems [5]

Recent electronic packaging technology, referred to as multi-chip packaging (MCP), integrates an electronic system by interconnecting a number of ICs in a single packaging structure. MCP technology is done either by multi-chip modules (MCMs) in the planar fashion or by 3D stacked-chip packaging referred to as system-in-package (SiP) which incorporates ICs stacked vertically. Chip stacking can be accomplished by either stacking single-chip packages or by stacking a number of chips in a single package, or a combination of these approaches.

More recently, wafer-level packaging (WLP), which involves creating the package while chips are still in wafer form and then separating them by dicing, is gaining popularity.[5] Wafer-level packaging of stacked wafers has the stacked chips interconnected by vias formed through the material used to physically separate the wafers. Thus, system packaging at the wafer level is possible and will permit the mixing of different technologies in a single package.

There is also a relatively new concept which is called system-on-package (SoP) that addresses the shortcomings of both SoC and SiP in two ways. SoP uses CMOS-based transistor integration and RF, optical and digital integration by means of IC-package-system co-design. System-on-package (SoP) helps to overcome both the computing limitations and integration limitations of SoC, SiP, MCM and traditional system packaging. SoP includes both active and passive components including embedded digital, RF and optical components and functions in a microminiaturized package or board.


Fig. 2.2 Electronic Package Evolution Trends


2.1 Recent Trends in Advanced Electronic Packaging

Traditional electronic packaging presents significant problems. The IC packaging which provides I/O connections from the chip to the rest of the system is typically bulky and costly, limiting both the performance and the reliability of the IC. In addition, system packaging that provides the interconnection of components on a circuit board is similarly bulky and costly and limits the electrical and mechanical performance. To address these concerns, current trends in electronic packaging technology fall into two categories; the high performance system packaging and mobile platform packaging.

Fig. 2.3 Recent Electronic Package Trends

The quest for small, better integrated packaging is primarily being driven by portable and wireless products such as cellular phones, which demand portability and lower cost. This type of packaging, called form-factor packaging has led to new directions in both IC and systems packaging. These include a variety of wafer level technologies such as chip scale packaging (CSP), thin film organic package technologies pioneered originally by IBM in Japan called surface-laminar circuit (SLC) or build-up technology, and flip-chip to organic assembly also pioneered by IBM.

Another trend in packaging technology is being driven by high performance products such as servers with microprocessors. These products require a more effective power distribution system, as the platform of the processor requires lower voltage levels and more power consumption at the same time.


Fig. 2.4 some of more than 30 companies currently pursuing SiP [5]

System-in-package (SiP) technology (the vertical stacking of similar or dissimilar ICs) is one way to address this challenge. ICs can be stacked bare or stacked as packaged structures. SiP has clear benefits relative to SoC such as simpler design and design verification, IC processing with minimal mask steps, minimal time-to-market, and minimal IP issues. Because of these benefits, about 30 IC and packaging companies have been gearing up to produce SiP-based multichip modules. SiPs come in many flavors as fabricated in organics, ceramics or Si wafers.

Fig. 2.5 Advanced Packaging Technology Roadmap by NEC [10]

2.1.1 Trends in the Electronic Packages for Mobile Platforms

Because mobile platforms have faster development cycles than most other products, reliable predictable package technologies that maximize cost and performance are essential. The traditional mobile platform is divided into RF and baseband parts. Although the integration of these parts into one has been attempted, traditional RF Front-end-Module areas are still required.


Fig. 2.6 Shrinking Radio Technology [8]

Chip Scale on Package (CSP) Technology Apples iPod Nano

Fig. 2.7 iPod Nano with main chips packaged in CSPs [9]

The iPod Nano contains SDRAM, a processor, a memory controller, a switching regulator and a power management IC packaged in CSPs shown in Fig. 2.7.

Fig. 2.8 Comparison with CSP & QFP structure [10]


Chip scale package (CSP) is a general term for a cutting edge semiconductor package that is close to the same size as the bare chip itself. CSPs are generally BGA (Ball Grid Array) or LGA (Land Grid Array) packages, in which electrodes are directly installed on the package bottom, thus making it slightly larger than the chip size. This package can be used to make ultra-small and ultra-thin semiconductor devices, and thus has been mainly used for electronic products requiring a small implementation area on the board. [10]

Wafer-Level Chip Scale on Package (WL-CSP) Technology Nokia 702 Wafer-level packaging (WLP) refers to the technology of packaging an integrated circuit at

wafer level, instead of the traditional process assembling the package of each individual unit after wafer dicing. WLP is essentially a true chip-scale packaging (CSP) technology, since the package size is practically of the same as the die. Furthermore, wafer-level packaging can accomplish true integration of wafer fab, packaging, test, and burn-in at wafer level. Thus, the device manufacturing process can be streamlined ultimately using WLP technology.

Fig. 2.9 Photos of two wafer-level packaged devices from Dallas/Maxim; Source: www.maxim-ic.com


Fig. 2.10 WL-CSP Examples Nokia 702 Main Board [9]

Wafer-level packaging (WLP) is basically an extension of wafer fab processes including device interconnection and protection processes. Although there is no single industry-standard method, according to an article in www.future-fab.com, at least four major WLP technology classifications exist today. The four classifications according to Prismark and TechSearch International are:

1. Redistribution Layer and Bump technology, which is used by: Amkor (Ultra CSP), Apack, Aptos, ASE (Ultra CSP), ASAT Chipbond, Dallas Semi (2 lead), FCT (Ultra CSP), Fraunhofer Institute, FuPo, Hitachi, Hyundai, National Semi (SMD), PacTech, Sandia Labs, Seiko Epson, SPIL (Ultra CSP), Unitive (ExtremeCSP);

2. Encapsulated Copper Post technology, which is used by: Casio, Fujitsu (SuperCSP), IEP, Oki Electric, TI, Shinko (SuperCSP license), Toshiba;

3. Encapsulated Wire Bond technology, which is used by: Form Factor (Wow, MOST), Shinko, Hyundai, Infineon (Wow licensees); and

4. Encapsulated Beam Lead technology, which is used by: ChipScale (Intarsia, M-Pulse Microwave), ShellCase (ShellBGA), and Tessera (WAVE).


Redistributed Chip Packaging (RCP) Technology Freescale Redistributed chip packaging (RCP) is an interconnect buildup technology in which the

package is a functional part of the die. This technology addresses the limitations associated with previous generations of packaging technologies by eliminating wire bonds, package substrates and flip chip bumps. In addition, RCP does not utilize blind vias or require thinned die to achieve thin profiles. These advancements simplify assembly, lower costs, and provide compatibility with advanced wafer manufacturing processes utilizing low-k interlayer dielectrics.

Fig. 2.11 RCP and other package structures [11]

Exceptional flexibility makes it a virtually universal package technology that is compatible with advanced assembly technologies such as System in Package (SiP), Package on Package (POP) and integrated cavity packages. RCP has the potential to increase the performance of products for the wireless, industrial, networking, and transportation markets. Freescale expects to ship products that utilize RCP by 2008.

Fig. 2.12 Radio in Package, an Example of RCP by Freescale [11]


System-In-Package (SiP) Technology

System-in-package (SiP) technology configurations can be divided into four categories such as stacked die inside CSP, package-on-package (POP), package-in-package (PIP) or stacked module package and planar constructions. Stacked die CSP is the thinnest solution within the categories. Die are typically thinned and stacked inside the package that contains two or more die. Wire-bond is most common interconnection method, flip-chip is increasing. The substrate is typically a flex circuit or laminate.

Fig. 2.13 Stacked Die CSP Structure by Intel [9]

Package-on-package (POP) technology involves stacking separate packages for logic and memory. At least 10 major OEMs in the handset and digital still camera market are trying to implement a POP structure in their products.

Fig. 2.14 Package-on-Package Structure by AMKOR [9]


Fig. 2.15 PIP structure (before final overmold) [9]

Package-in-package (PIP) technology involves two or more packages assembled together and overmolded, resulting in a single package that connects to the products circuit board. Typically PIP is more expensive than stacked die package, but allows for flexibility in configuration of the memory and full testability before assembly. This technology has been implemented by IC package subcontractors such as STATSChipPAC and Amkor.

Fig. 2.16 Intels Folded Stacked Configurations [9]

Fig. 2.17 Intels SiP in Motorolas E680 Tri-band phone [9]

Fig. 2.16 and Fig. 2.17 show the folded flex technology adopted in Motorolas E680 Tri-band phone. Folded flex technology uses two-metal-layer tape.


RF System-In-Package (SiP) SyChip

An RF system-in-package (SiP) includes an RFIC, PA, LNA, balun, filter, switch, and antenna. A more integrated approach could also include a base-band IC. Large passives (inductors, capacitors, resistors) may be integrated for cost and performance reasons. 0201 SMD packages are currently most efficient in modules. 0105 SMDs are the next step but they currently have higher component and assembly costs. The ultimate goal of SiP for RF modules is minimizing the sizes of all passives (RLC and functional blocks).

Fig. 2.18 Package evolutions into smaller form-factor and more functionality in Wireless LAN 802.11[8]

System in Package NEC SMAFTITM SMAFTI (SMArt connection with Feed-Through Interposer) technology features a three-

dimensional chip connection with a 50-micron pitch that can support transmissions up to 100 gigabits per second (Gbps), ten times faster than conventional technologies. Designers who use SMAFTI technology in cellular phones and other portable equipment that have stringent size and power constraints can achieve resolutions comparable to those achieved in high-definition television.

Fig. 2.19 SMAFTI (SMArt connection with Feed-Through Interposer) structure [10]

This technology uses a 7-micron-thick polyimide dielectric layer and copper interconnects 15 microns wide to build up trace routing to an interposer layer, creating vertical interconnects with a 50-micron-pitch. A plastic compound encapsulates the package. A typical size is 15 mm on a side. SMAFTI utilizes an interposer that eliminates thermal mismatch between the memory and


logic die. The die are probed at the wafer level and attached to the interposer. This approach creates wafer-level wiring using lithographic patterning and a semi-additive process. Die are attached to the wires and encapsulated, and the rest of the silicon wafer is removed. Then the second chip is attached to the interposer. Ball grid arrays are used to connect the finished package to the system board with a 500-micron spacing. The company expects to use the SMAFTI for internal products targeted at NEC's own 3G cell phone business group, as well as selling it to external customers.

LGA (Land-Grid-Array) Freescale The LGA package is a standard flip-chip ball grid array (BGA) shipped with no spheres.

Fig. 2.20 (a) shows the top and bottom sides of an LGA device. LGA has been available for hand-held devices in a small plastic package from Freescale and others for several years. Freescale is now introducing the LGA package using a high coefficient of thermal expansion (HCTE) ceramic in larger body sizes. The LGA solder interconnect is formed solely by solder paste applied at board assembly because there are no spheres attached to the LGA, resulting in a lower stand-off height of approximately 0.06 mm to 0.10 mm, depending on solder paste volume and printed circuit board (PCB) geometry.

Fig. 2.20 (a) Top and Bottom View of a HCTE 360 Pad LGA Devices (b) Unmounted Device Profile (BGA on Left, LGA on Right) [12]

2.1.2 Electronic Packaging Trends in High-Performance Platforms

(a) PGA Package and Socket


(b) LGA Package and Socket

Fig. 2.21 Comparison between PGA and LGA package and socket [13]

High-Volume Land Grid Array (LGA) Technology for Pentium IV Processor Traditionally, in desktop personal computer (PC) platforms, the state-of-the-art socket

technology for organic packages has been a surface-mounted Micro-Pin-Grid-Array (PGA) socket. However, PGA technology imposes limitations on the electrical and thermal capability and form-factor requirements of next-generation platforms. Land-Grid-Array (LGA) socket technology was developed as a means to avoid those limitations.

As shown in Fig. 2.22 (a), power is supplied from the voltage regulator through the pins from two sides on the package. Power delivery performance is limited by the power distribution (PD) architecture and motherboard real estate.

Fig. 2.22 (a) Old PD Architecture for Single-Core Servers

Fig. 2.22 (b) Novel PD Architecture for Multi-Core Servers [13]

A novel PD Architecture for Multi-Core Servers is illustrated in Fig. 2.22 (b). The performance has improved by a four-sided power delivery scheme. Also, the dedicated power connector is more scalable. Voltage regulator (VR) components are moved to the VR board to free up motherboard real estate. A new TIM3 material was introduced to cool VR components.


System in a Package (SiP) Solution for DC-DC Converters AMKOR

Historically, DC-DC converters have been provided either as a discrete solution or pre-packaged in a single inline package. A system-in-package with very few external passive components is an alternative. This solution includes a bare die controller/driver IC, bare die FETs and the majority of the required passive components mounted on a thermally enhanced substrate with LGA (land grid array) pads.

Fig. 2.23. An Example of System-in-Package Solution for DC-DC Converters [14]

System in package (SiP) is generally defined as one or more semiconductor chips along with passive components integrated onto a substrate, which together forms a functional sub-system. This integration offers the following advantages: SiP simplifies the OEM product design and assembly by modularizing certain functions, allows standardization of sub-systems across products, and improves time to market. It improves electrical performance through proximity of die and critical passives, increases functionality in a fixed board space, or reduces the space required for a specific function and reduces system level assembly costs

The SiP is a chip array style package and is transfer molded. This limits the overall package height and means that the few higher profile capacitors and inductors must be external to the integrated package. Because SiP is transfer molded, it can be tested, packaged and assembled by the OEM, using industry standard, high volume equipment. Solder balls are used for the external I/O. They are generally required when the I/O density is high. However I/O count is normally low in a DC-DC converter, LGA is a more practical solution. More importantly, LGA has lower thermal resistance and provides a more reliable 2nd-level solder joint.


Fig. 2.24 Comparison of the characteristics between SiP and SoC [7]

2.1.3 CoC (Chip-on-Chip) Technology Trends in Japanese Industry

A new chip-on-chip (CoC) semiconductor packaging technology has been developed, offering high performance at low cost for a wide range of equipment including digital household appliances, mobile gear, servers and routers. Until now, mounting memory and logic in the same package has required a system-on-chip (SoC) approach using dynamic random access memory (DRAM) technology, or a system-in-package (SiP) solution connecting the chips to each other with wire bonding. Each approach has its own advantages and disadvantages, but it has been difficult to achieve both high-capacity memory and high-speed data transfer between memory and logic. CoC packaging fulfills both demands simultaneously with a manufacturing cost significantly lower than merged DRAM. Different CoC architectures are illustrated in Fig. 2.25.


Fig. 2.25 Different Architectures for Different CoC Applications [7]

Table 2.1 shows representative CoC packaging techniques outlining the specifications designed for commercial applications.

Table 2.1 Representative CoC Technologies [7]


System Fabrication Technologies mounts multiple logic ICs, memory chips, etc on a silicon interposer on the Si wafer, which has chip-to-chip interconnect wiring as illustrated in 2.26. There are no restrictions on the footprint of the stacked chips, and the memory chip can be larger than the logic IC. The Si interposer is connected to the plastic interposer with wire bonding, etc

Fig. 2.26 Mounting Multiple Chips with a Silicon Interposer [7]

2.1.4 Trends on the IC Substrate Technology

The electronic packaging industry has been crippled by the incremental technology advancement in substrates over the past decade. While semiconductors and related packaging technologies progress at a rapid rate, typically doubling in functionality every couple of years, the substrate portion of the IC packaging industry continues to fall further behind. This has created a technology gap, forcing the semiconductor manufacturers to compromise their chip designs by adding more redistribution layers or even increasing the size of the chip itself. Thus, the IC packaging industry is in need of a significant change at the substrate level to remove the barriers that exist today. Figure 2.27 illustrates substrate technology evolution trends.


Fig. 2.27 Substrate Technology Evolution Trends (Source: JIEP, APC)

Substrate Technology for RF SiP Modules can be divided into 4 categories: Laminate Module, LTCC, Liquid Crystal Polymer and Si/Glass/GaAs as illustrated in Fig. 2.28. Laminated modules are traditionally and widely used for passives. Assembly for the laminated module is relatively easy compared to other technologies. Low-temperature co-fired ceramic (LTCC) Modules are good for power circuits, as they have good thermal and electrical properties. However, their assembly cost is relatively high. Liquid crystal polymer (LCP) techniques are used to provide low loss LCP layers in printed circuit boards for RF performance. High-Q inductors can be readily embedded using liquid crystal polymer (LCP) techniques. Si, Glass, GaAs Modules are used to achieve the highest possible integration from base-band circuits to the antenna port.


(a) Laminate Module (b) LTCC

(c) Liquid Crystal Polymer (d) Si, Glass, GaAs Fig. 2.28 Substrate Technology for RF SiP Modules [8]

SFC (Smart Functional Circuit) - SEMCO Samsung Electro-Mechanics developed a 0.32-mm thick 6-layer prototype substrate

embedded with an LSI chip. The thickness of the embedded LSI chip was 0.08 mm. This LSI-embedded substrate is a 10 x 10 mm interposer targeting mobile equipment applications.

Fig. 2.29 0.32-mm Thick 6-Layer Substrate Embedded with LSI by SEMCO


Samsung Electro-Mechanics also showed several other embedded substrates for interposers, such as a substrate incorporating 0603 multilayer ceramic condensers and chip-type resistors as well as one mounting thin-film type condensers with 16 pF/mm2 capacitance and another one containing a wiring layer embedded with resistors.

Fig. 2.30 SFC (Smart Functional Circuit) by SEMCO

Embedded Component/Die Technology STI Electronics

Fig. 2.31 Embedded component/die technology by STI Electronics

STI Electronics was awarded a patent for its embedded component/die technology (IC/DT), which involves the use of integrated circuits embedded within a laminate substrate on a thermally conductive core providing a thermal sink. STI applied for the patent on May 23, 2003.


Integrated Module Board (IMB) technology - Imbera

Imbera Electronics has developed an Integrated Module Board (IMB) technology which integrates active components into electronic modules and high density printed circuit boards. The IMB process combines PCB manufacturing, component packaging, and assembly into a single manufacturing process. All interconnections between the IC and substrate are processed simultaneously.

Fig. 2.32 Integrated Module Board (IMB) technology by Imbera

Diverse IC and Passive Component Integration Technologies Six to seven years ago, Casio Computer & CMK has developed an IC embedded in board

using wafer-level CSP technology. The IC was 400 m thick and board was 600 m. Three ICs were embedded. The substrate size was 16 mm square. As shown in Fig. 2.33 (a), Matsushita Electric Industrial developed components that are pressed into place while heating dielectric film, deforming it to embed the components. For this reaction, the glass fiber (used as reinforcement in standard boards) was removed from the dielectric layer. The board substrate size was 1.2 mm thick, and the component spacing was 150 m. Tests are underway to evaluate embedded bare chips, WL-CSP, and 50 m thick ICs.

DENSO also developed a board with both embedded passives and ICs. The embedded components included 16 resistors and capacitors with a 1608 size. The bare chip was 9 mm square 0.65 mm, and board thickness was 29 layers of 75 m plastic sheet. The board size was 25 mm square.

(a) by Matsushita (b) by Denso

Fig. 2.33 Diverse IC and Passive Component Integration Technologies



2.2 Future of Electronic Packaging Technology 2.2.1 Future Design Issues of Electronic Packaging Structure

As the operation frequency of the on-chip silicon system is higher than data rates that can be sent on the interconnects, the package is already the bottleneck to the system performance. Furthermore, as the cost of bare silicon chips goes down, the portion of the manufacturing cost attributed to the packaging is becoming higher, resulting in a trend toward higher circuit densities and operating speeds on a chip.

Interconnections are lossy transmission lines in higher frequency applications, so the quality and timing of the electric signal can be affected. New methods for signal distribution are necessary in the future. The parasitics associated with the interconnections for signal communication affect the product quality. Low-loss, low-relative-permittivity dielectric insulating materials will be necessary to reduce the delays associated with interconnects. Also, reflections will have to be suppressed through various termination schemes. Controlling crosstalk will continue to be an important consideration affecting the quality and timing of the signal.

Supplying clean power to the chips will also be a major bottleneck in the near future. Power planes within the package and board will be necessary to provide a low impedance power source at high frequencies. The power distribution for the core and I/O will need to be separated to avoid noise coupling caused by the planes. This will require new and efficient ways of supplying power to the chips. Decoupling at frequencies greater than 1 GHz is likely to become a major problem requiring integrated decoupling solutions.

2.2.2 Future Concept of the Advanced Electronic Package

System-on-chip (SoC) solutions, which try to integrate numerous system functions on one silicon platform (chip) horizontally, will place fundamental limits on the computing and integration density for the cost effective and high performance applications in the future.

The disadvantages of SoC are the long design times due to integration complexities, high wafer fabrication costs, test costs, and mixed-signal processing complexities requiring dozens of mask steps and IP issues. Therefore, a new paradigm to overcome the shortcomings of both SoC and traditional package structures is necessary. Electronic packages for digital convergence of the system can be divided into four basic approaches: SoC (System-on-Chip), MCM (Multichip Module), SiP (System-in-Package), and SoP (System-on-Package) as shown in Fig. 2.34.

Fig. 2.34 a) System-on-Chip (SoC) based on a complete system on one chip; b) Multi-Chip Module (MCM) based on interconnected components; c) System-in-Package (SiP) based on a

stacked chip/package for reduced form factors; and d) System-on-Package (SoP), offers the best of IC and packaging technologies by optimizing functions between ICs and the package while

miniaturizing systems. [5]

The SoP concept overcomes a number of the engineering limits of SoC. As IC integration moves to nano-scale and wiring resistance increases, the global wiring delay in SoC becomes too high for computing applications. SoP can handle the latency due to the wiring delay by either moving global wiring from the nano-scale on ICs to the micro-scale on SoP or making the digital chips much smaller. SoP can handle the wireless integration limits of SoC also. RF components such as capacitors, filters, antennas, switches, and high frequency and high Q inductors, are best fabricated in the package rather than on silicon. To meet the amount of decoupling capacitance necessary to suppress the expected power plane noise due to very high performance ICs requiring more than 100 watts per chip, a major portion of the chip area will have to be dedicated to decoupling capacitance.


Fig. 2.35 SoP concept of system integration of components [5]

SoP concept seeks to integrate multiple system functions into one compact, light-weight, thin profile, low-cost, high performance packaged system requiring high performance digital logic, memory and graphics, and analog signals for RF and video as well as broadband optical functions. Unlike SoC, however, no performance compromises have to be made in order to integrate these disparate technologies since each technology is separately integrated into the SoP package. In addition, the SoP concept allows for shorter time-to-market and greater flexibility. The chip size within SoC concept can be as small as required to be manufacturable with high yields and its wiring length can be as small as needed to overcome the high resistance-imposed global signal delays. SoP concepts can achieve the ability to integrate digital, analog and mixed-signal devices in a single module with not only RF and optoelectronic devices, but also sensors and bioelectronic components.


Fig. 2.36 Difference between SiP and SoP concepts [5]

SiPs can easily combine digital chips with passive devices. However, they are often limited by the use of CMOS to play the role of a packaging or sub-system technology, rather than a system-level technology. SOPs go further than SiPs by incorporating multiple dissimilar components and materials, such as silicon, gallium arsenide (GaAs) and silicon germanium (SiGe), as well as passives. SOPs utilize systems-on-chips for IC integration, along with SiP, multi-chip module (MCM) and 3D chip stacking techniques for package integration, and MEMS, optoelectronic and RF components for system-level integration. SOPs use thin-film component integration to achieve multi-function packages.

One of the most compelling features of SOPs is the fact that they are not SOCs. Like the ASICs they are based on, SOCs require very long development times, and are quite costly. For these reasons, SOCs are only feasible for very high-volume applications where economies of scale can maintain a low cost per unit. SoP technology, along with the SiPs and chip stacking techniques it incorporates, can more quickly combine the dissimilar materials and process technologies required for highly complex, highly integrated system-level designs. SOPs partition the system into the most cost-effective and appropriate functional blocks based on each component's requirements, and overcome the shortcomings of SOCs, in particular, latency and global delays, as well as RF integration. SOPs require new materials for the package and the printed circuit board (PCB) that combine the best electrical, mechanical and thermal characteristics. New substrate technology for the embedded actives and passives is required to realize SOPs as illustrated in Fig. 2.37.


Fig. 2.37 Integrated Substrate Technology Concepts and Evolution

To achieve the best possible SoP designs, co-design and co-fabrication practices are needed to optimize the functions in the ICs via SoCs and those best implemented in the package itself using SiP and/or 3D techniques. The entire system including the chips, package, and PCB must be designed through collaboration.

Fig. 2.38 Basic & Core Technology for the Implementation of SoP [15]


3. Critical Issues for Decoupling Capacitors

A decoupling capacitor is used as a low impedance current source to minimize supply voltage fluctuations caused by rapid switching of the active devices. Typically, the decoupling used for silicon processors occurs in multiple stages ranging from large bulk capacitance devices physically located near regulated power supplies, to board-level capacitors to stabilize the voltage supply on the PCB, to package-level decoupling incorporated on the processor package, and die-level capacitance located on the die itself. This decoupling network accommodates current pulses moving through the system between the Si chip and the regulated voltage supply.

The required response time of capacitors necessarily increases as the current moves towards the processor. The impedance versus frequency behavior can be used to characterize the decoupling capacitor response time. At relatively low frequencies, low impedance is achieved with high capacitance (i.e., low capacitive reactance). At relatively high frequencies, low impedance is obtained with low inductance; and of course, at series resonance, low impedance directly correlates to low series resistance. Therefore, to make a capacitor work at the highest possible frequencies, it should have the lowest possible inductance.

Fig. 3.1 System Decoupling Loops for PCB-mounted decoupling capacitors [16]

3.1 Electrical Characteristics of Capacitors When considering the parasitics of bypass capacitors, a widely used simple model is a series

C-R-L network, where C is the capacitance of the part, R is the Equivalent Series Resistance (ESR) and L is the Equivalent Series Inductance (ESL). The capacitance may be frequency dependent, primarily due to dielectric losses. The inductance is determined by the connection of the capacitor to the rest of the circuit as well as the geometry of the capacitor itself.


Fig 3.2 Simple RLC equivalent circuit of a capacitor (Left) and vertical cross section of an MLCC mounted to PCB planes (Right) [17]

Fig 3.3 Bypass Capacitor Impedance vs. Frequency, MHz

In a multi-layer capacitor (MLCC), the inductance is higher at low frequencies where the resistance in the copper plates forces the current to flow uniformly through all plates. At high frequencies the current flows in the lowest inductance path and is concentrated on the lower plates.

3.1.1 Low Inductance Path (ESL)

The parasitic inductance of MLCCs is becoming more and more important in the decoupling of high speed digital systems. The relationship between the inductance and the ripple voltage induced on the DC voltage line can be seen from the simple inductance equation, V=Ldi/dt. The parasitic inductance is a result of the interaction of magnetic flux fields created by the electric current flow in and out of the device on a circuit board.


Fig. 3.4 ESL in a mounted MLCC directly relates to the area of an idealized current loop (LHLW) formed in the board and capacitor [19]

The current path or loop includes not only the multilayer capacitors internal electrodes and external termination, but also the power planes, vias, mounting pads and solder fillets of the substrate/packages. At very high frequencies, the current path is not defined by the entire capacitor multilayer stack, most of the current is confined to the lowermost internal electrodes as the path of least impedance for the current flow.

Fig. 3.5 Mounted Bypass Capacitor Induction Loop [20]

This induction loop above the plane cavity is a function of no fewer than nine independent variables which are completely beyond the control or even knowledge of the component maker:

Capacitor size Capacitor terminal configuration Capacitor bottom cover layer thickness Via extension height above the uppermost plane Via count Via diameter Via separation X-Y plane offset of vias from device pad


Etch configuration of the surface layer

Fig. 3.6 Bypass Network Induction Loop Components [21]

3.1.2 Controlled-ESR [22]

Low-Q bypass capacitors with controlled ESR can be used to create a resonance-free power distribution network (PDN) with low sensitivity to component tolerances, and achieving a predictable impedance profile with the minimum number of components. Low-Q bypass capacitors can be created either by reducing the inductance of the part, and/or by raising the equivalent series resistance (ESR). In multi-layer capacitors, ESR can be raised by using resistive plates, and/or resistive terminations, or by adding resistance externally with low inductance. Low-resistance capacitor plates can be patterned outside the high-frequency current loop as shown in Fig. 3.7. In thin-film capacitors, ESR can also be raised by reducing the thickness of capacitor plates.

Fig. 3.7 Adjusting MLCC ESR by changing the connection geometry of capacitor plates [22]


Fig. 3.8 Three construction options to add resistive material to MLCC [22]

As shown in Fig. 3.8, series resistance can be added by incorporating highly resistive material into the capacitor construction: resistive capacitor plates, resistive terminations, or low-inductance external embedded resistors.

3.1.3 Distributed Capacitor Models

A transmission line circuit model has been proposed that mimics the construction of MLC capacitors and mounting structures as discussed in the previous section. The topology of the model is shown in Fig. 3.9. [18]

Fig. 3.9 Transmission line circuit model for MLC capacitor [18]

The capacitance of the working plates is represented by capacitors that are effectively in parallel at low frequency (Cp). The ESR is mostly in the conductive plates and is represented by the resistors (Rp) which are also effectively in parallel at low frequency. Because of the many thin ceramic dielectrics and relatively wide dimensions of the conductive plates, the inductance associated with the horizontal plates is very small.



The dominant inductance of the capacitor is associated with the vertical dimensions and mounts. Lbottom is the inductance assigned to the portion of the loop near the filler plate. The loop area is further increased as current proceeds up the terminals past the working plates of the capacitor. These vertical inductances are in series and are designated Ls. The comparable series resistance is designated Rs. The frequency dependent nature of the capacitor can be envisioned by considering the relationship between the vertical and horizontal components of this model. At low frequencies, the relatively high reactance of the capacitance 1/ (jC) dominates over the reactance of the series inductance jL. At high frequencies (above series resonance) the impedance roles of the inductance and capacitance reverse. The relatively high reactance of the Ls inductors dominates and impedes current from reaching the capacitance that is higher up the ladder. The effective inductance of the capacitor is diminished. At high frequencies there are effectively fewer Rp resistors in parallel so the ESR of the capacitor increases. This is a qualitative explanation for frequency dependent nature of capacitors on low inductance mounts. This phenomenon can only be observed when the fixture plus filler plate inductance (Lmount + Lbottom) is less or much less than the intrinsic inductance of the capacitor which is associated with the working plates (sum of Ls).

At series resonance, the vertical inductors and horizontal capacitors behave like a wavelength lossy transmission line with the high impedance open circuit at the end appearing to be low impedance at the PCB pads. This property enables the calculation of the circuit parameters shown in Fig. 3.9

3.2 Evolution of Decoupling Capacitor Design Concepts 3.2.1 Discrete Capacitor (MLCC)

Over the past 10-12 years, decoupling capacitors have evolved into diverse types. This evolution has been driven by the requirement to lower the inductance of power delivery systems to keep up with switching speeds and transistor density in silicon processors.

Fig. 3.10 Decoupling Capacitors Examples Nokia 702 Camera Module [9]

The board pads and vias form closely spaced cancellation paths and parallel loops in the boards that are support the low ESL design strategies used for the development of decoupling capacitors. When component companies characterize their devices, great care is taken to extract the influence of the test coupon to give a part-only ESL. However, inductance is a property of current loops and, in fact; a low-inductance capacitor does not have a well-defined ESL independent of the board it is mounted to.

Fig. 3.11 taken from the literature of one capacitor manufacturer shows a reduction of about 2 orders of magnitude by applying a strategy to maximize current cancellation in the terminal structures and segment terminations into small parallel current loops.


Fig. 3.11 Decoupling Capacitor ESL evolution [19]

Fig. 3.12 shows another example of a capacitor structure that uses flux cancellation to reduce inductance. This structure employs two separate capacitors in the same package.

Fig. 3.12 The structure of the X2Y capacitor[23]

Fig. 3.13 shows a cross section of a bumped chip capacitor package. The use of this technology allows the designer to minimize loop inductance further by utilizing via-in-pad technology.


Fig. 3.13 Bumped-Chip Electrode/Termination Structure[24]

Conventional decoupling devices utilize multiple capacitors, each with a dedicated function, to fulfill the needs of high-speed load response and noise suppression. As processor speeds increase, more and more capacitors are required. As a result, circuit design becomes increasingly complex. The Proadlizer by NEC-TOKIN, is designed to work at frequencies up to a few GHz, and has a relatively flat impedance characteristic.

Fig. 3.14 (a) Routing Area between the conventional caps and Proadlizer, (b) Structure[25]

3.2.2 Embedded Thin Film Capacitor

Embedded decoupling is normally considered a better solution than surface mount decoupling due to its shorter leads that result in a smaller parasitic inductance. Like a typical SMD capacitor, embedded capacitors have an equivalent series C-R-L. The inductance of an embedded capacitor depends not only on the electrode geometry and size, but also on the connection geometry. High dielectric constant (r) materials reduce the impedance of embedded capacitors at low frequencies while shifting the first resonant frequency to a lower frequency.

Embedded thin film capacitors can be integrated within the chip, packaging module or printed wiring board (PWB), offering a promising solution to achieve high packaging density, high performance and reliability with a low system cost.


Fig. 3.15 A Depiction of Embedded Passives Construction [27]

As illustrated in Fig. 3.15, SMD resistors and capacitors can be replaced with embedded components etched on layers dedicated to a particular component type. The resistive layer covers the entire surface, and is etched away to provide the resistors desired. Similarly, C1 and C2 capacitors become electrode patterns on a dielectric layer that is buried in the substrate.

Discrete SMT Decoupling

Embedded Planar Decoupling

Fig. 3.16. A Depiction of the Embedded Passives (Distributed Planar) Construction [27]

The embedded capacitors can be individual singulated components or be distributed as an entire plane of capacitance between the power and ground planes of a power distribution system. The distributed capacitance planes can be accessed by low inductance via connections resulting in an extremely low equivalent series inductance. The singulated embedded capacitors have the advantage of being individually tailored to their design needs, although this comes at the expense of added manufacturing complexity.


Fig. 3.17. Comparison between SMT and Embedded Components [28]

A number of PCB manufacturer have begun work on technologies to embedded components, although there is wide variation in the specifics of release date, board thickness, and types and characteristics of embedded components.

Fig. 3.18. Power, Frequency and Capacitance Density Needs

3.2.3 Future Strategies for Decoupling Capacitors

As the need for higher speed signals and more power consumption within convergent system architectures increases, new concepts of decoupling structures will be required. Capacitance density requirements are directly related to power and frequency requirements as indicated in Fig. 3.18.



Fig. 3.19. Power/Ground Impedance Curve seen at On-Chip [26]

Fig. 3.20 Moving Decoupling Capacitors Next to Bare Chip [29]

As illustrated in Fig. 3.20, reduction in power supply noise requires moving the decoupling capacitors next to the bare chip. As packaging structures continue to evolve, opportunities to develop new, optimal, low-inductance decoupling capacitors will present themselves.


ook/

4. References [1] Richard K. Ulrich, Advanced Electronic Packaging 2nd Edition, John Wiley & Sons, 2006 [2] Rao R. Tummala, Fundamentals of Microsystems Packaging, McGraw-Hill, 2001 [3] E.E. Davidson, Electrical Design of a High Speed Computer Packaging System, IEEE

Transactions on Computers, Hybrids and Manufacturing Technology, vol. CHMT-6, no. 3, September, 1983.

[4] Dean L. Monthei, et al., Package Electrical Modeling, Thermal Modeling, and Processing for GaAs Wireless Applications, Kluwer Academic Publishers, 1999.

[5] Rao R. Tummala, Packaging: Past, Present and Future, Proc. of the IEEE 6th International Conference on Electronic Packaging Technology, 2005

[6] IC Packages Data Handbook, Chapter 1: Overview of IC Packages, NXP, http://www.standardics.nxp.com/packaging/handb

[7] Chip-on-Chip Offers Higher Memory Capacity, Speed, Nikkei Electronics Asia, February 2007.

[8] Kai Liu, Trends on RF System-in-Package (SiP), IEEE Spectrum Tech Insider: RF Packaging Trends, IEEE Spectrum Online, February 15, 2007.

[9] E. Jan Vardaman, Drivers for IC Packaging Developments, TechSearch International. [10] Trends in Package Development, NEC Electric, http://www.necel.com/pkg/ [11] John Leung, Redistribution Scale Chip Technology, Packaging Technology for Mobile

Platform, Freescale Semiconductor, Shanghai, 2006 .

[12] Andrew Mawer, Alexandra Dopplinger, Manufacturing with the Land Grid Array Package, Application Note, Freescale Semiconductor.

[13] Kaladhar Radhakrishnan, Optimization of Package Power Delivery and Power Removal Solutions to meet Platform Level Challenges, Intel Developer Forum, ITRS004.

[14] David Bolognia, System in a Package Solution for DC-DC Converters, iMAPS2003. [15] Wee Jae Kyung, Co-Design Issue of the Chip Package for Low Power SoP, EP&C. [16] James Muccioli & Dale Sanders, High Speed Decoupling Strategies with fewer

Capacitors, X2Y Attenuators.

[17] Istvan Novak, A Black-Box Frequency Dependent Model of Capacitors for Frequency Domain Simulations, DesignCon East 2005.

[18] Istvan Novak, Inductance of Bypass Capacitors How to Define, How to Measure, How to Simulate, Tech Forum TF7, DesignCon East 2005.

[19] Andrew P. Ritter, Low Inductance Land Grid Array Decoupling Capacitors, IMAPS2006. [20] Steve Weir, Bypass Capacitor Inductance, Data Sheet Simplicity to Practical Reality,

Teraspeed Consulting Group LLC.


.htm.

[21] Steve Weir, Impact of PCB Stack-up and Capacitor Via Design In Power Distribution Design, IEEE EMC Society SCV Meeting, February 14, 2006.

[22] Istvan Novak, Sreemala Pannala, Jason. R. Miller, Overview of Some Options to Create Low-Q Controlled-ESR Bypass Capacitors, EPEP2004.

[23] Rob Derksen, Bart Bouma, Jim Muccioli, Dave Anthony, Integrated Passive Devices : A Breakthrough in High Speed Decoupling and Broadband Filtering.

[24] Jeff Cantlebary, LICA (Low Inductance Capacitor Array) Flip-Chip, AVX Application Note, http://www.avxcorp.com/.

[25] Proadlizer, NEC-TOKIN Site, http://www.nec-tokin.com/ [26] Hyunjeong Park, Modeling and Simulation of IC and Package Power/Ground Network,

Proc. of the 2006 Int. Symp. on EMC, August 2006. [27] Joseph Dougherty, The NEMI Roadmap Perspective on Integrated Passives, iMAPS

France

[28] Motorola Ships Passive-Embedded PCB for Mobile Phone, Nikkei Electronics, May, 2003.

[29] PCB Power Supply Noise Tacked, Nikkei Electronics, September 2003. [30] H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, 1990. [31] Pushkar Jain, Eugene J. Rymaszewski, Thin-Film Capacitors for Packaged Electronics,

Kluwer Academic Publishers, 2004.

[32] Steve Berry, Thanks to New Packaging Methods, ICs are Getting Smaller All the Time, Chip Scale Review, http://www.chipscalereview.com/

[33] Ann R. Thryft, From SiPs, SoPs to Convergent Systems, Nikkei Electronics, July 2005. [34] Clayton R. Paul, Effectiveness of Multiple Decoupling Capacitors, IEEE Transactions on

Electromagnetic Compatibility, vol. 34, no. 2, May 1992. [35] Steve Weir, Bypass Filter Design Considerations for Modern Digital Systems, a

Comparative Evaluation of the Big V, Multi-pole, and Many Pole Bypass Strategies, DesignCon East 2005.

[36] Dean L. Monthei, et al., Package Electrical Modeling, Thermal Modeling, and Processing for GaAs Wireless Applications, Kluwer Academic Publishers, 1999.

[37] Istvan Novak, Gustavo Blando, Jason R. Miller, History of Controlled-ESR Capacitors at SUN, DesignCon 2007.

[38] Elshabini, Aicha, Wang, Gangqiang, Future trends in electronic packaging, 2006 SPIE [39] Advanced Technologies for High Performance Systems, Intel Technology Journal,

2005, http://developer.intel.com/technology/itj/index

[40] Freescale Technology Forum, http://www.freescale.com/webapp/sps/site/. [41] Amkor Website, http://www.amkor.com/EnablingTechnologies/index.cfm.


[42] AVX Website, http://www.avxcorp.com/techinfo_doclisting.asp. [43] X2Y Website, http://www.x2y.com/bypass.htm.

1. Overview of Microelectronic Packaging1.1 Definition of Electronic Packaging1.2 Function of Electronic Packaging1.3 Packaging Hierarchy1.4 Driving Forces of Packaging Technology1.4.1 Electrical Packaging Design Consideration1.4.2 Electrical Packaging Design Process2. Trends in Electronic Packaging Technology2.1 Recent Trends in Advanced Electronic Packaging2.1.1 Trends in the Electronic Packages for Mobile Platforms2.1.2 Electronic Packaging Trends in High-Performance Platforms2.1.3 CoC (Chip-on-Chip) Technology Trends in Japanese Industry2.1.4 Trends on the IC Substrate Technology2.2 Future of Electronic Packaging Technology2.2.1 Future Design Issues of Electronic Packaging Structure2.2.2 Future Concept of the Advanced Electronic Package3. Critical Issues for Decoupling Capacitors3.1 Electrical Characteristics of Capacitors3.1.1 Low Inductance Path (ESL)3.1.2 Controlled-ESR [22]3.1.3 Distributed Capacitor Models 3.2 Evolution of Decoupling Capacitor Design Concepts3.2.1 Discrete Capacitor (MLCC)3.2.2 Embedded Thin Film Capacitor3.2.3 Future Strategies for Decoupling Capacitors

Documents

AN OVERVIEW OF ADVANCED ELECTRONIC PACKAGING TECHNOLOGY.pdf