AN2450 - Oscillator Jitter and Jitter-Causing Eventsww1.microchip.com/downloads/en/AppNotes/00002450A.pdf2016/11/07 · noise on the short-term oscillator jitter. At 20 kHz noise,

AN2450Oscillator Jitter and Jitter-Causing Events

INTRODUCTION

In a Switch-Mode Power Supply (SMPS) design, theIntegrated Circuit (IC) logic determines the SwitchingFrequency (FSW) and the duty cycle, often based onexternal component value and signal comparison. Asignificant issue found in legacy SMPS IC solutions isthe system oscillator’s susceptibility to noise thatgenerates frequency and duty cycle jitter.

This application note discusses the causes of jitter thatcan come with legacy SMPS ICs. Problems, such asEarly Clock Ramp Reset, external oscillator compo-nents, layout influence and duty cycle limiters, aredescribed and tested in detail. Comparative laboratorymeasurements show that a microcontroller with bothanalog and digital Core Independent Peripherals(CIPs), dedicated to SMPS applications, does notexhibit these issues.

NOISE SUSCEPTIBLE POINTS IN SMPS CONTROLLERS

The SMPS controller is sensitive to noise and cancause power supply problems if not used properly.

This section focuses on the cause of noise susceptibilityin ASIC SMPS controllers, its effects over the controlsignals, and test comparisons with the CIP solution. Theanalyzed noise effects are: Early Clock Ramp Reset,oscillator frequency jitter, frequency drift, and jitter due toduty cycle limits and timing events.

Early Clock Ramp Reset

Changing the switching frequency is not an easy orprecise task for ASIC SMPS controllers, as some havean internal fixed frequency relaxation oscillator and oth-ers need external components, such as resistors and/orcapacitors, to generate the frequency. In ASIC SMPScontrollers, the clock is generated by comparing a risingand a falling ramp to two thresholds. When the higherthreshold meets the rising ramp, the clock signal is low,and when the lower threshold meets the falling ramp, theclock signal is high. If there are noise induced voltagespikes on the rising ramp, the threshold will be crossedearlier and the clock signal will become low earlier than itshould. This will also start the low ramp early, as shownin Figure 1. This causes a sudden change in the switch-ing frequency and high jitter on the PWM signal. Theclock ramp is very susceptible to the PCB layout of thecomponents around the chip. As a result, unless theswitching frequency is generated internally, susceptibleetch and components can introduce noise that results inadditional jitter. This behavior can be avoided, or at leastminimized, by following proper SMPS layout rules.

Jitter determined by improper layout can easily be at30%-40%, or even more, of the switching period. AnEarly Clock Ramp Reset can also occur when operat-ing close to the maximum duty cycle. In this case, theeffects are of a smaller magnitude, but they can interactwith improper layout and become considerable. Evenwhen the switching frequency is generated internally,this effect can be present on a smaller scale.

FIGURE 1: EFFECTS OF EARLY CLOCK RAMP RESET TO THE SWITCHING FREQUENCY

Note: The PIC16F1769 is NOT a digital SMPSsolution. It is a solution that has analogperipherals, such as operational amplifiers(op amps), comparators, Digital-to-AnalogConverters (DACs), Analog-to-DigitalConverters (ADCs), Zero-Cross Detector(ZCD), Slope Compensation (SC) andoutput generators, that are asynchronousand work as an analog solution. ThePIC16F1769 combines the analog periph-erals with the digital flexibility of logic cells,timers, Pulse-Width Modulators (PWMs),temperature sensors and communicationcapabilities.

Author: Gheorghe ŢurcanMicrochip Technology Inc.

2017 Microchip Technology Inc. DS00002450A-page 1

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LEGACY SOLUTIONS

Figure 2 shows an Early Clock Ramp Reset event froma real SMPS design. The upper figure shows an EarlyClock Ramp Reset due to noise, while the lower figureillustrates an Early Clock Ramp Reset due to operationclose to the maximum duty cycle.

FIGURE 2: EARLY CLOCK RAMP RESET DUE TO IMPROPER LAYOUT AND OPERATION CLOSE TO MAXIMUM DUTY CYCLE

CIP SOLUTION

The CIP solution is immune to the Early Clock RampReset because the clock is created internally using adivider chain to generate the timing, and the oscillatoris biased and powered from a stabilized band gap ref-erence. Even if a high spike can trigger an Early ClockRamp Reset, it would still be at 32 MHz, which meansthe possible jitter would represent less than 0.1%.

LEGACY SOLUTIONS vs. CIP SOLUTION

The MCU is not influenced by layout or maximum dutycycle limits with respect to jitter; hence, the pulses willhave an accurate constant frequency. The use of anMCU with SMPS dedicated CIPs eliminates IC relatedstability problems from the design and providesapplication flexibility.

Oscillator Frequency Jitter

Oscillator jitter is inherent to the way the switchingfrequency is generated and it can be noticed as a smallfrequency change of the PWM signal. Oscillator jitterlimits the maximum duty cycle, as short-term variationsin frequency can create wide variations in off time forhigh duty cycle designs.

To illustrate these characteristics, tests are performedusing SMPS ICs: PIC16F1769 and “3843” architectureSMPS controllers. VDD is provided by the same labora-tory power supply. A 20Ω resistor is connected in seriesto VDD, where external noise is injected. An arbitrarysignal generator is set to provide a 100 mV p-p (peak-to-peak) sinusoidal waveform swept from 1 kHz to1 MHz. Noise is injected in the 20Ω resistance with thehelp of an isolation transformer to test how this affectsthe oscillator jitter. A 0.1 μF ceramic capacitor is usedin parallel with a 470 pF ceramic capacitor as VDD

bypass capacitors.

Debugging an SMPS to find potential jitter generatingsources can be difficult if the base oscillator jitter is notknown and measured.

LEGACY SOLUTIONS

The tested IC uses the “3843” SMPS architecture. TheVDD used for this IC is 12V DC. Figure 3 shows an ACcoupled VDD that goes into the controller. The noisespikes that can be seen have an amplitude of 50 mVand they are caused by the IC switching.

FIGURE 3: 12V VDD FOR A “3843” ARCHITECTURE; AC COUPLED MEASUREMENT

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Figure 4 shows the 100 mV p-p (peak-to-peak)sinusoidal noise added to the 12V.

The IC oscillator is set to approximately 250 kHz withtwo external components: a 3 kΩ resistor and a 2.2 nFcapacitor. The values were selected according to thedata sheet guidance to obtain a 250 kHz switching

frequency and a maximum duty cycle of approximately85%. The values are selected in order to verify the jitterissues at maximum duty cycle.

Figure 5 illustrates the short-term jitter of the next risingevent. The jitter is 16.4 ns or 0.41% of the switchingfrequency.

FIGURE 4: AC COUPLED 12V VDD WITH 1 kHz 100 mV p-p SINUSOIDAL NOISE ADDED

FIGURE 5: “3843” ARCHITECTURE SHORT-TERM OSCILLATOR JITTER (SHORT-TERM JITTER) WITHOUT NOISE ON VDD


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Figure 6 shows 100 kHz of 100 mV p-p noise on VDD.This noise frequency has the biggest impact on theoscillator jitter, 19 ns, which represents close to 0.5% ofthe SWF.

The same test was performed on a similar IC that usesPeak Current Mode Control (PCMC) and that can haveexternal Slope Compensation, which utilizes the “3842”architecture.

For the “3842” architecture device, the VDD and exter-nal components are the same as the ones used for the“3843” architecture, as it is pin compatible.

Figure 7 depicts the base short-term jitter of the oscilla-tor, with a result of 19.1 ns, or approximately 0.48%.The jitter peaks at around 300-500 kHz of noise, whichtranslates to 21.6 ns or an equivalent of 0.54% of theSWF.

FIGURE 6: SHORT-TERM JITTER WITH 100 kHz NOISE ON VDD

FIGURE 7: “3842” ARCHITECTURE SHORT-TERM OSCILLATOR JITTER (SHORT-TERM JITTER) WITHOUT NOISE ON VDD

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CIP SOLUTION

Figure 8 depicts an AC coupled VDD that goes into thePIC16F1769; the DC value is 5V. Figure 9 shows the100 mV p-p sinusoidal noise added to the 5V. The CIPsolution creates the clock internally using a divider

chain to generate the timing, and the oscillator isbiased and powered from a stabilized band gapreference, which allows for better noise immunity.

FIGURE 8: 5V VDD FOR PIC16F1769; AC COUPLED MEASUREMENT

FIGURE 9: AC COUPLED 5V VDD WITH 1 kHz 100 mV p-p SINE NOISE ADDED


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The first test is for short-term jitter of the oscillator with-out noise on VDD. This result sets the basic jitter value.Noise jitter will be considered without this value whencomparing the results. The frequency is set to 250 kHzand the duty cycle is close to 30%.

Figure 10 depicts the basic short-term jitter of thePIC16F1769. The oscilloscope probe is set to envelopemeasurement and is measured every few minutes. Thecaptured oscillator jitter is 11 ns or the equivalent of0.275% of the SWF.

FIGURE 10: PIC16F1769 SHORT-TERM OSCILLATOR JITTER (SHORT-TERM JITTER) WITHOUT NOISE ON VDD


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Figure 11 and Figure 12 show the influence of VDD

noise on short-term oscillator jitter. At 1 kHz, the noisedoes not influence jitter and stays at 11 ns. At 3 kHznoise, the jitter increases slightly to 11.3 ns.




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noise on the short-term oscillator jitter; at 5 kHz, thejitter is at 11.3 ns and at 10 kHz, the jitter increases to13 ns.




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noise on the short-term oscillator jitter. At 20 kHz noise,the jitter increases to 14 ns. The maximum jitter peak is15 ns and is obtained at 50 kHz of noise frequency,which represents ~0.375% oscillator jitter from VDD

noise.




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noise on the short-term oscillator jitter. At 100 kHz and300 kHz, the oscillator jitter is going down to 13 ns andby 300 kHz, the jitter is back to 12 ns until 1 MHz.


FIGURE 18: SHORT-TERM JITTER WITH OVER 300 kHz NOISE ON VDD


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The complete results are shown in Figure 19, whichshows the comparative measurements of the short-term oscillator jitter, with 100 mV p-p noise on VDD. Thefrequencies range from 1 kHz to 1 MHz, betweenPIC16F1769 and the “3843” or “3842” architecturecontrollers.

FIGURE 19: SHORT-TERM JITTER vs. NOISE FREQUENCY OF THE THREE SMPS CONTROLLERS

Figure 20 illustrates the basic short-term jitter withoutVDD noise on the three devices. It shows a comparisonbetween jitter times, jitter envelope, rising time andramps.

FIGURE 20: JITTER TIME, ENVELOPE AND RAMP COMPARISON BETWEEN PIC16F1769, “3843” AND “3842”

10

12

14

16

18

20

22

Jitte

r tim

e [n

s]

VDD Noise nfluence on Oscilator Jitter

PIC16F1769

3843

384


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Frequency Drift (Long-Term Jitter)

SMPS converters that use external components to setthe switching frequency can encounter a frequency vari-ation that takes several minutes to settle (>30 minutes).Because it takes several minutes to settle, it can beconsidered as long-term frequency drift.

The drift in frequency is not caused by input voltagechange or ambient temperature, as it can be seen aftercircuit start-up and in steady conditions, but rather it iscaused by the self-heating components to some extent.Unless all components are thermally stabilized, therewill be a drift.

Because designers or users change the components tomake products cheaper, this drift tends to be differentfrom SMPS to SMPS, even if they have the sameschematic.

The presence of this drift can influence stabilitymeasurements, as the circuit can be stable or at the limitof stability at the first 5 minutes from start-up andbecome instable after 30 minutes when the frequencyhas changed. It is important to measure for thisfrequency drift and make sure the SMPS is stable in allconditions.

LEGACY SOLUTIONS

Legacy SMPS controllers that use external compo-nents to generate the switching frequency generatefrom frequency drift.

Laboratory measurements show that the “3843”architecture and the “3842” architecture controllers havea frequency variation that can be perceived as frequencydrift, as it varies largely with time. It is not constant andis also influenced by external components andconditions, but not limited to them.

After starting the IC with the external components set toobtain close to 250 kHz, the switching frequency has adrift that takes several minutes. It is a significant transi-tion that can cause instabilities and it can be hard todebug. This drift can be seen at the second risingpulse, as the frequency change is faster after power-upand slower after a few minutes of operation.

Figure 21 and Figure 22 show the transition or drift ofthe rising pulse by approximately 30 ns after twominutes of operation at room temperature. For longerperiods of time, the drift is greater. Room temperaturedoes not change during the drift and no temperaturefrom external components influences the device.

FIGURE 21: “3843” RISING PULSE AT START OF OPERATION


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FIGURE 22: RISING PULSE AFTER TWO MINUTES OF OPERATION

The frequency drift takes several minutes, so it isconsidered as a long-term jitter and can be seen inFigure 23 to have 68 ns or 1.7% of the 250 kHz SWF.For this measurement, the DC is close to 35%-40%.

FIGURE 23: LONG-TERM OSCILLATOR JITTER IN “3843”


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The “3842” architecture controller experiences thefrequency drift, as shown in Figure 24, due to thegenerated switching frequency method. The driftmagnitude can differ at various chosen frequencies.

FIGURE 24: LONG-TERM OSCILLATOR JITTER IN “3842”

CIP SOLUTION

The PIC16F1769 microcontroller with analog peripheralsdoes not incur long-term frequency drift or frequencyshifts, as it ensures 2% oscillator accuracy over voltageand 5% over temperature. Once the controller hasstarted, the frequency stays as configured. The compo-nents are on-chip, so they are smaller, they stabilizefaster and they have a thermal compensation circuitwhich counters drift caused by temperature changes.They can achieve a 2%-5% accuracy as they use aband gap bias and a power supply.

This means that the set switching frequency willremain the same even after a long time operation. Formore details, access the “Oscillator Module” sectionin the “PIC16(L)F1764/5/8/9 14/20-Pin, 8-Bit FlashMicrocontrollers Data Sheet” (DS40001775).


The CIP solution shows a more stable behavior whengenerating the switching frequency for the SMPSconverter as compared to legacy solutions. This helpsdesigners achieve easier SMPS stability and worry-free controller problems. The big advantage is a moreconsistent OFF time, allowing the use of higher dutycycles.


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Jitter of Duty Cycle-Dependent Event Timing

In an SMPS controller, the generated PWM signal hasa duty cycle controlled by output requirements (outputvoltage or current level). When the PWM signal dutycycle is running close to the limit, it can create jitter. InSMPS applications, high duty cycles may present jitterissues. This could allow too high a duty cycle, but notsufficient time for the inductor to discharge, causingratcheting, and ultimately, failure of the MOSFET.

The duty cycle limits in controllers that use externalcomponents to generate the switching frequency aredependent on the values of the selected external com-ponents. These duty cycle limits are generated using acomparator and a ramp wave clock. The noise on theramp causes jitter in the maximum duty cycle. Eitherstarving the power supply at high currents, or allowingexcessive duty cycles, could prevent the inductor fromfully discharging into the load.

These limits tend to be variable in a small margin whenvoltage and temperature are constant or have highvariability with the change of temperature.

A high jitter can be noticed when approaching the dutycycle limits and can be differentiated as both duty cyclejitter and frequency jitter.

LEGACY SOLUTIONS

As mentioned previously, the external components forthe “3843” and “3842” architecture controllers areselected to generate approximately 250 kHz, so theywill have an inherent maximum allowed duty cyclebased on the data sheet information of the devices.The limit was selected to make the tests comparable towhat the PIC16F1769 microcontroller provides.

The maximum duty cycle that “3843” can have with theselected external components is approximately 85%,as shown in Figure 25. This is due to the timing resis-tance value. If other resistance values are selected, themaximum duty cycle will vary.

FIGURE 25: MAXIMUM ALLOWED DUTY CYCLE OF THE “3843” ARCHITECTURE CONTROLLER BASED ON EXTERNAL SWF GENERATING COMPONENTS

PWM SignalInductor CurrentFB Signal withSlope Compensation


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When the duty cycle gets close to the upper limit, anoscillator jitter of 72.4 ns, or the equivalent of 1.81% ofthe SWF, is recorded, as shown in Figure 26.

At the lower end, the duty cycle is close to a 5% mini-mum, as depicted in Figure 27; after which, the circuitworks in an open loop. This is inherent to the deviceconstruction.

FIGURE 26: OSCILLATOR JITTER CAUSED BY MAXIMUM DC LIMITING EVENTS IN THE “3843” ARCHITECTURE IC

FIGURE 27: MINIMUM ALLOWED DUTY CYCLE OF THE “3843” ARCHITECTURE IC BASED ON EXTERNAL SWF GENERATING COMPONENTS

PWM SignalInductor Current



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When getting close to the low duty cycle limit, instabili-ties can be detected in the oscillator and the SWFgenerator, and a jitter of 45.8 ns appears on the nextpulse rising edge. This represents 1.15% of the SWFand it is shown in Figure 28.

FIGURE 28: OSCILLATOR JITTER CAUSED BY MINIMUM DC LIMITING EVENTS IN THE “3843” ARCHITECTURE IC


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Considering a long rate jitter of 68 ns, a 19 ns peak oscil-lator jitter, a 72.4 ns of entering maximum duty cycle jitter,a 45.8 ns of entering minimum duty cycle jitter, andexcluding the improper layout jitter, a total jitter of 205.2ns is obtained. This can impact the stability of the deviceand represents 5.1% of the switching frequency.

For the “3842” architecture controller, the followingbehavior can be noticed: the minimum duty cycle limitis around 4.8% and surpassing the limit causes a 45.6ns jitter, as shown in Figure 29. At the maximum dutycycle limit, which is approximately 84%, the jitterreaches 43.3 ns, as illustrated in Figure 30.

FIGURE 29: OSCILLATOR JITTER CAUSED BY MINIMUM DC LIMITING EVENTS IN THE “3842” ARCHITECTURE IC

FIGURE 30: OSCILLATOR JITTER CAUSED BY MAXIMUM DC LIMITING EVENTS IN THE “3842” ARCHITECTURE IC

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The total oscillator jitter of the system controlled by the“3842” architecture controller reaches 162.2 ns oraround 4% of the SWF.

CIP SOLUTION

The PIC16F1769 can generate the PWM output with aduty cycle ranging from 0%, or pulse skipping to 100%,although 100% is not used in SMPS as some off timeis needed for the inductor to discharge. Duty cycleevents can be synchronous and asynchronous to theSWF; hence, it is possible to have both a minimumallowed duty cycle and a maximum allowed duty cycleif a 0%-100% swing is not desired.

To ascertain if these duty cycle limiters influence theoscillator jitter, or if they can cause any kind of instabil-ities, the PIC® MCU was configured to have a definedminimum and maximum duty cycle.

If a lower or upper limit is added to the duty cycle, theoscillator jitter can be identified by measuring thesecond cycle rising envelope. Changing the duty cyclefrom the lower limit to the upper limit does not add anyadditional oscillator jitter, as shown in Figure 31, whichindicates a high-accuracy and jitterless function withother duty cycle limits and actuators. The measured jit-ter stays within the maximum range determined by thebasic short-term oscillator jitter and proves that dutycycle dictating events do not influence the jitter, nor dothey create additional ones.

FIGURE 31: PIC16F1769 OSCILLATOR JITTER IS NOT INFLUENCED BY DUTY CYCLE DICTATING EVENTS


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The limits are set to show that they do not influence thestability of the system. With no set limits, the duty cyclecan go from pulse skipping at the lower end to 100% atthe higher end. The lowest stable duty cycle achievablebefore entering pulse skipping is 1% (of 250 kHz SWF)or 40 ns duration pulse, as shown in Figure 32. Theenvelope that includes the 10-11 ns jitter is illustrated inFigure 33.

FIGURE 32: MINIMUM ACHIEVABLE USABLE DUTY CYCLE ON PIC16F1769 BEFORE ENTERING PULSE SKIPPING

FIGURE 33: ENVELOPE OF MINIMUM ACHIEVABLE USABLE DUTY CYCLE BEFORE ENTERING PULSE SKIPPING


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At the upper end, before entering 100%, the achievableduty cycle is approximately 99% (98.7%). Figure 34shows the Current Sense (CS) signal and the Feed-back (FB) signal that generate the 99% DC PWM.Slope Compensation (SC) is applied to the FB signalinstead of the CS signal. The PIC16F1769 is capable

of adding the SC internally, in multiple ways, and with avariety of ramp slopes. Figure 35 depicts a close viewof the maximum duty cycle before 100%. No instabili-ties or jitter are added and the minimum low pulse inthis case is around 52 ns.

FIGURE 34: MAXIMUM DUTY CYCLE BEFORE ENTERING 100%

FIGURE 35: MAXIMUM DUTY CYCLE BEFORE ENTERING 100%, NO JITTER ADDED

Note: Lower and higher duty cycles can be achieved before 0% and 100% DC, as the events are asynchronousto the oscillator on the PIC16F1769 and the peripherals are analog. For this application note, the abovelimits are assumed.



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LEGACY SOLUTION vs. CIP SOLUTION

The CIP solution does not show jitter generation at theduty cycle limits and shows great control over thewhole duty cycle range. The legacy solution showsgreat control when the duty cycle is between limits, butapproaching the limits, creates restrictions and jitterthat can make a circuit unstable.

RESULT COMPARISON

The total oscillator jitter comparison of the threedevices is shown in Figure 36.

The maximum noise short-term jitter does not includethe basic short-term jitter.

The jitter caused by improper layout was not added inFigure 36, as it is higher than the values of other jittersources.

FIGURE 36: EVENT JITTER COMPARISON

0

10

20

30

40

50

60

JitterShort-term

JitterMax Noise S-T

JitterLow LimitJitter

PIC16F1769

3843

3842


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Figure 37 shows a comparison of improper layout influ-ence on the three ICs. The values for the jitter influenceare shown as approximately 35% of the switchingperiod, but the values can be higher or lower, depending

on layout construction and the selected components. Itis obvious that improper layout will not create oscillatorjitter on the PIC16F1769, but it will generate high jitter onother legacy SMPS ICs.

FIGURE 37: IMPROPER LAYOUT JITTER MAGNITUDE

EXPANDED CONTROL OF DUTY CYCLE DEPENDENT EVENTS

PIC16F1769 is a PIC MCU with analog peripherals thatcan be used to control an SMPS. The events causingthe PWM output, which controls the system, are bothsynchronous and asynchronous to the internal oscilla-tor. Some analog components, such as the op amp,COG, Slope Compensation or comparator, areasynchronous to the oscillator. This allows theaccuracy to be theoretically infinite, and if internallyconnected, between them they work as if an analogSMPS IC is placed inside the MCU.

For variable frequency topologies, control can be fullyasynchronous to any oscillator and can be accurate onevents if internal delays are taken into account. Fixedfrequencies or related topologies require an oscillator,while pure analog solutions use external RC compo-nents to dictate that, and as previously shown, jitter canbe caused by interactions and dependencies.

The PIC16F1769 can be considered a solution that com-bines analog and digital peripherals that run synchronousto the internal oscillator. They can be set from 500 kHz orlower, with the help of postscalers/prescalers, to thenative 8 MHz, or even to 32 MHz, using the PLL. Theoscillator has 2% accuracy and provides an accurateconstant frequency source for SMPS solutions.

Time-dependent events that are synchronous to theinternal oscillator are accurate within the limits of theconfigured frequency. Hence, if the internal oscillator isconfigured to run at 32 MHz, and a synchronous digitalperipheral runs out of FOSC, it will have an accuracy of32 ns. This means that the SWF can be generated with32 ns accuracy, and the digital limits will also have32 ns accuracy, while the analog control will have atheoretical infinite accuracy. This device can be easilyused to obtain spread spectrum frequencies andsynchronization with other devices.

0

1,58 1,58

00,5

11,5

22,5

33,5

44,5

PIC16F1769 3843 3842

Perio

d tim

e [u

s]

Switching Period

Improper Layout Jitter


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CONCLUSION

Similar setups were built for three different SMPS micro-controllers in order to compare their jitter capabilities andthe causing events. The PIC16F1769 solution, that com-bines both analog and digital internal components, wascompared to the classic analog devices that have the“3843” and the “3842” architecture SMPS controllers.The results demonstrate how the PIC16F176X/7X familyof MCUs does not have the oscillator and duty cycleevent jitter issues of legacy solutions, and provides moreflexibility to the design.

The results obtained through the same laboratorymeasurements show stability advantages of the CIPsolutions over legacy solutions. Designing an SMPSwith CIPs provides the advantages of analog SMPScontrollers and eliminates their disadvantages, whilekeeping all the analog design techniques.

REFERENCES

1. Figure 2 – Image credit: “Six Common Reasonsfor Power Supply Instability” by Dr. Ray Ridley.

2. “PIC16(L)F1764/5/8/9 14/20-Pin, 8-Bit FlashMicrocontrollers Data Sheet” (DS40001775).


Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights unless otherwise stated.

2017 Microchip Technology Inc.

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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ISBN: 978-1-5224-1768-2

DS00002450A-page 25


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Documents

AN2450 - Oscillator Jitter and Jitter-Causing Eventsww1.microchip.com/downloads/en/AppNotes/00002450A.pdf2016/11/07 · noise on the short-term oscillator jitter. At 20 kHz noise,