2
10ES32 + Ya +- v; \(_ d o o L a o ad o 3e 6v -o ,, ool troo .= c.i 6$ i: OO Yd) oE -O o> a* oo) o0i -s Ed OE p- 5. oj o= ad !o Y, ^= 50v ca0 o= o. ii VL 9- rJ< J6i (J o Z o Third Semester B.E. Degree Examination, Dec.2013/Jan.20l4 Analog Electronic Gircuits , Time: 3 hrs. Max. Marks:100 N ote : 1 : : ::: I!.Y^u *'! Iy:"'fi i: "! :::': s . PART _ A I a. Explain the following with respect to a semi conductor diode : (i) Diffusion capacitance. (ii) Transition capacitance (iii) Reverse recovery time. (06 NIarks) b. Explain the"working of bridge rectifier. (08 Marks) c. Design a suitable circuit represented by the box shown below which has input and output waveforms as indicated. (06 Marks) USN 2a. b. \r ;o'{ o -ro{ **t;lc U*j,^t 3\\i t fr. % 3v -toY Derive an expression for Ie, Ic and Vce for vohagg divider bias using exact analysis. (10 Marks) For the circuit shown below; determine (i) Ie (ii) Ic (iii) VcE. (06 Marks) Ycc -\5v Rc- c' Determine Rs and Rc for the transistor inverter of Fig. Q2 (c) if I61s,11 : 10 mA, Ie : 1500% Is1,nu*). (04 Marks) 3 a. Derive an expression for Av, ZiandZo for CE fixed bias using r. equivalent model. (10 Marks) Fig. Q1 (c) - (ii) C- to lo/qI nlg. qz iu; u,m //*"/ 3- .\\ '2 \. ifi \ q) For More Question Papers Visit - www.pediawikiblog.com For More Question Papers Visit - www.pediawikiblog.com www.pediawikiblog.com

Analog Electronics Circuits Jan 2014

Embed Size (px)

Citation preview

Page 1: Analog Electronics Circuits Jan 2014

10ES32

+Ya

+-v;

\(_

dooLa

oado

3e

6v

-o ,,

ooltroo.= c.i6$i: OOYd)oE-O

o>

a*oo)

o0i

-sEd

OE

p- 5.

oj

o=ad!o

Y,^=50vca0o=o. iiVL9-

rJ<J6i(J

oZ

o

Third Semester B.E. Degree Examination, Dec.2013/Jan.20l4Analog Electronic Gircuits

, Time: 3 hrs. Max. Marks:100N ote :

1 : : ::: I!.Y^u *'! Iy:"'fi i: "! :::': s .

PART _ AI a. Explain the following with respect to a semi conductor diode :

(i) Diffusion capacitance. (ii) Transition capacitance (iii) Reverse recovery time.(06 NIarks)

b. Explain the"working of bridge rectifier. (08 Marks)c. Design a suitable circuit represented by the box shown below which has input and output

waveforms as indicated. (06 Marks)

USN

2a.b.

\r;o'{

o

-ro{

**t;lcU*j,^t3\\i t fr.

%3v

-toY

Derive an expression for Ie, Ic and Vce for vohagg divider bias using exact analysis.(10 Marks)

For the circuit shown below; determine (i) Ie (ii) Ic (iii) VcE. (06 Marks)

Ycc -\5vRc-

c' Determine Rs and Rc for the transistor inverter of Fig. Q2 (c) if I61s,11 : 10 mA,Ie : 1500% Is1,nu*). (04 Marks)

3 a. Derive an expression for Av, ZiandZo for CE fixed bias using r. equivalent model.(10 Marks)

Fig. Q1 (c) - (ii)

C- to

lo/qI

nlg. qz iu;

u,m//*"/3-

.\\'2 \.

ifi \q)

For More Question Papers Visit - www.pediawikiblog.com

For More Question Papers Visit - www.pediawikiblog.com

www.pediawikiblog.com

Page 2: Analog Electronics Circuits Jan 2014

4 a. Determine the lower cut off frequency forCs : 0.1 Pf, Rs =' 1 Kf), Rr : 120 Kf), Rr-

f0:6, Vcc: 15 V, Var: 0.7 V.

3 b. For the circuit shown in Fig. Q3 (b), calculate ta, Zi, Zo, Ay, A1.

Fc

ttol{.rL

rJct q V

1_.1F..Jt-

10ES32

(10 Marks)

[-- rI\ roto/+

f =roe J \ItE; o'-fY

-fo = 6O !t su

Fig. Q3 (b)

the emitter follower using BJT amplifier with: 4 Kf), Re : 1.5 KO, Cc : 0.1 ptf 0 : 100,

(12 Marks)(08 Marks)

(10 Marks)

Ipss: 5 mAVp:-6V

Yos :40 ps

b. Derive equations for Miller input and output capacitance.

, PART _BDerive an expression for Zi, Ay, Ar for Darlington emitter follower circuit.34.

b. What are the effects of negative feedback in amplifier? Show how bandwidth of an amplifier(10 Marks)

6a.b.

7a.b.

8a.

b.

With a neat diagram explain the working of complementary symmetry push pull amplifier.(10 Marks)

Explain the operation of class B push pull amplifier and show that its efficiency is 78.5Yo atmaximum power dissipation. (10 Marks)

With a neat diagram; explain the working of RC phase shift oscillator. (08 Marks)With a neat diagram, explain the working of series resonant crystal oscillator. A crystal has

L : 0.334^H, C : 0.065 pt CM : 1 pf, R : 5.5 kQ. Calculate its series and parallelresonating frequency. (12 Marks)

Draw the JFET amplifier using fixed bias configuration. Derive Zi, ZO and AV using smallsignal model. (10 Marks)For the JFET amplifier shown in Fig. Q3 (b), calculate (i) g. (ii) 16 1111) Zi (iv) Zs(v) Av. (lo Marks)

t95 2or{2-*n-

F---YOz.o/t

€-l

I

*8*E{<

2 of2

Fie. Q8 (b)

+F*r'y*

For More Question Papers Visit - www.pediawikiblog.com

For More Question Papers Visit - www.pediawikiblog.com

www.pediawikiblog.com