ANALOG LAYOUT GENERATION FOR PERFORMANCE AND MANUFACTURABILITY

THE KLUWERINTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE

ANALOG CIRCUITS AND SIGNAL PROCESSING Consulting Editor: Mohammed Ismail. Ohio State University

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ANALOG LAYOUT GENERATION FOR

PERFORMANCE AND MANUFACTURABILITY

by

Koen Lampaert Katholieke Universiteit Leuven

Georges Gielen Katholieke Universiteit Leuven

and

Willy Sansen Katholieke Universiteit Leuven

SPRINGER SCIENCE+BUSINESS MEDIA, LLC

A C.I.P. Catalogue record for this book is available from the Library of Congress.

ISBN 978-1-4419-5083-3 ISBN 978-1-4757-4501-6 (eBook) DOI 10.1007/978-1-4757-4501-6

Printed on acid-free paper

AII Rights Reserved © 1999 Springer Science+Business Media New York

Originally published by Kluwer Academic Publishers, Boston in 1999 Softcover reprint ofthe hardcover Ist edition 1999

No part of the material protected by this copyright notice may be reproduced or utilized in any form or by any means, electronic or mechanical,

including photocopying, recording Of by any information storage and retrieval system, without written permission from the copyright owner.

Abstract

Analog integrated circuits are very important as interfaces between the digital parts of integrated electronic systems and the outside word. A large portion of the effort involved in designing these circuits is spent in the layout phase. Whereas the physical design of digital circuits is automated to a large extent, the layout of analog circuits is still a manual, time-consuming and error-prone task. This is mainly due to the continuous nature of analog signals, which causes analog circuit performance to be very sensitive to layout parasitics. The parasitic elements associated with interconnect wires cause loading and coupling effects that degrade the frequency behavior and the noise performance of analog circuits. Device mismatch and thermal effects put a funda­mental limit on the achievable accuracy of circuits. For successful automation of analog layout, advanced place and route tools that can handle these critical parasitics are required.

In the past, automatic analog layout tools tried to optimize the layout without quantifying the performance degradation introduced by layout parasitics. Therefore, it was not guaranteed that the resulting layout met the specifications and one or more layout iterations could be needed. In this work, we propose a performance driven layout strategy to overcome this problem; In our methodology, the layout tools are driven by performance constraints, such that the final layout, with parasitic effects, still satisfies the specifications of the circuit. The performance degrada­tion associated with an intermediate layout solution is evaluated at runtime using predetermined sensitivities. In contrast with other performance driven layout methodologies, our tools oper­ate directly on the performance constraints, without intermediate parasitic constraint generation step. This approach makes a complete and sensible trade-off between the different layout alterna­tives possible at runtime and therefore eliminates the possible feedback route between constraint derivation, placement and layout extraction.

Besides its influence on the performance, layout also has a profound impact on the yield and testability of an analog circuit. In this work, we develop a new criterion to quantify the detectability of a fault and combine this with a yield model to evaluate the testability of an in­tegrated circuit layout. We then integrate this technique with our performance driven routing algorithm to produce layouts that have optimal manufacturability while still meeting their per­formance specifications.

Contents

Abstract v

1 Introduction 1 1.1 Mixed-signal Design Methodology . ......... 1 1.2 A Hierarchical Performance-Driven Design Strategy 3 1.3 Physical Design Tools for Mixed-signal IC's . 7

1.3.1 Circuit Level Layout Generation . . 7 1.3.2 System Level Layout Generation. . 7 1.3.3 Layout Extraction and Verification . 8 1.3.4 Scope Of This Work 9

1.4 Layout Styles ..... 9 1.4.1 Full-Custom .... 9 1.4.2 Semi-Custom .... 10

1.4.3 Scope Of This Work 11 1.5 Existing Tools for Analog Layout 11

1.5.1 The Analog Macro-Cell Layout Style 11 1.5.2 Implementations of the Macro-Cell Layout Style 13 1.5.3 Situation Of This Work. . . . . . . . 17

1.6 Overview of the Analog Layout Tool LAYLA 18 1.6.1 Circuit Analysis 19 1.6.2 Device Generation 19 1.6.3 Placement ..... 19 1.6.4 Routing ...... 19

1.7 Summary and Conclusions 20

2 Performance Driven Layout of Analog Integrated Circuits 21 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2 Problem Formulation ................... 21 2.3 Previous Work in Performance Driven Layout Generation . 25

2.3.1 Digital Performance Driven Layout Generation 25 2.3.2 Analog Performance Driven Layout Generation . 26 2.3.3 Discussion ............... 27

2.4 A Direct Performance Driven Layout Strategy . . . . . . 28

viii

2.4.1 Modeling Performance Degradation . . 2.4.2 Generation of Performance Sensitivities 2.4.3 Modeling of Layout Parasitics

2.5 Interconnect Parasitics ..... . 2.5.1 Interconnect Modeling .. 2.5.2 Equivalent Circuit Model . 2.5.3 Parasitic Extraction.

2.6 Device Parasitics .. . . 2.7 Mismatch ......... .

2.7.1 Mismatch Model .. 2.7.2 Layout Rules for Optimum Matching

2.8 Thermal Effects ............... . 2.8.1 Effect of Operating Temperature on Electrical Parameters 2.8.2 Thermal Analysis of Electronic Systems. 2.8.3 Discussion ........................ .

2.9 Substrate Coupling . . . . . . . . . . . . . . . . . . . . . . . . . 2.9.1 Injection, Reception and Transmission of Substrate Current 2.9.2 Modeling of Substrate Coupling ........ . 2.9.3 Layout Measures to Reduce Substrate Coupling.

2.10 Summary and Conclusions ............... .

3 Module Generation 3.1 Introduction ......... . 3.2 Problem Formulation . . . . . 3.3 Module Generation Strategies

3.3.1 Fixed Library of Procedural Generators 3.3.2 Dynamic Merging .......... . 3.3.3 Simultaneous Placement and Module Optimization 3.3.4 Discussion . . . . . . .

3.4 Transistor Stacking Algorithms. 3.5 Procedural Module Generation 3.6 Technology Independence 3.7 Examples .......... .

3.7.1 MOS Transistor ... . 3.7.2 Cascode MOS Transistor Pair

3.8 Summary and Conclusions

4 Placement 4.1 Introduction 4.2 Problem Formulation . . . . . . 4.3 Overview of the Placement Tool 4.4 Previous Work in Placement Algorithms

4.4.1 Constructive Placement (CP) ..

CONTENTS

29 29 32 32 33 33 36 38 39 40 41 43 43 46 48 48 48 49 50 51

53 53 53 55 55 56 56 57 57 60 60 61 62 68 68

71 71 71 74 75 76

CONTENTS

4.4.2 Force-Directed Placement (FDP) .... 4.4.3 Placement by Partitioning (PbP) 4.4.4 Quadratic Optimization (QO) . 4.4.5 Simulated Evolution (SE) ... 4.4.6 Simulated Annealing (SA) . . . 4.4.7 Discussion ............ .

4.5 Simulated Annealing for Analog Performance Driven Placement 4.5.1 Placement Representation .... . 4.5.2 Device Representation ............. . 4.5.3 Interconnect Area Estimation ........ .

4.6 Handling Analog Constraints in Simulated Annealing . . 4.7 Move Set ................. . 4.8 Cost Function . . . . . . . . . . . . . 4.9 Estimating Performance Degradation. .

4.9.1 Interconnect Parasitics .... . 4.9.2 Device Mismatch ....... . 4.9.3 Thermal Effects. . . . . . . . ..

4.10 Dynamic Interconnect Area Estimation .. 4.11 Annealing Schedule. . . . . . . . . . . . 4.12 Experimental Results ...... .

4.12.1 Comparator. 4.12.2 Opamp1 .. . 4.12.3 Opamp2 .. . 4.12.4 Opamp3. . .

4.13 Summary and Conclusions

5 Routing 5.1 Introduction .. 5.2 Problem Formulation . . . . . .. 5.3 Overview of the Routing Tool .. 5.4 Classification of Routing Algorithms.

5.4.1 Routing Strategy 5.4.2 Routing Model ....... . 5.4.3 Search Strategies . . . ..

5.5 Previous Work in Area Routing ... . 5.5.1 Maze Routing ........ . 5.5.2 Line-Search Routing . . 5.5.3 Line-Expansion Routing .. . 5.5.4 Discussion ......... .

5.6 A Grid-Less Maze Routing Algorithm 5.6.1 Routing Model ...... . 5.6.2 Source Region Expansion 5.6.3 Path Expansion . . . . ...

ix

76 76 76 77 77 78 80 80 83 85 87 89 94 95 96

· . 100 · .... 101 · .... 104 · .... 105

. .. 107 · . 107

· .... 111 · .... 113

· . 115 · 118

119 · 119

· . 119 · 120

· . 121 · . 121

· 122 · . 123 · . 124

. ..... 124

...... 125 · 125

· . 126 · . 126 · . 127

· 130 · . 131

x CONTENTS

5.7 Cost Function . . . . . . · 134 5.7.1 Actual Path Cost · 134 5.7.2 Predictor Term · 136 5.7.3 Symmetric Routing . · 136 5.7.4 Multi-Terminal Nets · 137

5.8 Net Scheduling ....... · 138 5.8.1 Pre-Routing Phase · 139 5.8.2 Performance Driven Routing Phase · 139 5.8.3 Manufacturability Phase · 140

5.9 Estimating Yield and Testability · 140 5.9.1 Yield Modeling . · 141 5.9.2 Testability. . · 145

5.10 Experimental Results · 147 5.10.1 Opampl .. · 147 5.10.2 Opamp2. . . · 150 5.10.3 CPUTimes . · 152

5.11 Summary and Conclusions · 152

6 Implementation 153 6.1 Introduction . · 153 6.2 Implementation . . . · 153

6.2.1 Source Code · 153 6.2.2 Interface to Electronic Design Frameworks · 154

6.3 Use ofLAYLA in an Industrial Environment. · 155 6.3.1 Link to Schematic Capture . . . . . . · 155 6.3.2 Link to Simulation .......... · 155 6.3.3 Back-Annotation of Layout Parasitics · 156

6.4 Results ...... ............... · 156

7 General Conclusions 159

Bibliography 163

List of Tables

4.1 Comparator: performance characteristics ........... . 4.2 Comparator: offset voltage . . . . . . . . . . . . . . . . . . . . 4.3 Opamp1: performance characteristics obtained after placement. 4.4 Opamp2: performance characteristics. . . . . . . . . . . . . . . 4.5 Performance characteristics of the class NB operational amplifier 4.6 Opamp3: offset voltage. . . . . . . . . . . . . . . . . . . . . . .

· 107 · 108 · 112 · 113 · 115 · 115

5.1 Opamp 1 : Performance and Test Error Rate. . . . . . . . . . . . . 148 5.2 Performance and Test Error Rate for Opamp2 after performance-driven routing

(Stage 1) and after yield and testability optimization (Stage 2). . . . . . . . . .. 150 5.3 Execution times for the different layout generation steps for test circuits OpampJ

and Opamp2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 152

List of Figures

1.1 The design flow of a mixed AID chip. ..... 1.2 Hierarchical levels in mixed AID design. . . . . 1.3 The perfonnance-driven analog design strategy. 1.4 The design flow of the analog module generator AMGIE. 1.5 The Analog Macro-Cell Layout Style. 1.6 BiCMOS opamp divided into modules .. 1.7 Placement for the BiCMOS opamp. .. 1.8 Placed and routed BiCMOS opamp. . . 1.9 Softw~ Architecture of Analog Layout Tool LAYLA

2.1 Layout methodologies 2.2 Perfonnance constraints . 2.3 Layout flexibility . . . . 2.4 Perfonnance driven layout methodologies 2.5 Schematic representation of an IC interconnection. 2.6 T and IT transmission line models . . . . . 2.7 IC interconnection model used in LAYLA. . 2.8 Parasitic Capacitance components . . . 2.9 Diffusion sharing . . . . . . . . . . . . 2.10 Influence of device shape on matching .. 2.11 Matched transistor pairs. ....... . 2.12 Influence of device orientation on matching. 2.13 Matched resistor pair ........... . 2.14 Multi-layer integrated circuit thennal model 2.15 Flow of substrate current 2.16 Guard rings ................ .

3.1 Different variants for the same MOS transistor. 3.2 Device merging. . . . . . . . . ........ . 3.3 Transistor stacking example: Highspeed OTA . 3.4 A generic MOS layout structure .. . ... 3.5 Folded MOS transistor layout. . . . . . .. 3.6 Layout structures for large MOS transistors 3.7 High current MOS transistor layout 2 ...

2 4 5 6

12 13 13 14 18

22 24 27 28 33 35 35 37 39 43 44 45 45 47 50 51

54 55 59 62 65 66 67

xiv

3.8 Cascode MOS transistor pair ..

4.1 Symmetry constraint . . . . . 4.2 Matching contraint . . . . . . 4.3 Overview of the analog placement tool. 4.4 The simulated annealing placement algorithm 4.5 Slicing style placement representation 4.6 Different polygon covers 4.7 Terminal representation .... 4.8 Terminal representation . . . . 4.9 Independent relocation moves 4.10 Symmetric relocation moves. 4.11 Reorientation moves 4.12 Reshaping move ... 4.13 Net length estimators 4.14 Distance Metrics .. 4.15 Interconnect Parasitics Extraction 4.16 Fractures resistor ........ . 4.17 Comparator: schematic. ... .. 4.18 Comparator: performance driven placement. 4.19 Comparator: not performance driven placement. 4.20 Opamp1 : schematic. 4.21 Opamp1: placement. 4.22 Opamp2: schematic. 4.23 Opamp2: placement. 4.24 Opamp3: schematic. 4.25 Opamp3: placement 4.26 Opamp3: thermal profile

5.1 Overview of the analog routing tool. 5.2 Routing models ....... . 5.3 The line expansion algorithm. 5.4 Layout representations . . . 5.5 Routing cells ..... ... 5.6 Reconstructing a partial path. 5.7 Source region expansion ... 5.8 Expansion of regular routing cells 5.9 Expansion of via cells. 5.10 Path cost computation ... . 5.11 Symmetric routing ..... . 5.12 Routing multi-terminal nets. 5.13 Defect to fault mapping ... 5.14 Critical area for dielectric pinhole defects.

LIST OF FIGURES

68

73 74 75 81 82 84 86 86 90 91 92 92 97 97 99

103 108 109 110 111 112 113 114 116 117 117

121 123 127 128 129 130 130 132 132 135 137 138 141 142

LIST OF FIGURES

5.15 Critical area for shorts .................. . 5.16 Critical area for opens ................... . 5.17 Critical area and defect density as a function of defect size 5.18 Layout fragments, with equal expected number of faults. 5.19 Opamp1 : schematic. 5.20 Opampl : layout. .. 5.21 Opamp2: schematic. 5.22 Opamp2: layout. . .

6.1 Software architecture of the analog layout tool LAYLA 6.2 Layout models .................... .

xv

143 144

· 144 · 145

148 149 150 151

154 · 156