Analog to Digital Convertor MTT48 V1.0 ADC - 1

ANALOG TO

DIGITALCONVERTOR

(ADC)

Analog to Digital Convertor MTT48 V1.0 ADC - 3

Module Objective

Configure ADC for polled or interrupt operation

Configure the control registers

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Analog to Digital Convertor Module

• 14 Channels with Multiplexed Input

• Linear Successive Approximation

• 8 bit resolution

• Single or Continuous Conversion

• Conversion Complete Flag or Conversion Complete Interrupt

• Selectable ADC Clock

68HC08CPU

SystemIntegration

Module(SIM)

ClockGeneration

Module(CGM)

TimerInterfaceModule(TIM)

Byte Data Link

Controller

SerialCommunications

Interface(SCI)

Internal Bus (IBUS)

SerialPeripheralInterface

(SPI)

RandomAccess

Memory(RAM)

ElectronicallyProgrammable

ROM

LVR

COP

BREAK

RESET

Monitor ROM

IRQ

Analog to Digital Convertor

Analog Arming Function

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ADC Signals

I/O Signals : 13 I/O pins (port B and D)

ADC Analog Power Pin (VDDA)

ADC Analog Ground Pin (VSSA)

ADC Voltage Reference Pin (VDDAREF)

Power supply for setting the reference voltage VREFH

ADC Voltage Reference High Pin (VREFH)

One of two reference supplies and is generated from VDDAREF with a value VDDAREF/2

ADC Voltage Reference Low Pin (VLOW)

Lower Reference Supply for ADC

ADC Voltage In (ADVIN)

Input voltage signal from one of the fourteen channels

Analog to Digital Convertor MTT48 V1.0 ADC - 6

ADC Block DiagramINTERNALDATA BUS

Read DDRB/DDRD

DDRBx/DDRDxRESET

Write DDRB/DDRD

PTBx/PTDxWrite PTB/PTD PTB/Dx

Read PTB/PTD

• •

••

•

•

(ADC Channel 1)

Disable

Disable

ChannelSelect

ADCH[4:0]ADCSuccessive

ApproximationRegister

ADC Data Register

ADC Voltage In (ADVIN)

ClockGenerator

ADC Clock

InterruptLogic

ConversionComplete

AIEN COCO/IDMAS

Bus Clock

CGMXCLK

ADIV[2:0] ADICLK

Analog to Digital Convertor MTT48 V1.0 ADC - 7

CONTROL LOGICANALOG

CMP

DAC

V

7 0 0 DAC>V 1 DAC<VIN

INSAR ADR after

8 SHIFTS

SAR AND CONTROL

SAR

ADRIN

SAR SUCCESSIVE APPROXIMATIONS RESULT SUCCESSIVE APPROXIMATIONS ALGORITHM IN PSEUDO-CODE: ADR( )

{ FOR (m = 7 ; m > 0 ; – – m) { SAR = SAR << 1 ; IF ( DAC>VIN ) SAR = SAR & 0XFE; ELSE SAR = SAR|0X01; } RETURN (SAR) }

/* 8 TIMES THROUGH LOOP */ /* SAR SHIFTED LEFT ONE TIME */ /* SAR LSB = 0 IF V < DAC */ /* SAR LSB = 1 IF V > DAC */IN

Sample and hold

IN

Successive Approximations Method

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TIME

R E L A T I V E V O L T A G E

DAC OUTPUT

1011000010100000

11000000

10000000

10111000

A/D Conversion Successive Approximation Method

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ADC Registers

Three registers control and monitor ADC operations:

• ADC status and control register (ADSCR)

• ADC data register (ADR)

• ADC clock register (ADCLK)

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ADC Clock

RESET: 0 0 0 0 0 0 0 0

WRITE:

READ:

ADCLK

• ADC Clock Presacler Bits (ADIV2:ADIV0)– Selects divide ratio used by ADC to generate internal ADC clock

• ADC Input Clock Select (ADICLK)– Selects either bus clock or CGMXCLK as input clock source

1 = Internal bus clock0 = External clock (CGMXCLK)

Please Note: Internal ADC Clock must not exceed 1MHz

ADC Clock Register (ADCLK)

ADICLK ADIV0ADIV1 ADIV20 0 0 0

ADIV2 ADIV1 ADIV0 ADC Clock Rate

0 0 0

0 0 1

0 1 00 1 1

1 X X

ADC Input clock /1

ADC Input clock /2

ADC Input clock /4

ADC Input clock /8

ADC Input clock /16X = Don't Care

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ADC Status and Control

RESET: 0 0 0 1 1 1 1 1

WRITE:

READ:

COCO/ AEIN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 ADSCR

• Conversion Complete / Interrupt DMA Select (COCO/IDMAS)– Set when conversion is complete – Selects either CPU or DMA to service ADC interrupt request.– Cleared whenever ADC Status and Control Register is written or

whenever the ADC Data Register is read.

1 = Conversion completed(AEIN=0) / DMA Interrupt (AEIN=1)0 = Conversion not completed(AEIN=0) / CPU Interrupt (AEIN=1)

• ADC Interrupt Enable(AEIN)– Interrupt at end of ADC conversion1 = ADC Interrupt Enabled0 = ADC Interrupt Disabled

• ADC Continuous Conversion (ADCO)1 = Continuous ADC conversion0 = One ADC conversion

• ADC Channel Select Bits (ADCH[4:0])

– Select one of fourteen channels– If all bits are set to one ADC subsystem is turned off

ADC Status and Control Register (ADSCR)

IDMAS

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ADC Channel Select ADCH3 ADCH2 ADCH1 ADCH0 Input Select

0 0 0 0 ATD0, PTB0

0 0 0 1 ATD1, PTB1

0 0 1 0 ATD2, PTB20 0 1 1 ATD3, PTB3

0 1 0 0 ATD4, PTB4

0 1 0 1 ATD5, PTB5

0 1 1 0 ATD6, PTB60 1 1 1 ATD7, PTB7

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 0 0 0

0 0 0 10 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 01 0 0 1

1 0 1 0

1 0 1 1 RESERVED **

1 1 0 0 2*VREFC1 1 0 1 V REFC

1 1 1 0

0

0

0

0

0

0

0

0

0

0

00

0

0

0

0

1

1

1

1

1

11

1

1

1

1

1

1

1

1

1 1 1 1 1 [ADC power off]

ADCH4

ATD8, PTD5

ATD9, PTD4

ATD10, PTD3

ATD11, PTD2

ATD12, PTD1

ATD13, PTD0

Unused *

Unused *

Unused *

Unused *

Unused *

Unused *

Unused *

Unused *

Unused *

Unused *

Unused *

Unused *

Unused *

2*VREFL

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ADC Result

• ADC Data Register (ADR) – Contains 8-bit conversion result– Updated each time ADC conversion completes

RESET: X X X X X X X X

WRITE:

READ:

ADR

AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

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- Low Power Modes -

WAIT

• ADC module remains active

• ADC registers are not accessible– Except to DMA

• ADC module interrupt can wake MCU

STOP

• ADC module is inactive

• Any pending conversion is aborted

• Conversions resume when MCU exits stop mode after an extenal interrupt

• Allow one conversion cycle to stabilize the analog circuitry