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ANALYSIS AND DESIGN OF MASTER/SLAVE CURRENT SHARING VALIDATED BY CIRCUIT SIMULATIONS
Brian T. Irving Tim Daun-Lindberg
Development EngineerIBM Power, Technology and Qualification
Rochester MN
Member of R&D StaffDelta Products Corp.
RTP, NC
SEPTEMBER 2004
INTRODUCTION
Current sharing of paralleled power supplies used to achieve higher system reliability
each power supply has similar thermal performance
Master/slave current sharing scheme most often used
Design of master/slave current sharing generally not well understood
many design pitfalls exist• e.g. interconnect impedance between units critical for loop design
Due to its complexity, optimum design not often achieved
frequent last minute design changes leads to increased development time/cost
OBJECTIVE
To obtain physical insight into the dynamics of the master/slave current sharing scheme by analyzing its small-signal behavior
determine pole and zero positions relative to components values and operating conditions
Once pole and zero positions are determined, an optimum design can be obtained
Before system hardware is developed, validation of analytical calculations (e.g., calculations using Mathcad) should be obtained through circuit simulation (e.g., Pspice, SIMPLIS, etc.)
OUTLINE
Basic operation
Modelingexample circuit
phase-shift full-bridge with current mode controlrelate circuit to block diagram
Analyze block diagramidentify key loop gainsdesign voltage loop compensationdesign current sharing loop compensation
Validate design through simulationfrequency domaintime domain
Example of poor design
Conclusion
AUTONOMOUS MASTER/SLAVE IMPLEMENTATION
V OR L
I Ok
V CS
I On
I O1
CURRENTSENSE
D 1
EA
CS
V REF1
V CS1
POWERSTAGE
CURRENTSENSE
D k
EA
CS
V REFk
V CSk
POWERSTAGE
CURRENTSENSE
D n
EA
CS
V REFn
V CSn
POWERSTAGE
• Each unit connected in parallel
• common output voltage VO
• common current share bus VCS
ESTABLISHING MASTER/SLAVE RELATIONSHIP
V OR L
I Ok
I On
I O1
CURRENTSENSE
EA
CS
V REF1
POWERSTAGE
CURRENTSENSE
D k
EA
CS
V REFk
V CSk
POWERSTAGE
CURRENTSENSE
D n
EA
CS
V REFn
V CSn
POWERSTAGE
D 1
V =0 CS1
0
V CS
I01 > I0k > I0n
• Current-share bus voltage determined by module with highest current (master module)
• Any module can be
master
• In case of failure of current master, one of remaining modules becomes new master
VCS = VCS1 = VCS(MASTER)
MASTER
SLAVE
SLAVE
SIMPLIFIED CIRCUIT DIAGRAM OF SINGLE UNIT
HA16163TPHASE-SHIFT FULL-BRIDGE IC
n:1
DRIVER
RL
R INT
RS
PWM
I O
VO R CS
VIN
ADJUST AMPLIFIER
LOAD SHAREBUS
CURRENT SENSEAMPLIFIER
SHARE DRIVEAMPLIFIER
ERRORAMPLIFIER
VCS
EA
VREF
UC3902
VCS
R 40R
DEFINITION OF FUNCTIONAL BLOCKS – LOCAL SENSING
n:1
DRIVERRS
PWM
I O
VO
Kd
K
VIN
ADJUST AMPLIFIER
LOAD SHAREBUS
CURRENT SENSEAMPLIFIER
SHARE DRIVEAMPLIFIER
g m
ERRORAMPLIFIER
VIBUS
VILOCAL VADJ
V1VEA
EA
GEAVREF
GCA
GVC
RL
R INT
R CS
R 40RVCS
VCS
GADJ
G =1SD
GCS
LOCAL SENSING
( )OADJREFO1 I,V,V,VV f=
O3
ADJADJOd1
IG
VGVKV
+
+=
( )OEAO V,VI f=
O2EA1O VGVGI +=
0VREF =
DEFINITION OF FUNCTIONAL BLOCKS – REMOTE SENSING
n:1
DRIVERRS
PWM
VO
Kd
K
VIN
ADJUST AMPLIFIER
LOAD SHAREBUS
CURRENT SENSEAMPLIFIER
SHARE DRIVEAMPLIFIER
g m
ERRORAMPLIFIER
VIBUS
VILOCAL VADJ
V1VEA
EA
GEAVREF
GCA
GVC
RL
R INT
R CS
R 40RVCS
VCS
GADJ
G =1SD
GCS
I OREMOTE SENSING
O3
ADJADJOd1
IG
VGVKV
+
+=
O2EA1O VGVGI +=
0G3 =0VREF =
( )OADJREFO1 I,V,V,VV f=
( )OEAO V,VI f=
BLOCK DIAGRAM OF SINGLE UNIT
GVC
+
-
V EA^
V O ^
G1
GEAK
TV
VREF-+
G2
GADJ
GCA
G3
Kd
V ^1
+
- +-V ILOCAL^
I O ^
V IBUS^
GCS
T D TCS
GSD
V ADJ^
• Multiloop control system
• voltage loop TV
• current share loop TCS
• droop share loop TD
KGKGT EAdVCV =
ADJCACS1EACS GGGKGGT =
31EAD GKGGT =
DESIGNING A MULTILOOP SYSTEM
• Voltage loop→ requires high bandwidth for good load regulation performance
• Current sharing loop→ requires high gain at low frequency for good dc current sharing→ loop bandwidth not critical
• must ensure stable design
• Separation of crossover frequencies of voltage and current-share loops is necessary to minimize interaction between loops
→ loop interaction causes oscillations in output current of paralleled units
• High bandwidth loops closed first
DESIGN OF VOLTAGE LOOP COMPENSATION
0
- 1
0
0
f p1
cv
f [kHz]
f [kHz]v [dB]T
[dB]
f [kHz]0
- 1 0
f zc f p
0
- 1
[dB]
G EA
f z1
G vcK Kd
OPENLOOPGAIN
- 1
f cv
f
- 1
GVCKdK
GEA
TV
• Current sharing loop TCS is open
• Loop gain TV requirements• high dc gain for regulation
accuracy• high loop bandwidth (crossover
frequency) fcv for fast dynamic response
• stable
CIRCUIT DIAGRAM OF TWO UNITS CONNECTED IN PARALLEL
RL
DRIVER
VCS
VILOCAL
VREF
VIN
VCS
VCS
VREF
VILOCAL
DRIVER
VIN
VCS
V O
V IBUS
UNIT 1 UNIT 2
BLOCK DIAGRAM OF TWO UNITS CONNECTED IN PARALLEL
GVC
+
-
G1
GEAK VREF-+
G2
GADJ
GCA
G3
Kd
+
- +-V ILOCAL^
GCS
GSD
s
+
s s
s
s
s
s
ss
s
s
s
s
s
s
GVC
+
-VREF -
+
G3
+
-+ -GCS
GSD
KGEA
Kd
G2
GCA m
G1
GADJ
+
m
mm
m
m
m
m
m m
m
V ILOCAL^ m
m
V O ^
V IBUS ^
UNIT 1 UNIT 2
ESTABLISHING MASTER/SLAVE RELATIONSHIPmILOCAL
sILOCAL VV <
GVC
+
-
G1
GEAK VREF-+
G2
GADJ
GCA
G3
Kd
+
- +-V ILOCAL^
GCS
GSD
s
s s
s
s
s
s
ss
s
s
s
s
s
s
GVC
+
-VREF -
+
G3
+
-+ -GCS
GSD
KGEA
Kd
G2
GCA m
G1
GADJ
m
mm
m
m
m
m
m m
m
V ILOCAL^ m
m
+ +
V O ^
V IBUS ^
SLAVE MASTERUNIT 1 UNIT 2
SIMPLIFIED BLOCK DIAGRAM
IBUSmILOCAL
sILOCAL VVV =<
GVC
+
-
G1
GEAK VREF-+
G2
GADJ
GCA
G3
Kd
+
- +-V ILOCAL^
GCS
s
s s
s
s
s
s
ss
s
s
s
s s
GVC
+
-VREF -
+
G3
+
-GCS
GSD
KGEA
Kd
G2G1
m
mm
m
m
m
m
m m
m
V ILOCAL^ m
+ +
V O ^
V IBUS ^
SLAVE MASTERUNIT 1 UNIT 2
SIMPLIFIED BLOCK DIAGRAM
IBUSmILOCAL
sILOCAL VVV =<
GVC
+
-VREF-
+
G2
GADJ
GCA
Kd
+
- +-V ILOCAL^
GCS
s
G1
GEAK
G3
s s
s
s
s
s
ss
s
s
s
s s
GVC
+
-VREF -
+
G3
+
-GCS
GSD
KGEA
Kd
G2G1
m
mm
m
m
m
m
m m
m
V ILOCAL^ m
+ +
V O ^
V IBUS ^
TCST
D
SLAVE MASTERUNIT 1 UNIT 2
CURRENT SHARING LOOP GAIN FOR IDENTICAL POWER SUPPLIES WITH REMOTE SENSING
+
-
v EA^
G1
GEAK VREF-+
GADJ
GCA
G =03
v ^1
+
- +-v ILOCAL^I 0
^GCS
TCS
v IBUS^
T1
v O^ G 2
v O^ K d• Identical blocks
• Remote sensing (G3 = 0)
CA
G
1EAADJCSCS GKGGGGTPLANT 444 8444 76
=
CAPLANT0G1RS
1 GGTT3
−===
f 0
- 1
0
0
- 1
REMOTEPLANTG
G zeroEA
G pole1
Due to finite open loop gain of G
EA
CURRENT SHARING LOOP GAIN FOR IDENTICAL POWER SUPPLIES WITH LOCAL SENSING
+
-
v EA^
G1
GEAK VREF-+
GADJ
GCA
G3
v ^1
+
- +-v ILOCAL^I 0
^GCS
TCS
v IBUS^
T1
v O^ G 2
v O^ K d
f 0
- 1
0
0
- 1
0 - 1
0 - 1
REMOTE
LOCAL
PLANTG
D
PLANT
T1
G+
KGGGT EA31D =
CAD
PLANTLS1 G
T1
GT+
−=
CA
G
1EAADJCSCS GKGGGGTPLANT 444 8444 76
=
• At breakpoint T1→ gain significantly higher at low
frequency when remote sensing is implemented
→ low frequency poles do not coincide
• Good design practice→ compensate for remote sensing
• Identical blocks
DESIGN OF CURRENT SHARE LOOP FOR REMOTE SENSING
• Crossover frequency (bandwidth) of current share loop fCI must be at least one
decade (ten times) lower than crossover frequency (bandwidth) of voltage loop fCV
CVCI ff <<
• Separation of crossover frequencies of voltage and current-share loops is necessary to minimize interaction between loops
→ loop interaction causes oscillations in output current of paralleled units
• Loop gain optimization can only be performed using analytic approach
→ knowledge of pole and zero positions relative to components values and operating conditions is necessary for proper loop compensation
• Validation of loop gain should be done using simulation software prior to hardware development
DESIGN OF CURRENT SHARE LOOP FOR REMOTE SENSING
f 0
- 1
0
f CI
0 - 1
T1RS
f
f
GCA
GPLANT
0 - 1
- 1
- 1
- 2
2-3 octaves
T crossover frequency
V
G zeroEAG pole1
f CI
f CV
f CV
0
01-2 decades
- 2
• Compensation GCA→ current sharing loop bandwidth fCI
1-2 decades below voltage loop bandwidth fCV
→ zero placed 2-3 octaves below desired current sharing crossover frequency fCI
• to boost phase margin
→ integrator for good current sharing accuracy
CURRENT SHARE LOOP GAIN FOR LOCAL SENSING INHERENTLY STABLE
f 0
- 1 0
f CI
0 - 1
T1
f
f
GCA
GPLANT
0 - 1
- 1
- 1
- 2
T crossover frequency
V
f CI
f CV
f CV
0
0
- 2
0 - 1
0
- 1
- 2
- 1 0
- 1
- 1 -1 slopePM=90 o
LOCAL
REMOTE
LOCALREMOTE
D
PLANT
T1
G+
• Compensation GCA
→ local sensing significantly lowers loop bandwidth
→ crossover with –1 slope, ensuring acceptable phase margin PM
VERIFICATION OF VOLTAGE LOOP GAIN
• Good agreement between analytical calculations and Simplis circuit simulation up to half of switching frequency fSW
0.1 1 10 100 1 .103 1 .104 1 .105 1 .106100
80
60
40
20
0
20
40
60
80
frequency [Hz]
[dB
]
0.1 1 10 100 1 .103 1 .104 1 .105 1 .106100
80
60
40
20
0
20
40
60
80
100
120
140
160
180
fequency [Hz]
[deg
]
PM=80o
SimulationSimulation
AnalyticalAnalytical
fSW
fSW
GAIN PHASE + 180o
fCV
fCV
VERIFICATION OF CURRENT SHARE LOOP GAIN FREQUENCY DOMAIN
• Good agreement between analytical calculations and Simplis circuit simulation up to voltage loop crossover frequency fCV
REMOTE SENSING
0.1 1 10 100 1 .103 1 .104 1 .105 1 .106150
125
100
75
50
25
0
25
50
75
100Gain
[dB
]
0.1 1 10 100 1 .103 1 .104 1 .105 1 .10690
45
0
45
90
135Phase + 180 deg
frequency [Hz]
[deg
]
SimulationSimulation
Analytical
AnalyticalPM=76o
fCV
fCV fSW
fSW
GAIN PHASE + 180o
VERIFICATION OF CURRENT SHARE LOOP GAIN FREQUENCY DOMAIN
• Good agreement between analytical calculations and Simplis circuit simulation up to voltage loop crossover frequency fCV
LOCAL SENSING
0.1 1 10 100 1 .103 1 .104 1 .105 1 .106150
125
100
75
50
25
0
25
50
75
100
[dB
]
0.1 1 10 100 1 .103 1 .104 1 .105 1 .10690
45
0
45
90
135
frequency [Hz]
[deg
]fCV
fCV fSW
fSW
Local
RemoteLocal
Remote
GAIN PHASE + 180o
PM=100o
SimulationSimulation
Analytical
Analytical
VERIFICATION OF CURRENT SHARE LOOP GAIN TIME DOMAIN
REMOTE SENSING
MASTER
SLAVEcurrent loop openedfor 1msec
V23.1V
V25.1VsREF
mREF
=
=
• Individual output currents shown to converge→ demonstrates stability
EFFECT OF INTERCONNECT RESISTANCE RINT ON CURRENT SHARING LOOP GAIN
• As interconnect resistance RINT decreases, current share loop gain increases at low frequency
LOCAL SENSING
0.1 1 10 100 1 .103 1 .104 1 .105 1 .106100
80
60
40
20
0
20
40
60
80
100
[dB
]
0.1 1 10 100 1 .103 1 .104 1 .105 1 .10690
45
0
45
90
135
frequency [Hz]
[deg
]fCV
fCV fSW
fSW
Local
Remote Local
Remote
GAIN PHASE + 180o
3.3mΩ
RINT = 0.5mΩ
3.3mΩ
RINT = 0.5mΩ
EXAMPLE OF POOR DESIGN
f 0
- 1 0
f CI
0 - 1
T1
f
- 1
- 1
- 2
f CI
f CV
f CV 0
- 2
0 - 1
0
- 1
- 2
- 1
- 1
LOCAL
REMOTE
LOCALREMOTE
- 3
- 2 - 2
- 2
- 3
45< PM < 90oo
f
GCA0
- 1
0
- 1
PM < 0 !!o
G1GADJ GEA K
G1
1 + GADJ GEA K
TD
f - 1
0GCS
0
without Cfl
with C fl
• Poor loop design
→ Example• using traditional 2 pole,
1 zero compensation while filtering current sense signal
→ Local sense• stable with excellent
phase margin
→ Remote sense• unstable with negative
phase margin!
VCS
R 40R
RCS Cfl
IO
GCS
EXAMPLE OF POOR DESIGN – FREQUENCY DOMAIN
• Good agreement between analytical calculations and Simplis circuit simulation up to voltage loop crossover frequency fCV
LOCAL SENSING
0.1 1 10 100 1 .103 1 .104 1 .105 1 .106250
180
110
40
30
100
[dB
]
0.1 1 10 100 1 .103 1 .104 1 .105 1 .10690
60
30
0
30
60
90
frequency [Hz]
[deg
]
SimulationSimulation
Analytical
Analytical fCV
fCV fSW
fSW
Local
RemoteLocal
Remote
GAIN PHASE + 180o
PM=70o
PM= -8o
EXAMPLE OF POOR DESIGN – TIME DOMAIN
MASTER
SLAVE
REMOTE
LOCALV23.1V
V25.1VsREF
mREF
=
=
• Individual output currents→ stable for local sensing→ unstable for remote sensing
CONCLUSION
• Detailed knowledge of each power supply essential for proper current sharing loop design
• Design of current share loop gain compensation should be done for remote sensing
• Analytical modeling shown to gain physical insight into pole/zero locations
→ knowledge of pole and zero positions relative to components values and operating conditions is necessary for proper loop compensation
• Simulation tools provide validation of the design which is useful prior to hardware development
APPENDIX
kHz143fSW =
358.2mc =
665.0D =
HA16163TPHASE-SHIFT FULL-BRIDGE IC
n:1
DRIVER
RL
R INT
RS
PWM
I O
VO R CS
VIN
ADJUST AMPLIFIER
LOAD SHAREBUS
CURRENT SENSEAMPLIFIER
SHARE DRIVEAMPLIFIER
ERRORAMPLIFIER
VCS
EA
VREF
UC3902
VCS
R 40R
g m
C F L F
L F
RD1
RD2
RI
C FP
C FS RF
RADJ C CA
RCA
C PCA
385 V
12V
80A
0.15Ω
2R
R
3.3mΩ
9.4mΩ
6.6mF
3.9mΩ6.8µΗ
6.8µΗ
n=10.67
17.2kΩ
950µΩ
2kΩ
1.25V
14.4kΩ
32pF
1.6nF820kΩ
40kΩ
4.5mS
450µΩ
51µΩ 28Ω
r c
APPENDIX
( )( )2n
2
pn
p
zc
cfSW
LS
LVC s
Qs1
1
s1
s1
5.0D1m2Lf
R1
1
R
RG
ω+
ω+ω+
ω+
−−+=
fczc
Cr
1=ω
( )( )5.0D1mCLf
2
CR
1c
ffSWfLp −−+=ω
SWn fπ=ω
( )( )5.0D1m
1Qc
p−−π
=
O
REFd
V
VK =3
1K =
ω+
ω+
ω=
1p
1zIEA s1
s1
sG ( )fpfsI
ICCR
1
+=ω
fsf1z
CR
1=ω
fpfs
fpff
1p
CC
CCR
1
+
=ω
1pg
zc
S1 s1
s1
R
1G
ω+
ω+
=
( )INTCScf1pg
RRrC
1
++=ω
1pg
f2 s1
sCG
ω+
=
1D2DI
2DIINT3
RR||R
R||RRG+
=
CSCS R40G =
ADJ
1D2DIADJ
R
R||R||RG =
REFERENCES
1. V.J. Thottuvelil, G.C. Verghese, “Stability analysis of paralleled dc/dc converters with active current sharing”, IEEE Power Electronics Specialists Conf. (PESC) Rec., June 1996.
2. V.J. Thottuvelil, G.C. Verghese, “Analysis and control design of paralleled dc/dc converters with current sharing”, IEEE Applied Power Electronics Conf. (APEC) Proc., Feb. 1997.
3. Q. Chen, “Stability analysis of paralleled rectifier systems”, IEEE International Telecommunications Energy Conf. (INTELEC) Proc., Oct. 1995.
4. L. Balogh, “The ucc3902 load share controller and its performance in distributed power systems”, Texas Instruments application note SLUA128A.
