© Semiconductor Components Industries, LLC, 2015

September, 2015 − Rev. 11 Publication Order Number:

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MatrixCam� Video Development Kit Hardware Developer's Guide

IntroductionThis document describes the MatrixCam Video Development Kit’s

HW design information from a system design perspective. Usersseeking more detailed component level hardware specifications areencouraged to read the respective component data sheet from eachvendor. The links to all vendors website are included in the end of thedocument.

This HDG (Hardware Developer’s Guide) includes the followinginformation:• MatrixCam� VDK Hardware Architecture Overview• MatrixCam VDK Hardware Blocks in Details• MatrixCam VDK System Board Schematics• MatrixCam VDK System Board Layout File• MatrixCam VDK System Board Gerber File• MatrixCam VDK System Board BOM

MatrixCam VDK OverviewThe MatrixCam VDK is a low power smart 1080p camera over

Wi-Fi® and Ethernet for the IoT applications. It is a reference designand can be easily integrated into a third party ID casing mechanical.MatrixCam VDK has different resolutions and frame rates for videostreaming, as well as various options for video storage.

The main features of the MatrixCam VDK are:• Low Power Sleep Mode can be Woken Up by PIR Motion Sensing

or BLE• JPEG or Video Clips Stored in Local SD Card in Camera• Video Clips can be Optionally Stored in the Cloud• View Streaming from a Remote Device through Cloud or Local

Wi-Fi Viewing from any Smart Device, or PC Viewing throughWi-Fi/Wired Ethernet

• Two Way audio Communications: Speaker and Microphone• Push Notifications to Smart Devices

The diagram below shows the top level blocks of the camera:

Figure 2. MatrixCam VDK Camera Block Diagram

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APPLICATION NOTE

Figure 1. MatrixCam VDK Camera

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MatrixCam VDK Key Components and Specs

Application Processor: TI−DM368• 1080p @ 30 fps H264 Video Streaming• Picture Capture Mode: 1920 × 1080 JPEG• Built-In Image Signal Processor (ISP)• Intelligent Video Streaming• DDR2 SDRAM Support with 256 MB Memory

Capacity• NAND/NOR Memory Support for Boot

Image Sensor: AR023Z• Low Noise, 1/3″, 2 MP CMOS Sensor• Parallel Interface• Resolution: 1920 × 1080 @ up to 60 fps

Wireless Connectivity:• Wi-Fi: GainSpain GS2011MIES

♦ Single Band (2.4 GHz) Wi-Fi Module Supporting802.11 b/g/n

♦ Client Mode Wi-Fi Support♦ Low Power in Standby Mode

• Bluetooth®: nRF51822♦ BLE 4.0♦ Be able to Configure the Camera via Bluetooth

Lens Specification:• Horizontal and Vertical Field of View

♦ HFOV: 110°♦ VFOV: 82°

• Manual Focus• IR Cut Filter• F 2.0

Audio:• Microphones: Omni-Directional Microphones• Audio Encoding: 8/16 kHz, 32/64 kbps AAC−LC or

G.711• Speaker: Soberton 0.5 W Cellphone Speaker

Ethernet:• IEEE 802.3u 10/100 mbps

Motion Sensor:• Passive Infra-Red• Horizontal Range Up to 140°

Storage:• microSD� Card Slot for microSD or SDHC� Cards

LED:• Multi-Color LED for Status Display

Real Time Clock:• RTC in GS2011MIES Module• 32.768 kHz

(Micro) USB Connector:• For Debugging• Retrieving Pictures from SD Card• DC Power and Charging

Power Switch:• To Turn ON/OFF the System

Reset Button:• To Reset the Board, Including DM368 and Wi-Fi

Module

Debug Header:• UART Header for GS2011MIES

POWER Source:• Power/Charge through Micro-USB Port

• Single Cell Lithium Ion Battery

Mechanical Dimensions:• Main Board Dimension 95 mm × 65 mm

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MatrixCam VDK Overall Block DiagramThe top level system architecture diagram of MatrixCam

VDK is shown in Figure 3.

Figure 3. MatrixCam VDK Interconnection Diagram

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MAIN PROCESSOR

The TI DaVinciDM368 SoC contains an ARM926EJ−S®

Core, ARM9 Memory Architecture, Video ProcessingSubsystem as well as many peripherals and sub-systems.

Following diagram shows the internal architecture ofDM368 application processor.

Figure 4. DM368 Internal Architecture

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DM368 Memory Interfaces and External Interconnections

DDR2 Controller• 256 MB memory space• 16 bits data bus width• CAS latencies DDR2: 2, 3, 4, and 5• Internal banks: DDR2: 1, 2, 4, and 8• Burst length: 8

• 1 CS signal• Page sizes: 256, 512, 1024, and 2048• DDR2 SDRAM with 340 MHz operating frequency• Mobile LP DDR with 167 & 200 MHz operating

frequency

Figure 5. DM368 DDR2 Controller

DDR_A[13:0]

DDR_BA[2:0]

DDR_DQ[15:8]

DDR_DQ[7:0]

DDR_DQM[1]

DDR_DQS[1]

DDR_DQS[1]#

DDR_DQM[0]

DDR_DQS[0]

DDR_DQS[0]#

DDR_CLK

DDR_CLK#

DDR_CS#

DDR_CAS#DDR_RAS#

DDR_WE#

DDR_CKE

DDR_VREF

DDR_PADREF

DM368 DDR2 Controller

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DDR2 DRAMDDR2 part number MT47H128M16RT−25E/

AS4C128M16D2−25BCN is used in the MatrixCam VDK.It supports 8M location with 8 Banks in 16-bit data interfaceand CAS latency of CL = 5.

The diagram below shows the interface between DDR2memory controller of DM368 and the DDR2 memory.

Figure 6. DDR2 Memory Interface

DMSoCDM368 TI

DDR2MT47H64M16HR−25E

MICRON

DDR_A[13:0] A[13:0]

DDR_BA[2:0] BA[2:0]

DDR_VREF

DDR_CLKDDR_CLK#DDR_CS#

DDR_CAS#DDR_RAS#

DDR_WE#DDR_CKE

DDR_PADREF

DDR_DQ[15:8] DQ[15:8]DDR_DQM[1] UDMDDR_DQS[1]DDR_DQS[1]#

DDR_DQM[0]

UDQS

LDM

UDQS#

DDR_DQS[0] LDQSDDR_DQS[0]# LDQS#

CKCK#CS#CAS#RAS#WE#CKE

VREFODT

DDR_DQ[7:0] DQ[7:0]

NOR Flash InterfaceNOR flash is used to support the fast booting of the

system* [In a later FW update].

DM368 support asynchronous memory interface:• SRAM on up to two asynchronous ships selects

addressable up to 16 MB with 16 bit and 8 MB with8 bit data line interface

• Asynchronous memory controller of DM368 supportsboth normal mode and strobe mode of operation

• Normal mode of operation would be a suitable mode ofoperation for NOR Flash memory interface

* NOR Flash boot is not supported in the initial release.

Figure 7. DM368 EMIF Controller

EMC_CE#[3:2]

DM368−EMIFController

EM_WE#

EM_OE#

EM_WAIT

EM_D[15:0]

EM_A[13:0]

EM_BA[13:0]

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• The EMIF address pin EM_A [0] always provides theleast significant bit of a 32-bit address

• EM_A [0] does not represent the lowest AEMIFaddress bit. The EMIF supports only 16-bit and 8-bitdata widths

• In 8-bit mode, EM_BA [1:0] represent the 2 leastsignificant address bits

• Chip select with 16 MB with 16-bit is used in theMatrixCam VDK

Micron NOR Flash PC28F128M29EWLA has thefollowing specifications:• 65 nm Single-Level Cell (SLC) technology• Uniform block flash memory, highest block protected

by VPP/WP#• Supply voltage: 2.7 to 3.6 V• VPP/WP# pin protection – protects first or last blocks

regardless of block protection settings• Low power consumption: standby and automatic mode• Minimum 10000 PROGRAM/ERASE cycles per block• Random access: 70 ns

Table 1. UNIFORM BLOCK MEMORY MAP OF NOR FLASH

Block Block Size

Address Range (x8)

Block Size

Address Range (x16)

Start End Start End

127 128 kB 0FE 0000h 0FE FFFFh 64 kB 07F 0000h 07F FFFFh

… … … … …

63 07E 0000h 07E FFFFh 03F 0000h 03F FFFFh

… … … … …

0 000 0000h 001 FFFFh 000 0000h 000 FFFFh

Following image shows the mapping between the EMIFand the connected device’s data and address pins for 16-bitdata bus interface.

Figure 8. NOR Flash Interface

DM368−EMIF

EM_D[15:0]

EM_A14/EM_BA[0]

EM_A[13:0]

EM_A[21:15]

EM_BA[1]

NOR FlashPC28F128M29EWLA

MICRON

DQ[15:0]

A[15]

A[14:1]

A[22:16]

A[0]

RY/BY#GPIO

WP#

VCC

GPIO Reset

EMC_CE#[0]

EM_WE#

EM_OE#

CE#

OE#

WE#

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NAND FlashThe on-board 128 MB NAND flash is used for system

booting.EMIF address lines are used to drive the NAND Flash

device’s command latch enable (CLE) and address latchenable (ALE) signals. Any EMIF address line may be usedto drive the CLE and ALE signals of the NAND Flash.However, it is recommended, especially when booting fromNAND Flash, that EM_A[2:1] be used. This is because thesepins are not mux with another peripheral and are thereforealways available.NOTE: The EMIF will not control the NAND Flash device’s write

protect pin. The write protect pin must be controlled outsideof the EMIF.

Micron NAND Flash MT29F2G08ABAEAH4−ITE hasthe following specifications:• Open NAND Flash Interface (ONFI) 1.0-compliant• Single-Level Cell (SLC) technology• Memory organization

♦ Page size x8: 2112 bytes (2048 + 64 bytes)♦ Block size: 64 pages (128 KB + 4 KB)♦ Device size: 2 GB: 2048 blocks

• Ready/Busy# (R/B#) signal provides a hardwaremethod for detecting operation completion

• WP# signal: write protect entire device• Internal data move operations supported within the

device from which data is read.

Figure 9 shows the NAND flash memory interface withEMIF of DM368.

Figure 9. NAND Flash Interface

DM368 EMIF

CLE_EM_A[2]

CLE_EM_A[1]

EM_CE#[0]

EM_WE#

EM_OE#

FLASH−NANDMT29F2G08ABAEAH4−IT:E

MICRON

CLE

ALE

CE

WE

OE

IO[7:0]EM_D[7:0]

WP#

R/B#EM_WAIT

VCC

SD Card InterfaceThe MatrixCam VDK has a microSD card slot for local

storage and development purpose. It has a Push in-Push outmechanical design for ease of use.

The part number of the microSD connector isDM3BT−DSF−PEJS from Hirose.

Secure Digital Card Controller has these features:• Supports a max clock rate of 50 MHz (Fast Mode) for

microSD cards• Secure Digital (SD) Physical layer specification V1.1

• Note the MMC/SD controller does not support the SPImode of operation

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Figure 10. SD Card Interface

DM368

SD_CLK

uSD Card

SD_CMD

SD_DATA[3:0]

CLK

CMD

DATA[3:0]

The MMC/SD controller has two clocks, the functionclock and the memory clock.

The function clock determines the operational frequencyof the MMC/SD controller and is the input clock to theMMC/SD controller on the device. The MMC/SD controlleris capable of operating with a function clock up to 100 MHz.

The memory clock appears on the SD_CLK pin of theMMC/SD controller interface. The memory clock controlsthe timing of communication between the MMC/SDcontroller and the connected memory card. The memoryclock is generated by dividing the function clock in theMMC/SD controller. The divide-down value is set byCLKRT bits in the MMC memory clock control register(MMCCLK) and is determined by the equation:• Memory Clock Frequency = Function Clock

Frequency / (2 ⋅ (CLKRT + 1))• CLKEN bit in MMCCLK determines whether the

memory clock appears on the SD_CLK pin. If CLKENis cleared to 0, the memory clock is not provided exceptwhen required

• SD card is interfaced to SD0 of the DM368

Table 2. SD INTERFACE SIGNAL DESCRIPTION

Pin Type SD Communications

MMCSD0_CLK O Clock Line

MMCSD0_CMD I/O Command Line

MMCSD0_DAT0 I/O Data Line 0

MMCSD0_DAT1 I/O Data Line 1

MMCSD0_DAT2 I/O Data Line 2

MMCSD0_DAT3 I/O Data Line 3

USB InterfaceTwo micro-USB connectors present on the MatrixCam

VDK supporting the following features:• For debugging• Retrieving pictures from the SD card• For DC power and for battery charging

Figure 11. USB Ports Feature Mapping

Serial Console forDebugging

USB TOUART

Converter

USBMicro USB

PORT2

For Debugging

DM368

UART

USB

Dedicated Charger

PC/LAPTOP

BATTERYCAHRGERBATTERYFor Battery

Charging

Micro USBPORT1

USB

FirmwareUpgrade

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Features of DM368 USB2.0 controller:• Supports USB 2.0 peripheral at high speed (480 Mbps)

and full speed (12 Mbps)• Supports USB 2.0 host at high speed (480 Mbps), full

speed (12 Mbps), and low speed (1.5 Mbps)

• Each endpoint can support all transfer types (control,bulk, interrupt, and isochronous)

Table 3. USB 2.0 INTERFACE DESCRIPTION

Name I/O Description

USB_DP A I/O/Z USB D+ (Differential Signal Pair)

USB_DM A I/O/Z USB D− (Differential Signal Pair)

USB_ID A I/O/Z USB operating mode identification pin for device mode operation only, pull up this pin to VDDwith a 1.5 k� resistor. For Host mode operation only, pull down this pin to ground (VSS) with a1.5 k� resistor. If using an OTG or mini-USB connector, this pin will be set properly via the cable/connector configuration.

USB_VBUS A I/O/Z Five volt input that signifies that VBUS is connected. The OTG section of the PHY can also pullup/down on this signal for HNP and SRP. For device or host mode operation only, pull up this pinto 5 V with a 1 k� resistor. For host mode operation, tie USB power signal on USB connector to5 V also. For mixed host/device mode operation, tie this to the charge pump.

USBDRVVBUS I/O/Z Digital Output to Control External 5-V Supply

For DebuggingMatrixCam VDK has an on-board FT230XS USB to

UART converter therefore there is no need tu use an externalUSB to UART device for debugging.

Retrieving Pictures/Video from SC CardWhen the product USB port connect into host PC in client

mode, it will detected as USB mass storage to transfer thestored data from microSD card into Host PC [To beimplemented in the future release].

For DC Power and Battery ChargingThe internal main battery of the product is charged by the

external wall charger or USB downstream port though USBconnector. The DC 5 V power can also be fed to theMatrixCam VDK through the USB connector.

DM368 Audio InterfaceAn omnidirectional microphone and a 0.5 W Speaker are

in the MatrixCam VDK. 8/16 kHz, 32/64 kbps AAC−LCand G.711 audio encoding are supported for capturingsurrounding noise and playing back the recorded files storedin the SD card.

DM368 has a Voice Codec with FIFO (Read/Write). Thefollowing features are supported on the Voice Codecmodule:• Full differential microphone amplifier• Monaural single ended line output• Monaural speaker amplifier (BTL)

• Dynamic range: 70 dB (DAC)• Dynamic range: 70 dB (ADC)• 200-300 mW speaker output at RL = 8 �

• Sampling frequency: 8 kHz or 16 kHz• Automatic level control for recording

Figure 12. Voice Codec Interface

Microphone

Speaker

Pre−Amp

DM368−Voice Codec

MICIP

MICIN

VCOM

SPP

SPNAmplifierNCP2824

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Speaker OutputThe SPP and SPN pins are monaural speaker differential

outputs (BTL) with a maximum of 240 mW rms into an 8 �

load per spec, but for this product this power would not besufficient hence a Class-D Amplifier NCP2824 of 0.6 W@ 3.6 V THD + N < 1% or 0.8 W THD + N < 1% is used.

The NCP2824 is a Filter less Class D amplifier capable ofdelivering up to 2.4 W to a 4 � load with a 5 V supplyvoltage. With the same battery voltage, it can deliver 1.2 Wto an 8 � load with less than 1%THD+N. The non-clippingfunction automatically adjusts the output voltage in order tocontrol the distortion when an excessive input is applied tothe amplifier. This adjustment is done from an AutomaticGain Control circuitry (AGC) built into the chip. A simplesingle wire interface allows to the non-clipping function tobe enabled and disabled. It also allows the maximumdistortion level in the output to be configured.A programmable power limit function is also embedded inorder to protect speakers from damage caused by anexcessive sound level.

MIC InputThe microphone input pins (MICIN and MICIP) can be

used as a fully differential microphone of line input withselectable 20 dB or 26 dB boost and 0.07 V rms input. Theseanalog inputs have high input impedance (10 k�), which isnot changed by gain setting.

The single ended output mic shall be connected withPre-amplifier circuit to meet full scale input voltage range ofMic input and Band pass filter circuit to bypass thehigh & low frequency noise.

Table 4. DM368 AUDIO INTERFACE DESCRIPTION

SignalName

SignalType Function

MICIP Input MIC Positive Signal

MICIN Input MIC Negative Signal

SPP Output Speaker Amplifier Positive Signal

SPN Output Speaker Amplifier Positive Signal

VCOM Input Analog Block Common Voltage

Microphone Interface DetailsPlease refer to the DM368 data sheet for a detailed

description of the microphone anti-aliasing filter,preamplifier design, and single ended to differentialconversion.

DM368 Boot ModesDM368 supports 8 different Boot modes and configurable

Power-Saving modes. These boot modes support in twodifferent ways.• On-chip ARM ROM Boot Loader (RBL) to boot from

NAND Flash, MMC/SD, UART, USB, SPI, EMAC, orHPI

• AEMIF (NOR and one NAND)

The ARM can boot from either Asynchronous EMIF (forNOR Boot) or from ARM ROM (for NAND Boot), asdetermined by the setting of the device configuration pinsBTSEL[2:0]. The boot selection pins (BTSEL[2:0])determine the ARM boot process.• BTSEL[2:0] = 000 − NAND Boot mode• BTSEL[2:0] = 001 − NOR/One NAND Boot mode• BTSEL[2:0] = 010 − MMC0/SD0 Boot mode• BTSEL[2:0] = 011 − UART0 Boot mode• BTSEL[2:0] = 100 − USB Boot mode• BTSEL[2:0] = 101 − SPI0 Boot mode• BTSEL[2:0] = 110 − EMAC Boot mode• BTSEL[2:0] = 111 − HPI Boot mode

Device Boot Configuration RegistersThe device boot configuration value is the state of the

BTSEL[2:0] and AECFG[2:0] signals are captured in theBOOTCFG register. The AECFG[2:0] input pins determinethe AEMIF configuration immediately after reset. By usingAECFG[2:0] to properly configure the AEMIF address andData pins.

Booting OptionsThe MatrixCam VDK supports both NOR Flash and

NAND Flash boot in the initial FW release.

NOR Flash BootIf BTSEL[2:0] = 001 − Asynchronous EMIF boot mode

(NOR Flash). This mode is handled by hardware control anddoes not involve the ROM. If booting from NOR Flash thenthe appropriate number of address output must be enabledby the AECFG[2:0] inputs at reset. In 16-bit mode,EM_BA[1] represents the least significant address bit (thehalf−word address) and EM_BA[0] represents the addressbit (A[14]). The device has 23 address lines and 2 chipselects with an 8-bit or 16-bit option.

For boot from 16 bit NOR Flash interface, theresistor/register setting of AECFG is set to 101 to get MSBdata lines and 16 address lines (EM_A[14:0] andEM_BA[1]) for NOR Flash boot.

NAND Flash BootIf the value of BTSEL[2:0] = 000, the NAND Boot mode

executes. NAND Flash boot wouldn’t support for a fullfirmware boot. Instead, copies a second stage user-bootloader (UBL) from NAND Flash to ARM internal RAM(AIM) and transfers control to the user-defined UBL and itsupport 4-bit ECC.

The NAND boot mode assumes the NAND is located onthe EM_CE0 interface, the bus configuration is configuredby the AECFG[2:0] pins. There is specific AECFGconfiguration required for NAND boot as all the requiredsignals are available in the default state AECFG[2:0] = 000.

NAND Boot supports 8-bit Flash interface only and it isrecommended that EM_A[2:1] should be used for CLE andALE especially when booting from NAND Flash. This is

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because these pins are not muxed with another peripheraland are therefore always available.

Chip Select: EM_CE[0] is used for the default boot andROM boot modes. By default, NOR Flash will be connectedin EM_CE[0] and NAND Flash will be connected in

EM_CE[1]. And option will be provided to swap the chipselects, to select NAND Flash as a Boot memory.

Following flow chart shows the Boot sequence in case ofNAND Flash as boot device:

Figure 13. Boot Mode Selection Flow Chart

NANDBoot

MMCSDBoot

UARTBoot

USBBoot

BootOK?

No

Yes

No

Yes

No

Yes

No

Yes

UBL

Reset

RBLBOOT

?

Yes

NAND MMCSD UART USB

Supported

RBL Boot Loader

BTSEL[2:0] = 001

NOR

BootOK?

BootOK?

BootOK?

SD Card Boot:If BTSEL[2:0] = 010 or NAND boot fails. No support for

a full firmware boot. Instead, copies a second stage UserBoot Loader (UBL) from MMC/SD to ARM Internal RAM(AIM) and transfers control to the user software.• Support for MMC/SD native protocol (MMC/SD SPI

protocol is not supported)• Support for descriptor error detection and retry

(up to 24 times) when loading UBL• Support for up to 30 kB UBL

(32 kB − ~2 kB for RBL stack)• SDHC boot supported by RBL

UART Boot:If the state of BTSEL[2:0] pins at reset is 011, then the

UART boot mode executes. This mode enables a smallprogram, referred to here as a user boot loader (UBL), to be

downloaded to the on-chip ARM internal RAM via theon-chip serial UART and executed. A host program,(referred to as serial host utility program), manages theinteraction with RBL and provides a means for operatorfeedback and input.• The UART moot mode execution assumes the

following UART settings: 24 MHz reference clock,time-out 500 ms, one-shot Serial RS−232 port115.2 kbps, 8-bit, no parity,one stop bit Command,data, and check sum format. Everything sent from thehost to the device UART RBL must be in ASCII format

• No support for a full firmware boot. Instead, loadsa second stage user boot loader (UBL) via UART toARM internal RAM (AIM) and transfers control to theuser software

• Support for up to 30 kB UBL (32 kB − ~2 kB for RBL stack)

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DM368 Clock RequirementDM368 requires Main oscillator (MXI1) that provides the

Primary reference clock for the device with external crystalor resonator. The optimal frequencies for the crystals are19.2 MHz, 24 MHz, 27 MHz, and 36 MHz and typical

operating frequency is 24 MHz, which is the frequency usedin the MatrixCam VDK. The 24 MHz input drives twoseparate PLL for ARM and clock required for peripherals.The external crystal load capacitors must be connected onlyto the oscillator ground pin (VSS_MX1).

Table 5. CRYSTAL REQUIREMENT FOR THE DM368 INPUT CLOCK

Parameter Min Typ Max Unit

Start-Up Time (from Power-Up until Oscillating at Stable Frequency) − − 2 ms

Oscillation Frequency − 19.2/24/27/36 − MHz

Crystal ESR19−30 MHz30−36 MHz

−−

−−

6040

�

Frequency Stability − − ±50 ppm

In the MatrixCam VDK the ABM8−24.000MHZ−R60−D−1−W−T part is used along with C1 and C2 witch are both36 pF.

The DM368 has two pins (RTCXI/RTCXO) for theexternal crystals or ceramic resonators to provide clockinputs. The oscillator mainly supplies the clock to the RTCblock and since the internal RTC of DM368 is not used in thedesign, the RTCXI shall be pulled down & RTCXO shall beNC.

DM368 Reset RequirementDM368 requires reset for PRTC subsystem and DM368

device. Reset pin RESETN is for Global reset and PWRSTis for PRTC subsystem. The active low width of thenRESETpulse should be less than 12 Clock cycle.(C = MXI1/CLKIN)

Figure 14.

RESET

PRTCSS of DM368 is not used in the design and will beoperated in the External reset mode. In External reset mode,PWRCNTON input pin should be held at 1 and the PWRSTpin should be held at 0 and the device reset signal (RESET#)will reset the PRTCSS.

DM368 Power-Supply Sequencing

Simple Power-On and Power-Off MethodThe following steps must be followed in sequential order

for the simple power-on method:1. Power on the PRTCSS/ Main core (1.35-V)2. Power on the PRTCSS/Main I/O (1.8-V)3. Power on the Main/Analog I/O (3.3-V)

Note for simple power-on:• RESET must be low until all supplies are ramped up

The following steps should be followed for the simplepower-off method:

1. Power off the Main/Analog I/O (3.3-V)2. Power off the PRTCSS/Main I/O (1.8-V)3. Power off the PRTCSS/Main core (1.35-V)

Notes for simple power-off:• If RESET is low, steps 2 and 3 may be performed

simultaneously• If RESET is not low, these steps must be followed

sequentially

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AR023Z Imager and DM368

Figure 15. AR023Z

AR023Z

DATA[11:0]

PIXCLK

LINE_VALID

FRAME_VALID

FLASH

SHUTTER

TRIGGER

OE_BAR

RESET_BAR

EXTCLK

SADDR

SCLK

SDATA

1.8 V to 3.3 VTranslator

PCA9306

DM368−VPFE

DATA[11:0]

PIXCLK

LINE_VALID

FRAME_VALID

GIOxx

GIOxx

GIOxx

GIO93

I2C_SCLK

I2C_DATA

For the AR023Z the parallel pixel data interface isdisabled by default at power up and after a reset. It can beenabled by programming the AR023Z’s R0x301A register.

Please refer to the AR023Z data sheet for other details aboutthe configuration of this image sensor.

Table 6. PARAMETERS OF AR023Z IMAGE SENSOR

Parameter Typical Value

Optical Format 1/2.7-inch (6.6 mm)

Active Pixels 1924 (H) × 1088 (V) (19:9 Mode)

Pixel Size 3.0 × 3.0 �m

Color Filter Array RGB Bayer

Shutter Type Electronic Rolling Shutter and GRR

Input Clock Range 6−48 MHz

Output Clock Maximum 148.5 Mp/s (4-Lane HiSPi)74.25 Mp/s (Parallel)

OutputSerialParallel

HiSPi 10-, 12-, 14-, 16-, or 20-bit10-, 12-bit

Frame Rate − 1080p 60 fps

Responsivity 4.0 V/Lux-sec

SNRMAX 41 dB

Max Dynamic Range Up to 105 dB

Supply VoltageI/ODigitalAnalogHiSPi

1.8 or 2.8 V1.8 V2.8 V0.3−0.6 V (SLVS), 1.7−1.9 V (HiVcm)

Power Consumption (Typical) < 896 mW (HDR 1080p 60, 8x gain, 25°C)

Operating Temperature −30°C to 85°C Ambient

Package Options 10 × 10 mm 80-pin iBGA

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AR023Z Imager Data/Control from DM368:• AR023Z has two interface options with the processor

♦ HiSPi♦ Parallel

• DM368 does not support the MIPI interface. So a parallel interface is implemented in this design.

• The 12 bit data lines are connected to the ISIF block ofDM368 processor

• The data and control line implementation for sensorinterface is shown in Figure 15

• The Data lines are interfaced directly with the ISIFblock as it can be directly powered with 1.8 V. So the level translators can be avoided

• However for clock out from processor and other controllines which are not in ISIF block need a level shiftingfrom 3.3 V to 1.8 V

• External clock input for the imager is given by theDM368 processor on pin CLKOUT0

• The CLKOUT0 of DM368 is directly coming frommain clock i.e. 24 MHz

AR023Z Parallel Interface• The parallel pixel data interface uses these output-only

signals:♦ FV♦ LV♦ PIXCLK♦ DOUT[11:0]

• The parallel pixel data interface is disabled by default atpower up and after reset. It can be enabled byprogramming R0x301A

• When the parallel pixel data interface is in use, theserial data output signals and VDD_SLVS can be leftunconnected

AR023Z Output Enable Control• When the parallel pixel data interface is enabled, its

signals can be switched asynchronously between thedriven and High-Z under pin or register control

Table 7. OUTPUT ENABLE CONTROL OF AR023Z IMAGE SENSOR

OE_BAR Pin Drive Signals R0x301A−B[6] Description

Disabled 0 Interface High-Z

Disabled 1 Interface Driven

1 0 Interface High-Z

X 1 Interface Driven

0 X Interface Driven

AR023Z Imager Configuration from DM368 I2C Interface• The imager is configured via I2C interface from the

processor• The two-wire serial interface bus enables read/write

access to control and status registers within theAR023Z. This interface is designed to be compatiblewith the electrical characteristics and transfer protocolsof the I2C specification

• The interface protocol uses a master/slave model inwhich a master controls one or more slave devices. The sensor acts as a slave device. The master generatesa clock (SCLK) that is an input to the sensor and isused to synchronize transfers. Data is transferredbetween the master and the slave on a bidirectionalsignal (SDATA). SDATA is pulled up to VDD_IOoff-chip by a 1.5 k� resistor. Either the slave or masterdevice can drive SDATA LOW − the interface protocoldetermines which device is allowed to drive SDATA atany given time

• The protocols described in the two-wire serial interfacespecification allow the slave device to drive SCLKLOW; the AR023Z uses SCLK as an input only andtherefore never drives it LOW

• The I2C interface from processor to the Imager requiresa level translator. PCA9306 I2C level shifter is used forthis purpose

• AR023Z SADDR pin is used for configuring I2Caddress. An option of pull-up and pull-down resistorwould be provided to configure the address

AR023Z Unconnected Pins• When parallel interface is implemented the serial HiSPi

lines & VDD_SLVS can be left unconnected• The shutter and the flash lines if not used can also be

left unconnected• Trigger and OE_BAR are pulled down to DGND

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AR023Z Power-Up and Power-Down Sequence

Power-Up SequenceThe recommended power-up sequence for the AR023Z

is shown in Figure 16. The available power supplies(VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA,VAA_PIX) must have the separation specified below.

1. Turn on VDD_PLL power supply2. After 100 �s, turn on VAA and VAA_PIX power

supply3. After 100 �s, turn on VDD_IO power supply4. After 100 �s, turn on VDD power supply5. After 100 �s, turn on VDD_SLVS power supply

6. After the last power supply is stable, enableEXTCLK

7. Assert RESET_BAR for at least 1 ms. The parallelinterface will be tri-stated during this time

8. Wait 150000 EXTCLKs (for internal initializationinto software standby

9. Configure PLL, output, and image settings todesired values

10. Wait 1 ms for the PLL to lock11. Set streaming mode (R0x301a[2] = 1)

Figure 16. AR023Z Sensor Initialization

VDD_PLL (2.8)

VAA_PIXVAA (2.8)

VDD_IO (1.8/2.8)

VDD (1.8)

VDD_SLVS (0.4)

EXTCLK

RESET_BAR

t0

t1

t2

t3

tX

t4

t5 t6

HardReset

InternalInitialization

SoftwareStandby PLL Lock Streaming

Table 8. AR023Z POWER-UP SEQUENCE TIMING PARAMETERS

Definition Symbol Minimum Typical Maximum Unit

VDD_PLL to VAA/VAA_PIX (Note 3) t0 0 100 − �s

VAA/VAA_PIX to VDD_IO t1 0 100 − �s

VDD_IO to VDD t2 0 100 − �s

VDD to VDD_SLVS t3 0 100 − �s

Hard Reset t4 1 (Note 2) − − ms

Internal Initialization t5 150000 − − EXTCLKs

PLL Lock Time t6 1 − − ms

1. Xtal settling time is component-dependent, usually taking about 10–100 ms.2. Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard reset is held down by RC circuit, then the

RC time must include the all power rail settle time and Xtal settle time.3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the

others. If the case happens that VDD_PLL is powered after other supplies then sensor may have functionality issues and will experiencehigh current draw on this supply.

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Power-Down SequenceThe recommended power-down sequence for the

AR023Z is shown in Figure 17. The available powersupplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA,and VAA_PIX) must have the separation specified below.

1. Disable streaming if output is active by settingstandby R0x301a[2] = 0

2. The soft standby state is reached after the currentrow or frame, depending on configuration, hasended

3. Turn off VDD_SLVS4. Turn off VDD5. Turn off VDD_IO6. Turn off VAA/VAA_PIX7. Turn off VDD_PLL

Figure 17. AR023Z Power-Down Sequence

VDD_PLL (2.8)

VAA_PIXVAA (2.8)

VDD_IO (1.8/2.8)

VDD (1.8)

VDD_SLVS (0.4)

EXTCLK

t0

t1

t2

t3

t4

Power Down until next Power Up Cycle

Table 9. AR023Z POWER-DOWN SEQUENCE TIMING PARAMETERS

Definition Symbol Minimum Typical Maximum Unit

VDD_SLVS to VDD t0 0 − − �s

VDD to VDD_IO t1 0 − − �s

VDD_IO to VAA/VAA_PIX t2 0 − − �s

VAA/VAA_PIX to VDD_PLL t3 0 − − �s

PwrDn until Next PwrUp Time (Note 4) t4 100 − − ms

4. t4 is required between power-down and next power-up time; all decoupling caps from regulators must be completely discharged.

Camera LensThe MatrixCam VDK uses an F2.0 2.8 mm fixed lens

manufactured by Xiamen Leading Optics.

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MICROCONTROLLER

To maintain the low power consumption of theMatrixCam VDK the application processor will be put in thelow power/off mode. All the other devices will be put in thedeep sleep/off mode as well. To wake up the application

processor and to monitor the trigger coming from the PIRand the BLE module, a housekeeping microcontroller isused. The MatrixCam VDK uses GainSpan GS2011MIESmodule for this purpose.

Figure 18. Application Processor Trigger Event

DM368 uCWAKE on PIR Sensor

WAKE on BLE

GS2011MIES Module OverviewThe MatrixCam VDK has the following requirements and

the GS2011MIES Module meets all of these requirements:1. Application controller should be always active in

low power state2. Be proactive for the interrupts from PIR sensor

and wake up the application3. Be proactive for the interrupts from BLE and wake

up the application processor

4. Control the DM368 power on/off sequence5. Control and monitor the battery charger and fuel

gauge6. Real time controller7. To provide status indication

Figure 19. GS2011MIES Internal Architecture

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The GS2011MIES Module uses GS2000 SoC, whichcombines ARM Cortex® M3-based processors witha 802.11b/g/n Radio, MAC, security, and PHY functions, aswell as RTC and SRAM. It has up to 2 MB FLASH, and onboard and off module certified antenna options. The moduleprovides a Wi-Fi and regulatory certified IEEE 802.11b/g/nradio with concurrent network processing services forvariety of applications.

GS2011MIES Boot ModesThe respective GPIO pins are sampled at reset by device

and depending on the values seen on these pins the modulegoes into the appropriate mode. Code for the GS2011MxxSresides on the internal flash of the module and up to twoback-up copies could be stored in flash. If a softwaredesigner wants to restore the execution code to one of the

backup copy, it can be accomplished by asserting theappropriate GPIO pins as shown in the table below duringpower up or reset.

GS2011MIES Pin MultiplexingThe GS2011MxxS pins have multiple functions that can

be selected by software. Each pin has an independent MUXselect register. Table 10 below shows the various MUXfunctions for each pin. All pins are GPIO inputs at reset. Forpins that are inputs to functional blocks only one pin may beassigned to any input function. For example, UART1_RXmay be assigned to GPIO3 but not to both GPIO3 andGPIO37.

GPIO assignment of GS2011MIES can be seen in themain block diagram and for a quick reference. Please referTable 10 below.

Table 10. GS2011MIES PIN ASSIGNMENT

S# Pin Name Net Name Function I/O Interface Sense Remarks

1 ADC_1 ADC_MCU TP NA NC

2 RTC_IO_1 TP NA NC

3 RTC_IO_2 SoC_MCU_STDY_WAKE I NA Not Required but Connected forFuture Use

4 I2C_CLK/GPIO9

MCU_I2C_SCL I2C CLK I I2C Refer to I2C Interface Section

5 I2C_DATA/GPIO8

MCU_I2C_SDA I2C DATA I/O I2C Refer to I2C Interface Section

6 DC_DC_CNTRL/RTC_I/O_4

DC_DC_CNTRL TP NC

7 SPI0_CS#_0/SDIO_DAT3/

GPIO33

MCU_SPI_CS SPIInterface

I SPI Active Low SPI1 of DM368

8 SPI0_CLK/SDIO_CLK/

GPIO35

MCU_SPI_CLK SPIInterface

I SPI SPI1 of DM368

9 SDIO_DAT1_INT/GPIO37

MCU_BT_GPIO GPIO I/O SDIO Connected to BT GPIO P0_7 forHandshaking if Required

10 SPI0_DIN/SDIO_CMD/

GPIO34

MCU_SPI_MOSI SPIInterface

I SPI SPI1 of DM368

11 SPI0_DOUT/SDIO_DAT0/

GPIO36

MCU_SPI_MISO SPIInterface

O SPI SPI1 of DM368

12 SPI1_CS#_0/GPIO4

MCU_SoC_GPIO2 GPIO I/O As perRequirement

Connected to DM368 GPIO44 forHandshaking

13 SPI1_CS#_1/GPIO13

MCU_OFF_REQ GPIO I Active Low Int# from LTC2950−1 IC. After a pushbutton turn-off event is detected, theLTC2950 interrupts the system (�P)by bringing the INT pin low. Once thesystem finishes its power down andhousekeeping tasks, it sets KILL low(MCU_OFF), which in turn releasesthe enable output. If at the end of thepower down timer (1024 ms) KILL(MCU_OFF) is still high, the enableoutput is released immediately.

14 SPI1_CLK/GPIO5

MCU_OFF GPIO O Active Low Forcing KILL(MCU_OFF) lowreleases the enable output. Duringsystem turn on, this pin is blanked bya 512 ms internal timer to allow thesystem to pull KILL high. This pin hasan accurate 0.6 V threshold and canbe used as a voltage monitor input.

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Table 10. GS2011MIES PIN ASSIGNMENT (continued)

S# RemarksSenseInterfaceI/OFunctionNet NamePin Name

15 SPI1_DIN/GPIO6

PIR_DIG_OUT GPIO I Active High

16 SPI1_DOUT/GPIO7

ON_OFF_SWITCH GPIO I Active Low This Signal will be used for FactoryReset of the Device

17 UART0_RX/GPIO0

MCU_UART0_RX UART I UART Provided on 4-pin Header

18 UART0_TX/GPIO1

MCU_UART0_TX UART O UART Provided on 4-pin Header

19

UART0_CTS/GPIO24

MCU_SoC_GPIO1 GPIO I/O As perRequirement

Connected to DM368 GPIO22 forHandshaking

20 UART0_RTS/GPIO25

MCU_PRGM_SoC_WAKE GPIO O Connected to GIO0 of DM368

21 UART1_RX/GPIO3

MCU_BT_UART_RX UART O UART Connected to P0_11 of the BT

22 UART1_TX/SDIO_DAT2/

GPIO32

MCU_BT_UART_TX UART I UART Connected to P0_09 of the BT

23 UART1_CTS/GPIO26

SoC_nRESET GPIO O Active Low Drive High to Take Out the DM368Out of Reset

24 UART1_RTS/GPIO27

MCU_PRGM_BT_PWR_EN GPIO O Active High Terminated on the DIP Switch

25 PWM0/GPIO10 SYS_PWR_EN GPIO O Drive High to Enable DM368 Power

26 PWM1/GPIO31 GPIO_IO_EXP_INT GPIO Interrupt from I/O Expander

27 CLK_HS_XTAL/GPIO19

MCU_SoC_GPIO4 GPIO I/O As perRequirement

Connected to DM368 GPIO37 forHandshaking

28 CLK_RTC/GPIO21

CLK_RTC RTC_CLK NC

29 EXT_RESET# MCU_RESET_SCH RESET I Reset Button is Connected forGS2011MIES Reset

30 VPP MCU_OTP_VPP TP NA

NOTE: MCU_OFF and MCU_OFF_REQUEST signals need to be taken care for power on and off as mentioned.

GS2011MIES Host InterfaceGS2011MIES supports SPI0, SPI1 and SDIO as host

interface. Due to the lack of SDIO interface in DM368, SPI0is used as the host interface to DM368. SPI0 ofGS2011MIES is in slave mode and can support 10 MHzmax. Note that OEM can also use SPI1 as the host interfaceto DM368.

GS2011MIES I2C InterfaceIn MatrixCam VDK the GS2011MIES module is required

to operate in the master mode to control and monitor theSensor interfaces. Image sensor primary control is byGS2011MIES through I2C slave select and it can behandover to DM368 by GS2011MIES. Please refer to the“System I2C Interface” section for details.

RTC in the GS2000 SoCGS2011MIES has a RTC which provides the global time

(and date) to the system. The RTC is always on to manage

the Standby state. It is powered by a supply pin (VRTC) fromthe digital core, or it can receive power directly froma battery. The RTC implementation supports a voltage rangeof 1.6 V to 3.6 V.NOTE: The MatrixCam VDK is battery powered and the same

battery is used for the RTC backup. A “Battery Low”notification will be provided to the user over Wi-Fi when themain battery is discharged to 3.2 V.

GS2000 SoC Clock RequirementThe GS2000 SoC requires two separated clocks for its

operation:• A slow clock running at 32.768 kHz is used for the RTC• A fast clock running at 40 MHz is used by the module

for the internal processor and the WLAN subsystem

The GS2011MIES module has both clocks built in so noexternal clock is required.

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GS2011MIES Module ResetEXT_RESET_n is an active low signal. It is an output

during power up to indicate to the system whenGS2011MxxS device is coming out of the power-on-reset.After power-on-reset this pin is an input. It is not necessaryto assert reset to the GS2011MxxS after power on becausethe GS2011MxxS has a built-in power on reset. Also, theEXT_RESET_n signal does not clear the RTC, RTC RAM,or the SRAM. If the external host is driving theEXT_RESET_n pin, it MUST do so with an open draindriver. This is because this pin is also driven by the RTC. Inaddition, if an external host is connected to theEXT_RESET_n pin, there must be an external 10 k�resistor pulling the pin to VDDIO.

Figure 20. GS2011MIES Reset Section

GS2011MIES

EXT_RESET_N

3V3

GS2011 GPIO I/O ExpanderDue to non-availability of the GPIOs in GS2011MIES, we

are using the I/O expander PCA9538BS from NXP toprovide some extra GPIOs. Table 11 shows how this IOexpander’s GPIOs are used.

Table 11. GS2011MIES AND THE I/O EXPANDER PIN ASSIGNMENT

I2C I/OExpanderPin Name Signal Name Direction Sense Remarks

I/O1 BT_MCU_WAKE_UP I Programmable Wake Up the System through “GPIO_IO_EXP_INT”Signal Connected to GPIO31Note: GPIO31 Needs to be Configured as InterruptSource.

I/O2 SoC_MCU_WAKE_UP I Programmable

I/O3 MCU_LED_RED_CTRL O Active High Drive to Glow the LED

I/O4 MCU_LED_GREEN_CTRL O Active High Drive to Glow the LED

I/O5 FG_ALARMB I Active Low Wake Up the System through “GPIO_IO_EXP_INT”Signal Connected to GPIO31Note: GPIO31 Needs to be Configured as InterruptSource.

I/O6 MCU_BT_PWR_EN O Active Low Drive High to Enable BT Power

I/O7 MCU_SoC_GPIO3 I/O Programmable Handshaking Signal between DM368 andGS2011MIES

I/O8 USB_WAKEUP_MCU I Active High To Tell the GS Module USB Plug In

GS2011MIES WLAN RFGS2011MIES has on board UFL connector for

connecting the external flexible PCB antenna. TheMatrixCam VDK uses Taoglas FXP73.07.0100A antenna.

Table 12. GS2011MIES WLAN RECEIVER CHARACTERISTICS

Parameter Minimum Typical Maximum Unit Notes

RF Frequency Range 2400 − 2497 MHz

Radio Bit Rate 1 − HT20MCS7

Mbps

TRANSMIT/RECEIVE SPECIFICATION FOR GS2011MIxS

Output Power (Average) −−−−−−

17121410126

−−−−−−

dBm 11b, 1 Mbps11b, 11 Mbps11g, 6−18 Mbps11g, 64-QAM11n, MCS 0 − MCS 311n, MCS 7

Spectrum Mask − − − dBr Meet 802.11 Requirements for Selected DataRates

Receive Sensitivity atAntenna Port

−−−

−93−74−71

−−−

dBm 11b, 1 Mbps, BPSK/DSSS11g, 54 Mbps, 64-QAM/OFDM11n, MCS 7 (72 Mbps), 64-QAM/OFDM

NOTE: Sufficient clearance should be kept between the two (BLE and Wi-Fi) antennas.

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System Wake Up through GS2011MIESAs stated earlier, to maintain the low power state of the

MatrixCam VDK the application processor should be in thelow power/off mode and all other devices should also be indeep sleep/off mode. The main processor can be woken upby the PIR and BLE module through interfacing to theGS2011MIES and some glue logic.

The glue logic is the I/O expander mentioned in GS2011GPIO I/O Expander section.

There are three low power states in the GS2011MIES.They are standby, Sleep and Deep-sleep. The MatrixCamVDK is designed to be in the Deep-sleep mode all the timeand will only be woken up on interrupt from PIR or BLE.Any GPIO of the GS2011MIES can be configured as aninterrupt source to wake up the DM368.

The MatrixCam VDK will give a push notification to theuser in case the battery is low. The interrupt form the fuelgauge “FG_ALARMB” connected to I/O4 of the I/Oexpander will wake up the system and give a notification tothe user when battery is low.

There is one more I/O which needs to be configured asinterrupt to do the factory reset. Tactile switch is connectedto the GPIO7 of the GS2011MIES.

PIR is directly connected to the GPIO6 of theGS2011MIES and GPIO6 needs to be configured asinterrupt.

Please refer to GS2011MIES DS for complete descriptionof the different low power modes. Note that the MatrixCamVDK does not support STANDBY mode of GS2011MIES.

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BLE MODULE

In the MatrixCam VDK BLE (Bluetooth Low Energy) isused to wake up the system but it can also be used for otherpurposes, such as to configure the MatrixCam VDK fromthe smart devices. The MatrixCam VDK uses a Multiprotocol BLE 4.0 SoC nRF51822 from Noridicsemiconductors. Figure 25 shows the BLE & Wi-Fi moduleinterface on a block diagram level.

nRF51822−QFAA Specification• 2.45 GHz transceiver• ARM Cortex−M0 32-bit processor• Built-in 256 kB Flash memory and 16 kB RAM• UART & SPI interface for intercommunication

• Supports non-concurrent multi-protocol operation• Flexible power management• Power supply features:

♦ Supply voltage range of 1.8 to 3.6 V using internalLDO regulator

♦ Low voltage mode of 1.75 to 1.95 V (external voltage regulator is required)

♦ Supply voltage range of 2.1 to 3.6 V using internalbuck DC/DC converter

BLE Interface Block DiagramBLE will be used to wake up the GS2011MIES and it will

in turn wake up the DM368.

Figure 21. BLE Interface Block Diagram

nRF51822 Power SupplyFigure 22 shows the power supply module present in

nRF51822 BLE SoC.

Figure 22. BLE Power Supply

System PowerLDODC/DC

Converter

VDDnRF51

DCDCEN

DCC AVDD VSSDEC1DEC2

VDD

nRF51822 has an internal DC/DC converter to step downthe input supply voltage (VDD). By default the DC/DCconverter is disabled (DCDCEN = 0x0 default). Withoutenabling it the AVDD pin of the IC will have the VDDvoltage. This VDD will be the input to the internal LDO.

The internal LDO outputs 1.8 V at the DEC2 pin. TheDEC1 pin is only used for decoupling purpose.

For the MatrixCam VDK the BLE part is powered by a3.3 V pre-regulated power source, so the IO voltage is also3.3 V.

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CPU in nRF51822A low power ARM Cortex−M0 32 bit CPU is embedded

in the nRF51822. The ARM Cortex−M0 has a 16 bitinstruction set with 32 bit extensions (Thumb�−2technology) that delivers high density code with a smallmemory footprint.

There are 32 GPIOs available in the BLE controller.Among these GPIOs any of the pin can be configured to anyfunctionality supported by nRF51822 SoC.

nRF51822 InterfaceUART & SPI interfaces are available for

Intercommunication in nRF51822 SoC.BLE interfaces to the GS2011MIES through an UART

interface. For a development option, the SPI on the deviceis connected to the DM368. Upon receiving any BLE packetthe device will wake up the GS2011MIES through“BT_MCU_WAKE_UP”.

UART is featuring a Full-Duplex operation and automaticFlow Control. Enabling and disabling the flow control isavailable.

SPI Master/Slave mode is configurable in the nRF51822SoC. SPI Master can provide a simple interface with CPU.The SPI master does not implement support for chip selectdirectly. Therefore, the CPU must use available GPIOs toselect the correct slave and control this independently of theSPI master. The SPI master supports SPI modes 0 to 3.

SPIS is a SPI slave with EasyDMA support for ultra-lowpower serial communication from an external SPI master.For this product SPIS is chosen for communication betweenDM368 application processor and the BLE SoC.NOTE: UART of the device will also be provided on the header

to provide the flexibility to program the device by Segger.

nRF51822 Clock ManagementThe system depends on, and generates, two different

clocks, i.e. a high frequency clock (HFCLK) and a lowfrequency clock (LFCLK). These clocks are only availablewhen the system is in ON mode. The HFCLK is fixed to16 MHz and the LFCLK is fixed to 32.768 kHz.

HFCLK − The system supports two high frequency clocksources 16/32 MHz crystal oscillator and the 16 MHz RCoscillator. The HFCLK crystal oscillators require anexternal AT-cut quartz crystal (16/32 MHz) to be connectedto the XC1 and XC2 pins in parallel resonant mode.

When the system enters ON mode, the 16 MHz RCoscillator will start up automatically to provide the HFCLKto the CPU and other active parts of the system. The 16 MHzRC oscillator is automatically switched off when one of theHFCLK crystal oscillators is running.

LFCLK − Possible clock sources for the LFCLK are the32.768 kHz crystal oscillator, the 32.768 kHz RC oscillator,and the 32.768 kHz synthesized clock.

For crystal oscillator AT-cut quartz crystal to be connectedto the XL1 and XL2 pins in parallel resonant mode. The XL1and XL2 share pins with the GPIO.

For the MatrixCam VDK design a 16 MHz crystal (with12 pF load capacitors) is used for the HFCLK, and a32.768 kHz crystal (with 18 pF load capacitors) is used forthe LFCLK.

To achieve correct oscillation frequency, the loadcapacitance must match the specification of nRF51822 SoC.

Figure 23. 16/32 MHz Crystal Oscillator Circuit Diagram

16/32 MHzCrystal

XC2

C2

XC1

C1

The load capacitance (CL) is the total capacitance seen bythe crystal across its terminals and is given by:

CL �C1� � C2�

C1� � C2�(eq. 1)

C1� � C1 � C_pcb1 � C_pin (eq. 2)

C2� � C2 � C_pcb2 � C_pin (eq. 3)

Where:C_pin − Pin Input CapacitanceC_pcbX − Stray Capacitance

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nRF51822 Software Debugging InterfaceSWD − Serial Wire Debugging interface is used for

software debugging.

Figure 24. nRF51822 Debug Interface

POWER

DIFDAP

ARM CoreSigth� DAP-Lite

nRE

SE

T

SWDCLK

SWDIO/nRESET

SWDCLK

SWDIO

The interface has two lines SWDCLK and SWDIO.SWDIO and nRESET share the same physical pin. TheDebugger Interface (DIF) module is responsible forhandling the resource sharing between SWD traffic andreset functionality. The SWDCLK pin has an internal pulldown resistor and the SWDIO/nRESET pin has an internalpull up resistor.

The DIF module will be in normal mode after poweron reset. In this mode the SWDIO/nRESET pin acts asa normal active low reset pin. To guarantee that the deviceremains in normal mode, the SWDCLK line must be heldlow, that is, ‘0’, at all times. Failing to do so may result inthe DIF entering into an unknown state and may lead toundesirable behavior and power consumption.

Debug interface mode is initiated by clocking one clockcycle on SWDCLK with SWDIO = 1. Due to delays causedby starting up the DAP’s power domain, a minimum of 150

clock cycles must be clocked at a speed of minimum125 kHz on SWDCLK with SWDIO = 1 to guaranty that theDAP is able to capture a minimum of 50 clock cycles.

In debug interface mode, the SWDIO/nRESET pin will beused as SWDIO. The pin reset mechanism will therefore bedisabled as long as the device is in debug interface mode.

Normal mode can always be resumed by performinga “hard-reset” through the SWD interface:

1. Enter debug interface mode2. Enable reset through the RESET register in the

POWER peripheral3. Hold the SWDCLK and SWDIO/nRESET line

low for a minimum of 100 �s

In the MatrixCam VDK a 6-pin JTAG header is used forthe SWD and UART interface.

Figure 25. nRF51822 JTAG Header

DB_SWDIO/BLE_RST#

DB_SWDCLK

BT_UART_RX

H15

HDR_2X3

VCC_BT_3V3

BT_UART_T-X 6

42

5

31

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RESET to the nRF51822The RESET signal for the nRF51822 is coming from the

DM368 Application processor. The reset pin in nRF51822is an low active pin multiplexed with SWDIO (in softwaredebugging mode). The default condition of this SWDIO pinis for “RESET”, and it will be changed to “SWDIO” underDIF when certain special conditions are met (see sectionnRF51822 Software Debugging Interface above).

Under normal mode the minimum Hold time for RESETpin to do a full RESET is 0.2 �s. It is 100 �s during the debugmode.

BLE RFThe nRF51 series 2.4 GHz RF transceiver is designed and

optimized to operate in the worldwide ISM frequency bandat 2.400 to 2.4835 GHz. Radio modulation modes andconfigurable packet structure make the transceiverinter-operable with Bluetooth low energy (BLE), ANT�,Enhanced ShockBurst�, and other 2.4 GHz protocolimplementations.

The transceiver receives and transmits data directly to andfrom system memory for flexible and efficient packet datamanagement. The nRF51822 transceiver has the followingfeatures:• General modulation features• GFSK modulation• Data whitening• On-air data rates

♦ 250 kbps♦ 1 Mbps♦ 2 Mbps

• Transmitter with programmable output power of+4 dBm to −20 dBm, in 4 dB steps

• Transmitter whisper mode −30 dBm• RSSI function (1 dB resolution)• Receiver with integrated channel filters achieving

maximum sensitivity♦ −96 dBm at 250 kbps♦ −93 dBm at 1 Mbps BLE♦ −90 dBm at 1 Mbps♦ −85 dBm at 2 Mbps

• RF synthesizer• Baseband controller

The MatrixCam VDK has an UFL connector for theexternal antenna to connect to. The model number of theUFL connector is U.FL−R−SMT−1 from Hirose.

Please refer to the nRF51822 data sheet for the layoutinstructions details.

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PIR SENSOR

The components for PIR section include PIR detector(Dual Type Pyroelectric Infrared Sensor IRA−E700 Seriesfrom Murata), PIR signal conditioning IC (NCS36000DGfrom ON Semiconductor), I2C controlled digitalPotentiometer (CAT5132ZI-00-GT3 fromON Semiconductor) and the Fresnel Lens. The MatrixCamVDK PIR has the following features:• The sensitivity can be controlled by software• The lens has the coverage of 140° in the horizontal axis• The length of coverage is around 10 to 15 feet

PIR DetectorDual Type Pyro electric Infrared Sensor IRA−E700

Series from Murata has high sensitivity around 4.3 mV(Peak-to-Peak), and can be amplified and filtered by thesignal conditioning unit. The fundamental frequency rangeof detector output is in the range of 0.5 Hz to 25 Hz.

The PIR detector supports the single face of 45 degree;hence for both faces it can support 90 degree. The 140 degreecoverage can be achieved by using the external Fresnel lens.

PIR Detector Controller − NCS36000DGThe ON Semiconductor NCS36000 is a fully integrated

mixed-signal CMOS device designed for low-cost passiveinfrared controlling applications. The device integrates twolow-noise amplifiers and a LDO regulator to drive thesensor. The output of the amplifiers goes to a windowcomparator that uses internal voltage references from thebuilt in regulator. The digital control circuit processes theoutput from the window comparator and provides the outputto the OUT and LED pin.

Figure 26. NCS3600 Internal Block Diagram

DigitalControlCircuit

WindowComparator

AmplifierCircuit

SystemOscillator

LDO & VoltageReferences

2

2

VREF

OP1_P

OP1_N

OP1_O

OP2_N

OP2_O

OSC

MODE

XLED_EN

LED

OUT

VS

S

VD

D

NCS3600DG Two Stage AmplifierThe 2.15 mV output from the PIR detector can be

amplified with gain up to 70 dB which can be achieved bythe two consecutive amplifier stages which are the OP1_xand OP2_x pins. The output of PIR detector is fed to the firstamplifier section (opamp−1), which is then fed to the secondamplifier to achieve the total gain of gan1+gain2.

For details of the R, C calculation and selection for the firstand the second stage amplifier please refer to the NCS3600data sheet.

PIR Fresnel LensThe Fresnel Lens is from Fresnel Factory to best match the

PIR detector. The lens model number is PD55−14006.

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SYSTEM I2C INTERFACE

Following I2C interface mapping shows the I2Cintercommunication between the various devices in thesystem.

Figure 27. GS2011MIES I2C Interface with Address

GS2011MIES

Battery Charger

NCP1855

Fuel Guage

LC709202F

Digital POT

CAT5132ZI−00−G

Slave Address:1101100

Slave Address:0001011

Slave Address:0101000

Figure 28. DM368 I2C Interface with Address

DM368I2C Master Select

PCA9306

Image Sensor

AR023ZI2C SDA

I2C CLK

Slave Address:1111000 Slave Address:0010000

I2C SDA

I2C CLK

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ETHERNET PHY

RTL8201CP part from Realtek is used for providing theEthernet functionality to the MatrixCam VDK.

Main Features of RTL8201CP−LF are:• Fully compliant with IEE802.3/IEEE802.3u Base-TX

standard• Selectable MII and RMII interface• Auto-negotiation ability, compliant with IEE802.3u• Support auto-cross over detection

• Support power down mode• Support scrambling and de-scrambling• Provide loopback mode for easy system diagnostics• LED outputs for link/activity, speed 10/100

Ethernet PHY is interfaced to DM368 through MIIinterface.

Figure 29. Ethernet PHY Interface

DM368 SoCMAC

10 /100M Ethernet PhyRTL8201CP−LF

PHY_ADDR: 10000B

TXD[3:0] TXD[3:0]

TX_CLK TXCLK

GPIO

GPIO

MDCLK

MDIO

GPIO

RXD[3:0] RXD[3:0]RX_CLK RXCLK

RX_ER

RX_DV

COL

RXER

COL

RXDV

CRS CRSGPIO

INTR#

RESET

LINKSTS

MDC

MDIO

PWRDWN

TXER

TXEN TXEN

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RTL8201CP Pin DefinitionThe table below has information about the pins in

RTL8201CP. For detailed pin connections and setupinformation please refer to the RTL8201CP data sheet fordetails.

Table 13. ETHERNET MII INTERFACE

Pin Name Type FunctionConnected to EMAC

of DM368

TXD [3:0] I Data Transmit, Synchronous with TXC when TXEN is Asserted EMAC_TXD[3−0]

RXD[3:0] O Receive Data, Driven Synchronously to RXC for Reception by PHY EMAC_RXD[3−0]

TXC O Transmit clock EMAC_TX_CLK

RXC O Receive Clock. RXC is 25 MHz in 100 Mbps and 2.5 MHz in10 Mbps Mode (for MII)

EMAC_RX_CLK

TXEN I Transmit Enable, Indicates that Presence of Valid Data on TXD[3:0]

EMAC_TX_EN

Collision Detect, Asserted high when a collision is detected onmedia.During power on reset mode, this pin status is latched to determineat which LED mode to operate

1: BL LED Mode0: CP LED Mode

CRS LI/O Carrier sense, Asserted high if media is not in ideal state. EMAC_CRS

RXDV O Receive Data Valid, Asserted high when received data is presentedon RXD[3:0] and de-asserted at the end of packet

EMAC_RX_DV

RXER/FXEN LI/O Receive Error, any Invalid Symbol, this Pin Goes High. MRXER

Fiber/UTP Enable

MDC I Management Data Clock, Clock Synchronous to MDIO MDCLK

MDIO I/O Management Data Input and Output, Used to TransferManagement Information

MDIO

Table 14. ETHERNET 10 Mbps/100 Mbps NETWORK INTERFACE

Pin Name Type FunctionConnected to EMAC

of DM368

TPTX+ O Differential Transmit Output, Shared by 100Base-Tx, 100Base-FXand 10Base-T Modes

Connected to Magnetics

TPTX−

TPRX+ I Differential Receive Input, Shared by 100Base-Tx, 100Base-FXand 10Base-T Modes

Connected to Magnetics

TPRX−

RTSET I Transmit Base Resistor, will Clear the Resistor and Re-Initializethem by Using 2 k� (1%) Resistor, by Pull Down this Pin

Connected to 2 k� 1%Resistor

Table 15. ETHERNET SERIAL MANAGEMENT INTERFACE

Pin Name Type FunctionConnected to EMAC

of DM368

MDC I Management Data Clock, Clock Synchronous to MDIO MDCLK

MDIO I/O Management Data Input and Output, Used to TransferManagement Information

MDIO

Table 16. ETHERNET CLOCK INTERFACE

Pin Name Type FunctionConnected to EMAC

of DM368

X2 O 25 MHz Crystal Output Crystal Part number: 25 MHz,403C35D25M00000 fromCTS with C1, C2 = 24 pFX1 I 25 MHz Crystal Input

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Table 17. ETHERNET DEVICE CONFIGURATION INTERFACE

Pin Name Type FunctionConnected to EMAC

of DM368

Isolate I Set high isolate the RTL8201Cp from the MAC. This will alsoisolate the MDC/MDIO management interface. In this mode, thepower consumption is minimum. This Pin can be directly connectedto GND or VCC

GND as this Functionality isNot Required

RPTR I Set high to put the RTL8201CP in to repeater mode. This pin canbe directly connected to GND or VCC

GND as this Functionality isNot Required

SPEED LI This pin is latched to input during a power on or reset condition. Sethigh to put the RTL8201CP in to 100 Mbps operation. This pin canbe directly connected to GND or VCC

Connected to VCC to Put itinto 100 Mbps Mode

DUPLEX LI This pin is latched to input during a power on or reset condition. Sethigh to enable full duplex. This pin can be directly connected toGND or VCC

Connected to VCC to Put itinto Full Duplex Mode

ANE LI This pin is latched to input during a power on or reset condition. Sethigh to enable Auto-Negotiation mode, set low to force mode. Thispin can be directly connected to GND or VCC

Connected to VCC to EnableANE Mode

LDPS I Set high to put the RLT8201CP into LPDS mode. This pin can bedirectly connected to GND or VCC.

Connected to VCC to EnableLPDS Mode

MII/SNIB LI/O This pin is latched to input during a power on or reset condition.Pull high to set the RLT8201CP into MII mode. Set low for SNImode. This pin can be directly connected to GND or VCC.

Connected to VCC to EnableMII Mode

Table 18. ETHERNET LED/PHY ADDRESS CONFIGURATION

Pin Name Type FunctionConnected to EMAC

of DM368

PHYAD0/LED0

LI/O PHY Address [0]Link LEDLit when Linked

PHYAD0 = 0Used as LED as well

PHYAD1/LED1

LI/O PHY Address [1]Full Duplex LEDLit when in Full Duplex Operation

PHYAD1 = 0Used as LED as well

PHYAD2/LED2

LI/O PHY Address [2]CP LED Mode: 10ACT LEDBlinking when Transmitting or Receiving DataBL LED Mode: Link 10/ACT LEDActive when Linked in 10base-T Mode, and Blanking whenTransmitting or Receiving Data

PHYAD2 = 0

PHYAD3/LED3

LI/O PHY Address [3]CP LED Mode: 100ACT LEDBlinking when Transmitting or Receiving Data.BL LED Mode: Link 100/ACT LEDActive when Linked in 100base-T Mode, and Blanking whenTransmitting or Receiving Data

PHYAD3 = 0

PHYAD4/LED4

LI/O PHY Address [4]Collision LEDBlinks when Collisions Occur

PHYAD1 = 0

Table 19. ETHERNET POWER & GND

Pin Name Type Function Connected to EMAC of DM368

AVDD33 P 3.3 V Analog Power Input3.3 V should be well Decoulpled

Connected to 3.3 V through FerriteBead to Isolate from Digital Power

Supply

AGND P Analog GNDShould be Connected to Larger GND Plane

Connected to AGND, AGNDSeparated to DGND by Ferrite Bead

DVDD33 P 3.3 V Digital Power Input3.3 V Power Supply for Digital Circuit

Connected to 3.3 V

DGND P Digital GND.Should be Connected to a Larger GND Plane

DGND

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SYSTEM RESET SCHEME

System reset scheme is shown below in Figure 31. Thoughthe resets are interconnected, they can be grouped as thefollowing subsets:

System ResetTo reset the complete system there is a factory reset button

connecting to the GPIO7 of the GS2011MIES. This willreset the whole camera system.

GS2011MIES ResetGS2011MIES has an internal POR circuitry to take care

of any dip in power rail. If GS2011MIES is reset then it willreset the rest of the system. There is tactile switch connectedto “EXT_RESET#” pin to reset the GS2011MIES which inturn resets the whole system.

Figure 30. Reset Button to the GS2011MIES Module

DM368 ResetDM368 will be reset by any of the following conditions:

• If there is any voltage drop at 1.35 V, 1.8 V, 3.3 V and2.8 V voltage rails

• When microcontroller asserts reset• When manual reset switch is pressed (SW2)

Note that the Global RESET# pin of the DM368 has aweak pull down resistor (10 k�). The signalSoC_POR_nRESET connected to this RESET# pin willdrive it (high) out of the reset state.

Peripheral ResetThrough some of the DM368 GPIO pins, peripheral can

be independently reset. The following device resets arecontrolled by DM368.

1. NOR Flash2. AR023Z Image sensor3. Ethernet PHY (RTL8201CP−LF)

Figure 31 shows the complete reset scheme as discussedabove.

Figure 31. System Reset Scheme

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POWER SUPPLY DESIGN

Power ConsumptionThe estimated total power consumption of the MatrixCam

VDK under various conditions are:• Sleep mode: 7.5 mW• Video streaming Wi-Fi: 2894 mW• Video streaming wired Ethernet: 2333 mW

• Video saved to the SD card: 2467 mW• Total maximum power: 4009 mW

Note that the above numbers do not consider theefficiency of the DC−DC converters.

As it is a USB powered device, it should follow thefollowing criteria as per USB BCS Rev1.2.

1. For a Dedicated Charge Port (DCP) it is allowed todraw 1.5 A

2. A DCP shall output a voltage of 4.75 to 5.25 V forall currents less than 1.5 A min

3. Portable device allowed operating range: V = 4.75 to 5.25 V and I = 0.5 to 1.5 A

Figure 32. USB Powered Operating Condition

Portable Device Allowed Operating Range

Current (A)

Vo

ltag

e (V

)

0

1.0

2.0

3.0

4.0

5.05.25

4.754.50

5.02.01.51.00.50

Portable DeviceOperation

Not Allowed

Allowed OperatingRange for a

Portable Device

1

Battery Charger ManagementBattery management comprise of Li-Ion Battery with

temperature sensor, Battery charger and Fuel Gauge.

Li-Ion BatteryLi-Ion battery capacity should provide long run support

for this product during the day time where the manual accessis not possible for battery charging.

Battery Specifications are follows:

Table 20. BATTERY SPECIFICATIONS

Parameter Value

Battery Model No U884048−2P

Battery Pack Construction 2 Cells of 2100 mAh

Battery Cell 2100 mAh

Nominal Voltage 3.7 V

Maximum Charge Voltage 4.2 V

Voltage at End Discharge 3.3 ±0.1 V

Suggestion Charge Current 840 mAh

Suggestion Continuous Discharge Current(max) 1000 mAh

Operation Temperature Charge: 0°C ~ 45°C; Discharge: −20°C ~ 60°C

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The selected battery has built-in protection function asshown in the following table.

Table 21. BATTERY PROTECTIONS

Parameter Description

Over Charge Prohibition Shut Down Circuitry and Stop Charge if anyone of Cells Voltage Exceeds more than4.28 ±0.0025 V

Over Discharge Prohibition Shut Down Circuitry and Stop Discharge if Cell Voltage Becomes less than 2.90 ±0.08 V

Battery Charger OverviewTo satisfy the MatrixCam VDK’s goal of minimal power

dissipation (Higher efficiency), the Switching mode typecharging is used in the design. This camera uses theON Semiconductor NCP1855 battery charger andLC709202F battery fuel gauge. Since a higher switchingfrequency leads to the selection of smaller components,1.5 MHz switching frequency is used in this camera.

Here the NCP1855IC accepts the input voltage in therange of 3.8 V to 16 V and the recommended maximuminput current is 2 A (Default value input current limit isset to 100 mA). And it would produce the output voltage ofminimum 3.3 V (3.6 V default) at the system (load) side.

The charge current can be controlled through I2C with theminimum current of 1000 mA and maximum of 2.5 A.The NCP1855IC charging profile is shown in Figure 33.

Figure 33. Battery Charge Cycles

ICHG

IPRE

IEOC

ISAFE

IBAT VBAT

VCHG

VRECHG

VPRE

VSAVE

SafeCharge

PreCharge

ConstantCharge

ConstantVoltage

End ofCharge

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NCP1855 Battery Charger DetailsNCP1855 has the following features:

• Single input USB-compliant/adapter charger• High efficiency 2.5 A switch mode charger• Autonomous battery charging with or without host

management• 1.5 MHz switching frequency for low profile inductor

The NCP1855is an I2C controlled power pathmanagement and a single cell Li-Ion battery charger device.It integrates the input reverse-blocking FET, high-sideswitching FET, low-side switching FET, and BAT FETbetween system and battery.

Figure 34. Battery Charger Functional Blocks

NCP1855

BUCK/BOOST

USBDetection

I2C Slave

Control and Monitoring

USBConn

GS2011MIES

USB Data+/−

5V

SCL

SDA

VSYS

FET

BAT

STATUS

FTRY

SPM

NC

NC

The selected battery pack will cutoff the supply when thecell voltage goes below 3.0 V. If the voltage of the battery isvery low the battery must be slow charged to 2.8 V first, andonce the battery is above 2.8 V the battery can be chargedwith the fast current.

Switch-Mode Battery Charger Design – NCP1855The NCP1855 is a highly-integrated switch-mode battery

charge management and system power path managementdevices for single cell Li-Ion battery in a wide range of tabletand other portable devices. For the system design detailsabout the inductor selection, input capacitor selection,output capacitor selection, capacitor ripple voltage, inductorripple current etc please refer to the NCP1855 data sheet.

Power Path ManagementPower path management can be supported when a battery

FET (QBAT) is placed between the application and thebattery. When the battery is fully charged (end of chargestate), power path management disconnects the battery from

the system by opening QBAT, while the DC-DC remainsactive. This will keep the battery in a fully charged state withthe system being supplied from the DC-DC. If a loadtransient appears exceeding the DC-DC output current andthus causing VSENSEN to fall below VRECHG, the FETQBAT is instantaneously closed to reconnect the battery inorder to provide enough current to the application. The FETQBAT remains closed until the end of charge stateconditions are reached again. The power path managementfunction is enabled through the I2C interface (registerCRTL2 bit PWR_PATH = 1). In the MatrixCam VDKON Semiconductor’s NTLUS3A18PZ is used as the QBAT.

Fuel GaugeThe ON Semiconductor LC709202F measures the power

level of 1-cell Lithium (Li+) battery used for a portabledevice. It is normally referred to as a “Fuel Gauge”.

Figure 35 is an interface diagram showing how the FuelGauge interfaces the microcontroller.

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Figure 35. Fuel Gauge Interconnection

Fuel GaugeLC709202FGS2011MIES

SCL

SDA BatteryPack

TEMP

PACK+

PACK−

VDD2

VDD1

Power Supply ManagementFigure 36 shows the detailed power supply architecture

with battery management:

Figure 36. Power Supply Architecture

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Power supply regulators are selected by considering thefollowing parameter:

1. It should operate from battery voltage range 3.0 Vto 4.25 V

2. Power on sequence should meet “Fast Boot &Capture” requirement

3. High efficient power components to improvebattery life cycle time

Power Supply Design for 3.3 V3.3 V is a primary IO Voltage and it is an operating voltage

of many devices in the design including microcontroller andDM368. A Buck/Boost converter LM3668SD−2833 isselected for 3.3 V to operate in battery voltage with highefficiency. This is a synchronous Buck/Boost converteremployed to source constant 3.3 V output for the inputvariations in the range of 2.6 V to 4.75 V. The automaticbuck mode is enabled when the input voltage is more than3.3 V and boost mode is enabled when the input is less than3.3 V. Battery charger IC output which ranges from 2.6 V to4.25 V can be directly connected to the input supply of theBuck/Boost converter.

Please refer to the LM3668 data sheet for details of theinductor and input/output capacitor selection under both theBuck and the Boost modes.

Power Supply Design for 1.35 VThe synchronous Buck converter NCP6332B is

employed to source adjustable outputs with maximum of1.2 A current. Two NCP6332B is employed to sourceoutputs of 1.35 V at 1 A and 1.8 V at 0.5 A current forloading the peripherals section in the SoC DM368 and 1.8 VIO devices. These high efficient regulators will be controlledby the enable signal from GS2011MIES controller. Rest ofthe time these down converters will be disabled to savebattery backup power.

Please refer to the NCP6332B data sheet for details of“inductor selection”, “input/output capacitor selection”related topics.

Output Voltage Setting for 1.35 V:For the adjustable output voltage version, an external

resistor divider is used to set the output voltage. By selectingthe R1 and R2, the output voltage is programmed to thedesired value and the relation is given by:

VOUT � VFB � �1 � R1R2� (eq. 4)

Where:

VOUT = 1.35 VVFB = 0.6 V

R1 is the resistance from VOUT to FB, which has a normalvalue range from 50 k� to 1 M� and a typical value of220 k� for applications with the typical output filter.

Assume R1 = 220 k�

Then R2 = 176 k�

Since the 176 k� is not a standard value hence 174 k� and178 k� are considered. Output voltage is 1.358 and 1.341with 174 k� and 178 k� respectively. DM368 has corevoltage range 1.28 to 1.42 hence any of the value can beused. The MatrixCam VDK design is using 174 k� with0.5% tolerance.

Power Supply Design for 1.8 VThe synchronous Buck converter NCP6332B is

employed to source adjustable output voltage 1.8 V withmaximum of 1.2 A current.

For the adjustable output voltage version, an externalresistor divider is used to set the output voltage. By selectingthe R1 and R2, the output voltage is programmed to thedesired value and the relation is given by:

VOUT � VFB � �1 � R1R2� (eq. 5)

Where:

VOUT = 1.8 VVFB = 0.6 V

R1 is the resistance from VOUT to FB, which has a normalvalue range from 50 k� to 1 M� and a typical value of220 k� for applications with the typical output filter.

Assume R1 = 220 k�

Then R2 = 110 k�

110 k� with 0.5% tolerance resistor is used in theMatrixCam VDK.

Power Supply Design for 2.8 VAptina image sensor AR023Z requires 2.8 V for

VDD_PLL, VAA_PIX and VAA for its internal operationwith around 58 mA as a current requirement. To meet thisrequirement low noise LDO NCP752BSN28T1G is used inthe MatrixCam VDK. NCP752BSN28T1G is an 130 mVlow dropout regulator with input voltage of 2.0 V to 5.5 V.

Please refer to the NCP752BSN28T1G data sheet fordetails about the “input/output capacitor selection”.

3.3 V Power MOSFETTo use the same power 3.3 V power source i.e.

LM3668SD−2833 extra MOSFET is used to turn on the3.3 V power of the DM368. The MOSFET will be enabledby the power sequence IC (LM3881).

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The complementary P−CH and N−CH will be used here asshown in the below figure.

Figure 37. 3.3 V MOSFET Switching

P−CHFET

N−CHFET

MCU_3V3 VCC_3V3

EN by Seq IC

N-Channel MOSFET: NTK3134NT1G and P-Channel MOSFET: NTLUS3A18PZTCG.

Voltage Monitoring CircuitThe MAX708TESA−TG device has a fixed-sense

threshold voltage VIT (3.08 V) set by an internal voltagedivider. In addition to the fixed sense threshold monitored atVDD, the MAX708 devices provide a second adjustableSENSE input. RESET is asserted in case VDD voltage dropsbelow VIT.

i.e. The following conditions make the RESET pin gohigh:

1. The voltage at VDD should be greater than 3.08 V2. The Voltage at the sense PIN should be greater

than 1.25 V

This is used to monitor the 3.3 V and 1.8 V for DM368and check the Manual reset switch position condition. Resetis maintained with 200 ms of delay time after VCC riseabove the reset threshold. Reset pin shall be pull down to100 k� to keep the output valid when VCC < 1 V.

The reset output is driven active within 20 �s of VCCfalling through the reset voltage threshold.

Note: Transient immunity can be improved by addinga capacitor (100 nF for example) in close proximity tothe VCC pin of theMAX708TESA−TG.

Calculating R1: 2.4 k� & R2: 10 k�

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SYSTEM POWER ON/OFF SEQUENCE

The MatrixCam VDK has a button to turn on the completesystem.

Tactile ON/OFF Button: A tactile button is connected toLTC2950−1 to enable the power of the system. Afterpressing the button, GS2011MIES is supposed to drive the

“MCU_OFF” high with in 500 ms to keep the power enable.This switch is used to turn ON the power of GS2011MIESonly. Rest of the system (DM368, Image Sensor and otherperipherals) will remain powered OFF and will be poweredbased on the interrupt i.e. PIR, BLE and WOW.

Figure 38. DM368 Power On Sequence

DM368 Power On Sequence

CC3200 GPIO − To Trigger Power On Sequence

1.35 V REGULATION

POWER GOOD SIGNAL

2.8 V: VDD_PLL

2.8 V: VAA, VAA_PIX

1.8 V: REGULATION

3.3 V (Enable MOSFET)

Reset# to DM368

Vo

ltag

e

Time

VTH = 1.1 V

300 �s 100 �s

1.15 ms

30 ns

VTH = 1.2 V

120 �s

120 �s

VTH = 1.2 V

300 �s 100 �s

200 ms + 7.4 ns

Propagation Delay ofAND Gates = 7.4 ns

TOTAL POWER ON RESET TIME = 200.79 ms

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REFERENCE

All design files; schematics, PCB layout files, Gerber filesas well as the BOM file can be found in the “HardwareDesign Files” folder.

http://tiny.cc/matrixcam

ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessedat www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representationor guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, andspecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheetsand/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for eachcustomer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whichthe failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended orunauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, andexpenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claimalleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicablecopyright laws and is not for resale in any manner.

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AND9237/D

ARM, Cortex, and Thumb are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. Bluetooth is a registeredtrademark of Bluetooth SIG. Wi-Fi is a registered trademark of the Wi-Fi Alliance. MatrixCam is a trademark of Semiconductor ComponentsIndustries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. microSD and SDHC are trademarks of SD−3C, LLCin the United States, other countries or both. ANT is a trademark of Dynastream Innovations Inc. ShockBurst is a trademark of NordicSemiconductor ASA. All other brand names and product names appearing in this document are registered trademarks or trademarks of theirrespective holders.

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