APPLE A1311 K60 820-3126-A

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

DRAWING

DRAWING

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3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

3

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DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

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3456

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8 7 6 5 4 2 1

12

APPDCK

DESCRIPTION OF REVISION

K60 MLB

1 OF 98

051-8115

11.1.0

1 OF 110

2011-02-08

Contents SyncDate(.csa)

Page49

01/06/2011

K60_MARK

52

SMBUS CONNECTIONSTable of Contents1

1 K60

05/21/2009

ABBREV=DRAWING

TITLE=K22

LAST_MODIFIED=Tue Feb 8 14:39:56 2011

LAST_MODIFIED=Tue Feb 8 14:39:56 2011

Page(.csa)

ContentsDate

Sync

5001/06/2011

K62

53

CPU/PCH/GPU POWER SENSE

5101/06/2011

K62

54

HDD OOB SENSE

5201/06/2011

K60_MARK

55

TEMP SENSORS

5301/06/2011

K62

56

HD AND OD FAN

5401/06/2011

K60_JERRY

57

CPU FAN

5501/06/2011

K62

61

SPI ROM

5601/06/2011

K60_DAVID

62

AUDIO: CODEC/REGULATOR

5701/06/2011

K60_DAVID

63

AUDIO: FILTER/BUFFER

5801/06/2011

K60_DAVID

64

AUDIO: SPEAKER AMP_1

5901/06/2011

K60_DAVID

65

AUDIO: SPEAKER AMP

6001/06/2011

K60_DAVID

66

Audio: MLB to I/O Conn.

6111/24/2010

K60_DAVID

67

AUDIO: Detects/Grounding

6201/06/2011

K60_DAVID

68

AUDIO: Mikey

6301/06/2011

K62

69

POWER SEQUENCING ENABLES

6401/06/2011

K62

70

POWER SEQUENCING PGOOD

65N/A

K60_AARON

71

VREG: PPVCORE_S0_CPU

6601/06/2011

K62

72

VREG: CPU CORE - PHASES 1-3

67N/A

K60_AARON

73

VREG:AXG PHASE/CORE - CAPS

6801/06/2011

K62

74

1V05 REGULATOR

6911/15/2010

K62

75

CPU VCCSA REGULATOR

7001/06/2011

K62

77

5V_S3 / 3V3_S5 VREGS

7101/06/2011

K62

78

1.5V / 1.8V VREGS

7201/06/2011

K62

79

3.42 G3HOT SUPPLY

7301/06/2011

K62

80

S3+S0 FETS

7401/06/2011

K60_JERRY

81

12V_S0 & 12V_S5 switch

7501/06/2011

K62

84

MXM PCIe, DP & Power

76N/A

K60_MASTER

85

MXM I/O

7701/06/2011

K62

86

MXM PCIE CAPS

7807/18/2010

K60_AARON

87

DP ALIAS AND CONTROL

7901/06/2011

K62

88

GREEN CLOCK

8001/06/2011

K62

89

T29 POWER

8101/06/2011

K62

90

Display: Int DP Connector

8211/14/2010

K62

91

2V9/3V3/12V POWER SWITCH

8301/06/2011

K62

92

Internal DP MUXing

8411/14/2010

K62

93

DisplayPort/T29 A MUXing

8501/06/2011

K62

94

DisplayPort/T29 A Connector

8601/06/2011

K62

97

T29 Host (1 of 2)

8701/06/2011

K62

98

T29 Host (2 of 2)

8801/06/2011

K62

100

K60/K62 RULE DEFINITIONS

8901/06/2011

K60_ROSITA

101

Memory Constraints

9001/06/2011

K62

102

PCIE/DMI/FDI/SATA CONSTRAINTS

9101/06/2011

K62

103

IBEX PEAK CONSTRAINTS

9201/06/2011

K62

104

USB/ENET/SD/FW/AUD CONSTRAINTS

9301/06/2011

K62

105

GRAPHICS CONSTRAINTS

9401/06/2011

K62

106

SMC Constraints

9501/06/2011

K62

107

POWER CONSTRAINTS

9601/06/2011

K62

108

T29 CONSTRAINTS

9701/06/2011

K62

109

PM RESETS ENABLES PGOOD CONST

9801/06/2011

K62

110

K60/K62 ICT/FCT

System Block Diagram2

2 K60_SIJI

01/06/2011

Power Block Diagram3

3 K60_JERRY

01/06/2011

BOM Configuration4

4 K60_AARON

N/A

DEBUG LEDS5

5 K62

01/06/2011

Power Conn / Alias6

6 K60_MARK

12/30/2010

Holes7

7 K74_MASTER

N/A

UNUSED SIGNAL ALIAS8

8 K62

01/06/2011

Signal Aliases9

9 K62

01/06/2011

CPU DMI/PEG/FDI/RSVD10

10 K62

01/06/2011

CPU CLOCK/MISC/JTAG11

11 K62

01/06/2011

CPU DDR3 INTERFACES12

12 K62

01/06/2011

CPU POWER13

13 K62

01/06/2011

CPU GROUNDS14

14 K62

01/06/2011

STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU15

15 K62

01/06/2011

CPU NON-GFX DECOUPLING16

16 K62

01/06/2011

GFX DECOUPLING & PCH PWR ALIAS17

17 K62

01/06/2011

PCH SATA/PCIE/CLK/LPC/SPI18

18 K62

01/06/2011

PCH DMI/FDI/GRAPHICS19

19 K62

01/06/2011

PCH PCI/FLASHCACHE/USB20

20 K62

01/06/2011

PCH MISC21

21 K62

01/06/2011

PCH POWER22

22 K62

01/06/2011

PCH GROUNDS23

23 K62

01/06/2011

PCH DECOUPLING24

24 K62

01/06/2011

CPU & PCH XDP25

25 K62

01/06/2011

CLOCK (CK505)26

26 K62

01/06/2011

CHIPSET SUPPORT28

27 K62

01/06/2011

DDR3 VREF MARGINING29

28 K62

01/06/2011

MEMORY CAPS30

29 K62

01/06/2011

DDR3 SO-DIMM 0 & 231

30 K62

01/06/2011

DDR3 SO-DIMM 1 & 332

31 K62

01/06/2011

DDR3 SUPPORT AND BITSWAPS33

32 K62

01/06/2011

PCI-E Wireless Connector34

33 K62

01/06/2011

USB HUB 135

34 K62

01/06/2011

USB HUB 236

35 K62

01/06/2011

CAESAR IV SUPPORT38

36 K62

01/06/2011

ETHERNET PHY (CAESAR IV)39

37 K62

01/06/2011

Ethernet Connector40

38 K60_MARK

01/06/2011

FireWire LLC/PHY (FW643)41

39 K60_ROSITA

01/06/2011

FireWire: 1394B MISC42

40 K62

01/06/2011

FIREWIRE CONNECTOR43

41 K62

01/06/2011

SATA Connectors45

42 K60_JERRY

01/06/2011

EXTERNAL USB CONNECTORS46

43 K62

01/06/2011

Internal USB Connections47

44 K62

01/06/2011

SD READER CONNECTOR48

45 K62

01/06/2011

SMC49

46 K62

01/06/2011

SMC Support50

47 K62

01/06/2011

LPC+SPI Debug Connector51

48 K62

01/06/2011

SCH,K60,MLB

www.vinafix.vn

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:


36

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IV ALL RIGHTS RESERVED

SHEET

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Apple Inc.

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USB CAMERAPG 47

J47XX

J47XX SD CARDPG 47

TO ENET

25MHz XTAL IN 25MHz XTAL IN

25MHz XTAL IN

X4 PCI-E GEN2

PG 88

U8800

GREEN CLK

X16 PCI-E GEN2

FDI INTERFACE

DDR3 1333 CHB

DDR3 1333 CHA

J4800

SATA-A2

SATA CONNODD

T3900

MAGNETICS

PG 38

AND PHY

GB E-NET

SATA CONN

LGA1155 - SANDY BRIDGE

PG 19

PG 47

J4700

ALS

XDP CONN

SO-DIMMS

XDP CONN

PG 55

FAN CONN AND CONTROLPG 56,57

J5600, J5601, J5700

FW643

SD CARD HDA

SMB

E-NETCONNECTOR

J4530

X1 PCIE GEN1 LANE 2.5GBITPS


PG 19

CONTROLLER

HDMI/DVI/DP

(UP TO 14 DEVICES)

LPC6 SATA 2.O PORTS

PG 18

X4 DMI

(PORT B)

RGB OUT

DIGITAL VIDEO OUTPUT

(PORT C)

13

12

11

10

83

SATA

(SUPPORTED UPTO 4 REQ/GNT)

E-NET

PCI

PWR


SATA 3.0 6GHZ.

SATA 3.0 6GHZ.

HDD

SSD

MIDBUS PROBE

PG 25

J2500

Port80,serialPG 51

XDP

J3900

(PORT D)

PG 39

U3800

PG 18

INTERFACE

PG 18

PG 19

DMI INTERFACE

PG 18

HDMI/DVI/DP

PG 19

PG 18

PG 18

PG 18

PG 20

PG 19

PG 20

PG 25

U2510

PG 39

01

25

67

9

USB 2.0

DIMM’s

SPIBoot ROM

PG 13

U6100

PG 32

PG 31

J3200, J3200

J3100, J3100 PG 53 POWER SENSE

TO BIDIVI HW

PG 10

CTRL

Fan

MIKEY

J4300

SPI

B,0 BSB

SMCADC

4

PG 34 PG 43

AirPortMini PCI-E

PG 49

U4900


ConnFireWire

J3400

PG 41

U4100

HDMI/DVI/DP

U1000

2 SO-DIMMS

J5100

PrtSer

PG 61

CLK

LPC+SPI CONN

(PORT A)

ANALOG VIDEO OUTPUT

SATA-A0

SYNTH

PG 45

J4510

J4520

PG 45

PG 45

PCI-E GEN2

UP TO 8 LANES3

U6201

Audio

Audio

Conns

Codec

U6400, U6500

SPEAKER AMPS

HEADPHONES INTERNAL/EXTERNAL

MICROPHONES LINE INPUT

J6600,J6601,J6602,J6603

2 SO-DIMMS

GPIOs

SO-DIMMS

PG 48

INTEL CPU

POWER SUPPLY

TEMP SENSORS

TEMP, CURRENT SENSE

GPU HEATSINK AMBIENT INTAKE CPU DIE-PECI

LEFT SKIN TEMP RIGHT SKIN TEMP

MXM CONNECTORJ8400

X4 DP

X4 DPLOGIC

PG 84

X4 DPX4 DP

T29 ROUTER

X4 DP

T29 LANES

T29 LANES

DP LANES TO INT MUX

EXTERNALPG 94

PORT CONNDISPLAY

J9400

X4 DP

PG 90

DISPINTERNALJ9002

Misc

INTEL

COUGAR POINT

U1800

PG 46

PG 46

PG 47

EXTA

EXTB

BLUETOOTH

J4610

PG 46

J4700

J4600

PG 47

PG 46

EXTDJ4630

IR

EXTCJ4620

J4780

PG 36

PG 35

USB HUB1

U3500

U3600

USB HUB2

LCD TEMP

OPTICAL DRIVE HARD DRIVE (OOB)

MXM - GPU DIE CPU HEATSINK

SATA CONN


SATA 2.0 3GHZ.

SATA-A1

SYNC_MASTER=K60_SIJI

System Block DiagramSYNC_DATE=01/06/2011

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8 7 5 4 2 1

PP12V_T29

PP12V_S5_LED 3.75A

USB Ext Port 4.7APP5V_USB_PORTx

Spec:14A(170W)

PM_SLP_S3

ODD_PWR_EN_L (GPIO-22)

ENET_PWR_EN(GPIO-42)

AP_PWR_EN(GPIO-59)PP3V3_S3 BT

PAGE 34

PP3V3_S3_ENET

PM_SMC_G2_EN

PP12V_S5:Peak 6.9A(83W)

PCH

SMSC USB Hubx2

SWReg ISL8013A 1A

PAGE 78

PP3V3_S3_MINIFET 2.75A/1.1A/0.19A

FET 0.25A/0.2A/0.06A

PP12V_G3H:

FET 7A/2.7ASSD 0.8AHDD 1.8A

P5VS0_EN

FET 2.9A/1.2A

PAGE 80

BOOT ROM

PAGE 80

USB_CAMERAUSB_IR

PM_EN_USB_PWR

FET 12V [email protected]

1.1A/12VPP12V_T29

FANS 0.75A

LCD PANEL 0.6APP12V_S0_FWR 1.2A

AUDIO 1.7APP12V_S0_HDD 1.2A

MXM 3.38A(45W TDP)

PP12V_S0:Peak 16.9A(203W)

12V_G3H INA219EMC1403

I2C CLK,DATATEMP SENSOR

PAGE 76

8.8AVCCSAPPVCCSALDO [email protected]

PAGE 76

SWReg ISL9563A

PAGE 76

AIRPORT

DP_RDRV 0.7/0.02A

ISL62383 [email protected]

PP3V3_S5_REG

PAGE 77

P3V3S3_EN

ODD 1.5A

PAGE 38

ETHERNET

SD Card(250mA)

MXM 1A MaxFIREWIRE

FET 3.4A/ 1.9A PCH

Lazarus(100mA)

PP3V3_S0_SD

AUDIO PP3V3_S0

ISL62383 [email protected]

PP5V_S3_REG

1V05 VCCIO 6.5A (PCH)

1V05 T29 3A (T29)

PP1V05_S0

AC/DC POWER SUPPLY (Spec:215W)

PAGE 48

SMC VREF

VAXG 6.5ACORE 75A

CPU VCCIO 8.5A (CPU)

1.1V @ 30A

PAGE 71-73

SWreg ISL6364

.65V-1.5V @ 75A/55A

PPVCORE/AXG

CPU PLL

PAGE 46

AUDIO

MXM 2.5APCH

FW

PAGE 42

CPU MEMAUDIO

MEM_VTTPP0V75_S0

TPS2560

PP5V_S0

P3V3S0_EN

PAGE 77

MAIN MEMORY

PAGE 78

PP1V5_S0FET 6.2A/3A

PM_SLP_S3

PAGE 80

0.75V @ 0.6A

PAGE 75

PAGE 78

PP1V5_S3_REGTPS51116, 1.5V 11A/6.7A

PP3V3_S5_AVREF_SMC

PAGE 50

LDO SN0903048

SMC

SW LT3470A

PP3V42_G3H_REG

PAGE 79

12V LED Power

Spec:3.75A (45W)

PP1V8_S0_REG

BJT 1.0V @ 0.08A

PP1V0_FWPHY

SYNC_DATE=01/06/2011SYNC_MASTER=K60_JERRY

Power Block Diagram

3 OF 110

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BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

CRITICAL BOM OPTIONTABLE_5_HEAD

PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM


PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM


PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM



TABLE_5_ITEM

TABLE_5_ITEM



TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM


TABLE_ALT_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM




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8 7 5 4 2 1

67

BOTTOM

43

5

2TOP

POWER

GROUNDSIGNAL

POWER

SIGNAL

GROUNDSIGNAL

BOARD STACK-UP

SIGNAL

K60 ALTERNATE PARTS

BOM Variants

RAW: 335S0539

CPUS

RAW: 335S0709

RAW: 337S3997

COMMON

RAW: 335S0550

RAW: 338S0878

RAW: 335S0807

K60 PARTS

BOM GROUPS

CPU SOCKET & ILM SUB-BOMS

SYNC_MASTER=K60_AARON

BOM ConfigurationSYNC_DATE=N/A

K60,2P7GHZ_SNB_CPU_PRQ,BASIC1,BASIC2,CPUVCORE-3PH,ODD_SATA:P2,YES_DBGPCBA,MLB,K60,2.7G,4C,PRQ,P2_ODD639-1820


PCBA,MLB,K60,2.7G,4C,PRQ,P2_ODD,NO_DBG K60,2P7GHZ_SNB_CPU_PRQ,BASIC1,BASIC2,CPUVCORE-3PH,ODD_SATA:P2,NO_DBG639-2159



PCBA,MLB,DEV,K60085-0801 DEVELOPMENT,DEV_GROUP

BASIC2 AP,BT,IR,T29

BASIC1 COMMON,ALTERNATE,MXM,FCIM,CPU_1V5_SENSE,CPU_VCCSA_SENSE,1V05_PCH_SENSE,HUB_USX2061,PRODUCTION,VAXG,SSD

NO_DBG MOJOMUX:NO,LPCPLUS:NO

371S0652 PIN DIODE371S0679

USB DIODE377S0107 377S0066

376S0972 376S0612 ROHM TRA-BJT

128S0293 330UF128S0298

341T0184 1 FLASH,EFI BOOTROM,K60/K62 CRITICALU6100

U3990SFLASH ENET 2MBIT,CIV341T0328 CRITICAL1

T29 ROUTER, IC ASSP T29338S0945 CRITICAL1 U9700

IC,T29,SERIAL EEPROM T29341T0257 CRITICAL1 U9790

IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25341T0326 T29CRITICALU93301

IC,MXM SYS ROM,24C02 U8570341T0330 1 CRITICAL

IC,SMC,K60 CRITICAL1 K60341T0185 U4900

PCBF,MLB,K60 MLB11 K60820-2641

K60SCH,MLB,K60051-8115 SCH11

2P5GHZ_SNB_CPU_PRQSNB,SR00S,PRQ,D2,2.5,65W,4+1,6M,LGA337S4043 CPU1 CRITICAL

2P7GHZ_SNB_CPU_PRQSNB,SR009,PRQ,D2,2.7,65W,4+1,6M,LGA CPU1 CRITICAL337S4062

2P8GHZ_SNB_CPU_PRQCPU1 CRITICALSNB,SR00E,PRQ,D2,2.8,65W,4+1,8M,LGA337S4061

TYCO_SOCKETU1000511S0071 CRITICAL1 SOCKET,LGA1155,CPU-LF

ILM604-1474 1 TYCO_SOCKETASSY,PURCHASED,ILM,TYCO CRITICAL

U1000 MOLEX_SOCKETCRITICALSOCKET,LGA1155,CPU-LF1511S0073

604-1161 MOLEX_SOCKETILM1 ASSY,PURCHASED,ILM,MOLEX CRITICAL

SUB ASSY,CPU SOCKET,K60,TYCO TYCO_SOCKET085-2452

085-2453 SKT_ILM MOLEX ALTERNATE085-2452

CRITICAL1 TYCO CPU SOCKET AND ILM SKT_ILM085-2452

085-2453 MOLEX_SOCKETSUB ASSY,CPU SOCKET,K60,MOLEX

DEV_GROUP VREFMRGN_A,VREFMRGN_B,DIMM_1V5_SENSE

YES_DBG XDP,XDP_CONN,XDP_CPU_BPM,MOJOMUX:YES,LPCPLUS:YES

IC,BCM57765,ENET&SD,8X8 CRITICAL343S0534 1 U3900

MLB LABEL,48.0X4.8 X14 CRITICAL825-7122 1

353S3055 IC,PI3VEDP212,X2 DP MUX,QFN CRITICAL1 U9390

IC,FW643,1394B_PCIE,PHY/LINK U4100 CRITICAL338S0753 1

337S4088 IC,COUGAR POINT,SLJ4F,BD82Z68,PRQ,B31 CRITICALU1800

639-2118 PCBA,MLB,K60,2.5G,4C,PRQ,P1_ODD K60,2P5GHZ_SNB_CPU_PRQ,BASIC1,BASIC2,CPUVCORE-3PH,ODD_SATA:P1,YES_DBG

PCBA,MLB,K60,2.7G,4C,PRQ,P1_ODD639-2122 K60,2P7GHZ_SNB_CPU_PRQ,BASIC1,BASIC2,CPUVCORE-3PH,ODD_SATA:P1,YES_DBG

PCBA,MLB,K60,2.8G,4C,PRQ,P1_ODD K60,2P8GHZ_SNB_CPU_PRQ,BASIC1,BASIC2,CPUVCORE-3PH,ODD_SATA:P1,YES_DBG639-2119



K60,2P8GHZ_SNB_CPU_PRQ,BASIC1,BASIC2,CPUVCORE-3PH,ODD_SATA:P1,NO_DBG639-2134 PCBA,MLB,K60,2.8G,4C,PRQ,P1_ODD,NO_DBG


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IN

G

D

SIN

G

D

SIN

G

D

SIN

ING

D

S

G

D

S

IN

G

D

SIN

G

D

SIN

G

D

SIN

IN

G

D

S




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S5 Led

SILKSCREEN:1

SILKSCREEN:6SILKSCREEN:7

SILKSCREEN:8

SILKSCREEN:10

SILKSCREEN:11

VIDEO ON LedMXM PWR GOOD Led

SILKSCREEN:4

SILKSCREEN:3SILKSCREEN:2

SILKSCREEN:9

SILKSCREEN:12

ALL_SYS_PWRGD Led

PROTO DEBUG LEDS ARE SHOWN BELOW

SILKSCREEN:5

19 26 32 36 46 47 63 82 97

K

A

LED550DEVELOPMENT

GREEN-3.6MCD2.0X1.25MM-SM

SILK_PART=VCORE_PGOOD

4

5

3

Q540

SOT-3632N7002DW-X-G

DEVELOPMENT

25 64 65 97

K

A

LED500

2.0X1.25MM-SM

DEVELOPMENT

GREEN-3.6MCD

SILK_PART=SLP_S4

K

A

LED530 SILK_PART=DDR_PGOODDEVELOPMENT


2

1R540DEVELOPMENT

MF-LF

5%3.3K1/16W

402

1

2

6

Q5202N7002DW-X-GSOT-363

DEVELOPMENT

63 71 97

K

A

LED540SILK_PART=PCHCORE_PGOOD2.0X1.25MM-SMGREEN-3.6MCD

DEVELOPMENT

1

2

6

Q540

SOT-3632N7002DW-X-G

DEVELOPMENT

64 97

2

1R5003.3K5%

MF-LF

DEVELOPMENT

1/16W

402

2

1R530DEVELOPMENT

3.3K5%

MF-LF1/16W

402

2

1R5503.3K5%

MF-LF

DEVELOPMENT

1/16W

402

2

1R5021/16W5%

MF-LF

1K

402

81

K

A

LED502GREEN-3.6MCD2.0X1.25MM-SM

4

5

3

Q5022N7002DW-X-GSOT-363

4

5

3

Q500DEVELOPMENT

SOT-3632N7002DW-X-G

2

1R5045%

MF-LF1/16W

402

1K

32 64 97

K

A


2

1R505DEVELOPMENT

MF-LF

5%1K1/16W

402

K

A

LED5052.0X1.25MM-SMGREEN-3.6MCD

DEVELOPMENT

2

1R5011K1/16W

402MF-LF

5%

K

A


2

1R510

402

1/16W

DEVELOPMENT

5%3.3K

MF-LF

2

1R503

402

1K5%1/16WMF-LF

K

A


1

2

6

Q5022N7002DW-X-GSOT-36321 25 97

2

1R549DEVELOPMENT

3.3K

MF-LF

5%1/16W

402

K

A


SILK_PART=VAXG_PGOODDEVELOPMENT

4

5

3

Q5202N7002DW-X-GSOT-363

DEVELOPMENT

65 97

K

A

LED510SILK_PART=SLP_S3DEVELOPMENT


2

1R560DEVELOPMENT

5%

MF-LF

3.3K1/16W

402

K

A

LED560

DEVELOPMENT

2.0X1.25MM-SMGREEN-3.6MCD

SILK_PART=SLP_S5

4

5

3

Q5302N7002DW-X-GSOT-363

DEVELOPMENT

19 46 47 63 97

2

1 C50120%0.1UF10V

402CERM

19 32 46 47 63 97 1

2

6

Q500

SOT-363

DEVELOPMENT

2N7002DW-X-G

SYNC_MASTER=K62 SYNC_DATE=01/06/2011

DEBUG LEDS

=PP3V3_S5_LED

=PP3V3_S5_LED

CORE_VOLTAGES_ON

PM_PGOOD_PVCORE_CPU

=PP3V3_S0_LED

GPU_PRESENT_R

VIDEO_ON_L

PM_LED1_AXG

=PP3V3_S0_LED

PM_LED_AXGPM_LED_PCHCORE

PM_LED1_PCHCORE

PGOOD_PCH_S0

MXM_GOOD

GPU_PRESENT_DRAIN

=PP3V3_S0_LED

LCD_SHOULD_ON_R

=PP3V3_S0_LED

PM_LED1_DDRREG

PM_LED_DDRREG

PM_LED1_S3

PM_LED_S3

PM_LED1_PVCORE

CORE_VOLTAGES_ON_R

=PP3V3_S3_LED

ITS_PLUGGED_IN

PM_PGOOD_DDR1V5_S3_REG

PM_LED_PVCORE

PM_PGOOD_PVAXG

=PP3V3_S3_LED

ITS_ALIVE

PM_SLP_S4_L

PM_LED1_S4

=PP3V3_S5_LED

PM_LED_S4

PM_LED_S5

=PP3V3_S5_LED

PM_LED1_S5

PM_SLP_S5_L

PM_SLP_S3_L

ALL_SYS_PWRGD_R

=PP3V3_S5_LED

=PP3V3_S0_LED

5 OF 110

11.1.0

051-8115

5 OF 98

5 6

5 6

5 6

5 6

5 6 5 6

5 6

5 6

5 6

5 6

5 6

5 6

www.vinafix.vn

IN

BI

G S

D

IN

G

S D

BI

IN

G

S D

IN

IN

BI

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

3V3 RISES BEFORE

MLB TO BLC

ISOLATION CIRCUIT

FET DIODE IS S TO DMLB 3V3).

(FACES BLC WHICH

POWER SUPPLY TO MLB

"G3H" RAILS

T29 RAILS

ON IN RUN AND SLEEP

BLC SDA/SCL

518S0543

MLB TO PS

518S0813

518-0373

ALWAYS ON WHEN UNIT HAS AC POWER AND IN S5

ONLY ON IN RUN

"S0" RAILS"S5" RAILS

GND RAILS

"S3" RAILS

ALWAYS ON WHEN UNIT HAS AC POWER AND IN G3HOT PER SMC

G3H: ALIASES

2

1 C602

402CERM50V5%47PF

21

R602

4021/16W

0

5%

2

1 C604

CERM402

50V

47PF5%

21

R601

402

0

5%

1/16W

2

1 C6030.001UF10%

X7R50V

402

PLACE C603 CLOSE TO CONNECTOR

49

49

2

1 C610

603-1


25VX5R

10%1UF

21R605 0

402 5%1/16W

6

5

4

3

2

1

J600M-RT-TH

76833-0106

2

1

3

Q6102N7002SOT23-HF1

2

1 C606

X7R


10%0.001UF50V

40263 97

2

1 C611


25VX5R

10%1UF

603-1

7

6

5

4

3

2

1

J60150293-00771-H01

M-ST-SM

CRITICAL

21

R6310

1/16W4025%

2

1 C628NOSTUFF

402

47PF5%50VCERM

8

7

6

5

4

3

2

1

10

9

J602CRITICAL

F-RT-SM53780-8608

2

1R620

402MF-LF1/16W5%021

R6220

1/16W4025%

21

L602FERR-1000-OHM

0402

2

1 C627NOSTUFF

47PF

402

5%50VCERM

21

R630

5%

1/16W

0

402

1

2

6

Q6002N7002DW-X-GSOT-363

49 81 94

49 81 94

2

1 C62147PF5%

402CERM50V

NOSTUFF

21

R617

1/16W4025%

0

NOSTUFF

21

R618

5%402

0

NOSTUFF

1/16W

4

5

3

Q6002N7002DW-X-GSOT-363

15 21 91

81 97

49

49

2

1 C622NOSTUFF

50V5%

402

47PF

CERM

Power Conn / AliasSYNC_MASTER=K60_MARK SYNC_DATE=12/30/2010

GND

MAX_NECK_LENGTH=4.1 MM

MIN_LINE_WIDTH=0.6MM

NET_SPACING_TYPE=GNDVOLTAGE=0V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2MM

=PP3V3_G3H_LPCPLUS

=PP3V3_G3H_SMCUSBMUX

=PP3V3_G3H_SMC

PP3V42_G3H_REG

=PP12V_S5_T29_A

=PP12V_S5_PWRCTL

=PP12V_S5_P5VS3_VREG

PP12V_S5_FET

PP5V_S5_LDO

=PP5V_S5_PCH

NET_SPACING_TYPE=POWER

MIN_LINE_WIDTH=0.6MMVOLTAGE=3.42V


MAKE_BASE=TRUE

MAX_NECK_LENGTH=3 MM

PP3V42_G3H

VOLTAGE=12VMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmNET_SPACING_TYPE=POWER

MAKE_BASE=TRUE


PP12V_S5

MAKE_BASE=TRUE


VOLTAGE=5VMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 mm


PP5V_S5

=PP3V3_S5_RSTBUF

=PP3V3_S5_PCH_VCCSUS3_3_USB

=PP3V3_S0_SMC_LS

=PP3V3_S0_SMBUS

=PP3V3_S0_ENET_PHY

=PP3V3_S0_T29I2C

=PP3V3_S0_DP

=PP3V3_S0_PCH_VCC3_3_PCI

=PP3V3_S0_PCH_PM

=PP3V3_S0_P1V05_VREG

=PP3V3_S0_PCH_VCC3V3

=PP3V3_S3_VRD

=PP3V3_S3_VREFMRGN

=PP3V3_S0_DPSDRVA

=PP3V3_S0_INTDPMUX

=PP1V5_S0_CK505

=PP3V3_S0_SATALED

=PP3V3_S0_PCH_VCC3_3_GPIO

VOLTAGE=1.5VMIN_LINE_WIDTH=0.4MM

NET_SPACING_TYPE=POWERMAX_NECK_LENGTH=3 MM


MAKE_BASE=TRUEPP1V5_S0

=PP1V5_S0_PWR

PP1V5_S0_FET

=PP1V5_S0_AUD_DIG

=PPVCCSA_S0_PWRCTL

=PPVCCIO_S0_CPU_VCCSA

PPVCCSA_S0_INPUT_SNS

MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM

VOLTAGE=1.05V


MAKE_BASE=TRUE


PP1V05_S0_INPUT_VCCSA

=PP3V3_S0_T29PWRCTL

=PP3V3_S0_P3V3T29FET

=PP3V3_S0_LED

=PP3V3_S0_VRD

=PP3V3_S0_SDCARD

=PP3V3_S0_SMBUS_SMC_BSA

=PP3V3_S0_RSTBUF

=PP3V3_S0_PCH_VCC3_3_SATA

=PP3V3_S0_PCH_STRAPS

=PP3V3_S0_PCH_GPIO

=PP3V3_S0_FWPHY

=PP3V3_S0_PWRCTL

=PP3V3_S0_SENSE

=PP3V3_S0_ODD

=PP3V3_S0_MXM

=PP3V3_S0_SMBUS_SMC_0

=PPSPD_S0_MEM_B

=PP3V3_S0_PCH

PP3V3_S0_FET

=PP1V5_S0_CPU_MEM

PPVAXG_S0MAKE_BASE=TRUEVOLTAGE=1.05VMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.3MM

MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=POWER

PP1V05_S0_REG

=PP1V05_S0_PWR

PP12V_S0_PS

=PP5V_S0_LPCPLUS

=PP5V_S3_P3V3R2V9_REG_A

=PP5V_S3_VREFMRGN

=PP5V_S3_DDR_VREG

=PP5V_S3_MEMRESET

=PP5V_S3_IR

=PP5V_S3_CAMERA



VOLTAGE=5VMAKE_BASE=TRUE



PP5V_S3

=PP3V3_S5_CPU_VCCSA

=PP3V3_S5_MEMRESET

=PP3V3_S5_PCH

=PP3V3_S5_PCH_GPIO

=PP3V3_S5_PCH_VCCSPI

=PP3V3_S5_S3FET

=PP3V3_S5_VRD

PP3V3_S5_REG

NET_SPACING_TYPE=POWERMIN_NECK_WIDTH=0.25MM

MAKE_BASE=TRUEVOLTAGE=1.05VMIN_LINE_WIDTH=0.5MM


PP1V05_S0

=PP1V05_S0_PCH_VCCIO_SATA

=PP1V05_S0_PCH_VCCIO_PCIE

=PP1V05_S0_PCH_VCC_CORE

=PP12V_S0_CPU_VCCSA

PP12V_S0_MXM_SNS

=PP12V_S0_MXM

=PP12V_S0_SENSE

=PP12V_S0_PWRCTL

=PP12V_S0_P1V05_VREG

=PP12V_S0_LCD

=PP12V_S0_VRD

=PP12V_S0_AUDIO_SPKRAMP

=PP3V3_SW_DPAPWR

=PP3V3_S3_MEMRESET

=PP1V05_S0_PCH_VCCADPLLMIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE


MIN_LINE_WIDTH=0.6 mmVOLTAGE=1.05V

PP1V05_S0_PCH

=PPVCCIO_S0_CPU

=PPVCCIO_S0_XDP

=PP12V_S0_MXM_PWR

PP1V5_S3_REG


MAKE_BASE=TRUE


VOLTAGE=12V


PP12V_S0_MXM

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH

=PP1V8_S0_PCH

=PP5V_S0_P1V8_REG

PPVCORE_S0_CPU_REG

=PP1V5_S3_MEMRESET

=PP1V5_S3_MEM_PWR

=PP3V3R1V8_S0_PCH_VCCDFTERM

=PP1V8_S0_CPU_PLL

=PP0V75_S0_MEM_VTT_A

=PPVCORE_S0_CPU

=PPVCCSA_S0_INPUT_PWR =PP5V_S0_P1V05_VREG

=PP5V_S0_PCH

=PP1V05_S0_PCH_VCC_DMI

=PP1V05_S0_PCH_PWR

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V8_S0_PWRCTL

PP1V8_S0_REG

PP0V75_S0

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE


MIN_LINE_WIDTH=0.4 mmVOLTAGE=0.75V

=PP1V05_S0_PCH_V_PROC_IO


MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmVOLTAGE=1.5VMAKE_BASE=TRUE

PP1V5_S3

=PP12V_S0_SATA

PPVAXG_S0_REG

=PP3V3_T29_RTR

=PP12V_G3H_S5_FET

=PP1V05_S0_PCH_VCCSSC

=PP0V75_S0_MEM_VTT_B

PPVTT_S0_DDR_FET


VOLTAGE=1.1VMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.3MMNET_SPACING_TYPE=POWER

MAKE_BASE=TRUEPPVCORE_S0_CPU

=PP5V_S0_MXM

=PP5V_S0_AUDIO

=PP5V_S0_VRD

PP1V05_T29_FET

=PP1V05_T29_RTR

=PP1V05_T29



MAKE_BASE=TRUE


PP1V05_S0_T29

=PPVCCIO_S0_SMC

=PP1V5_S3_S0FET

PP3V3_T29_FET

=PP1V05_S0_PCH_VCCDIFFCLK

PP1V05_S0_PCH_SNS

=PP5V_S0_ISENSE

=PP1V05_S0_CK505

PP12V_G3H_ACDC



MAKE_BASE=TRUEVOLTAGE=3.3V


PP3V3_S0_T29

=PP0V75_S0_MEM_VTT_S0FET

PP5V_S0_FET

=PP12V_G3H_3V42

MAKE_BASE=TRUEVOLTAGE=12VMIN_LINE_WIDTH=0.6 mm

NET_SPACING_TYPE=POWERMIN_NECK_WIDTH=0.2 MM


PP12V_G3H

=PP12V_S0_FAN

=PP5V_S0_SATA

=PP3V3_S3_LED

MAKE_BASE=TRUEVOLTAGE=5VMIN_LINE_WIDTH=0.5 mm

NET_SPACING_TYPE=POWERMIN_NECK_WIDTH=0.2 MM


PP5V_S0

PP1V5_S3_MEM_SNS


VOLTAGE=1.5VMAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm


PP1V5_S3_MEM

=PP3V3_S3_SDCARD

=PP3V3_S3_ENET_PHY

=PP3V3_S3_USB_HUB

=PP3V3_S3_PWRCTL

=PP3V3_S3_SMBUS_SMC_A

=PP3V3_S0_AUDIO

=PP3V3_S5_ROM


=PP3V3_S5_P3V3R2V9_A

MAKE_BASE=TRUE


VOLTAGE=3.3VMIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.2MM


PP3V3_S5

=PP3V3_S5_SMCUSBMUX

=PP3V3R1V5_S5_PCH_VCCSUSHDA

=PP12V_S0_FW

NET_SPACING_TYPE=POWERMIN_NECK_WIDTH=0.5mmMIN_LINE_WIDTH=1mmVOLTAGE=12V


MAKE_BASE=TRUEPP12V_S0


=PP1V05_S0_PCH_VCCIO_DMI

=PP1V05_S0_PCH_VCCIO_USB

=PPVCCSA_S0_CPU



MAKE_BASE=TRUE



VOLTAGE=3.3V

PP3V3_S0

=PP1V5_S0_MINI

PPVTT_S0_DDR_LDO

MAKE_BASE=TRUE



VOLTAGE=1.8V



PP1V8_S0

=PP3V3_S0_SMBUS_SMC_B

=PP3V3_S0_SMBUS_SMC_MGMT


PPVTT_S0_DDR

MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE


VOLTAGE=0.75V

PP12V_G3H_ACDC

PP12V_S0_PS

PS_ON

BL_PWM

BL_EN

SMB_ACDC_SCL_RC

ISOLATED_GND2

=SMB_ACDC_SDA

PM_EN_P12V_S0_FET

=SMB_ACDC_SCL

SMB_BLC_PCH_SDA_R

ISOLATED_GND

VSYNC_DP_CONN_R

BLC_GPIO_R

VSYNC_DP_CONN

BLC_GPIO

=SMB_BLC_PCH_SCL=PP3V3_G3H_RTC_D

=PP12V_S5_DDR_VREG

=PP3V3_S5_LED

=PP3V3_S5_USB_HUB

=PP3V3_S5_PCH_VCCDSW

=PP3V3_S5_LPCPLUS

=PP3V3_S5_XDP

=PP3V3_S5_S0FET

=PP3V3_S5_PWRCTL

SMB_BLC_TCON_SCL

=PP1V5_S0_DP

=PPVAXG_S0_CPU

SMB_BLC_TCON_SCL_R

SMB_BLC_TCON_SDA_RSMB_BLC_TCON_SDA

SMB_BLC_PCH_SCL_R

=PP3V3_S0_CK505

PP1V5_S0_CPU_MEM_SNSPP1V5_S0_CPU_MEM




=SMB_BLC_PCH_SDA

=PP3V3_S0_SMBUS

SMB_ACDC_SDA_RC

VOLTAGE=0.925V


MAKE_BASE=TRUE



PPVCCSA_S0_CPU PPVCCSA_S0_FET


=PPSPD_S0_MEM_A

=PP3V3_S0_PCH_VCCADAC

=PP3V3_S0_FAN

=PP5V_S3_S0FET

=PP5V_S3_USB

PP5V_S3_REG

=PP3V3_S3_SYSCLK

=PP3V3_S3_MINI

=PP3V3_S3_BT

PP3V3_S3_FET

=PP1V5_S3_MEM_B

=PP1V5_S3_MEM_A

=PP3V3_S3_P3V3R2V9_REG_A

=PP3V3_S3_PCH



MAKE_BASE=TRUE


PP3V3_S3

6 OF 110

11.1.0

051-8115

6 OF 98

48

43

46 47

72

82

33 64 73

70

74 95

70

24

95

95

95

27

22 24

47 51

6 49

36 37

49

81

22 24

27

68

22 24

71

28

84

83

26

18 42

22 24

95

50

73

56

64

69

50 95

80

80

5

65 68

45

49

11 27

22 24

15

20 45

39 40 41

63 64 73 80

50 52

42

21 64 75 76

49

31

18 21 24

73

11 13 16 28 29

95

68

50

6

48

82

28

71

32

44

44

95 98

69

32

18 19 21 24

20

22 24

73

70

70

95

18 22 24

18 19 22 24

22 24

69

50

75

51

63 64 80

68

81

65

58 59

78

32

17

95

10 11 13 16 65

25

50

71

95

22 24

18 24 79

19

71

66

32

50

22 24

13 16

30

13 16 50 65

50 69 68

24

22 24

50

24 79

64

71

95

22 24

95

42

67

79 80 86 87

74

22 24

31

32

95

75

56

65 67

80

87

80

95

46 47

73

80

22 24

50

50

26

6

95

32

73

72

95

53 54

42

5

95 98

50 95

44 45

36

34 35

64 73 82

49

56 58 59 60 61 62

48 55

15

82

95

43

24

41

95

80

22 24

22 24

13 50

95

33

71

95

49

49

95

6

6

83 97

81 97

27

71

5

34

22 24

48

25

73

11 63 64

83

13 17 50 65

26

50 95

6 49

95 69

24

30 47

17

53 54

73

43

70

79

33

44

73

28 29 31

28 29 30

82

21

95 98

www.vinafix.vn

REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD

QTY DESCRIPTIONPART#TABLE_5_ITEM




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

MXM STANDOFFS (835-0272)

Rear Cover

Standoffs (was 860-1255 but now replaced with 860-1430)

4mm Plated Holes (998-0850)

DIMM CONNECTOR NUTS

Nuts (805-9582)

CPU Heatsink

PCH HEATSINK

MOUNTING HOLES (998-0873, 998-0976)

EMC Spring (870-1577); Near DIMMs

For EMC

1

ZH0700OMIT

4P75R41

ZH0701OMIT

4P75R41

ZH0702OMIT

4P75R41

ZH0703OMIT

4P75R4

1SC0702

NOSTUFF

EMI-SPRINGCLIP-SM-K2

1

SDF0713CRITICAL

STDOFF-6.8OD15.0H-1.56-TH

OMIT_TABLE

1

NUT0753CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

1

NUT0752CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

1

NUT0751CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

1

NUT0750CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

1

SDF0714CRITICAL


OMIT_TABLE

1

SDF0715CRITICAL


OMIT_TABLE

1

SDF0717CRITICAL


OMIT_TABLE

1

SDF0718CRITICAL


OMIT_TABLE

1

ZH0711OMIT

5P45R3P61

ZH07125P45R3P6

OMIT

1

SDF0721CRITICAL

NUT-6.5OD2.7H-1.56-3.8-TH

1

SDF0720NUT-6.5OD2.7H-1.56-3.8-TH

CRITICAL

HolesSYNC_MASTER=K74_MASTER SYNC_DATE=N/A

STANDOFF,MLB,K60/K62860-1430 5 SDF0713,SDF0714,SDF0715,SDF0717,SDF0718

7 OF 110

11.1.0

051-8115

7 OF 98

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36

BRANCH

REVISION

DRAWING NUMBER SIZE

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SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NC ON UNUSED PCI ALIASES

UNUSED CPU SIGNALS

NC ON UNUSED MISC ALIASES

NC ON UNUSED FDI ALIASES

NC ON UNUSED MEM ALIASES

NC ON UNUSED DISPLAY ALIASES

NC ON UNUSED USB ALIASES

NC ON UNUSED SATA ALIASES

NC ON UNUSED PCIE ALIASES

SYNC_DATE=01/06/2011

UNUSED SIGNAL ALIASSYNC_MASTER=K62

TP_CRT_IG_HSYNC

NC_DP_IG_C_AUXNNO_TEST=TRUEMAKE_BASE=TRUE

TP_DP_IG_C_HPD

TP_SATA_E_R2D_CN

TP_SATA_D_D2RN

TP_SATA_F_D2RN

NC_PE_RXN<3..0>NO_TEST=TRUEMAKE_BASE=TRUE

TP_DP_IG_B_MLN<3..0>

TP_DP_IG_B_MLP<3..0>

TP_DP_IG_B_AUX_N

TP_DP_IG_B_AUX_P

MAKE_BASE=TRUE NO_TEST=TRUENC_DP_IG_B_HPD

MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_CLK100M_PE5N

MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_R2D_PETP4

TP_PCIE_D2R_PERP4

TP_PCIE_R2D_PETP4

TP_PCIE_R2D_PETN4 NC_PCIE_R2D_PETN4NO_TEST=TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_D2R_PERN4

NO_TEST=TRUEMAKE_BASE=TRUENC_PCIE_D2R_PERP4

TP_USB_13NMAKE_BASE=TRUENC_USB_13N

NO_TEST=TRUETP_USB_13P

MAKE_BASE=TRUENC_USB_13P

NO_TEST=TRUE

TP_USB_12P NC_USB_12PMAKE_BASE=TRUE NO_TEST=TRUE

TP_USB_12N NC_USB_12NNO_TEST=TRUEMAKE_BASE=TRUE

TP_USB_11PNO_TEST=TRUE

NC_USB_11PMAKE_BASE=TRUE

TP_USB_11NMAKE_BASE=TRUENC_USB_11N

NO_TEST=TRUE

TP_USB_10N NC_USB_10NMAKE_BASE=TRUE NO_TEST=TRUE

TP_USB_10P NC_USB_10PMAKE_BASE=TRUE NO_TEST=TRUE

TP_USB_7NMAKE_BASE=TRUE NO_TEST=TRUENC_USB_7N

TP_USB_7PNO_TEST=TRUEMAKE_BASE=TRUE

NC_USB_7P




TP_USB_5N NC_USB_5NMAKE_BASE=TRUE NO_TEST=TRUE




NC_USB_4P


NC_USB_3P

TP_USB_4NNO_TEST=TRUEMAKE_BASE=TRUE

NC_USB_4N

TP_USB_3N NC_USB_3NNO_TEST=TRUEMAKE_BASE=TRUE






TP_USB_1NNO_TEST=TRUE

NC_USB_1NMAKE_BASE=TRUE

TP_CRT_IG_BLUE

TP_PCI_RESET_LMAKE_BASE=TRUENC_PCI_RESET_L

NO_TEST=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_PCI_AD<31..0>

NC_PCI_PARNO_TEST=TRUEMAKE_BASE=TRUE

TP_DP_IG_B_DDC_DATA

MAKE_BASE=TRUENC_MEM_A_DQ_CB<7..0>

NO_TEST=TRUE

TP_PE_RX_N<3..0>

NC_PE_TXN<3..0>NO_TEST=TRUEMAKE_BASE=TRUE

TP_DP_IG_C_CTRL_CLK

TP_PCH_FDI_RX_P<7..0>

NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_B_MLP<3..0>

NO_TEST=TRUENC_DP_IG_B_AUXNMAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_CRT_IG_VSYNC

NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_B_MLN<3..0>

TP_PCI_C_BE_L<3..0>

TP_PCH_L_BKLTCTL

TP_PCH_L_BKLTEN

TP_PCH_L_VDD_EN

TP_SDVO_TVCLKINN

NC_SDVO_TVCLKINPNO_TEST=TRUEMAKE_BASE=TRUE

TP_PCH_FDI_RX_N<7..0>

TP_CPU_FDI_TX_N<7..0>

MAKE_BASE=TRUE NO_TEST=TRUENC_SATA_D_D2RN

NC_PCH_FDI_RXN<7..0>MAKE_BASE=TRUE NO_TEST=TRUE

NC_PCIE_CLK100M_PE7NNO_TEST=TRUEMAKE_BASE=TRUE

NO_TEST=TRUENC_PCIE_CLK100M_PE7PMAKE_BASE=TRUE

TP_DP_IG_B_HPD

TP_DP_IG_C_AUX_N

TP_CRT_IG_DDC_DATA

TP_MEM_A_DQS_N<8>MAKE_BASE=TRUENC_MEM_A_DQSN<8>

NO_TEST=TRUE

TP_MEM_A_DQ_CB<7..0>

MAKE_BASE=TRUENC_PCH_CL_RST1

NO_TEST=TRUE

TP_PCH_SST

TP_PCH_PWM2

MAKE_BASE=TRUENC_PCH_L_BKLTEN

NO_TEST=TRUE

TP_PCH_CLKOUT_DPN

TP_PCH_CLKOUT_DPP

NC_PCH_CLKOUT_DPNMAKE_BASE=TRUE NO_TEST=TRUE

NC_PCH_CLKOUT_DPPNO_TEST=TRUEMAKE_BASE=TRUE

NC_PCH_L_VDD_ENNO_TEST=TRUEMAKE_BASE=TRUE

TP_SATA_E_R2D_CP

TP_SATA_F_R2D_CN

TP_SATA_F_R2D_CPMAKE_BASE=TRUE NO_TEST=TRUENC_DP_IG_D_MLN<3..0>

NO_TEST=TRUEMAKE_BASE=TRUENC_SATA_F_D2RN

NO_TEST=TRUEMAKE_BASE=TRUENC_SATA_E_R2D_CP

NC_SATA_E_R2D_CNNO_TEST=TRUEMAKE_BASE=TRUE

NC_SATA_E_D2RPMAKE_BASE=TRUE NO_TEST=TRUE

NC_SATA_D_R2D_CPNO_TEST=TRUEMAKE_BASE=TRUE

NO_TEST=TRUENC_SATA_D_R2D_CNMAKE_BASE=TRUE

MAKE_BASE=TRUENC_SATA_E_D2RN

NO_TEST=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_SATA_D_D2RP

TP_SATA_E_D2RP

TP_SATA_D_D2RP

TP_SATA_E_D2RN

TP_SATA_D_R2D_CP

TP_SATA_D_R2D_CN

TP_SATA_F_D2RP

NO_TEST=TRUEMAKE_BASE=TRUENC_PCH_FDI_RXP<7..0>

TP_CPU_FDI_TX_P<7..0>

NC_CPU_FDI_TXN<7..0>NO_TEST=TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUENC_SDVO_TVCLKINN

NO_TEST=TRUE

NC_DP_IG_D_CTRL_CLKNO_TEST=TRUEMAKE_BASE=TRUE

NC_DP_IG_D_AUXNMAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUENC_DP_IG_D_MLP<3..0>

NO_TEST=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_C_CTRL_DATA

NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_C_HPD

NC_DP_IG_B_CTRL_DATAMAKE_BASE=TRUE NO_TEST=TRUE

NC_DP_IG_B_CTRL_CLKNO_TEST=TRUEMAKE_BASE=TRUE

NC_CRT_IG_HSYNCNO_TEST=TRUEMAKE_BASE=TRUE

NC_CRT_IG_BLUEMAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUENC_CRT_IG_GREEN

NO_TEST=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_CRT_IG_DDC_DATA

TP_CRT_IG_RED

TP_MEM_B_DQS_P<8>

NC_HDA_SDIN1MAKE_BASE=TRUE NO_TEST=TRUE

TP_DP_IG_D_HPD

TP_DP_IG_D_CTRL_DATA

TP_SDVO_STALLN

TP_DP_IG_D_MLP<3..0>

TP_DP_IG_C_CTRL_DATA

TP_DP_IG_C_AUX_P

TP_DP_IG_C_MLP<3..0>

TP_DP_IG_C_MLN<3..0>

TP_DP_IG_B_DDC_CLK

TP_CRT_IG_VSYNC

NO_TEST=TRUENC_PCH_PWM0MAKE_BASE=TRUE

NC_HDA_SDIN3MAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUENC_HDA_SDIN2

NO_TEST=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_MEM_B_DQSP<8>MAKE_BASE=TRUE NO_TEST=TRUENC_MEM_B_DQSN<8>TP_MEM_B_DQS_N<8>

NC_MEM_B_DQ_CB<7..0>MAKE_BASE=TRUE NO_TEST=TRUE

NC_MEM_A_DQSP<8>MAKE_BASE=TRUE NO_TEST=TRUE

TP_MEM_A_DQS_P<8>

TP_PCH_PWM1

TP_HDA_SDIN1

TP_MEM_B_DQ_CB<7..0>

TP_HDA_SDIN3

TP_HDA_SDIN2

NC_SATA_F_D2RPNO_TEST=TRUEMAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_D_CTRL_DATA

NC_SATA_F_R2D_CPMAKE_BASE=TRUE NO_TEST=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_SATA_F_R2D_CN

NC_DP_IG_D_HPDMAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUENC_DP_IG_C_AUXP

NO_TEST=TRUE

MAKE_BASE=TRUENC_DP_IG_C_MLN<3..0>

NO_TEST=TRUE

MAKE_BASE=TRUENC_CPU_FDI_TXP<7..0>

NO_TEST=TRUE

NC_DP_IG_C_MLP<3..0>MAKE_BASE=TRUE NO_TEST=TRUE

TP_DP_IG_D_CTRL_CLK

TP_DP_IG_D_AUXP

MAKE_BASE=TRUENC_DP_IG_C_CTRL_CLK

NO_TEST=TRUE

NC_DP_IG_D_AUXPMAKE_BASE=TRUE NO_TEST=TRUE

NO_TEST=TRUENC_SDVO_STALLNMAKE_BASE=TRUE

TP_SDVO_INTP

TP_SDVO_INTN

TP_SDVO_STALLP

MAKE_BASE=TRUENC_SDVO_INTP

NO_TEST=TRUE

NO_TEST=TRUENC_SDVO_INTNMAKE_BASE=TRUE

NC_PCH_L_BKLTCTLMAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUENC_DP_IG_B_AUXP

NO_TEST=TRUE

TP_DP_IG_D_AUXN

NC_SDVO_STALLPMAKE_BASE=TRUE NO_TEST=TRUE

TP_PCH_PWM3

NO_TEST=TRUENC_PCH_SSTMAKE_BASE=TRUE

NO_TEST=TRUENC_PCH_PWM3MAKE_BASE=TRUE

TP_PCH_CL_DATA1

TP_PCH_CL_RST1

NO_TEST=TRUEMAKE_BASE=TRUENC_PCH_PWM2

MAKE_BASE=TRUENC_PCH_PWM1

NO_TEST=TRUE

TP_PCH_PWM0

NC_PCH_CL_DATA1NO_TEST=TRUEMAKE_BASE=TRUE

TP_PCH_CL_CLK1 NC_PCH_CL_CLK1NO_TEST=TRUEMAKE_BASE=TRUE

TP_PCI_AD<31..0>

TP_LPC_DREQ0_L

NO_TEST=TRUEMAKE_BASE=TRUENC_CRT_IG_DDC_CLK

TP_DP_IG_D_MLN<3..0>

TP_CRT_IG_DDC_CLK

MAKE_BASE=TRUE NO_TEST=TRUENC_PE_RXP<3..0>TP_PE_RX_P<3..0>

TP_PE_TX_N<3..0>

NC_PE_TXP<3..0>NO_TEST=TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUENC_CRT_IG_RED

NO_TEST=TRUE

NO_TEST=TRUENC_PCI_C_BE_L<3..0>MAKE_BASE=TRUE

TP_SDVO_TVCLKINP

TP_CRT_IG_GREEN

TP_PCIE_CLK100M_PE5P

TP_PCIE_CLK100M_PE5N



NO_TEST=TRUENC_PCIE_CLK100M_PE5PMAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_PCIE_CLK100M_PE6P



NC_PCIE_CLK100M_PE4PMAKE_BASE=TRUE NO_TEST=TRUE





TP_CPU_RSVD<46..19>

TP_CPU_RSVD<16..1>NO_TEST=TRUEMAKE_BASE=TRUE

NC_CPU_RSVD<16..1>

MAKE_BASE=TRUE NO_TEST=TRUENC_CPU_RSVD<46..19>

TP_PCI_PAR

NO_TEST=TRUEMAKE_BASE=TRUENC_LPC_DREQ0_L

TP_PCIE_D2R_PERN4

TP_PE_TX_P<3..0>

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11.1.0

051-8115

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19

19

18

18

18

19

19

19

19

18

18

18

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

19

20

19

10

19

19

20

18

18

18

19

19

10

19

19

19

12

12

21

21

18

18

18

18

18

18

18

18

18

18

18

10

19

12

19

19

19

19

19

19

19

19

19

19

12

12

21

18

12

18

18

19

19

19

19

19

19

21

18

18

21

18

20

18

19

19

10

10

19

19

18

18

21

21

18

18

21

21

10

10

20

18

10

www.vinafix.vn

OUT

OUTIN

IN

IN

IN

OUT

OUT

IN

IN

IN OUT

OUTIN

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

THIS SIGNAL NAME IS CONNECTED TO MXM

PEG Slot Support

77 90

77 90 10

10

77 90

77 90

10

10

18

18

19 91 97 21

R929

PLACEMENT_NOTE=PLACE CLOSE TO U18001/16W5%

MF-LF

22

402

46 91 97

75 97 21

75

75

SYNC_DATE=01/06/2011SYNC_MASTER=K62

Signal Aliases

CLK_100M_MXM_P

MAKE_BASE=TRUEPEG_RESET_LMXM_RESET_L

PEG_CLK100M_P

PM_CLK32K_SUSCLK_R PM_CLK32K_SUSCLK

=PEG_D2R_P<0..15>MAKE_BASE=TRUEPEG_D2R_P<0..15>

=PEG_R2D_C_N<0..15>

=PEG_D2R_N<0..15>

MAKE_BASE=TRUEMXM_CLKREQ_LPEG_CLKREQ_L

=PEG_R2D_C_P<0..15>MAKE_BASE=TRUEGPU_CLK100M_PCIE_N

MAKE_BASE=TRUEPEG_R2D_C_P<0..15>

MAKE_BASE=TRUEPEG_R2D_C_N<0..15>

CLK_100M_MXM_N

MAKE_BASE=TRUEPEG_D2R_N<0..15>

GPU_CLK100M_PCIE_PMAKE_BASE=TRUE

PEG_CLK100M_N

9 OF 110

11.1.0

051-8115

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27 97 75

90

90

www.vinafix.vn

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

PEG_TX_6*

PEG_RX_5*

PEG_RX_0*

PEG_RX_2*

PEG_RX_7*

PEG_RX_8*

PEG_RX_9*

PEG_RX_10*

PEG_RCOMPO

PEG_RX_14

PEG_RX_13

PEG_RX_6*

PEG_RX_12*

PEG_RX_14*

PEG_RX_1

PEG_ICOMPO

PEG_COMPI

FDI_INT

FDI_ICOMPO

FDI_COMPIO

DMI_RX_0

DMI_RX_0*

DMI_RX_1

DMI_RX_1*

DMI_RX_2

DMI_RX_2*

DMI_RX_3

DMI_RX_3*

DMI_TX_0

DMI_TX_0*

DMI_TX_1

DMI_TX_2

DMI_TX_2*

DMI_TX_3

DMI_TX_3*

FDI_FSYNC_0

FDI_FSYNC_1

FDI_LSYNC_0

FDI_LSYNC_1

FDI_TX_0

FDI_TX_0*

FDI_TX_1

FDI_TX_1*

FDI_TX_2

FDI_TX_2*

FDI_TX_3

FDI_TX_3*

FDI_TX_4

FDI_TX_4*

FDI_TX_5

FDI_TX_5*

FDI_TX_6

FDI_TX_6*

FDI_TX_7

FDI_TX_7*

PEG_RX_0

PEG_RX_1*

PEG_RX_2

PEG_RX_3

PEG_RX_3*

PEG_RX_4

PEG_RX_4*

PEG_RX_5

PEG_RX_6

PEG_RX_7

PEG_RX_8

PEG_RX_9

PEG_RX_10

PEG_RX_11

PEG_RX_11*

PEG_RX_12

PEG_RX_13*

PEG_RX_15

PEG_RX_15*

PEG_TX_0

PEG_TX_0*

PEG_TX_1

PEG_TX_1*

PEG_TX_2

PEG_TX_2*

PEG_TX_3

PEG_TX_3*

PEG_TX_4

PEG_TX_4*

PEG_TX_5

PEG_TX_5*

PEG_TX_6

PEG_TX_7

PEG_TX_7*

PEG_TX_8

PEG_TX_8*

PEG_TX_9

PEG_TX_9*

PEG_TX_10

PEG_TX_10*

PEG_TX_11

PEG_TX_11*

PEG_TX_12

PEG_TX_12*

PEG_TX_13

PEG_TX_13*

PEG_TX_14

PEG_TX_14*

PEG_TX_15

PEG_TX_15*

PE_RX_0

PE_RX_0*

PE_RX_1

PE_RX_1*

PE_RX_2

PE_RX_2*

PE_RX_3

PE_RX_3*

PE_TX_0

PE_TX_0*

PE_TX_1

PE_TX_1*

PE_TX_2

PE_TX_2*

PE_TX_3

PE_TX_3*

DMI_TX_1*

PCI EXPRESS

DMI

FLEXIBLE DISPLAY INTERFACE

(1 OF 10)

PCI EXPRESS -- GRAPHICS

RSVD_C39

RSVD_D38

RSVD_C38

RSVD_H7

RSVD_H8

RSVD_J9

RSVD_AY10

RSVD_AW34

RSVD_AV34

RSVD_AU10

RSVD_AT14

RSVD_AT11

RSVD_AP20

RSVD_AN20

RSVD_AJ31

RSVD_AJ30

RSVD_AJ29

RSVD_AJ11

RSVD_AG4

RSVD_AF4

RSVD_AE6

RSVD_AD37

RSVD_AD35

RSVD_AD34

RSVD_AB7

RSVD_AB6

RSVD_R40

RSVD_R38

RSVD_R36

RSVD_R34

RSVD_P39

RSVD_P37

RSVD_P35

RSVD_N34

RSVD_N33

RSVD_M34

RSVD_L34

RSVD_L33

RSVD_L31

RSVD_L9

RSVD_K34

RSVD_K31

RSVD_K9

CFG_17

CFG_16

CFG_15

CFG_14

CFG_13

CFG_12

CFG_11

CFG_10

CFG_9

CFG_7

CFG_6

CFG_5

CFG_4

CFG_3

CFG_2

CFG_1

CFG_0

RSVD_J31

RSVD_J33

RSVD_J34

CFG_8

NCTF_A38

NCTF_C2

NCTF_D1

NCTF_AU40

NCTF_AW38

RSVD_NCTF_B39

RSVD_NCTF_AY3

RSVD_NCTF_AW2

RSVD_NCTF_AV1

RESERVED

(5 OF 10)

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(Unused)

ThermDC

ThermDA

SHORT B4 & C4 TOGETHER, ROUTE AS A SINGLE 4 MIL TRACE TO R1010.1

ROUTE B5 TO R1010.1 AS A SEPERATE 10 MIL TRACE.

FOR SANDYBRIDGE PROCESSOR

CFG [6:5] :PCIE CONFIGURATION SELECT 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

INTEL SUGGESTS TO KEEP THESE TPS

CFG [2] :PCIE LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

(Available for Workstation only)

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

21

R1010

MF-LF

1%1/16W

24.9

402

PLACEMENT_NOTE=Place within 12.7MM of CPU

15 25 90

15 25 90

25 90

25 90

25 90

25 90

25 90

25 90

25 90

25 90

25 90

15 25 90

15 25 90

25 90

15 25 90

15 25 90

15 25 90

25 90

G9

G10

F7

F8

E5

E6

C3

D3

D7

D8

J13

J14

F11

F12

G13

G14

N6

N5

L5

L6

M7

M8

J6

J5

K8

K7

G6

G5

E13

E14

C14

C13

G1

G2

F3

F4

E1

E2

A6

A5

C5

C6

B7

B8

E9

E10

C9

C10

N2

N1

M4

M3

L2

L1

K4

K3

J2

J1

H4

H3

D11

D12

B12

B11

C4

B5

B4

U6

U5

R5

R6

T8

T7

P7

P8

U1

U2

T3

T4

R1

R2

P4

P3

AG1

AG2

AF2

AF3

AE8

AE7

AD6

AD7

AD3

AD4

AD1

AD2

AC3

AC2

AC7

AC8

AE4

AC4

AG3

AE1

AE5

AC5

AE2

AA8

AA7

Y7

Y6

W8

W7

V6

V7

AA5

AA4

Y4

Y3

V4

V3

W4

W5

U1000LGA1155-SKT

SANDY_BRIDGE

OMIT

R40

R38

R36

R34

P39

P37

P35

B39

AY3

AW2

AV1

N34

N33

M34

L9

L34

L33

L31

K9

K34

K31

J9

J34

J33

J31

H8

H7

D38

C39

C38

AY10

AW34

AV34

AU10

AT14

AT11

AP20

AN20

AJ31

AJ30

AJ29

AJ11

AG4

AF4

AE6

AD37

AD35

AD34

AB7

AB6

D1

C2

AW38

AU40

A38

L35

J38

M36

L37

N35

L36

K36

J37

G36

G37

N40

N37

N39

N38

N36

M38

J36

H36

U1000SANDY_BRIDGE

LGA1155-SKT

OMIT

52 94

52 94

2

1R1011

PLACEMENT_NOTE=Place within 12.7MM of CPU

402

1/16WMF-LF

5%0

CPU DMI/PEG/FDI/RSVD

TP_CPU_FDI_TX_P<6>TP_CPU_RSVD_NCTF<3>

TP_CPU_NCTF<2>

TP_CPU_NCTF<3>

CPU_CFG<6>

CPU_CFG<5>

=PEG_R2D_C_P<6>

=PEG_R2D_C_P<8>

DMI_N2S_N<0>

TP_CPU_FDI_TX_N<6>

TP_CPU_FDI_TX_N<4>

DMI_S2N_P<2>

DMI_S2N_P<3>

CPU_FDI_LSYNC<0>

TP_PE_RX_N<1>

TP_PE_TX_P<1>

TP_PE_TX_N<1>

TP_PE_RX_P<3>

TP_PE_RX_P<2>

TP_PE_RX_P<1>

CPU_FDI_INT

DMI_S2N_N<0>

DMI_S2N_P<1>

DMI_S2N_P<0>

TP_PE_TX_P<2>

TP_PE_TX_N<3>

CPU_CFG<8>

=PEG_R2D_C_P<3>

TP_CPU_RSVD<8>

CPU_CFG<13>

CPU_CFG<9>

TP_CPU_RSVD<35>

CPU_CFG<11>

TP_CPU_RSVD<36>

TP_PE_TX_N<2>

TP_PE_TX_N<0>

TP_PE_RX_P<0>

=PEG_R2D_C_N<9>

TP_CPU_FDI_TX_P<2>

TP_CPU_FDI_TX_P<1>

TP_CPU_FDI_TX_P<0>

CPU_FDI_FSYNC<1>

DMI_N2S_P<1>

CPU_FDI_LSYNC<1>

=PEG_R2D_C_P<11>

=PEG_R2D_C_P<13>

TP_CPU_RSVD<38>

TP_CPU_RSVD<5>

TP_CPU_RSVD<28>

TP_CPU_RSVD<21>

TP_CPU_RSVD<10>

CPU_CFG<12>

TP_CPU_NCTF<4>

TP_CPU_RSVD<41>

TP_CPU_RSVD<39>

CPU_CFG<1>

TP_CPU_RSVD<23>

CPU_CFG<10>

TP_CPU_RSVD<40>

TP_CPU_RSVD<20>

TP_CPU_RSVD<34>

TP_CPU_RSVD<37>

TP_CPU_RSVD<16>

TP_CPU_RSVD<15>

TP_CPU_RSVD<14>

SNS_CPU_THERMD_N

SNS_CPU_THERMD_P

TP_CPU_FDI_TX_N<7>

TP_CPU_RSVD<25>

TP_CPU_RSVD<26>

TP_CPU_FDI_TX_N<1>

=PEG_R2D_C_P<5>

=PEG_R2D_C_N<11>

TP_CPU_FDI_TX_N<2>

DMI_S2N_N<3>

TP_CPU_FDI_TX_P<5>

TP_CPU_FDI_TX_N<5>

DMI_N2S_P<2>

TP_PE_TX_P<3>

=PEG_R2D_C_P<1>

=PEG_R2D_C_P<9>

TP_PE_RX_N<3>

TP_PE_RX_N<2>

TP_CPU_RSVD<22>

=PEG_D2R_P<9>

TP_CPU_FDI_TX_N<0>

TP_CPU_FDI_TX_P<7>

CPU_FDI_FSYNC<0>

TP_PE_RX_N<0>

TP_PE_TX_P<0>

TP_CPU_RSVD<29>

TP_CPU_RSVD<27>

TP_CPU_RSVD<33>

TP_CPU_RSVD<19>

TP_CPU_RSVD<32>

TP_CPU_RSVD<31>

DMI_N2S_P<0>

DMI_N2S_N<1>

DMI_N2S_N<2>

TP_CPU_RSVD<9>

CPU_CFG<17>

=PEG_R2D_C_P<2>

TP_CPU_RSVD<46>

TP_CPU_RSVD<45>

TP_CPU_RSVD<43>

TP_CPU_RSVD<42>

TP_CPU_RSVD_NCTF<1>

TP_CPU_NCTF<5>

TP_CPU_FDI_TX_N<3>


NET_SPACING_TYPE=CPU_RCOMPMIN_NECK_WIDTH=0.2MM

CPU_FDI_COMPIO

=PEG_R2D_C_N<6>

=PEG_R2D_C_P<15>

=PEG_R2D_C_P<14>

=PEG_R2D_C_P<12>

=PEG_R2D_C_P<7>

=PEG_R2D_C_N<10>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<7>

=PEG_D2R_P<10>

=PEG_D2R_P<6>

=PEG_R2D_C_P<4>

=PEG_D2R_P<3>

=PEG_R2D_C_N<2>

=PEG_D2R_N<14>

DMI_S2N_N<2>

DMI_S2N_N<1>

DMI_N2S_N<3>

=PEG_R2D_C_N<4>

=PEG_R2D_C_N<1>

TP_CPU_FDI_TX_P<4>

DMI_N2S_P<3>

=PEG_D2R_P<1>

=PEG_D2R_P<4>

=PEG_D2R_N<13>

=PEG_D2R_N<11>

=PEG_D2R_N<1>

=PEG_D2R_P<8>

=PEG_D2R_N<4>

=PEG_D2R_N<3>

=PEG_D2R_N<6>

=PEG_D2R_N<5>

=PEG_D2R_P<0>

=PEG_D2R_N<15>

=PEG_R2D_C_N<0>

=PEG_D2R_P<15>

=PEG_D2R_P<14>

=PEG_D2R_P<12>

=PEG_D2R_P<11>

=PEG_R2D_C_P<10>

=PEG_R2D_C_P<0>

=PEG_R2D_C_N<15>

=PEG_R2D_C_N<14>

=PEG_R2D_C_N<13>

=PEG_R2D_C_N<12>

=PEG_D2R_N<12>

=PEG_D2R_N<8>

=PEG_D2R_N<7>

CPU_PEG_COMP

NET_SPACING_TYPE=CPU_RCOMPMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM

=PEG_D2R_N<0>

=PEG_D2R_N<2>

TP_CPU_RSVD<13>

TP_CPU_RSVD<12>

TP_CPU_RSVD<11>

TP_CPU_RSVD<7>

TP_CPU_RSVD<30>

TP_CPU_RSVD<2>

=PPVCCIO_S0_CPU

=PEG_D2R_P<2>

=PEG_D2R_P<7>

=PEG_D2R_P<5>

TP_CPU_RSVD_NCTF<2>

TP_CPU_RSVD_NCTF<4>

TP_CPU_NCTF<1>

CPU_CFG<16>

CPU_CFG<15>

CPU_CFG<14>

CPU_CFG<7>

CPU_CFG<3>

CPU_CFG<2>

CPU_CFG<0>

CPU_CFG<4> TP_CPU_RSVD<44>

=PEG_D2R_N<10>

=PEG_D2R_N<9>

TP_CPU_RSVD<6>

TP_CPU_RSVD<4>

TP_CPU_RSVD<3>

TP_CPU_RSVD<1>

TP_CPU_RSVD<24>

=PEG_D2R_P<13>

TP_CPU_FDI_TX_P<3>

=PEG_R2D_C_N<3>

=PEG_R2D_C_N<5>

10 OF 110

11.1.0

051-8115

10 OF 98

8

8

8

15

8

8

8

8

8

8

15

8

8

8

8

8

8

8

8

8

8

8

15

15

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

15

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

90

8

8

8

8

8

8

6 11 13 16 65

8

8

8

8

8

8

8

www.vinafix.vn

BI

BI

BI

BI

BI

IN

IN

OUT

IN

IN

OUT

OUT

BI

BI

G

D

S

IN

NC

IN

IN

OUT

IN

IN

IN

OUT

IN

IN

IN

IN

IN

FC_AH4

FC_AH1

SM_VREF

SM_DRAMRST*

SM_DRAMPWROK

PM_SYNC

PREQ*

TMS

TRST*

TDI

TDO

DBR*

BPM[0]*

BPM[1]*

BPM[2]*

BPM[3]*

BPM[4]*

BPM[5]*

BPM[6]*

BPM[7]*

TCK

PRDY*

BCLK_ITP

BCLK_0

BCLK_ITP*

BCLK_0*

UNCOREPWRGOOD

SKTOCC*

RESET*

THERMTRIP*

CATERR*

PECI

PROCHOT*

PROC_SEL

THERMAL

DDR3 MISC

PWR MGMT

CLOCKS

(2 OF 10)

JTAG & BPM

OUT

OUT

BI

BI

BI




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PM_MEM_PWRGD MUST ASSERT MIN. 100ns AFTER =PP1V5_S0_CPU_MEM IS STABLE

CAN ADJUST R1190 AND C1180

OPEN-DRAIN BUFFER

FROM PCH

BASED ON INTEL MOBILE SOLUTION

25 90

25 90

25 90

25 90

25 90

2

1R1111

MF-LF1/16W

402

5%1K

28 89

21 25 97

2

1 C1111NOSTUFF

402

16VX5R

10%0.1UF

2

1C1110

16V

0.1UF

NOSTUFF

10%

X5R402

32 97

18 90

18 90

19 97

47 97

47 65 97

21 46 97

2

1R1126

1/16WMF-LF

402

NOSTUFF

5%0

2

1R1124PLACEMENT_NOTE=PLACE WITHIN 2 INCHES OF CPU

402

5%

MF-LF1/16W

75

2 1

R1121

1%

402MF-LF

121

1/16W

2

1R1120

402

2001%

1/16WMF-LF

1

2

6

Q1180SOT-563DMB53D0UV

19 97

2

1R11834.7K

402MF-LF1/16W5%

4

3

5 Q1180SOT-563DMB53D0UV

2

1C11800.015UF

16V

402

10%

X7R

2

1R1190

402

5%1/16WMF-LF

12K

4

5

3

2

U119074LVC1G07SC70

2

1C1190

402

20%10V

CERM

0.1UF

64 73 97

2

1R1101

MF-LF402

515%

1/16W

2

1R11001K

1/16W

402MF-LF

5%

NOSTUFF

25

25

25 90

25 90

25 90

25 90

25 90

18 90

18 90

19 97

2

1R1104

1/16W

402MF-LF

5%51

NOSTUFF

2 1

R1125

1/16WMF-LF402

5%

4327 97

J40

J39

L38

G35

L39

L40

M40

AJ22

AW18

AJ19

AJ33

F36

H34

K32

K40

K38

E38

J35

AH4

AH1

E39

E37

F40

E40

F38

G39

G40

G38

H38

H40

D40

C40

W1

W2

U1000SANDY_BRIDGE

LGA1155-SKT

OMIT

63 97

2

1R1102

402

NOSTUFF

1K

MF-LF

5%1/16W

25 97

25 90

25 90

25 90

CPU CLOCK/MISC/JTAG

ITPCPU_CLK100M_P

ITPCPU_CLK100M_N

DMI_CLK100M_CPU_P

DMI_CLK100M_CPU_N

XDP_CPU_PRDY_L

XDP_CPU_PREQ_L

XDP_CPU_TCK

XDP_CPU_TMS

XDP_CPU_TRST_L

XDP_CPU_TDI

XDP_CPU_TDO

XDP_DBRESET_L

XDP_BPM_L<0>

XDP_BPM_L<1>

XDP_BPM_L<2>

XDP_BPM_L<3>

XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_BPM_L<6>

XDP_BPM_L<7>

CPU_PROC_SEL

CPU_CATERR_L

CPU_SKTOCC_L

PM_SYNC

CPU_MEM_RESET_L

CPU_DDR_VREF

CPU_PECI

CPU_PROCHOT_L

CPU_THRMTRIP_L

CPU_PWRGD

CPU_RESET_L

PM_MEM_PWRGD_L

PM_PGOOD_P1V5_S0_FET

=PPVCCIO_S0_CPU

TP_CPU_DIMM_VREF_A

TP_CPU_DIMM_VREF_B

PLT_RESET_LS1V05_L

PGOOD_P1V5_S0_DLY

PM_MEM_PWRGD_R=PP1V5_S0_CPU_MEM

=PPVCCIO_S0_CPU

=PP3V3_S5_PWRCTL

=PP3V3_S0_RSTBUF

NO_TEST=TRUENC_U1190_P1

=PP3V3_S0_RSTBUF

PM_MEM_PWRGD

11 OF 110

11.1.0

051-8115

11 OF 98

1

97

97

6 10 11 13 16 65

97

97

97 6 13 16 28 29

6 10 11 13 16 65

6 63 64

6 11 27

6 11 27

www.vinafix.vn

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT OUT

DDR SYSTEM MEMORY A

(3 OF 10)

SA_ODT_3

SA_MA_9

SA_MA_8

SA_MA_7

SA_MA_6

SA_MA_5

SA_MA_4

SA_MA_3

SA_MA_2

SA_MA_15

SA_MA_14

SA_MA_13

SA_MA_12

SA_MA_11

SA_MA_10

SA_MA_1

SA_MA_0

SA_ECC_CB_7

SA_ECC_CB_6

SA_ECC_CB_5

SA_ECC_CB_4

SA_ECC_CB_3

SA_ECC_CB_2

SA_ECC_CB_1

SA_ECC_CB_0

SA_DQS_8

SA_DQS_7*

SA_DQS_7

SA_DQS_6*

SA_DQS_6

SA_DQS_5*

SA_DQS_5

SA_DQS_4*

SA_DQS_4

SA_DQS_3*

SA_DQS_3

SA_DQS_2*

SA_DQS_2

SA_DQS_1*

SA_DQS_1

SA_DQS_0*

SA_DQS_0

SA_DQ_8

SA_DQ_7

SA_DQ_6

SA_DQ_59

SA_DQ_58

SA_DQ_57

SA_DQ_56

SA_DQ_55

SA_DQ_54

SA_DQ_53

SA_DQ_52

SA_DQ_51

SA_DQ_50

SA_DQ_5

SA_DQ_49

SA_DQ_48

SA_DQ_47

SA_DQ_46

SA_DQ_45

SA_DQ_44

SA_DQ_43

SA_DQ_42

SA_DQ_41

SA_DQ_40

SA_DQ_4

SA_DQ_39

SA_DQ_38

SA_DQ_37

SA_DQ_36

SA_DQ_35

SA_DQ_34

SA_DQ_31

SA_DQ_30

SA_DQ_3

SA_DQ_29

SA_DQ_28

SA_DQ_27

SA_DQ_26

SA_DQ_25

SA_DQ_24

SA_DQ_23

SA_DQ_22

SA_DQ_21

SA_DQ_20

SA_DQ_2

SA_DQ_19

SA_DQ_18

SA_DQ_17

SA_DQ_16

SA_DQ_15

SA_DQ_14

SA_DQ_13

SA_DQ_12

SA_DQ_11

SA_DQ_10

SA_DQ_1

SA_DQ_0

SA_CS_3*

SA_CS_2*

SA_CS_1*

SA_CS_0*

SA_CKE_3

SA_CKE_2

SA_CKE_1

SA_CKE_0

SA_CK_3*

SA_CK_3

SA_CK_2*

SA_CK_2

SA_CK_1*

SA_CK_0*

SA_CK_0

SA_WE*

SA_RAS*

SA_ODT_0

SA_ODT_1

SA_ODT_2

SA_CK_1

SA_DQ_9

SA_DQ_60

SA_DQ_61

SA_DQ_62

SA_DQ_63

SA_BS_0

SA_BS_1

SA_CAS*

SA_BS_2

SA_DQS_8*

SA_DQ_33

SA_DQ_32

DDR SYSTEM MEMORY B

(4 OF 10)

SB_ODT_3

SB_ODT_2

SB_ODT_1

SB_ODT_0

SB_MA_9

SB_MA_8

SB_MA_7

SB_MA_6

SB_MA_5

SB_MA_4

SB_MA_3

SB_MA_2

SB_MA_15

SB_MA_14

SB_MA_13

SB_MA_12

SB_MA_11

SB_MA_10

SB_MA_1

SB_MA_0

SB_ECC_CB_7

SB_ECC_CB_6

SB_ECC_CB_5

SB_ECC_CB_4

SB_ECC_CB_3

SB_ECC_CB_2

SB_ECC_CB_1

SB_ECC_CB_0

SB_DQS_8

SB_DQS_7*

SB_DQS_7

SB_DQS_6*

SB_DQS_6

SB_DQS_5*

SB_DQS_5

SB_DQS_4*

SB_DQS_3

SB_DQS_2*

SB_DQS_1*

SB_DQS_1

SB_DQS_0*

SB_DQS_0

SB_DQ_9

SB_DQ_8

SB_DQ_7

SB_DQ_63

SB_DQ_62

SB_DQ_61

SB_DQ_60

SB_DQ_6

SB_DQ_59

SB_DQ_58

SB_DQ_57

SB_DQ_56

SB_DQ_55

SB_DQ_54

SB_DQ_53

SB_DQ_52

SB_DQ_51

SB_DQ_50

SB_DQ_5

SB_DQ_49

SB_DQ_48

SB_DQ_47

SB_DQ_46

SB_DQ_45

SB_DQ_44

SB_DQ_43

SB_DQ_42

SB_DQ_41

SB_DQ_40

SB_DQ_4

SB_DQ_39

SB_DQ_38

SB_DQ_37

SB_DQ_36

SB_DQ_35

SB_DQ_34

SB_DQ_32

SB_DQ_31

SB_DQ_30

SB_DQ_3

SB_DQ_29

SB_DQ_28

SB_DQ_27

SB_DQ_26

SB_DQ_25

SB_DQ_24

SB_DQ_23

SB_DQ_22

SB_DQ_21

SB_DQ_20

SB_DQ_2

SB_DQ_19

SB_DQ_18

SB_DQ_17

SB_DQ_16

SB_DQ_15

SB_DQ_14

SB_DQ_13

SB_DQ_12

SB_DQ_11

SB_DQ_10

SB_DQ_1

SB_DQ_0

SB_CKE_2

SB_CKE_1

SB_CKE_0

SB_CK_3*

SB_CK_3

SB_CK_2*

SB_CK_2

SB_CK_1

SB_CK_0*

SB_CK_0

SB_BS_2

SB_BS_1

SB_BS_0

SB_WE*

SB_RAS*

SB_CAS*

SB_CS_3*

SB_CS_2*

SB_CS_1*

SB_CS_0*

SB_CKE_3

SB_DQS_8*

SB_DQS_2

SB_DQS_4

SB_DQ_33

SB_DQS_3*

SB_CK_1*




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

30 89

30 89

30 89

30 89

30 89

30 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

30 89

30 89

30 89

30 89

30 89

30 89

30 89

30 89

30 89

30 89

30 89

30 89

30 89

30 89

30 89

32 89

32 89

30 89

32 89

32 89

30 89

30 89

30 89

30 89

30 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

31 89

31 89

31 89

31 89

31 89

31 89

32 89

32 89

31 89

32 89

32 89

31 89

31 89

31 89

31 89

31 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

32 89

31 89

31 89

31 89

31 89

31 89

31 89

31 89

31 89

31 89

31 89

31 89

31 89

31 89

31 89

31 89

30 89

30 89

30 89

30 89

32 89

32 89

30 89

32 89

32 89

30 89

32 89

32 89

31 89

32 89

32 89

31 89

31 89

31 89

31 89

31 89

30 89 31 89

AW29

AU28

AW33

AU30

AU32

AV31

AT22

AV22

AU22

AT23

AT24

AV23

AW23

AW24

AT20

AU20

AW32

AT21

AU21

AV28

AY24

AV27

AW12

AY12

AU11

AU13

AY13

AW13

AU14

AU12

AV12

AV13

AF39

AF38

AK39

AK38

AP39

AP38

AV36

AV37

AW8

AV8

AV4

AW4

AP2

AP3

AK2

AK3

AN4

AN1

AL1

AE40

AE39

AG38

AG39

AL2

AE37

AE38

AG37

AG40

AJ40

AJ39

AL38

AL39

AJ37

AJ38

AJ1

AL37

AL40

AN40

AN39

AR38

AR39

AN37

AN38

AR37

AR40

AJ2

AU37

AU38

AY36

AW35

AU36

AU39

AW37

AU35

AY9

AW9

AL4

AW7

AV7

AU9

AV9

AU7

AY7

AY5

AU5

AU3

AU2

AL3

AW5

AV5

AW3

AV2

AR1

AR2

AN3

AN2

AR4

AR3

AJ4

AJ3

AU33

AW30

AV32

AU29

AV18

AU18

AT19

AV19

AW26

AV26

AY27

AW27

AU25

AU24

AW25

AY25

AV30

AV20

AW28

AY29

U1000OMIT

LGA1155-SKTSANDY_BRIDGE

AR25

AP24

AK26

AM26

AP26

AL26

AY17

AN18

AL18

AM18

AP18

AP19

AK18

AM19

AV16

AY16

AR26

AT18

AU17

AN23

AM20

AK24

AP15

AR15

AM15

AL15

AR16

AP16

AM16

AL16

AN15

AN16

AG34

AG35

AM33

AL33

AR33

AP33

AN28

AN29

AN12

AN13

AP8

AR8

AL8

AM8

AH6

AH7

AM7

AL7

AJ7

AF35

AF33

AJ34

AJ35

AJ6

AE35

AE34

AH34

AH35

AL34

AM35

AL31

AM34

AL32

AL35

AG6

AM31

AM32

AR34

AR35

AR31

AR32

AP34

AP35

AP31

AP32

AG5

AM29

AM28

AP29

AP28

AL29

AL28

AR29

AR28

AP12

AR12

AJ8

AL13

AL12

AP13

AR13

AM13

AM12

AR9

AP9

AR6

AP6

AJ9

AR10

AP10

AR7

AP7

AM9

AL9

AM6

AL6

AL10

AM10

AG8

AG7

AT26

AL25

AN26

AN25

AV15

AW15

AY15

AU16

AN21

AP21

AM22

AL23

AK20

AL20

AL22

AL21

AK25

AW17

AM24

AP23

U1000OMIT



CPU DDR3 INTERFACES

TP_MEM_B_DQS_P<8>

MEM_B_A<6>

TP_MEM_A_DQ_CB<7>

MEM_A_DQ<26>

MEM_A_DQ<17>

MEM_A_DQ<12>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_DQ<32>

MEM_A_DQ<33>

TP_MEM_A_DQS_N<8>

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<9>

MEM_A_CLK_P<1>

MEM_A_ODT<2>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<2>

MEM_A_CLK_N<2>

MEM_A_CLK_P<3>

MEM_A_CLK_N<3>

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_CKE<2>

MEM_A_CKE<3>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CS_L<2>

MEM_A_CS_L<3>

MEM_A_DQ<0>

MEM_A_DQ<1>

MEM_A_DQ<10>

MEM_A_DQ<11>

MEM_A_DQ<13>

MEM_A_DQ<14>

MEM_A_DQ<15>

MEM_A_DQ<16>

MEM_A_DQ<18>

MEM_A_DQ<19>

MEM_A_DQ<2>

MEM_A_DQ<20>

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_DQ<23>

MEM_A_DQ<24>

MEM_A_DQ<25>

MEM_A_DQ<27>

MEM_A_DQ<28>

MEM_A_DQ<29>

MEM_A_DQ<3>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_DQ<39>

MEM_A_DQ<4>

MEM_A_DQ<40>

MEM_A_DQ<41>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<44>

MEM_A_DQ<45>

MEM_A_DQ<46>

MEM_A_DQ<47>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_DQ<5>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<52>

MEM_A_DQ<53>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<6>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQS_P<0>

MEM_A_DQS_N<0>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

MEM_A_DQS_P<5>

MEM_A_DQS_N<5>

MEM_A_DQS_P<6>

MEM_A_DQS_N<6>

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

TP_MEM_A_DQS_P<8>

TP_MEM_A_DQ_CB<0>

TP_MEM_A_DQ_CB<1>

TP_MEM_A_DQ_CB<2>

TP_MEM_A_DQ_CB<3>

TP_MEM_A_DQ_CB<4>

TP_MEM_A_DQ_CB<5>

TP_MEM_A_DQ_CB<6>

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_A<14>

MEM_A_A<15>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_ODT<3> MEM_B_ODT<3>

MEM_B_ODT<2>

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<1>

MEM_B_A<0>

TP_MEM_B_DQ_CB<7>

TP_MEM_B_DQ_CB<6>

TP_MEM_B_DQ_CB<5>

TP_MEM_B_DQ_CB<4>

TP_MEM_B_DQ_CB<3>

TP_MEM_B_DQ_CB<2>

TP_MEM_B_DQ_CB<1>

TP_MEM_B_DQ_CB<0>

MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQS_N<4>

MEM_B_DQS_P<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<1>

MEM_B_DQS_P<1>

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<6>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<5>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<4>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQ<3>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<20>

MEM_B_DQ<2>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_CKE<2>

MEM_B_CKE<1>

MEM_B_CKE<0>

MEM_B_CLK_N<3>

MEM_B_CLK_P<3>

MEM_B_CLK_N<2>

MEM_B_CLK_P<2>

MEM_B_CLK_P<1>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_BA<0>

MEM_B_CS_L<3>

MEM_B_CS_L<2>

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_CKE<3>

TP_MEM_B_DQS_N<8>

MEM_B_DQS_P<2>

MEM_B_DQS_P<4>

MEM_B_DQ<33>

MEM_B_DQS_N<3>

MEM_B_CLK_N<1>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_RAS_L

MEM_B_WE_L

12 OF 110

11.1.0

051-8115

12 OF 98

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

www.vinafix.vn

CPU CORE SUPPLY

VCCSA

NCTF

CPU CORE SUPPLY

(10 OF 10)

POWER

VCC_097

VCC_092

VCC_091

VCC_090

VCC_089

VCC_088

VCC_087

VCC_083

VCC_112

VCC_117

VCC_113

VCC_114

VCC_115

VCC_116

VCC_118

VCC_119

VCC_120

VCC_121

VCC_122

VCC_123

VCC_124

VCC_125

VCC_128

VCC_129

VCC_130

VCC_131

VCC_132

VCC_133

VCC_134

VCC_135

VCC_136

VCC_137

VCC_138

VCC_139

VCC_140

VCC_141

VCC_142

VCC_143

VCC_144

VCC_145

VCC_146

VCC_147

VCC_148

VCC_149

VCC_150

VCC_151

VCC_152

VCC_153

VCC_156

VCC_157

VCC_158

VCC_159

VCC_160

VCCSA0

VCCSA1

VCCSA2

VCCSA3

VCCSA4

VCCSA5

VCCSA6

VCCSA8

VCCSA9

VSS_NCTF3

VSS_NCTF2

VSS_NCTF1

VCC_073

VCC_072

VCC_071

VCC_155

VCC_154

VCC_084

VCC_093

VSS_NCTF0

VCC_100

VCC_101

VCC_104

VCC_106

VCC_105

VCC_096

VCC_095

VCC_094

VCC_086

VCC_085

VCCSA7

VCCSA10

VCC_107

VCC_082

VCC_077

VCC_074

VCC_076

VCC_161

VCC_126

VCC_127

VCC_111

VCC_098

VCC_099

VCC_075

VCC_081

VCC_103

VCC_102

VCC_078

VCC_079

VCC_080

VCC_108

VCC_109

VCC_110

VCCSA_VID

VCCIO_39

VCCIO_38

VCCIO_37

VCCIO_32

VCCIO_25

VCCIO_24

VCCIO_23

VCCIO_21

VCCIO_22

VCCIO_18

VCCIO_17

VCCIO_15

VCC_019

VCCIO_03

VCC_053

VCC_054

VCC_055

VCC_056

VCC_SENSE

VCCIO_41

VSS_SENSE

VIDSOUT

VIDSCLK

VIDALERT*

VCCSA_SENSE

VCCIO_19

VCCIO_16

VCCIO_14

VCCIO_13

VCCIO_12

VCCIO_11

VCCIO_10

VCCIO_08

VCCIO_07

VCCIO_06

VCCIO_05

VCCIO_04

VCCIO_43

VCCIO_40

VCCIO_36

VCCIO_35

VCCIO_34

VCCIO_33

VCCIO_26

VCCIO_20

VCCIO_01

VCCIO_02

VCC_070

VCC_069

VCC_068

VCC_067

VCC_066

VCC_065

VCC_064

VCC_063

VCC_062

VCC_061

VCC_060

VCC_059

VCC_058

VCC_057

VCC_052

VCC_051

VCC_050

VCC_049

VCC_048

VCC_047

VCC_046

VCC_045

VCC_044

VCC_043

VCC_042

VCC_041

VCC_040

VCC_039

VCC_037

VCC_036

VCC_035

VCC_034

VCC_033

VCC_032

VCC_031

VCC_030

VCC_029

VCC_028

VCC_027

VCC_026

VCC_025

VCC_023

VCC_022

VCC_021

VCC_020

VCC_018

VCC_017

VCC_016

VCC_014

VCC_013

VCC_011

VCC_010

VCC_009

VCC_008

VCC_007

VCC_006

VCC_005

VCC_015

VCC_012

VCCIO_27

VCC_004

VCC_003

VCC_002

VCC_001

VCCIO_09

VCCIO_28

VCCIO_29

VCCIO_42

VCC_038

VCC_024

VCCIO_SENSE

VSSIO_SENSE

VCCAXG_SENSE

VSSAXG_SENSE

VCCIO_30

VCCIO_45

VCCIO_SEL

VCCIO_44

VCCIO_31

SENSE LINES

CPU CORE SUPPLY

IO POWER

POWER

CPU VIDS

(6 OF 10)

VCCAXG_08

VCCAXG_01

VDDQ5

VDDQ18

VDDQ17

VDDQ15

VCCAXG_20

VCCAXG_23

VCCAXG_17

VCCAXG_18

VCCAXG_19

VCCAXG_21

VCCAXG_22

VCCAXG_24

VCCAXG_25

VCCAXG_26

VCCAXG_27

VCCAXG_28

VCCAXG_29

VCCAXG_30

VCCAXG_31

VCCAXG_32

VCCAXG_33

VCCAXG_34

VCCAXG_35

VCCAXG_36

VCCAXG_37

VCCAXG_38

VCCAXG_39

VCCAXG_40

VCCAXG_41

VCCAXG_42

VCCAXG_04

VCCAXG_05

VCCAXG_06

VCCAXG_07

VCCAXG_09

VCCAXG_10

VCCAXG_11

VCCAXG_12

VCCAXG_13

VCCAXG_14

VCCAXG_15

VCCAXG_16

VDDQ0

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ11

VDDQ12

VDDQ13

VDDQ14

VDDQ16

VDDQ19

VDDQ20

VDDQ21

VDDQ22

VCCPLL0

VCCPLL1

VDDQ10

VCCAXG_03

VCCAXG_02

VCCAXG_43

VCCAXG_44

GRAPHICS

DDR3-1.5V RAILS

POWER

1.8V

( 7 OF 10 )

OUT

OUT

OUT

OUT

OUT

IN

BI

OUT

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Fixed at 1.05V

PLACEMENT NOTE:

R1302 NEAR CPUPLACE R1300 AND

(NOT controlled by VCCIO_SEL)

AY37

AV39

B3

A4

M11

M10

L12

L11

K11

K10

J10

H12

M12

H11

H10

M30

M28

M27

M25

M24

M22

M21

M19

M18

M16

M15

M14

L30

L28

L27

L25

L24

L22

L21

L19

L18

L16

L15

L14

L13

K30

K28

K27

K25

K24

K22

K21

K19

K18

K16

K15

J30

J28

J27

J25

J24

J22

J21

J19

J18

J16

J15

J12

H32

H31

H30

H28

H27

H25

H24

H22

H21

H19

H18

H16

H15

H14

H13

G33

G32

G31

G30

G28

G27

G25

G24

G22

G21

G19

G18

G16

G15

F34

F33

F32

F31

F30

F28

F27

F25

F24

F22

F21

F19

F18

F16

U1000OMIT

SANDY_BRIDGELGA1155-SKT

AB3

M32

B36

B37

C37

A37

P34

T2

AB4

P33

W3

V8

U7

U4

U3

R7

R4

R3

N7

N4

N3

M13

L7

L4

L3

J8

J7

J4

J3

G4

G3

E4

E3

D6

D10

B9

AK30

AK29

AK27

AK23

AK21

AK19

AK17

AK15

AJ32

AJ28

AJ26

AJ17

AJ16

AG33

AF8

AB8

AA3

A7

A11

L32

A36

F15

E35

E34

E33

E31

E30

E28

E27

E25

E24

E22

E21

E19

E18

E16

E15

D36

D35

D34

D33

D31

D30

D28

D27

D25

D24

D22

D21

D19

D18

D16

D15

D14

D13

C36

C34

C33

C31

C30

C28

C27

C25

C24

C22

C21

C19

C18

C16

C15

B34

B33

B31

B30

B28

B27

B25

B24

B18

B16

B15

A28

A27

A25

A24

A18

A16

A15

A14

A13

A12

U1000OMIT


AR24

AR23

AR22

AR21

AR20

AJ24

AJ23

AY28

AY26

AY23

AJ20

AW31

AV33

AV29

AV25

AV24

AV21

AU31

AU27

AU23

AU19

AJ14

AJ13

AK12

AK11

Y38

Y37

Y36

Y35

Y34

Y33

W38

W37

W36

W35

W34

W33

U40

U39

U38

U37

U36

U35

U34

U33

T40

T39

T38

T37

T36

T35

T34

T33

AC40

AC39

AC38

AC37

AC36

AC35

AC34

AC33

AB40

AB39

AB38

AB37

AB36

AB35

AB34

AB33

U1000OMIT


69 95

65 95

65 95

68 95

68 95

2

1R1300

PLACEMENT_NOTE=Place close to CPU

MF-LF

75

1/16W

402

1%

2

1R1302

402

1/16WMF-LF

1101%


21

R1310

402MF-LF1/16W1%

44.265 95

21

R1312

MF-LF 402

1/16W5%0

65 95

21

R1311

402

5% 1/16W

MF-LF

065 95

65 95

65 95


CPU POWERSYNC_MASTER=K62

=PPVAXG_S0_CPU

=PP1V5_S0_CPU_MEM

=PP1V8_S0_CPU_PLL

=PPVCCIO_S0_CPU

CPU_VIDALERT_L

CPU_VIDSCLK

CPU_VIDSOUT

CPU_VAXG_SENSE_N

CPU_VAXG_SENSE_P

CPU_VCCIO_SENSE_N

CPU_VCCIO_SENSE_P

CPU_VCCSA_SENSE

CPU_VIDALERT_L_R

CPU_VCC_SENSE_N

CPU_VCC_SENSE_P

TP_CPU_VCCSA_VID

CPU_VIDSOUT_R

CPU_VIDSCLK_R

=PPVCORE_S0_CPU

=PPVCCIO_S0_CPU

TP_CPU_VCCIO_SEL

=PPVCORE_S0_CPU

=PPVCCSA_S0_CPU

13 OF 110

11.1.0

051-8115

13 OF 98

6 17 50 65

6 11 16 28 29

6 16

6 10 11 13 16 65

95

95

95

6 13 16 50 65

6 10 11 13 16 65 6 13 16 50 65

6 50

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36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

AV10

AU8

AU6

AU4

AU34

AU26

AU15

AU1

AT9

AT8

AT7

AT6

AT5

AT40

AT4

AT39

AT38

AT37

AT36

AT35

AT34

AT33

AT32

AT31

AT30

AT3

AT29

AT28

AT27

AT25

AT2

AT17

AT16

AT15

AT13

AT12

AT10

AT1

AR5

AR36

AR30

AR27

AR19

AR18

AR17

AR14

AR11

AP5

AP40

AP4

AP37

AP36

AP30

AP27

AP25

AP22

AP17

AP14

AP11

AP1

AN9

AN8

AN7

AN6

AN5

AN36

AN35

AN34

AN33

AN32

AN31

AN30

AN27

AN24

AN22

AN19

AN17

AN14

AN11

AN10

AM5

AM40

AM4

AM39

AM38

AM37

AM36

AM30

AM3

AM27

AM25

AM23

AM21

AM2

AM17

AM14

AM11

AM1

AL5

AL36

AL30

AL27

AL24

AL19

AL17

AL14

AL11

AK9

AK8

AK7

AK6

AK5

AK40

AK4

AK37

AK36

AK35

AK34

AK33

AK32

AK31

AK28

AK22

AK16

AK14

AK13

AK10

AK1

AJ5

AJ36

AJ27

AJ25

AJ21

AJ18

AJ15

AJ12

AH8

AH5

AH40

AH39

AH38

AH37

AH36

AH33

AH3

AH2

AG36

AF7

AF6

AF5

AF40

AF37

AF36

AF34

AF1

AE36

AE33

AE3

AD8

AD5

AD40

AD39

AD38

AD36

AD33

AC6

AC1

AB5

AA6

AA38

AA37

AA36

AA35

AA34

AA33

A35

A29

A26

A23

A17

U1000SANDY_BRIDGE

LGA1155-SKT

OMIT

Y8

Y5

W6

V5

V40

V39

V38

V37

V36

V35

V34

V33

V2

V1

U8

T6

T5

T1

R8

R39

R37

R35

R33

P6

P5

P40

P38

P36

P2

P1

N8

M9

M6

M5

M39

M37

M35

M33

M29

M26

M23

M20

M2

M17

M1

L8

L29

L26

L23

L20

L17

L10

K6

K5

K39

K37

K35

K33

K29

K26

K23

K20

K2

K17

K14

K13

K12

K1

J32

J29

J26

J23

J20

J17

J11

H9

H6

H5

H39

H37

H35

H33

H29

H26

H23

H20

H2

H17

H1

G8

G7

G34

G29

G26

G23

G20

G17

G12

G11

F9

F6

F5

F39

F37

F35

F29

F26

F23

F20

F2

F17

F14

F13

F10

F1

E8

E7

E36

E32

E29

E26

E23

E20

E17

E12

E11

D9

D5

D4

D39

D37

D32

D29

D26

D23

D20

D2

D17

C8

C7

C35

C32

C29

C26

C23

C20

C17

C12

C11

B6

B38

B35

B32

B29

B26

B23

B17

B14

B13

B10

AY8

AY6

AY4

AY35

AY18

AY14

AY11

AW6

AW36

AW16

AW14

AW11

AW10

AV6

AV38

AV35

AV3

AV17

AV14

AV11

1158

1157

1156

U1000SANDY_BRIDGE

LGA1155-SKT

OMIT

CPU GROUNDS

14 OF 110

11.1.0

051-8115

14 OF 98

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36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

REMOVE THESE PULL DOWN RESISTORS AFTER PROTO

REMOVE THESE PULL DOWN RESISTORS AFTER PROTO

These can be Placed close to J2500 and Only for debug access

New SP_DESCRIPTOR_OVERRIDE_L strap

Multiplux with Mini

2

1R15001K5%

1/16WMF-LF402

2

1R1556

1/16W

10K

MF-LF402

5%

2

1R1572NOSTUFF

10K

1/16WMF-LF

5%

4022

1R157310K

MF-LF

5%1/16W

4022

1R1574

1/16W5%

MF-LF402

10K

2

1R1575

1/16WMF-LF

5%

402

10K

2

1R15851K

1/16W

402

5%

MF-LF

NOSTUFF

2

1R15861K

NOSTUFF

5%

MF-LF402

1/16W

2

1R15871K

NOSTUFF

MF-LF

5%

402

1/16W

2

1R1588NOSTUFF

1K

MF-LF

5%

402

1/16W

2

1R157610K

402MF-LF

5%1/16W

2

1R1571

1/16W5%

MF-LF

10K

402

NOSTUFF

2

1R1592NOSTUFF

1/16W5%

10K

MF-LF402

21

R1595

402

0

5%1/16WMF-LF

21

R1596NOSTUFF

0

MF-LF402

1/16W5%

2

1R1509

MF-LF1/16W

5%10K

402

2

1R1520NOSTUFF

402MF-LF

5%1/16W

4.7K

2

1R1541NOSTUFF

1K5%

402

1/16WMF-LF

2

1R1521NOSTUFF

1K

MF-LF

5%

402

1/16W

2

1R1515

402

1/16W

10K

NOSTUFF

MF-LF

5%

2

1R1525

1/16W

NOSTUFF

10K5%

402MF-LF

2

1R1524

MF-LF1/16W

402

5%10K

2

1R1523

MF-LF402

5%1/16W

10K

2

1R1530

1/16W

10K

MF-LF

5%

402

2

1R152710K

402

5%1/16WMF-LF

NOSTUFF

2

1R1528

MF-LF402

1/16W5%

10K

NOSTUFF

2

1R1526

5%10K

402MF-LF1/16W

2

1R1535

MF-LF402

10K5%

1/16W

2

1R1538

1/16W

NOSTUFF

4.7K5%

402MF-LF

2

1R153910K

402

1/16W5%

MF-LF

2

1R1543

5%

402

4.7K

MF-LF1/16W

2

1R1550

402MF-LF

1K5%

NOSTUFF

1/16W

2

1R1551NOSTUFF

10K5%

1/16WMF-LF402 2

1R1552NOSTUFF

10K5%

MF-LF402

1/16W

2

1R1553

5%

MF-LF402

1/16W

10K

NOSTUFF

2

1R1554

1/16W

NOSTUFF

402MF-LF

5%10K 2

1R1564NOSTUFF

5%

MF-LF402

1/16W

1K

2

1R1563NOSTUFF

MF-LF402

1/16W5%1K

2

1R1503

1/16WMF-LF

5%

402

10K

2

1R1562NOSTUFF

5%

MF-LF402

1/16W

1K

2

1R1561NOSTUFF

5%

402

1/16WMF-LF

1K

2

1R1560NOSTUFF

402MF-LF1/16W

5%1K

2

1R1569NOSTUFF

1K

402MF-LF

5%1/16W

2

1R1568NOSTUFF

MF-LF

1K5%

1/16W

402

2

1R15671K

MF-LF

NOSTUFF

1/16W

402

5%

2

1R1566NOSTUFF

1K

MF-LF402

5%1/16W

2

1R1565NOSTUFF

1K5%

1/16WMF-LF402

2

1R1504NOSTUFF

MF-LF402

1/16W5%

10K

2

1R1570NOSTUFF

10K5%

402

1/16WMF-LF

2

1R150610K

MF-LF1/16W

5%

NOSTUFF

4022

1R1507

5%

402

10K

1/16WMF-LF

2

1R150810K

5%1/16W

402MF-LF

2

1R1510

402MF-LF1/16W

5%10K

2

1R151110K

1/16W5%

MF-LF402

2

1R1590

1/16W

10K

MF-LF

5%

402

2

1R1591

1/16W5%

10K

MF-LF402

2

1R151210K

5%

MF-LF402

1/16W

2

1R1519

402

1/16W5%

MF-LF

10K

2

1R1517

1/16WMF-LF

5%10K

402

NOSTUFF

2

1R1522

402

NOSTUFF

10K5%

MF-LF1/16W

2

1R1534

5%

MF-LF402

1/16W

10K

NOSTUFF

2

1R154810K

1/16WMF-LF

5%

402

2

1R1555

402

5%1/16WMF-LF

10K

NOSTUFF


STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU

PM_CLKRUN_L

PCH_GPIO70_TACH6

PCH_GPIO71_TACH7

JTAG_T29_TMS

SDCARD_RESET

PCH_SPKR

CPU_CFG<2>

ENET_SW_RESET_L

PCH_GPIO19_SATA1GP

FW_PME_L

BLC_GPIO

PCH_GPIO0_BMBUSY_L

DP_AUXCH_ISOL

PCH_GPIO49_SATA5GP

T29_SW_RESET_L

FW_PWR_EN

FW_MINI_CLKREQ_L

JTAG_T29_TCK


PCH_GPIO36_SATA2GP

PCH_GPIO7_TACH3


JTAG_T29_TDI

MINI_CLKREQ_L


MINI_CLKREQ_L

ENET_MEDIA_SENSE

PCH_GPIO24

FW_CLKREQ_L

PCH_GPIO8

HDA_SDOUT

SMC_WAKE_SCI_L

PCH_GPIO29_SLP_LAN_L

CPU_CFG<0>

PCH_GPIO30_SUSWARN_L

PCH_FDI_FSYNC<1>

PCH_FDI_LSYNC<0>

PCH_FDI_LSYNC<1>

PCH_FDI_INT

CPU_FDI_FSYNC<0>

CPU_FDI_INT

CPU_FDI_FSYNC<1>

CPU_FDI_LSYNC<1>

CPU_FDI_LSYNC<0>

ODD_PWR_EN_L

PCH_PCI_GNT0_L

PCH_PCI_GNT1_L

PCH_INIT3V3_L

CPU_CFG<5>

T29_CLKREQ_L

FW_MINI_CLKREQ_L

CPU_CFG<1>

JTAG_T29_TDO

PCH_FDI_FSYNC<0>

PCH_GPIO15

CPU_CFG<3>

CPU_CFG<16> CPU_CFG<6>


ENET_CLKREQ_L

PM_BATLOW_L


PCH_PCI_GNT2_L

PCH_PCI_GNT3_L

ENET_LOW_PWR


15 OF 110

11.1.0

051-8115

15 OF 98

19 46 48 97

21

21

18 86 96

21 44 97 98

18

10 25 90

21 36 91

18 25

21 39 97

6 21 91

21 25

18 25 84 91

21 25

21 80 91

21 97

15 18 91

21 25 86 96

6 15

21 25

21

6 15

21 86 96

15 33 97

6 15

15 33 97

18 37 92

21

39 97

21

18 56 91

18 21 46 97

19

10 25 90

19

19

19

19

19

10

10

10

10

10

21 42 97

20

20

21

10 25 90

21 80 91

15 18 91

10 25 90

21 86 96

19

21 25

10 25 90

10 25 90 10 25 90

6 15

18 36 91

19 46 97

6 15

20

20

21 37 97

6 15

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36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

10x 10UF and 10x 1UF CAPACITORS

Note: VCCSA decoupling is on regulator page

INTEL RECOMMENDATION 9X22UF 0805,16X 0805 placeholders

BULK CAPS ON VTT REG PAGE 78

PLACEMENT_NOTE (C1660-C1665):

BULK CAPS ON CPU VREG PAGE 72

PLL (CPU VCCSFR) DECOUPLING

CPU VCORE DECOUPLING

2x 47uF, 1x 22uF 0805, 1x 10uF 0603, 1x 4.7uF 0603, 1x 2.2uF 0402, 2x 1uF 0402. INTEL RECOMMENDATION 10x 10uF 0805

8X 22UF 0805, 6X 10UF 0805



CPU VCCIO DECOUPLING


14x 22UF,0805 INTEL RECOMMENDATION 18X 22UF 0805 (14 Inside cavity and 4 North of processor)

6x 22uF 0805, 5x 1uF 0402. INTEL RECOMMENDATION 9X 22uF 0805

Memory (CPU VCCDDR) DECOUPLING

2

1 C1693

X5R

10%1UF

402

10V2

1 C1692

402

2.2UF

6.3V10%

X5R 2

1 C16914.7UF

X5R-CERM6.3V

603

10%

2

1 C1690

20%6.3V

22uF

CERM-X5R805

2

1 C1681

CERM-X5R805

20%22uF

6.3V2

1 C16851UF10%

402X5R10V

2

1 C1684

10V

402

1UF10%

X5R 2

1 C1686

10V

402

10%

X5R

1UF

2

1 C1609

Place inside socket cavity

805-3

22UF20%6.3VCERM-X5R2

1 C1608

20%6.3VCERM-X5R


22UF

805-3

2

1 C1607


22UF20%6.3VCERM-X5R805-3

2

1 C1613

20%6.3VCERM-X5R805-3

22UF


2

1 C161222UF20%6.3VCERM-X5R805-3


2

1 C1611

805-3

6.3V20%22UF

CERM-X5R


2

1 C1610

805-3CERM-X5R6.3V20%22UF


2

1 C1629


X5R603

10V20%10UF

2

1 C1600

805-3

22UF

CERM-X5R6.3V20%


2

1 C1628

X5R603

10UF10V20%


2

1 C1627

X5R603

10UF10V20%


2

1 C1626

X5R603

10UF10V


20%2

1 C162420%10V

10UF

603X5R


2

1 C1623

603X5R10V20%10UF


2

1 C162220%10V

10UF

603X5R


2

1 C162120%10V

603X5R

10UF


2

1 C162010UF20%

X5R603

10V


2

1 C16301UF10%16VX5R402


2

1 C1625

X5R

10UF10V20%


603

2

1 C16311UF10%16VX5R402


2

1 C16321UF10%16VX5R402


2

1 C1633

X5R402

1UF16V10%


2

1 C163410%16VX5R402


1UF

2

1 C16351UF10%

X5R402

16V


2

1 C16361UF10%16VX5R402


2

1 C16371UF10%

X5R16V


4022

1 C16381UF10%16VX5R402


2

1 C1639

402X5R16V10%1UF


2

1 C1601

20%

805-3

22UF

6.3VCERM-X5R


2

1 C1670

POLY2V

330UF-0.0045OHM20%

CASE-D2-SM

2

1 C1696

6.3V20%47UF

0805X5R2

1 C1695

20%6.3V

10UF

603X5R 2

1 C1697

X5R0805

47UF20%6.3V

2

1 C1679

6.3V

22uF20%

805CERM-X5R2

1 C1678

20%6.3V

22uF

CERM-X5R805

2

1 C1677

6.3V

22uF20%

805CERM-X5R2

1 C1676

20%6.3V

22uF

CERM-X5R805

2

1 C1602

805-3CERM-X5R


6.3V20%22UF

2

1 C1603

805-3CERM-X5R6.3V20%22UF


2

1 C1604

805-3

6.3V


22UF20%

CERM-X5R

2

1 C1650

6.3V

22UF

805

20%

CERM-X5R

Place under socket cavity on secondary side.

2

1 C1605


22UF20%6.3VCERM-X5R805-3

2

1 C1606

6.3V


22UF20%

805-3CERM-X5R

2

1 C1651

CERM-X5R


22UF20%6.3V

805

2

1 C1652


805

20%

CERM-X5R6.3V

22UF

2

1 C1653


CERM-X5R805

22UF20%6.3V

2

1 C1654


805

20%6.3VCERM-X5R

22UF

2

1 C1655

6.3VCERM-X5R


805

20%22UF

2

1 C1656

CERM-X5R805

22UF


20%6.3V

2

1 C1657

6.3V20%22UF

805


CERM-X5R

2

1 C1665

603

6.3V20%10uF

X5R

Place at edge of socket.

2

1 C1664


X5R6.3V20%

603

10uF

2

1 C1663

20%


603X5R6.3V

10uF

2

1 C166210uF20%


X5R6.3V

603

2

1 C1661

603

6.3V

10uF20%

X5R


2

1 C1660

6.3V

10uF20%


603X5R

2

1 C1680

805CERM-X5R

22uF

6.3V20%

2

1 C1682

402

10VX5R

10%1UF

2

1 C1683

10V10%

X5R402

1UF

2

1 C1694

10V

402

10%

X5R

1UF


CPU NON-GFX DECOUPLINGSYNC_MASTER=K62

=PPVCORE_S0_CPU=PPVCORE_S0_CPU

=PPVCCIO_S0_CPU

=PP1V5_S0_CPU_MEM

=PP1V8_S0_CPU_PLL

16 OF 110

11.1.0

051-8115

16 OF 98

6 13 16 50 65

6 13 16 50 65

6 10 11 13 65

6 11 13 28 29

6 13

www.vinafix.vn

TABLE_5_ITEM

TABLE_5_ITEM




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1


QTY DESCRIPTIONPART#


INTEL RECOMMENDATION 6X22UF 0805,3X 4.7UF

VAXG DECOUPLING


21

R1760

1/16W5%

0

402MF-LF

21

R1765

5%1/16W

0

402MF-LF

21

R17500

402

5%1/16WMF-LF

2

1 C170922UF20%6.3VCERM-X5R805-3

VAXG


2

1 C1708

6.3V

22UF20%

CERM-X5R805-3

VAXG


2

1 C170722UF20%6.3VCERM-X5R805-3


VAXG

2

1 C1706

805-3CERM-X5R6.3V20%22UF


VAXG

2

1 C1705

805-3CERM-X5R6.3V20%


22UF

VAXG

2

1 C1704

805-3

20%


CERM-X5R6.3V

22UF

VAXG

2

1 C1710

603X5R-CERM

4.7UF10%


6.3V

OMIT

2

1 C1711

X5R-CERM


603

VAXG

4.7UF10%6.3V

2

1 C1712

X5R-CERM

10%6.3V


603

VAXG

4.7UF

GFX DECOUPLING & PCH PWR ALIAS


C17101 CAP,4.7UF,10%,6.3V,0603138S0586 VAXG

NO_VAXGRES,0 OHM,5%,06031113S0022 C1710

PP1V05_S0_PCH_VCCADPLLB_F

VOLTAGE=1.05V

MAKE_BASE=TRUEMIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.2MM

VOLTAGE=1.05V


PP1V05_S0_PCH_VCCADPLLA_F=PP1V05_S0_PCH_VCCADPLL

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=3.3V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_PCH_VCCA_DAC_F

=PPVAXG_S0_CPU

=PP3V3_S0_PCH_VCCADAC

17 OF 110

11.1.0

051-8115

17 OF 98

22 95

22 95 6

22 95

6 13 50 65

6

www.vinafix.vn

IN

IN

OUT

OUT

OUT

IN

BI

BI

BI

BI

OUT

BI

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

BI

OUT

BI

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

BI

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

SATA1RXN

SATA0TXP

SATA0TXN

SATA2RXN

SATA2RXP

SATA5RXP

SATA0RXP

LDRQ0*

L_BKLTEN

L_VDD_EN

SATA3COMPI

SATA3RCOMP0

SATA3RBIAS

RTCRST*

SRTCRST*

INTRUDER*

INTVRMEN

HDA_BCLK

HDA_SYNC

HDA_RST*

SPKR

HDA_SDIN0

HDA_SDIN1

HDA_SDIN3

HDA_SDIN2

HDA_SDO

HDA_DOCK_EN*/GPIO33

HDA_DOCK_RST*/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CS0*

SPI_CLK

SPI_CS1*

SPI_MOSI

SPI_MISO

FWH0/LAD0RTCX1

RTCX2

SATA1TXP

SATA0RXN

SERIRQ

LDRQ1*/GPIO23

FWH1/LAD1

FWH2/LAD2

FWH3/LAD3

FWH4/LFRAME*

SATA1RXP

SATA1TXN

SATA2TXN

SATA2TXP

SATA3RXN

SATA3RXP

SATA3TXN

SATA3TXP

SATA4RXN

SATA4RXP

SATA4TXN

SATA4TXP

SATA5RXN

SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED*

SATA0GP/GPIO21

SATA1GP/GPIO19

L_BKLTCTL

JTAG

SPI

SATA

LPC

IHDA

RTC

SYM 1 OF 10

SMBDATA

SML0CLK

SML0ALERT*/GPIO60

SML0DATA

SML1ALERT*/PCHHOT*/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

PETP1

PERP2

PERN2

PERP3

PETN3

PERN4

PETP3

PERP4

PETN4

PERN5

PETP4

PERP5

PETN5

PETP5

PERN6

PERP6

PETP6

PETN6

PERN7

PERP7

PETN7

PERN8

PETP7

PETN8

PERP8

PETP8

SMBALERT*/GPIO11

SMBCLK

PERN1

PETN1

CLKOUT_PCIE0P

CLKOUT_PCIE0N

CLKOUT_PCIE1P

CLKOUT_PCIE1N

CLKOUT_PCIE2N

CLKOUT_PCIE2P

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE3N

CLKOUT_PCIE4N

CLKOUT_PCIE3P

CLKOUT_PCIE5N

CLKOUT_PCIE4P

PCIECLKRQ5*/GPIO44

CLKOUT_PCIE5P

CLKOUT_PEG_B_P

CLKOUT_PEG_B_N

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLKOUT_DMI_P

CLKOUT_DP_P

CLKOUT_DP_N

CLKIN_DMI_N

CLKIN_DMI_P

CLKIN_DOT_96N

CLKIN_DOT_96P

CLKIN_SATA_P

CLKIN_SATA_N

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

CLKIN_GND0_P

CLKIN_GND0_N

CLKIN_GND1_N

CLKIN_GND1_P

CL_CLK1

CL_DATA1

CL_RST1*

PERP1

PETN2

PETP2

PERN3

SMBUS

FLEX

CLOCK

FROM CLK BUFFER

PEG

PCI-E*

SYM 2 OF 10

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PLACE THESE 33 OHM RESISTORS CLOSE TO PCH (MIN 500MIL)

DOES THIS NEED LENGTH MATCH???

PLACE THIS RESISTOR NEAR THE PCH PIN

TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS

27 91

56 91

48 55 91

48 91

48 55 91

48 55 91

46 48 91

46 48 91

46 48 91

46 48 91

46 48 91

46 48

42 90

42 90

42 90

42 90

42 90

42 90

42 90

42 90

37 92

37 92

33 90

33 90

39 90

39 90

37 92

37 92

33 90

33 90

39 90

39 90

37 90

37 90

33 90

33 90

39 90

39 90

15 91

11 90

11 90

9

9

8

8

26 90

26 90

26 90

26 90

26 90

26 90

26 91

27 91

27 79 91

27 91

27 91

49 94

49 94

49 94

49 94

8

8

8

8

2

1R1800390K

402

1/16W5%

MF-LF

2

1R1801

402MF-LF

5%1/16W

1M

2

1R1802

402MF-LF

5%1/16W

20K

2

1R180320K

1/16W5%

402MF-LF

2

1 C18031UF10%

402

10VX5R2

1C1802

X5R402

1UF10%10V

2

1R183037.4

MF-LF402

1/16W1%

PLACE R1830 AT BALL AJ53

2

1R1820

402

1/16W

10K5%

MF-LF

86 96

86 96

2

1R1890

PLACE R1890 AT BALL AL2

MF-LF

402

1%1/16W

90.9

21

R1810

402MF-LF1/16W5%

33

21

R1811

402MF-LF

33

1/16W5%

21

R1812

1/16WMF-LF

33

402

5%

21

R1813

402

1/16W5%

MF-LF

33

56 91

56 91

56 91

15 56 91

2

1R1850

MF-LF402

10K5%

1/16W

15 36 91

49 94

49 94

2

1R1853

1/16W

10K

MF-LF402

5%

2

1R185410K

MF-LF1/16W5%

402 2

1R1855

MF-LF1/16W5%

402

10K

8

8

42 90

42 90

42 90

42 90

21R18601/16W MF-LF 4025%

33

21R18614025%

33MF-LF1/16W

21R18625%

334021/16W MF-LF

21R18635%

331/16W 402MF-LF

21R18644021/16W

33MF-LF5%

21R18225% 1/16W

22

MF-LF 402

21R18231/16W MF-LF

22

4025%

8

8

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

BN37

BE56

AU53

AT55

AR56

AT57

AR54

AV52

BF57

AJ53

AJ55

AV49

AV50

AT44

AT46

AT49

AT50

AN50

AN49

AM55

AN56

AN44

AN46

AE52

AC52

AE54

AL53

AL56

AL49

AL50

AG47

AG49

AA56

AA53

AY52

AE44

AE46

AB55

AC56

BC54

BN39

BR39

BT41

BA20

BK17

AG17

AG18

AG12

BC50

BF47

BC52

BA43

BN41

BM38

BP23

BT23

BJ22

BK22

BF22

BD22

BC22

BA25

BC25

BU22

BG17

BG20

BJ20

BJ17

BK15U1800

OMIT

WLCSPCOUGAR-POINT

AJ5

AJ3

AL2

BK46

BJ46

BR46

BM50

BT51

BU49

BR49

BT47

BN49

AN8

D13

F13

B15

C16

E17

B21

A22

F23

B13

F15

A16

B17

F18

E21

C22

F25

J10

H12

L15

M15

M17

J17

R20

L20

H10

J12

J15

N15

P17

H17

P20

J20

BL54

AV43

BA2

AW5

BA5

AT9

AE11

AE12

AG9

AG8

AG2

AF3

Y8

Y9

AB8

AB9

AB14

AB12

W5

AA5

AC6

AE6

N52

R52

M55

N56

R31

P31

AG56

AF55

BD15

P27

R27

V52

W53

BF38

BD38

R33

P33

BF49

BF50

BA50

U1800OMIT

COUGAR-POINTWLCSP

2

1R1832

PLACE R1832 AT BALL AC52

1/16W

402

1%

MF-LF

750

2

1R1831

1/16W

PLACE R1831 AT BALL AE52

402MF-LF

1%49.9

2

1R1870

402

5%1/16WMF-LF

10K

2

1R1871

MF-LF1/16W

402

10K5%

2

1R187310K

402

5%

MF-LF1/16W

2

1R1872

MF-LF1/16W

5%

402

10K21

R1841

402MF-LF1/16W

0

5%

NOSTUFF

21

R1840NOSTUFF

0

5%

MF-LF1/16W

402

46 97 21

R1880

PLACE R1880 CLOSE TO R1813

MF-LF

NOSTUFF

0

5%1/16W

402

21

R18950

MF-LF402

1/16W5%

NOSTUFF

SYNC_MASTER=K62

PCH SATA/PCIE/CLK/LPC/SPISYNC_DATE=01/06/2011

PCIE_CLK100M_MINI_P

PCIE_CLK100M_MINI_N

PCIE_CLK100M_ENET_N

PCIE_T29_R2D_C_N<2>

FW_MINI_CLKREQ_L

PCIE_CLK100M_T29_N



TP_DMI_MIDBUS_CLK100M_PEGB1N

TP_DMI_MIDBUS_CLK100M_PEGB1P


SATA_SSD_D2R_P

PCH_SATAICOMPTOTAL_ETCH_LENGTH=5 MM

PCIE_T29_R2D_C_P<1>

PCIE_T29_R2D_C_N<1>

PCIE_T29_D2R_N<1>

TP_PCH_L_BKLTCTL

PCH_SATA3COMPTOTAL_ETCH_LENGTH=5 MM

=PP1V05_S0_PCH

PCH_CLK96M_DOT_N

PCH_CLK96M_DOT_P

PCH_CLK33M_PCIIN

LPC_R_AD<0>

PCIE_ENET_R2D_C_N


PCH_CLK32K_RTCX2

=PP3V3_S0_PCH

LPC_FRAME_R_L

T29_PWR_EN

TP_LPC_DREQ0_L

LPC_AD<1>

LPC_SERIRQ

PCH_GPIO19_SATA1GP

DP_AUXCH_ISOL

PCH_SATALED_L

LPC_FRAME_LPCH_SRTCRST_L

HDA_SDIN0

TP_HDA_SDIN1

TP_HDA_SDIN2

TP_HDA_SDIN3

HDA_SDOUT_R

PCH_INTRUDER_L

PCH_INTVRMEN_L

TP_SATA_D_R2D_CP


PCIE_CLK100M_T29_P

PEG_CLK100M_N

SML_PCH_0_DATA

PCIE_FW_R2D_C_N

PCH_SPKR

HDA_RST_R_L

TP_PCH_GPIO65_CLKOUTFLEX1


DP_GPU_T29_SEL


ITPXDP_CLK100M_N

ITPXDP_CLK100M_P

PCH_CLK25M_XTALOUT

PCH_CLK25M_XTALIN

ENET_CLKREQ_L

HDA_SYNC_R

HDA_BIT_CLK_R

SPI_DESCRIPTOR_OVERRIDE_L

PP3V3_G3H_RTC

SPI_MOSI_R

HDA_SYNC_R

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW_N

PCIE_T29_D2R_P<2>

PCIE_T29_R2D_C_P<2>

PCIE_T29_D2R_N<3>

PCIE_T29_R2D_C_P<3>

PCIE_CLK100M_ENET_P

SATA_ODD_R2D_C_N

SATA_SSD_D2R_N

XDP_PCH_TDO

SPI_MOSI_1_R

PCH_CLKIN_GNDP0

PCH_CLKIN_GNDN1

PCH_CLKIN_GNDP1

TP_PCH_CL_DATA1

PCH_SRTCRST_L

LPC_R_AD<1>

TP_PCH_CL_CLK1

LPC_R_AD<3>

PCH_CLK100M_SATA_N

PCH_CLK100M_DMI_N

HDA_RST_LHDA_RST_R_L

HDA_SDOUT

LPC_AD<0>

SPI_CLK_R SPI_CLK_1_R

PCH_INTVRMEN_L

RTC_RESET_L

PCH_INTRUDER_L

PCIE_MINI_R2D_C_P

PCIE_T29_D2R_N<2>

HDA_SYNC

HDA_SDOUT_R

ITPXDP_CLK100M_P

TP_PCH_CL_RST1

PCH_CLK14P3M_REFCLK

PCH_CLK100M_SATA_P

PCH_CLK100M_DMI_P

SPI_CS0_R_L


SPI_MISO

XDP_PCH_TMS

TP_SPI_CS1_L

=PP3V3_S0_SATALED

PCIE_MINI_D2R_N

LPC_AD<3>

ITPCPU_CLK100M_N

PCH_CLKIN_GNDN0

SATA_SSD_R2D_C_P

LPC_AD<2>

ITPXDP_CLK100M_N

HDA_BIT_CLK

HDA_SDOUT_R

TP_PCH_CLKOUT_DPP

SML_PCH_1_DATA

SML_PCH_1_CLK

SML_PCH_1_ALERT_L

LPC_R_AD<2>

PCIE_T29_R2D_C_N<3>

PCIE_T29_D2R_P<3>

PCIE_FW_D2R_P

PCIE_T29_D2R_P<0>

PCIE_T29_R2D_C_P<0>

TP_PCIE_R2D_PETP4

TP_PCIE_R2D_PETN4

PCIE_FW_R2D_C_P

TP_PCH_L_VDD_EN

TP_PCH_L_BKLTEN

TP_SATA_E_R2D_CP

TP_SATA_E_R2D_CN

TP_SATA_E_D2RP

TP_SATA_E_D2RN

PCIE_T29_D2R_P<1>

PCIE_T29_R2D_C_N<0>

PCIE_T29_D2R_N<0>

SATA_ODD_D2R_P

SATA_ODD_R2D_C_P

TP_SATA_D_D2RN

TP_SATA_D_R2D_CN

TP_SATA_F_R2D_CN

TP_SATA_F_D2RN

TP_SATA_D_D2RP

PCH_SATA3RBIAS

XDP_PCH_TCK

ENET_MEDIA_SENSE

JTAG_T29_TMS

PCH_SATALED_L

XDP_PCH_TDI

PCIE_MINI_R2D_C_N

PCIE_FW_D2R_N

PCIE_MINI_D2R_PSML_PCH_0_CLK

TOTAL_ETCH_LENGTH=5 MMPCH_XCLK_RCOMP

PCH_GPIO11_SMBALERT_L

ITPCPU_CLK100M_P

SML_PCH_0_ALERT_L

PCH_GPIO11_SMBALERT_L

=PP3V3_S5_PCH

PCIE_ENET_D2R_N

TP_PCH_CLKOUT_DPN

DMI_CLK100M_CPU_P

DMI_CLK100M_CPU_N

PEG_CLK100M_P

SML_PCH_0_ALERT_L

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SATA_HDD_D2R_N

SATA_HDD_D2R_P

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

SATA_ODD_D2R_N

TP_SATA_F_D2RP

TP_SATA_F_R2D_CP

RTC_RESET_L

PCH_CLK32K_RTCX1

HDA_BIT_CLK_R

PCIE_ENET_R2D_C_P

PCIE_ENET_D2R_P

SATA_SSD_R2D_C_N

TP_PCIE_D2R_PERP4

TP_PCIE_D2R_PERN4

SML_PCH_1_ALERT_L

SMC_WAKE_SCI_L

18 OF 110

11.1.0

051-8115

18 OF 98

91

8

91

6 24 79

91

6 22 24

6 21 24

91

80 97

8

15 25

15 25 84 91

18 42

18 97

8

8

8

18 91

18

18 97

8

15

18 91

61 83 91

18 25 90

18 25 90

18 91

18 91

19 22 27 95

18 91

25 91

8

18 97

91

8

91

18 91

91

18 97

18 27 97

18

18 91

18 25 90

8

6 19 22 24

25 91

6 42

11 90 18 25 90

18 91

18

8

8

8

8

8

8

8

8

8

8

8

91

25 91

15 37 92

15 86 96

18 42

25 91

91

18

11 90

18

6 19 21 24

18

8

8

18 27 97

18 91

18

15 21 46 97

www.vinafix.vn

IN

OUT

OUT

OUT

OUT

OUT

IN

BI

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

SUSWARN*/SUSPWRDNACK/GPIO30

DPWROK

DMI3RXP

DMI2RXP

DMI1RXP

DMI0RXP

RSMRST*

APWROK

PWRBTN*

SLP_S3*

DMI_IRCOMP

DMI0TXN

DMI2RXN

DRAMPWROK

FDI_RXN6

FDI_RXN7

FDI_RXP0

FDI_RXP3

FDI_RXP1

FDI_RXP2

FDI_RXP5

FDI_RXP4

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_LSYNC0

FDI_FSYNC1

FDI_LSYNC1

WAKE*

CLKRUN*/GPIO32

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SLP_S5*/GPIO63

SLP_S4*

SLP_A*

SLP_LAN*/GPIO29

TP23

PMSYNCH

DF_TVS

DSWVRMEN

SLP_SUS*

SUSACK*

DMI2TXN

DMI1TXN

DMI0TXP

DMI3TXN

DMI1TXP

DMI2TXP

DMI3TXP

DMI_ZCOMP

SYS_RESET*

SYS_PWROK

PWROK

GPIO31

BATLOW*/GPIO72

RI*

FDI_RXN0

FDI_RXN1

FDI_RXN3

FDI_RXN2

FDI_RXN4

FDI_RXN5

DMI0RXN

DMI3RXN

FDI_RXP6

DMI2RBIAS

DMI1RXN

FDI

DMI

SYSTEM POWER

MANAGEMENT

SYM 3 OF 10

DAC_IREF

CRT_IRTN

CRT_VSYNC

CRT_HSYNC

CRT_DDC_DATA

CRT_DDC_CLK

CRT_RED

CRT_GREEN

CRT_BLUE

RESERVED_1

RESERVED_0

RESERVED_2

RESERVED_28

RESERVED_26

RESERVED_27

RESERVED_23

RESERVED_24

RESERVED_25

RESERVED_22

RESERVED_21

RESERVED_20

RESERVED_18

RESERVED_19

RESERVED_16

RESERVED_15

RESERVED_17

RESERVED_13

RESERVED_14

RESERVED_10

RESERVED_12

RESERVED_11

RESERVED_9

RESERVED_8

RESERVED_6

RESERVED_5

RESERVED_7

RESERVED_3

RESERVED_4

SDVO_TVCLKINP

SDVO_TVCLKINN

SDVO_STALLP

SDVO_STALLN

SDVO_INTP

SDVO_INTN

SDVO_CTRLDATA

SDVO_CTRLCLK

DDPB_AUXN

DDPB_AUXP

DDPB_0N

DDPB_HPD

DDPB_0P

DDPB_1N

DDPB_1P

DDPB_2P

DDPB_2N

DDPB_3N

DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN

DDPC_AUXP

DDPC_HPD

DDPC_0N

DDPC_1P

DDPC_0P

DDPC_1N

DDPC_2P

DDPC_2N

DDPC_3P

DDPC_3N

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXP

DDPD_AUXN

DDPD_HPD

DDPD_0N

DDPD_0P

DDPD_1N

DDPD_1P

DDPD_2N

DDPD_3N

DDPD_2P

DDPD_3P

CRT

DIGITAL DISPLAY INTERFACE

SYM 4 OF 10




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

KEEPING TP, IF NEED TO USE IT LATER

PLACE CLOSE TO U1800 PIN

INTERNAL DP

EXTERNAL DP

SHORT THESE TWO PINS VERY NEAR THE PINSPLACE THE RESISTOR VERY CLOSE TO COMMON POINT

10 90

15

15

15

15

15

2

1R1900

PLACE R1900 AT BALL E31

402

1%

MF-LF

49.9

1/16W

19 33 36 78 97

15 46 48 97

9 91 97

5 46 47 63 97

5 32 46 47 63 97

5 26 32 36 46 47 63 82 97

11 97

19 27 97

25 46 97

19

15 46 97

64 97

19 97

21 64 97

32 64 97

25 27 46 97

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

2

1R1905

5%10K

402MF-LF1/16W

11 97

46 48 97

2

1R1925

MF-LF

1K1%

1/16W

402

2

1R1951

402MF-LF1/16W5%1K

2 1

R1960

MF-LF

NOSTUFF

5%

0

402

1/16W

2

1R1961

5%1/16W

402

10K

MF-LF

2

1R1909

5%10K

1/16WMF-LF402

BC44

J25

BE52

BJ53

BU46

BA47

BP45

BN54

BD43

BH50

BN52

BM53

BH49

BC41

BK38

BJ48

BJ38

BT43

F55

BG43

P43

H43

C49

A46

D47

J41

F43

B43

M43

J43

B47

B45

C46

H41

F45

C42

D51

E49

H46

C52

B51

BR42

BG46

BT37

E31

B31

P41

M41

F38

E37

J38

H38

C36

B37

A32

R38

P38

B35

A36

H36

J36

B33

D33

R47

BC56

AV46

BC46

U1800OMIT

WLCSPCOUGAR-POINT U8

U9

W3

U5

U2

T3

AL17

AL15

U50

U46

U44

H50

Y41

R50

M50

M48

K50

K49

AB46

G56

Y44

L53

AB50

Y50

M49

K46

L56

J55

F53

H52

E52

AB49

AB44

U49

R44

U43

J57

M1

AL8

AL9

N6

R6

E11

B11

B7

C9

C6

D7

D5

B5

N2

AL14

AL12

U14

U12

E4

E2

F3

F5

G2

G4

L2

J3

T1

R8

R9

L5

M3

H8K8

M11

M12

R14

R12

AT3

AR2

AN6

AM6

AR4

AN2

AW1

AW3

AM1

U1800WLCSP

COUGAR-POINT

OMIT

2

1R1915

MF-LF1/16W

402

390K5%

2

1R1920

PLACE R1920 AT BALL A32

402MF-LF1/16W

7501%

2 1

R19900

5%1/16W

402MF-LF

2

1R1981

5%2.2K

402MF-LF1/16W

2 1

R19804.7K

5%1/16WMF-LF402

PCH DMI/FDI/GRAPHICS

TP_PCH_RESERVE_28

LPC_PWRDWN_L

TP_PCH_SLP_SUS_L

TP_PCH_SUSACK_LPCH_DAC_IREF

TP_CRT_IG_VSYNC

PM_SYS_PWRGD

PCH_DF_TVS

PCH_DSWVRMEN

DMI_N2S_N<1>

DMI_N2S_N<3>

PM_SLP_S4_L

PM_SLP_S5_L

PCIE_WAKE_L

DMI_S2N_P<3>

=PP3V3_S5_PCH


TP_PCH_FDI_RX_N<7>

TP_PCH_FDI_RX_P<0>

TP_PCH_FDI_RX_N<3>

TP_CRT_IG_RED

PM_SYNC

TP_PCH_RESERVE_0

TP_PCH_FDI_RX_P<1>

TP_PCH_FDI_RX_P<4>

PCH_FDI_INT

PCH_FDI_FSYNC<0>

PCH_FDI_FSYNC<1>

DMI_S2N_P<2>

TP_PCH_FDI_RX_N<4>

DMI_N2S_N<2>

PM_PCH_PWRGD

PM_MEM_PWRGD

PCH_GPIO31_ACPRESENT

PP3V3_G3H_RTC

TP_PCH_FDI_RX_P<5>

TP_PCH_FDI_RX_P<7>

TP_PCH_RESERVE_8

TP_PCH_RESERVE_9

DMI_N2S_P<3>

DMI_S2N_P<0>

=PP3V3_S5_PCHPCH_DSWVRMEN

CPU_PROC_SEL

=PP1V8_S0_PCH

TP_PCH_RESERVE_27

PCH_DF_TVS

SMC_ADAPTER_EN

PM_CLK32K_SUSCLK_R

PM_SLP_S3_L

TP_PM_SLP_A_L

PCH_GPIO29_SLP_LAN_L

PM_RSMRST_PCH_L

DMI_S2N_N<0>

TP_PCH_TP23

TP_PCH_RESERVE_18

TP_PCH_RESERVE_17

TP_PCH_RESERVE_15

TP_PCH_RESERVE_22

TP_CRT_IG_HSYNC

TP_CRT_IG_DDC_DATA

TP_CRT_IG_DDC_CLK

TP_CRT_IG_GREEN

TP_CRT_IG_BLUE

TP_PCH_RESERVE_1

TP_PCH_RESERVE_2

TP_PCH_RESERVE_26

TP_PCH_RESERVE_23

TP_PCH_RESERVE_24

TP_PCH_RESERVE_25

TP_PCH_RESERVE_21

TP_PCH_RESERVE_20

TP_PCH_RESERVE_19

TP_PCH_RESERVE_16

TP_PCH_RESERVE_13

TP_PCH_RESERVE_14

TP_PCH_RESERVE_10

TP_PCH_RESERVE_12

TP_PCH_RESERVE_11

TP_PCH_RESERVE_6

TP_PCH_RESERVE_5

TP_PCH_RESERVE_7

TP_PCH_RESERVE_3

TP_PCH_RESERVE_4

TP_SDVO_TVCLKINP

TP_SDVO_TVCLKINN

TP_SDVO_STALLP

TP_SDVO_STALLN

TP_SDVO_INTP

TP_SDVO_INTN

TP_DP_IG_B_DDC_DATA

TP_DP_IG_B_DDC_CLK

TP_DP_IG_B_AUX_N

TP_DP_IG_B_AUX_P

TP_DP_IG_B_MLN<0>

TP_DP_IG_B_HPD

TP_DP_IG_B_MLP<0>

TP_DP_IG_B_MLN<1>

TP_DP_IG_B_MLP<1>

TP_DP_IG_B_MLP<2>

TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLN<3>

TP_DP_IG_B_MLP<3>

TP_DP_IG_C_CTRL_CLK

TP_DP_IG_C_CTRL_DATA

TP_DP_IG_C_AUX_N

TP_DP_IG_C_AUX_P

TP_DP_IG_C_HPD

TP_DP_IG_C_MLN<0>

TP_DP_IG_C_MLP<1>

TP_DP_IG_C_MLP<0>

TP_DP_IG_C_MLN<1>

TP_DP_IG_C_MLP<2>

TP_DP_IG_C_MLN<2>

TP_DP_IG_C_MLP<3>

TP_DP_IG_C_MLN<3>

TP_DP_IG_D_CTRL_CLK

TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_AUXP

TP_DP_IG_D_HPD

TP_DP_IG_D_MLP<0>

TP_DP_IG_D_MLN<1>

TP_DP_IG_D_MLP<1>

TP_DP_IG_D_MLN<2>

TP_DP_IG_D_MLN<3>

TP_DP_IG_D_MLP<2>

TP_DP_IG_D_MLP<3>

TP_PCH_FDI_RX_N<5>

DMI_N2S_P<2>

DMI_S2N_N<2>

PM_PWRBTN_L

PCH_GPIO31_ACPRESENT

TP_PCH_FDI_RX_N<2>

TP_PCH_FDI_RX_N<6>

TP_PCH_FDI_RX_N<1>

TP_PCH_FDI_RX_N<0>

DMI_S2N_P<1>

DMI_N2S_P<0>

PCH_FDI_LSYNC<0>

PCH_GPIO30_SUSWARN_L

PM_CLKRUN_L

PM_BATLOW_L

PM_SYSRST_L

PCH_FDI_LSYNC<1>

DMI_N2S_P<1>

PM_DSW_PWRGD

PCIE_WAKE_L

=PP3V3_S5_PCH

DMI_N2S_N<0>

TP_DP_IG_D_MLN<0>

TP_DP_IG_D_AUXN

TP_PCH_FDI_RX_P<6>

PCH_RI_L

PM_RSMRST_PCH_L

PM_ASW_PWRGD

PM_DSW_PWRGD

TOTAL_ETCH_LENGTH=5 MM

PCH_DMI_COMP

PCH_DMI2RBIAS

DMI_S2N_N<3>

DMI_S2N_N<1>

TP_PCH_FDI_RX_P<3>

TP_PCH_FDI_RX_P<2>

19 OF 110

11.1.0

051-8115

19 OF 98

8

19 97

19 97

6 18 19 21 24

6 18 22 24

8

8

8

8

8

8

8

19

18 22 27 95

8

8

6 18 19 21 24 19 97

11 97

6

19 97

46 47 97

15

19 27 97

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

15

19 97

19 33 36 78 97

6 18 19 21 24

8

8

8

91

91

8

8

www.vinafix.vn

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

USBP2P

USBP3N

USBP3P

USBP4N

USBP4P

USBP5P

USBP5N

USBP6P

USBP6N

USBP7P

USBP7N

USBP8N

USBP8P

USBP9N

USBP9P

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

USBRBIAS

USBRBIAS*

OC0*/GPIO59

OC1*/GPIO40

OC2*/GPIO41

OC3*/GPIO42

OC4*/GPIO43

OC5*/GPIO9

OC6*/GPIO10

OC7*/GPIO14

AD6

AD7

AD9

AD8

AD12

AD10

AD11

AD14

AD13

AD17

AD16

AD15

AD18

AD19

AD20

AD22

AD21

AD24

AD23

AD25

AD27

AD26

AD29

AD28

AD30

C/BE0*

AD31

C/BE2*

C/BE1*

PIRQA*

C/BE3*

PIRQB*

PIRQC*

PIRQD*

REQ0*

REQ1*/GPIO50

REQ3*/GPIO54

REQ2*/GPIO52

GNT1*/GPIO51

GNT0*

GNT2*/GPIO53

PIRQE*/GPIO2

GNT3*/GPIO55

PIRQG*/GPIO4

PIRQF*/GPIO3

PCIRST*

PIRQH*/GPIO5

PERR*

SERR*

PAR

IRDY*

DEVSEL*

FRAME*

PLOCK*

STOP*

TRDY*

PME*

CLKOUT_PCI0

PLTRST*

CLKOUT_PCI2

CLKOUT_PCI1

CLKOUT_PCI3

CLKOUT_PCI4

USBP0P

USBP0N

USBP1P

USBP1N

USBP2N

AD1

AD0

AD2

AD3

AD4

AD5

PCI

USB

SYM 5 OF 10




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PCH SATA PORT 1 OPTION SELECT IS ODD OR SSD

PLACE THE RESISTOR CLOSE TO COMMON POINT

USB CAMERA

Unused

TIE TRACES TOGETHER CLOSE TO PINS

Unused

Unused

Unused

USB HUB 1

Unused

Unused

Unused

USB HUB 2

Unused

Unused

Unused

Unused

K60E MLB CFG SELECT

2

1R2065PRODUCTION

1/16W

10K5%

402MF-LF

2

1R2063

402

5%10K

1/16WMF-LF

21R2017 ODD_SATA:P2

1/16W 402MF-LF5%

10K

21R2098 ODD_SATA:P1

402MF-LF

10K5% 1/16W

21R2018402MF-LF1/16W

10K5%

T29

21R2099 10K4021/16W MF-LF5%

NO_T29

34 92

34 92

8

8

8

8

8

8

8

8

8

8

8

8

35 92

35 92

8

8

2

1R206610K

402

1/16WMF-LF

5%

2

1R2064

402

10K

1/16W5%

MF-LF2

1R2062

402MF-LF

5%10K

1/16W

2

1R2061

MF-LF1/16W5%

402

10K8

8

8

8

2

1R207022.6

1%

MF-LF1/16W

402

PLACE R2070 AT BALL BM25

21R20101/16W5% 402

10KMF-LF

21R20111/16W5%

10K402MF-LF

21R2012 10K1/16W5% 402MF-LF

21R2013 10KMF-LF5% 4021/16W

21R20155% 1/16W 402MF-LF

10K

21R2016402

10K5% MF-LF1/16W

21R2020 10K5% 402MF-LF1/16W

21R2021 10KMF-LF 4021/16W5%

21R2022 10K5% 4021/16W MF-LF

27 97

27 91

27 91

27 91

21R2023 10K5% MF-LF1/16W 402

21R20245%

10KMF-LF1/16W 402

21R2026 10K5% 1/16W MF-LF 402

21R20251/16W5% MF-LF

10K402

21R20271/16W5% MF-LF

10K402

8

8

8

8

21R2030MF-LF1/16W

10K5% 402

21R20311/16W

10K402MF-LF5%

44 92

44 92

BP25

BM25

BT27

BR26

BR29

BN27

BD31

BF31

BJ33

BK33

BM30

BN29

BT31

BR32

BU32

BT33

BM35

BM33

BA33

BC33

BK27

BJ27

BD27

BF27

BK31

BJ31

BJ25

BK25

BD36

BF36

BC8

BC12

BR6

AV11

BK8

BT5

BG5

AV15

BK48

BA17

BR4

BT15

AV9

BN9

BP5

BM15

BJ5

BK10

BM3

AV14

BH8

BM45

BT45

BJ41

BP43

BK43

BG41

BD41

BM43

BF11

BE2

BU12

AV8

BA15

BC11

BH9

AT14

AT17

AT12

AN14

AT11

BP13

BG2

BP7

BN4

BJ3

BR12

BU9

BJ12

BN11

BG12

BK12

AV17

BT13

BF8

BA8

BF9

BA9

BM13

BC2

BL4

BC4

BL2

BA14

BT7

BT11

BC6

BG15

BE6

BE4

BN2

BF3

BM8

BJ10

BR9

BF17

BF15 U1800WLCSP

COUGAR-POINT

OMIT

2

1R2068

1/16W5%

402MF-LF

10K

2

1R2060

5%

402

1/16WMF-LF

10K

PCH PCI/FLASHCACHE/USBSYNC_DATE=01/06/2011SYNC_MASTER=K62

=PP3V3_S0_PCH_GPIO

=PP3V3_S0_PCH_GPIOPCI_REQ2_L

PCI_REQ3_L

PCI_STOP_L

PCI_REQ3_L

PCI_REQ2_L

TP_PCI_AD<25>

TP_PCI_AD<27>

TP_PCI_AD<28>

TP_PCI_AD<29>

PCI_REQ0_L

PCI_INTB_L

PCI_INTA_L

PCI_INTD_L

PCH_PCI_GNT3_L

T29_MCU_INT_L

PCI_PERR_L

TP_PCI_PAR

TP_PCI_AD<11>

TP_PCI_AD<12>

TP_PCI_AD<13>

TP_PCI_AD<10>

TP_PCI_AD<9>

TP_PCI_AD<8>

TP_PCI_C_BE_L<0>

TP_PCI_AD<21>

AP_PWR_EN

SDCONN_STATE_CHANGE

T29_DP_PORTA_PWR_EN

TP_USB_10N

USB_CAMERA_P

PLT_RESET_L

TP_PCI_AD<23>

USB_HUB2_UP_N

TP_USB_7P

TP_USB_6P

TP_PCI_AD<3>

=PP3V3_S5_PCH_GPIO

TP_PCI_C_BE_L<1>

TP_PCI_C_BE_L<2>

PCI_INTC_L

USE_HDD_OOB_L

AUD_I2C_INT_L

PCI_SERR_L

TP_PCI_RESET_L

TP_USB_10P

TP_USB_11P

TP_USB_12P

TP_PCI_AD<0>

TP_PCI_AD<6>

TP_PCI_AD<22>

TP_USB_11N

TP_PCI_CLK33M_OUT2

TP_PCI_CLK33M_OUT3

PCH_CLK33M_PCIOUT

LPC_CLK33M_LPCPLUS_R

LPC_CLK33M_SMC_R

TP_PCI_PME_L

TP_PCI_C_BE_L<3>

TP_PCI_AD<24>

TP_PCI_AD<20>

TP_PCI_AD<19>

TP_PCI_AD<4>

TP_PCI_AD<17>

TP_PCI_AD<15>

TP_PCI_AD<5>

TP_PCI_AD<18>

TP_PCI_AD<7>

TP_PCI_AD<16>

TP_USB_2N

TP_USB_5N

TP_PCI_AD<1>

TP_USB_5P

TP_USB_6N

USB_HUB2_UP_P

TP_PCI_AD<14>

TP_USB_3P

TP_USB_3N

TP_USB_4P

TP_USB_4N

TP_USB_7N

TP_USB_2P

USB_HUB1_UP_P

TP_PCI_AD<31>

TP_USB_13P

AUD_IP_PERIPHERAL_DET

TP_USB_1P

TP_USB_1N

USB_HUB1_UP_N

TP_PCI_AD<2>

TP_PCI_AD<26>

TP_PCI_AD<30>

PCH_PCI_GNT2_L

PCH_PCI_GNT1_L

PCH_PCI_GNT0_L

TP_USB_12N

PCH_USB_RBIAS

USB_CAMERA_N

TP_USB_13N

USB_HUB_SOFT_RESET_L

PCH_GPIO14_OC7_L

PCH_GPIO10_OC6_L

T29_DP_PORTB_PWR_EN

ENET_PWR_ENPCI_REQ1_L

PCI_TRDY_L

PCI_PLOCK_L

PCI_FRAME_L

PCI_DEVSEL_L

PCI_IRDY_L

=PP3V3_S0_PCH_GPIO

20 OF 110

11.1.0

051-8115

20 OF 98

6 20 45

6 20 45 20 91

20 91

20 91

20 91

8

8

8

8

91

15

84 91

8

8

8

8

8

8

8

8

8

25 33 97

25 45 97

25 82 91 97

8

8

6

8

8

51 97

62 97

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

61 97

8

8

8

15

15

15

91

25 34 97

25

25

25 91

25 36 97 91

6 20 45

www.vinafix.vn

OUT

ININ

OUT

OUT

IN

PWM3

SST

PWM2

PWM1

PWM0

VSSADAC

TS_VSS3

TS_VSS4

TS_VSS2

VSS_NCTF_13

TS_VSS1

VSS_NCTF_12

VSS_NCTF_11

VSS_NCTF_8

VSS_NCTF_10

VSS_NCTF_9

VSS_NCTF_6

VSS_NCTF_7

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_3

VSS_NCTF_1

VSS_NCTF_2

VSS_NCTF_0

INIT3_3V*

NC_1

TP36

TP35

TP34

TP33

TP32

TP31

TP30

TP28

TP29

TP27

TP26

TP25

TP24

TP22

TP21

TP20

TP19

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP10

TP9

TP8

TP7

TP5

TP6

TP4

TP3

TP2

TP1

PROCPWRGD

THRMTRIP*

RCIN*

PECI

TACH1/GPIO1

TACH2/GPIO6

BMBUSY*/GPIO0

CLKOUT_PCIE6P

CLKOUT_PCIE7N

CLKOUT_PCIE6N

TACH7/GPIO71

TACH6/GPIO70

GPIO57

TACH4/GPIO68

SDATAOUT1/GPIO48

SATA5GP/GPIO49

PCIECLKRQ7*/GPIO46

PCIECLKRQ6*/GPIO45

SDATAOUT0/GPIO39

SLOAD/GPIO38

SATA2GP/GPIO36

GPIO35

GPIO28

GPIO27

SCLOCK/GPIO22

GPIO24/MEM_LED

TACH0/GPIO17

GPIO8

LAN_PHY_PWR_CTRL/GPIO12

TACH3/GPIO7

A20GATE

CLKOUT_PCIE7P

SATA4GP/GPIO16

GPIO15

STP_PCI*/GPIO34

TP18

TACH5/GPIO69

SATA3GP/GPIO37

RSVD

GPIO

SYM 6 OF 10

MISC

NCTF

CPU

D

GS




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

This has internal pull up and should not pulled low.

THIS SIGNAL IS INTEDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

Place this near the T point

MXM CLKREQ ISOLATION

11 25 97

47 97

2

1R2155

402MF-LF1/16W5%10K

2

1R215010K

5%

MF-LF1/16W

402

15

6 15 91

25 32 97

2

1R219047K

MF-LF

5%

402

1/16W

48

AU2

BU52

BU4

BT2

BP57

BP1

BM57

BM1

B2

F1

D1

BU6

BU54

A6

A4

D57

F57

A52

A54

AB17

AB18

Y17

Y18

L36

M38

D25

B27

E27

E29

B25

C26

F28

L33

C29

J22

L25

L27

J31

L22

J27

H31

Y12

L31

Y14

AY36

BA36

AE50

AE43

AE41

AE49

BC49

BA27

BM46

P22

E56

BP15

BN17

BM18

BU16

BR16

BA22

BR19

BT17

BL56

BC43

BE54

AW53

BF55

BA53

BA56

AU56

BG53

BB55

BG56

BN19

BM20

BT21

BN21

D53

H48

BP55

AV44

AY20

BK50

BN56

BP51

BT53

BJ57

BJ55

BJ43

BP53

BM55

AF1

AE2

AA2

AB3AW55

BB57

U1800WLCSP

OMIT

COUGAR-POINT

21

R2170NOSTUFF

1/16W5%402

MF-LF

0

21

R2140

1/16W5%402

MF-LF

0

21

R2134

4025%

MF-LF1/16W

0

21

3

Q2100

SOD-VESM-HF

SSM3K15FV

21

R2160NOSTUFF

0MF-LF

4025%

1/16W

2

1R2161

MF-LF

5%10K

402

1/16W

5

4

1

2

3

U2100SOT23-5-HF

MC74VHC1G08

2

1C21100.1UF

CERM402

10V20%

PCH MISCSYNC_MASTER=K62 SYNC_DATE=01/06/2011

AUD_IPHS_SWITCH_EN

PM_PCH_PWRGD

AUD_IPHS_SWITCH_EN_PCH

=PP3V3_S3_PCH

PCH_GPIO8


LPCPLUS_GPIO

ODD_PWR_EN_L

PCH_GPIO24

SMC_WAKE_SCI_L

TP_PCH_TP15

FW_PME_L

BLC_GPIO

PCH_GPIO7_TACH3

ENET_LOW_PWR

PCH_GPIO15

PCH_GPIO49_SATA5GP

SPIROM_USE_MLB

SDCARD_RESET

PCH_PEG_CLKREQ_L PEG_CLKREQ_L

=PP3V3_S5_PCH=PP3V3_S0_MXM

JTAG_T29_TDI

=PP3V3_S0_PCH

PCH_A20GATE

FW_PWR_EN


PCH_PECI

PCH_GPIO0_BMBUSY_L

SMC_RUNTIME_SCI_L

ISOLATE_CPU_MEM_L

T29_SW_RESET_L

MXM_GOOD

PCH_GPIO36_SATA2GP

JTAG_T29_TCK

JTAG_T29_TDO

PCH_PEG_CLKREQ_L

T29_CLKREQ_L

ENET_SW_RESET_L

PCH_GPIO70_TACH6

PCH_GPIO71_TACH7

TP_PCH_TP12

TP_PCH_PWM0

PM_THRMTRIP_L

TP_PCH_TP20

TP_PCH_TP16

TP_PCH_TP17

TP_PCH_TP9

TP_PCH_TP10

CPU_PECI

TP_PCH_PWM1

PCH_INIT3V3_L

TP_PCH_TP5

TP_PCH_TP24

TP_PCH_TP25

TP_PCH_TP26

TP_PCH_TP27

TP_PCH_TP28

TP_PCH_TP30

TP_PCH_TP31

TP_PCH_TP32

TP_PCH_TP33

TP_PCH_TP34

TP_PCH_TP35

TP_PCH_TP8

TP_PCH_TP14

TP_PCH_TP36

TP_PCH_NC

CPU_PWRGD

TP_PCH_TP3

TP_PCH_TP2

TP_PCH_TP13

TP_PCH_TP18

TP_PCH_TP11

TP_PCH_TP1

TP_PCH_TP7

TP_PCH_TP29

TP_PCH_TP22

TP_PCH_TP19

TP_PCH_SST

TP_PCH_PWM3

TP_PCH_TP21

TP_PCH_PWM2




=PP3V3_S0_PCH

TP_PCH_TP4

TP_PCH_TP6

PCH_RCIN_L

PCH_PROCPWRGD

21 OF 110

11.1.0

051-8115

21 OF 98

62 97

19 64 97

21 25 91

6

15

21 25 91

15 42 97

15 18 46 97

15 39 97

15

15 37 97

15 25

15 25

48 91

15 44 97 98

21 91 9

6 18 19 24 6 64 75 76

15 86 96

6 18 21 24

15 97

8

15 25

46 47 97

15 80 91

5 25 97

15 25

15 25 86 96

15 86 96

21 91

15 80 91

15 36 91

15

15

8

11 46 97

8

15

8

8

8

8

8

8

6 18 21 24

97

www.vinafix.vn

VCCIO_14

DCPSUSBYP

VCCACLK

DCPRTC

DCPRTC_NCTF

VCCVRM_2

VCCADPLLA

VCCADPLLB

DCPSST

DCPSUS_0

DCPSUS_2

DCPSUS_1

VCC3_3_6

V_PROC_IO

VCCDFTERM_1

VCCDIFFCLKN_2

VCCDIFFCLKN_1

VCCDIFFCLKN_0

VCCDSW3_3

VCCSPI

VCCSSC_0

VCCSSC_1

VCCRTC

VCCDFTERM_0

V_PROC_IO_NCTF

VCC3_3_5

VCCSUS3_3_0

VCCSUS3_3_1

VCCSUS3_3_2

VCCSUS3_3_3

VCCSUS3_3_4

VCCSUS3_3_5

VCCSUS3_3_6

VCCSUS3_3_7

VCCSUS3_3_8

VCCSUS3_3_9

VCCSUS3_3_10

V5REF_SUS

V5REF

VCC3_3_8

VCC3_3_9

VCCSUSHDA

VCCIO_8

VCCIO_15

VCCIO_4

VCCIO_13

VCCIO_7

VCCIO_6

VCCIO_5

VCC3_3_4

VCC3_3_7

VCCIO_12

VCCAPLLSATA

VCCVRM_3

VCCIO_0

VCCIO_3

VCCIO_1

VCCIO_2

SATA

HDA

CPU

PCI/GPIO/LPC

USB

CLOCK AND MISCELLANEOUS

RTC

SYM 10 OF 10

PCI/GPIO/LPC

VCCCORE_15

VCCASW_4

VCCASW_5

VCCASW_6

VCCASW_7

VCCASW_8

VCCASW_1

VCCASW_2

VCCASW_3

VCCAPLLDMI2

VCCAFDIPLL

VCC3_3_2

VCC3_3_1

VCC3_3_3

VCCCORE_20

VCCCORE_21

VCCCORE_19

VCCCORE_18

VCCCORE_14

VCCCORE_13

VCCCORE_12

VCCASW_20

VCCASW_10

VCCASW_11

VCCASW_12

VCCASW_13

VCCASW_14

VCCASW_15

VCCASW_16

VCCASW_17

VCCASW_18

VCCASW_19

VCCASW_9

VCCVRM_0

VCCASW_22

VCCASW_21

VCCDMI_1

VCCVRM_1

VCCADAC

VCCCORE_2

VCCCORE_3

VCCCORE_4

VCCCORE_5

VCCCORE_6

VCCCORE_7

VCCCORE_8

VCCCORE_9

VCCCORE_10

VCCCORE_11

VCCCORE_0

VCCCORE_1

VCCAPLLEXP

VCCDMI_0

VCCIO_16

VCCIO_28

VCCIO_17

VCCIO_9

VCCIO_23

VCCIO_10

VCCIO_22

VCCIO_19

VCCIO_26

VCCASW_0

VCCIO_27

VCC3_3_0

VCCCORE_17

VCCCORE_16

VCCCLKDMI

VCCIO_30

VCCIO_31

VCCIO_24

VCCIO_25

VCCIO_11

VCCIO_29

VCCIO_20

VCCIO_21

VCCIO_18VCCIO_PCIE

VCCASW

VCCIO_DMI/CLK

SMY 7 OF 10

CRT

DMI

VCC CORE

HVCMOS

FDI




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

10 mA Max, 1mA Idle

40mA Max, 5mA Idle

1.61A Max, 433mA Idle

PCH output, for decoupling only

Need to check layout decoupling

40mA Max, 10mA Idle

Max and Idle = 1mA

105mA Max, 90mA Idle

Max and Idle = 1mA

PCH output, for decoupling only

57 mA Max, 30mA Idle

97mA Max, 15mA Idle

(VCCSUS3_3 - 11 TOTAL)

(VCC3_3[1-9] total)

1.44 A Max, 474mA Idle

20mA Max, 1mA Idle

Max and Idle = 1mA

55mA Max, 5mA Idle

3mA Max, 1mA Idle



(VCCVRM 4 total)159mA Max, 114mA Idle

Max and Idle = 1 MA

(VCCIO[1-31] total)3.456A Max, 426mA Idle

20mA Max, 10mA Idle

2

1 C2210

20%0.1UF

402

10V

PLACE C2210 AT BR54

CERM

2

1 C2222

20%10VCERM402

0.1UF

PLACE CAP AT BALL BA46

2

1 C2230

CERM

20%

402

0.1UFNOSTUFF10V

PLACE C2230 AT BALL A39

R2

R54

AV28

AU38

AT40

BM36

BK36

BJ36

AY33

AY31

AV32

BT35

AV30

U31

AE20

AC20

AN52

BU42

AJ38

AN41

AN40

AL40

AG41

AY27

AY25

AG40

AG38

BA38

AE40

AV26

AV24

AV40

AG15

AE17

AE15

T57

T55

U56

AC2

AB1

AL5

AV20

AU20

A12

AU22

AN38

AL38

B56

D55

BT25

BF1

AV41

A39

AT41

AA32

BA46

BT56

BR54

U1800COUGAR-POINT

OMIT

WLCSP

R56

AJ1

Y36

Y22

Y20

V22

Y34

Y32

Y30

Y26

Y24

V33

V31

V27

V25

F30

F20

AA36

AA34

Y28

V36

B41

E41

AE34

AE32

AE30

AE28

AE24

AC32

AC30

AR34

AR32

AC28

AN34

AN32

AL34

AL32

AJ36

AJ34

AJ32

AG34

AG32

AE36

AC26

AC24

AJ20

AL24

AJ28

AJ26

AJ24

AG28

AG26

AG24

AU36

AU30

AR38

AU34

AR36

AR30

AR28

AR26

AR24

AN28

AN26

AN24

AN22

AL28

AV36

AU32

B53

A19

C54

AT1

BD20

BD17

BC17

AF57

U1800WLCSP

OMIT

COUGAR-POINT

2

1 C2232

10V20%

402CERM

0.1UF

PLACE C2231 AT BALL BU42

2

1 C2231

402CERM6.3V

1UF

PLACE C2232 AT BALL BU42

10%

PCH POWER

PP1V05_S0_PCH_VCCAPLL_EXP_F

PP1V8R1V5_S0_PCH_VCCVRM_F

PP1V05_S0_PCH_VCCADPLLB_F




=PP3V3R1V8_S0_PCH_VCCDFTERM


PP3V3_G3H_RTC





=PP5V_S0_PCH_V5REF

PP1V05_S0_PCH_VCCAPLL_SATA_F



=PP5V_S5_PCH_V5REFSUS


PP3V3_S0_PCH_VCCA_DAC_F

PP1V05_S0_PCH_VCCADPLLA_F




PPVOUT_S5_PCH_DCPSUSMIN_LINE_WIDTH=0.2 mm

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 mm

TP_DCPSUS_0


PP1V05_S0_PCH_VCCAPLLDMI2_F



PP1V05_S0_PCH_VCCCLKDMI_F


TP_1V05_S0_PCH_FDIPLL

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mmPPVOUT_G3_PCH_DCPRTC

MIN_LINE_WIDTH=0.2 mm

TP_1V05_S0_PCH_VCCA_CLK

TP_PPVOUT_PCH_DCPSUSBYP

MIN_LINE_WIDTH=0.2 mm VOLTAGE=3.3VPPVOUT_S0_PCH_DCPSSTMIN_NECK_WIDTH=0.2 mm

TP_DCPSUS_1



PP3V3R1V5_PCH_VCCSUSHDA

22 OF 110

11.1.0

051-8115

22 OF 98

24 95

22 24 95

17 95

22 24 95

6 24

6 24

6 24

6 24

18 19 27 95

6 24

6 24

6 24

6 18 19 24

24

24 95

6 24

6 24

24

22 24 95

17 95

17 95

6 24

6 24

22 24 95

95

6 24

24 95

6 24

6 24

24 95

6 24

95

95

6 24

6 18 24

24 95

www.vinafix.vn

VSSVSS

SYM 8 OF 10

VSSVSS

SYM 9 OF 10




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

AU26

AU24

AT8

AT6

AT52

AT47

AT43

AT18

AT15

AR6

AA20

AR52

AR22

AR20

AN9

AN54

AN47

AN43

AN4

AN36

AN30

A9

AN20

AN18

AN17

AN15

AN12

AN11

AM57

AM52

AM3

AL47

A49

AL46

AL41

AL36

AL30

AL26

AL22

AL20

AL18

AL11

AK6

A42

AK52

AJ57

AJ30

AJ22

AH6

AH52

AG53

AG50

AG5

AG46

A29

AG44

AG43

AG36

AG30

AG22

AG20

AG14

AG11

AF6

AF52

A26

AE9

AE8

AE47

AE4

AE38

AE26

AE22

AE18

AE14

AC54

AY22

AC4

AC38

AC36

AC34

AC22

AB6

AB57

AB52

AB47

AB43

C12

AB41

AB40

AB15

AB11

AA38

BG36

BG33

BG31

BG27

BG25

BG22

BF6

BF52

BF46

AA30

BF43

BF41

BF33

BF25

BF20

BF12

BD33

BD25

BC9

BC47

AA28

BC38

BC36

BC31

BC27

BC20

BC15

BC14

BB6

BB52

BB3

AA26

BB1

BA49

BA44

BA41

BA31

BA12

BA11

B23

AY6

AY38

AA24

AW57

AV6

AV47

AV38

AV34

AV22

AV18

AV12

AU5

AU28

AA22

BR36

AE56

U1800WLCSP

COUGAR-POINT

OMIT

P25

R25

P36

R36

AL44

AL43

Y6

Y52

Y49

Y47

Y46

Y43

Y40

Y38

Y15

Y11

W57

W55

W1

V6

V38

V20

U53

U47

U41

U38

U36

U33

U27

U25

U22

U20

U17

U15

U11

T6

T52

R49

R46

R43

R41

R4

R22

R17

R15

R11

N54

N4

M9

M8

M6

M57

M52

M46

M36

M33

M31

M27

M25

M22

M20

L43

L41

L38

L17

L12

K9

K6

K52

J53

J5

J48

J46

J33

J1

H6

H33

H27

H25

H22

H20

H15

G54

F8

F50

F48

F46

F42

F40

F36

F35

F33

F32

F26

F22

F16

F12

F10

E9

E6

E54

E39

E19

D45

D43

D35

D3

D23

D15

C4

C39

C32

C19

BU39

BU36

BU29

BU26

BU19

BR52

BR22

BP35

BP33

BP3

BN6

BN47

BN31

BM5

BM48

BM42

BM40

BM32

BM28

BM26

BM23

BM22

BM16

BM12

BM10

BK6

BK52

BK41

BK20

BJ15

BJ1

BH6

BH52

BG38 U1800COUGAR-POINT

WLCSP

OMIT

PCH GROUNDSSYNC_DATE=01/06/2011SYNC_MASTER=K62

23 OF 110

11.1.0

051-8115

23 OF 98

www.vinafix.vn

NC

NC

NC

NC




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PLACEMENT_NOTE:

PLACEMENT_NOTEs (all 3):

PLACEMENT_NOTEs:

PLACEMENT_NOTEs:

PCH VCCCORE BYPASS

PLACEMENT_NOTE:

(PCH DMI 1.05V PWR)

PCH VCCIO BYPASS

(PCH 1.05V CORE PWR)

1 mA

PCH VCCSATAPLL Filter

PLACEMENT_NOTE:

(PCH SATA PLL PWR)

PLACEMENT_NOTEs:

PLACEMENT_NOTEs:

(PCH USB 1.05V PWR)

PLACEMENT_NOTEs:

PCH V5REF_SUS Filter & Follower

PLACEMENT_NOTEs:

PLACEMENT_NOTEs:

PLACEMENT_NOTE:

PLACEMENT_NOTEs:

PLACEMENT_NOTEs:

PLACEMENT_NOTE:

PLACEMENT_NOTE:

(PCH Reference for 5V Tolerance on PCI)

(PCH Reference for 5V Tolerance on USB)1 mA S0-S5

<1 MA

PCH VCC3_3 BYPASS

(PCH PCI 3.3V PWR)

PLACEMENT_NOTEs:

PLACEMENT_NOTE:

(PCH SUSPEND USB 3.3V PWR)

PCH VCCSUS3_3 BYPASS

PCH VCCIO BYPASS

PLACEMENT_NOTEs:

PLACEMENT_NOTEs:

PLACEMENT_NOTE:

PLACEMENT_NOTE:

PCH V5REF Filter & Follower

(PCH HD Audio 3.3V/1.5V PWR)

PCH VCCSUSHDA BYPASS

PLACEMENT_NOTEs:

<1 MA S0-S5

2

1C2439

X5R

10%10V

402

1UF

PLACE C2439 AT BALL BF1

1

2R2405

MF-LF1/16W

402

5%100

2

1C2438

PLACE C2438 AT BALL BT25

10V

0.1UF

CERM402

20%

6

1

D2400BAT54DW-X-GSOT-363

1

2R240410

1/16WMF-LF

5%

4023

4

D2400

SOT-363BAT54DW-X-G

2

1 C2409NOSTUFF

X5R16V10%

402

1UF

PLACE C2409 AT BALL U56

21

R2400

402MF-LF

0

5%1/16W

2

1 C24230.1UF

PLACE C2423 AT BALL AF57 402X5R16V10%

2

1 C24400.1UF

10VCERM

20%

PLACE C2440 AT BALL T55402

2

1 C2441

PLACE C2441 AT BALL AV2810V

402CERM

20%0.1UF

2

1 C2450

6.3V10%

402CERM

1UF

PLACE C2450 AT BALL AV26

2

1 C2419

CERM6.3V

1UF10%

402

PLACE C2419 AT BALL B41

2

1 C24210.1UF

402PLACE C2421 AT BALL A12X5R

10%16V

2

1 C2422

PLACE C2422 AT BALL AU20

10%

402

6.3V

1UF

CERM

2

1 C2449

6.3V10%1UF

402CERM

PLACE C2449 AT BALL AY27

2

1 C2413

PLACE C2413 AT BALL BT35

402X5R

0.1UF

16V10%

2

1 C24552.2UF

603


16V10%

X5R

2

1 C2417

PLACE C2417 AT BALL D55

X5R16V10%

402

0.1UF

2

1C2416

402

20%

X5R6.3V

4.7UF

PLACE C2416 AT BALL D55

21

L2401NOSTUFF

1210

1.0UH-0.5A

2

1C2400

X5R-CERM

10UF10%16V

NOSTUFF

0805

21

L2404

1210

NOSTUFF

1.0UH-0.5A

2

1C2406

16V

NOSTUFF

10UF

0805X5R-CERM

10%

2

1C2408

X5R-CERM16V

NOSTUFF

10UF

0805

10%

21

L240510UH-0.45A

NOSTUFF

1210

2

1 C2484

PLACE C2484 AT BALL U31

0.1UF

402

16VX5R

10%

2

1 C2485

PLACE C2485 AT BALL AL38

402

0.1UF

25V10%

X5R

2

1C2410

805-1

PLACE C2410 AT BALL Y20

6.3V20%

10UF

CERM2

1 C2463

402CERM6.3V10%1UF

PLACE C2463 AT BALL V25

2

1C2480

805-1

PLACE C2480 AT BALL AC20

20%10UF

CERM6.3V

2

1 C24751UF10%6.3VCERM402

PLACE C2475 AT BALL AE20

2

1C2437

805-1


6.3V20%

CERM

10UF

2

1 C2435

CERM402

6.3V10%1UF


2

1 C2434

10%

CERM402

6.3V

1UF


2

1C2471

PLACE C2471 AT BALL AA34

CERM6.3V20%

10UF

805-1

2

1 C2469


402

6.3VCERM

1UF10%

2

1 C2414

CERM402


6.3V10%1UF

2

1C2401

805

10UF

CERM

20%6.3V


2

1 C2487

6.3V

1UF

CERM402

10%PLACE C2487 AT BALL E41

2

1 C2489

6.3V10%1UF

NOSTUFF

CERM


402

2

1 C2488

PLACE C2488 AT BALL A19CERM

10%

402

1UF

NOSTUFF

6.3V

2

1 C2452

10%

402

6.3VCERM

1UF

PLACE C2452 AT BALL AG38

2

1 C2453

10%

402

6.3VCERM

1UF

PLACE C2453 AT BALL AJ38

2

1 C2412

402

10%2.2UF

X5R

PLACE C2415 AT BALL AT40

6.3V

2

1C2499


0.1UF

10VCERM

20%

402

2

1 C2442

402

1UF10%6.3V

PLACE C2442 AT BALL AN52CERM

2

1C2445

PLACE C2445 AT BALL R2

10UF20%

6.3VCERM

805-1

2

1 C2443

CERM

10%1UF

402

6.3V


2

1 C2436

402

6.3V10%1UF


CERM2

1 C2447

10%

402

0.1UF


X5R16V

2

1 C2486

25V

402


X5R

10%0.1UF

2

1 C24441UF

CERM6.3V

402

10%

PLACE C2444 AT BALL BA38

2

1 C2446

10%6.3VCERM402

1UF

PLACE C2446 AT BALL AY25

2

1C2472


6.3VCERM

10UF20%

805-1

2

1 C2470

10%

CERM6.3V

402

1UF


2

1C2473

805-1

20%10UF

6.3VCERM

PLACE C2473 AT BALL F30

2

1 C2425

CERM

PLACE C2425 AT BALL BD20

1UF

6.3V

402

10%

2

1 C24240.1UF10%

X5R

PLACE C2424 AT BALL BC17 402

16V2

1 C24271UF

CERM

PLACE C2427 AT BALL BD17

6.3V

402

10%

2

1C2461

805-1

PLACE C2461 AT BALL AR32

CERM

20%10UF

6.3V2

1C2460

805-1


6.3V

10UF20%

CERM2

1 C2482

CERM

10%1UF

6.3V

402


2

1 C2481


6.3V

402

1UF10%

CERM 2

1 C2483

6.3V

1UF10%

CERM402

PLACE C2483 AT BALL AL34

2

1 C2407

6.3V10%1UF

CERM402


2

1C2415

805-1

PLACE C2415 AT BALL F20

CERM6.3V20%

10UF

2

1 C2429

CERM

1UF10%6.3V

402


2

1C2428

805-1

20%

CERM6.3V

10UF


2

1C2420

805-1

10UF

CERM

20%6.3V


2

1C2418

805-1

PLACE C2418 AT BALL AN32

10UF20%

6.3VCERM2

1 C2498

402

1UF10%6.3VCERM


2

1 C2496

402CERM

1UF10%6.3V


2

1 C2456

6.3V10%1UF

402CERM

PLACE C2456 AT BALL AG28

2

1 C2426


10%6.3VCERM402

1UF

2

1C244810UF

16VX5R-CERM

0805

10%

21

L2406

1210-HF

10UH-0.45A21

R2415

MF-LF

5%1/16W

402

1

2

1 C2411

10%

X5R16V

402

1UFPLACE C2411 AT BALL AJ20

2

1 C24300.1UF10%16VX5R


402

21

R2406NOSTUFF

1/16W5%

0

MF-LF402

21

R2407

1/16WMF-LF402

5%

0


PCH DECOUPLING


PP3V3R1V5_PCH_VCCSUSHDAVOLTAGE=3.3VMIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.2MM


MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MM


PP1V05_S0_PCH_VCCAPLL_SATA_F







=PP5V_S5_PCH

=PP3V3_S5_PCH

=PP5V_S0_PCH

MIN_NECK_WIDTH=0.25MMVOLTAGE=5V

MIN_LINE_WIDTH=0.3MMPP5V_S0_PCH_V5REF

MAKE_BASE=TRUE

=PP5V_S0_PCH_V5REF

=PP5V_S5_PCH_V5REFSUS

MIN_LINE_WIDTH=0.3MMPP5V_S5_PCH_V5REFSUS



PP3V3R1V5_PCH_VCCSUSHDA

=PP1V05_S0_PCH_VCCIO_SATA=PP3V3R1V8_S0_PCH_VCCDFTERM







=PP3V3_S0_PCH




=PP1V05_S0_PCH

PP1V8R1V5_S0_PCH_VCCVRM_FMIN_LINE_WIDTH=0.5MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25MMVOLTAGE=1.8V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MMVOLTAGE=1.05V

PP1V05_S0_PCH_VCCCLKDMI_F



PP1V05_S0_PCH_VCCAPLLDMI2_F

PP1V05_S0_PCH_VCCCLKDMI_LMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MMVOLTAGE=1.05V

VOLTAGE=1.05V


MAKE_BASE=TRUE


PP1V05_S0_PCH_VCCAPLL_EXP_F


24 OF 110

11.1.0

051-8115

24 OF 98

5

2

6

22 24 95

6 22

22 95

6 22

6 22

6 22

6 22

6 22

6 22

6

6 18 19 21

6

95

22

22

95

6 22

22 24 95

6 18 22 6 22

6 22

6 22

6 22

6 22

6 22

6 79

6 18 21

6 22

6 18 19 22

6 22

6 18 79

22 95

22 95

22 95

22 95

6

www.vinafix.vn

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

NC

IN

IN

IN

OUT

IN

IN

BI

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

IN

IN

OUT

IN

IN

IN

IN

OUT

IN

IN

OUT

IN

IN

IN

IN

IN

OUT

IN

IN

NC

BI

IN

IN

IN

IN

IN

BI

IN

OUT

IN

IN

IN

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

OC4#/GPIO43

OC3#/GPIO42

OBSFN_A0

OBSFN_A1

OBSDATA_A2

OBSFN_B1

OBSDATA_A3

OBSDATA_B0

OC5#/GPIO9

OC2#/GPIO41

OC0#/GPIO59

PWRGD/HOOK0

VCC_OBS_AB

OBSDATA_A0

SATA0GP/GPIO21

GPIO35

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

SATA3GP/GPIO37

<- 1K SERIES R ON PCH SUPPORT P. 28

SATA4GP/GPIO16

OBSDATA_C2

SDA

PLACE TCK/TDI/TMS/TRST*

XDP_PRESENT#

TRSTn

OBSDATA_C1

OBSDATA_D3

VCC_OBS_CD

OBSDATA_A1

OBSDATA_B1

RESET#/HOOK6

PLACEMENT NOTE:

SDA

OBSFN_D0

ITPCLK#/HOOK5

OBSDATA_D3

OBSDATA_A2

HOOK1

OBSDATA_C3

SCL

TCK1

SCL

TCK0 TMS

TRSTn

ITPCLK/HOOK4

OBSDATA_D2

HOOK1

HOOK2

ITPCLK/HOOK4

OBSDATA_B2

OBSDATA_C3

TDO

TMS

VCC_OBS_CD

OBSFN_C0

OBSFN_C1

HOOK3

XDP_PRESENT#

OBSDATA_D2

TDO

OBSDATA_D1

OBSDATA_D0

OBSDATA_C0

HOOK2

PLACEMENT NOTE:

TERM NEAR CPU

ODT AVAILABLE ON JTAG

PLACEMENT NOTE:

SNB XDP CONNPLACE TDO TERM NEAR

DESIGN NOTE:

PLACE TDO TERM NEAR

PLACEMENT NOTE:

PCH XDP CONN

OBSFN_B0

DBR#/HOOK7

OBSFN_D1

OBSFN_D1

OBSDATA_B3

PLACE TCK/TDI/TMS/TRST*

OBSDATA_C0

OBSFN_B0

PROCESSOR MINI XDP

OBSFN_A0

To Reset Button

OBSDATA_C2

OBSDATA_C1

OBSDATA_D1

TERM NEAR PCH

This is to derive 1.05V SUS RAIL

OBSDATA_D0

<- 1K SERIES R ON PCH SUPPORT P. 28

OBSDATA_A0

TDI

OBSDATA_B3

OBSFN_D0

OBSFN_C1

OBSFN_C0

TDI

DBR#/HOOK7

RESET#/HOOK6

ITPCLK#/HOOK5

SATA2GP/GPIO36

OBSDATA_B2

TCK1

TCK0

OBSFN_A1

OBSDATA_A1

OBSDATA_A3

OBSFN_B1

PCH MINI XDP

OC1#/GPIO40

PWRGD/HOOK0

VCC_OBS_AB

HOOK3

MGPIO7/GPIO28

GPIO15

OBSDATA_B0

OBSDATA_B1

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

518S0774

518S0774

10 15 90

27 91

11 90

11 90

10 90

5

6

7

8

4

3

2

1

RP2500XDP_CPU_BPM

SM-LF1/16W5%0

5

6

7

8

4

3

2

1

RP2501

PLACEMENT_NOTE=Place R2501 close to R2500 to minimize stubs

SM-LF

XDP_CPU_CFG

1/16W

05%

11 90

11 90

11 90

11 90

10 90

10 90

10 90

21

R2501PLACEMENT_NOTE=Place close to CPU

402

5%

XDP

1/16W1K

MF-LF

10 15 25 90

21 32 97

5 21 97

10 90

15 21 86 96

21

R2576 PLACEMENT_NOTE=Place close to PCH

1/16WMF-LF

05%

402

XDP

21


MF-LF

05%

402

XDP

1/16W

15 21

15 18

21

R2573XDP

PLACEMENT_NOTE=Place close to PCH

5%MF-LF

1/16W402

0

15 21

10 15 90

27 97

18 25 91

18 25 91

18 25 91

10 90

21

R2580PLACEMENT_NOTE=Place close to PCH

1/16W5%MF-LF 402

0

XDP

20

20

18 25 91

10 15 90

20 34 97

9

87

60

6

59

5857

5655

5453

5251

50

5

49

4847

4645

4443

4241

40

4

39

3837

3635

3433

3231

30

3

29

2827

2625

2423

2221

20

2

19

1817

1615

1413

1211

10

1

J2550XDP_CONN

F-ST-SM-HF

CRITICAL

DF40C-60DS-0.4V

2

1R2553XDP

1/16W


5%100

402MF-LF

2

1R2554100

MF-LF402

1/16W5%


XDP

2

1R2550

PLACEMENT_NOTE=Place close to J2550

402MF-LF

5%1/16W

XDP

200

2

1R2551

1/16W

402MF-LF

5%

XDP

200


2

1R2552

402

1/16WMF-LF

XDP


5%200

2

1R2555

402

100

MF-LF1/16W

5%


XDP

2

1R2556


402

XDP

5%1/16WMF-LF

51

25 49

25 49

11 25 97

2

1C25800.1uF

16V

402X5R

10%

XDP

2

1 C25810.1uF

16V

XDP

402

10%

X5R

21

R25020

XDP

5% 1/16W

MF-LF402

PLACEMENT_NOTE=Place close to SMC

19 25 46 97

21

R2585

MF-LF

XDP

0

4025% 1/16W

PLACEMENT_NOTE=Place close to SMC

19 25 46 97

21

R25041/16W5%

XDP

0

MF-LF402

5 64 65 97

21

R2584XDP

1/16WMF-LF5%


1K402

6 25

21

R25811/16W5%

XDP

0MF-LF


40220 45 97

19 27 46 97 21

R2506PLACEMENT_NOTE=Place close to SW2800

MF-LF

5%

XDP

1/16W

0

402

11 25 90

11 25 97

11 25 97

21

R25821/16W5%

0

XDP

402MF-LF


20 33 97

21


5%

XDP

402

0MF-LF

1/16W 15 21

21

R2587

MF-LF5%

PLACEMENT_NOTE=Place close to PCHXDP

01/16W402

20 36 97

10 90

11 25 90

18 90

18 90

21

R2515 PLACEMENT_NOTE=Place close to R1841

0

XDP

5% 1/16W

MF-LF402

21

R2516

MF-LF

5%

402

0

XDP

1/16W

PLACEMENT_NOTE=Place close to R1840

11 25 90

15 21

21 91 21

R2579 PLACEMENT_NOTE=Place close to PCHXDP

MF-LF 4021/16W5%

0

15 18 84 91 21


1/16W

XDP

4025%

0

MF-LF

21


1/16W5%MF-LF 402

XDP

020 82 91 97

21


05%

402MF-LF

XDP

1/16W20 91

11 25 90

10 15 25 90

2

1 C2501

16V

402X5R

10%0.1uF

XDP

10 15 90

2

1C2500

16V

XDP

402X5R

10%0.1uF

11

11

10 90

10 90

10 15 90

10 15 90

25 49

25 49

11 25 90

21

R2500PLACEMENT_NOTE=Place close to CPU

1K

XDP

5% 1/16W

MF-LF402

10 90

11 21 97

10 90

9

87

60

6

59

5857

5655

5453

5251

50

5

49

4847

4645

4443

4241

40

4

39

3837

3635

3433

3231

30

3

29

2827

2625

2423

2221

20

2

19

1817

1615

1413

1211

10

1

J2500DF40C-60DS-0.4V

CRITICAL

F-ST-SM-HF

XDP_CONN

2

1R2510

402

51

XDP

1/16WMF-LF

5%


2

1R2511XDP

515%

1/16WMF-LF402


2

1R2512

402MF-LF1/16W


5%51

XDP

2

1R2513

1/16W5%51

MF-LF402

XDP


2

1R2514XDP

51

1/16W5%


402MF-LF

11 90

11 90


CPU & PCH XDPSYNC_MASTER=K62

CPU_CFG<8>

CPU_CFG<6>

XDP_CPU_TMS

XDP_CPU_PWRGD

XDP_OBSDATA_B<1>

XDP_OBSDATA_B<0>

MXM_GOOD

=SMBUS_XDP_SCL

XDP_PCH_PWRBTN_L

TP_XDP_PCH_TRST_L

XDP_PCH_TMS

TP_XDPPCH_HOOK3

XDP_CPU_CLK100M_N

XDP_CPU_CLK100M_P

XDP_CPU_PWRBTN_L

XDP_PCH_T29_DP_PORTA_PWR_EN

XDP_VR_READY

XDP_OBSDATA_B<2>

XDP_OBSDATA_B<3>

XDP_CPU_CFG<0>

XDP_CPU_TCK

CPU_CFG<11>

=SMBUS_XDP_SDA

XDP_PCH_T29_DP_PORTB_PWR_EN

AP_PWR_EN

=SMBUS_XDP_SCL

=PP3V3_S5_XDP

TP_XDP_PCH_OBSFN_B<0>

TP_XDP_PCH_OBSFN_A<0>

XDP_PCH_SDCONN_CHANGE


PCH_GPIO36_SATA2GP

XDP_PCH_GPIO15

XDP_PCH_ISOLATE_CPU_MEM_L

XDP_BPM_L<0>

PCH_GPIO0_BMBUSY_L

PCH_GPIO19_SATA1GP

TP_XDP_PCH_OBSFN_D<0>

XDPPCH_PLTRST_L

TP_XDP_PCH_HOOK4

ISOLATE_CPU_MEM_L

PCH_GPIO49_SATA5GP

XDP_DBRESET_L

XDP_PCH_TDI

=PPVCCIO_S0_XDP

PM_PWRBTN_L

CPU_CFG<15>ITPXDP_CLK100M_P

TP_XDP_PCH_HOOK5

XDP_DBRESET_L

CPU_CFG<7>

CPU_CFG<9>

XDP_CPU_PRDY_L

XDP_CPU_PREQ_L

XDP_CPU_TDO

TP_XDP_PCH_OBSFN_D<1>

CPU_CFG<16>

CPU_CFG<1>

ITPXDP_CLK100M_N

CPU_CFG<0>

CPU_CFG<4>

CPU_CFG<5>

CPU_CFG<2>

CPU_CFG<3>

XDPCPU_PLTRST_L

PM_SYSRST_L

XDP_CPU_TRST_L

CPU_CFG<10>

CPU_CFG<17>

XDP_BPM_L<3>

XDP_CPU_TRST_L

XDP_PCH_TMS

XDP_BPM_L<2>

XDP_PCH_TDO

XDP_PCH_TDI

=PP3V3_S5_XDP

=PPVCCIO_S0_XDP

XDP_CPU_TCK

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPU_TMS

XDP_BPM_L<7>

CPU_CFG<0>

CPU_CFG<12>

XDP_BPM_L<1>

CPU_CFG<14>

XDP_BPM_L<5>

CPU_CFG<13>

XDP_BPM_L<6>

PM_PGOOD_PVCORE_CPU

CPU_PWRGD

XDP_PCH_TDO

SDCONN_STATE_CHANGE

XDP_BPM_L<4>

PM_PWRBTN_L

XDP_PCH_TCK

XDP_CPU_TDI

PCH_GPIO15

XDP_DBRESET_L

XDP_PCH_AUD_IPHS_SWITCH_EN

XDP_PCH_JTAG_T29_TCK


JTAG_T29_TCK

XDP_PCH_TCK

XDP_PCH_MXM_GOOD

DP_AUXCH_ISOL

XDP_PCH_DP_AUXCH_ISOL

T29_DP_PORTA_PWR_EN

ENET_PWR_EN

=PP3V3_S5_XDP

=SMBUS_XDP_SDA

TP_XDPPCH_HOOK2

TP_XDP_PCH_OBSFN_B<1>

XDP_PCH_ENET_PWR_EN

XDP_PCH_AP_PWR_EN

XDP_PCH_USB_HUB_SOFT_RST_L

TP_XDP_PCH_OBSFN_A<1>

PCH_GPIO14_OC7_L

PCH_GPIO10_OC6_L

T29_DP_PORTB_PWR_EN

XDP_PCH_S5_PWRGD

25 OF 110

11.1.0

051-8115

25 OF 98

90

90

90

90

90

90

90

6 25

6 25

11 25 90

18 25 91

18 25 91

18 25 91

6 25

6 25

11 25 90

11 25 90

11 25 90

11 25 90

18 25 91

www.vinafix.vn

REF

CPU

CPU*

SRC_2*

SRC_2

SATA*

SATA

27MHZ

27MHZ_SS

DOT_96*

X2

X1

SCL

SDA

CKPWRGD/PD*

VDD_CORE

VDD_REF

VDD_96_IO

VDD_27

VDD_SATA_IO

VDD_SRC_IO

VDD_CPU_IO

VSS_CPU

VSS_27

VSS_96

THRM

VSS_SATA

VSS_SRC

VSS_REF

VSS_CORE

DOT_96

27MHZ_EN

PAD

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

STUFF THIS TO POWER DOWN CK505 ->

R2605 OR R2606 CAN BE CHANGED TO "BUF_CLK" OPTION LATERWHEN FCIM IS FULLY VALIDATED -> PCH BCLK 133MHZ

PCH USB Clock 96MHz

PCH DMI/PCIe 100MHz

PCH SATA 100MHZ

PLACE IT CLOSE TO POWER PINS

PLACE IT CLOSE TO L2650





UNUSED clock terminations for FCIM MODE

2

1 C2616BUF_CLK

402

10%16V

0.1UF

X5R2

1 C2615

X5R402

10%16V

0.1UF

BUF_CLK

2

1C2610

X5R

20%6.3V

10UF

BUF_CLK

603

21

L2610BUF_CLK

0402

FERR-120-OHM-1.5A

2

1 C2605

X5R

0.1UF10%16V

402

BUF_CLK

2

1 C2604

X5R16V10%0.1UF

402

BUF_CLK

2

1 C2603

X5R

10%

402

0.1UF

BUF_CLK

16V2

1 C2602

16V

402X5R

10%0.1UF

BUF_CLK

2

1C2600BUF_CLK

603

6.3V

10UF

X5R

20%

21

L2600

0402

FERR-120-OHM-1.5A

BUF_CLK

23

24

12

13

27

20

215

28

9 16

25

17

22

4831

33

11

10

2

3

15

14

26

7

6

18

19

1

30

32

29

U2600QFN

CRITICAL

OMIT

SLG2AP108

2

1 C2621

CERM402

18pF

50V5%

BUF_CLK

21

Y2620

5X3.2-SM

BUF_CLK

CRITICAL

14.31818

2

1C2620BUF_CLK

CERM

18pF

50V5%

402

49

2

1 C2652BUF_CLK

0.1UF

X5R402

10%16V

2

1 C2651BUF_CLK

0.1UF

X5R402

10%16V2

1C2650BUF_CLK

10UF

X5R603

20%6.3V

21

L2650

0402

FERR-120-OHM-1.5A

BUF_CLK

18 26 91

21

R26502.2

5%1/16WMF-LF402

BUF_CLK

2

1R2690BUF_CLK

10K5%

402MF-LF1/16W

2

1R2616

1/16W

402

5%

MF-LF

10M

NOSTUFF

21

R26995%

PLACE R2699 NEAR PIN 26

40233

1/16W MF-LF

BUF_CLK

2

1R2600BUF_CLK

1/16W5%

402

10K

MF-LF

18 26 90

18 26 90

18 26 90

18 26 90

21

R2615BUF_CLK

1/16W5%

MF-LF

0

402

18 26 90

18 26 90

2

1R265710K

FCIM

402

1/16W5%

MF-LF2

1R2651FCIM

10K

MF-LF402

1/16W5%

2

1R2652FCIM

10K

MF-LF402

1/16W5%

2

1R2653FCIM

10K

MF-LF402

1/16W5%

2

1R265410K

FCIM

MF-LF402

1/16W5%

2

1R2655FCIM

10K

MF-LF402

1/16W5%

2

1R265610K5%1/16W

402MF-LF

FCIM

21

R2605NOSTUFF

1/16W

MF-LF

0

402

5%5 19 32 36 46 47 63 82 97

49

2

1R2620BUF_CLK

10K5%

1/16W

402MF-LF

21

R26065%

0

MF-LF

1/16W

NOSTUFF

402

64


CLOCK (CK505)

PM_PGOOD_CK505

PM_SLP_S3_L CK505_CKPWRGD_PD_L

PCH_CLK100M_DMI_N

TP_CLK133M_PCH_P

PCH_CLK14P3M_REFCLK

=PP3V3_S0_CK505

=PP1V5_S0_CK505 PP1V5_S0_CK505_FMIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mmVOLTAGE=1.5V

CK505_XTAL_IN

CK505_27MHZ_EN

=SMBUS_CK505_SDA

=SMBUS_CK505_SCL

PCH_CLK96M_DOT_N

TP_CK505_CLK27M_SS

PCH_CLK100M_SATA_P

PCH_CLK100M_DMI_P

TP_CLK133M_PCH_N

PCH_CLK14P3M_REFCLK_R

CK505_CLK27M

PCH_CLK14P3M_REFCLK

PCH_CLK96M_DOT_N

PCH_CLK100M_SATA_P

PCH_CLK100M_DMI_P

PCH_CLK100M_DMI_N

PCH_CLK100M_SATA_N

PCH_CLK96M_DOT_P

PCH_CLK96M_DOT_P

PCH_CLK100M_SATA_N

CK505_XTAL_OUT_R

MIN_NECK_WIDTH=0.2mm

PP3V3_S0_CK505_FMIN_LINE_WIDTH=0.5mm

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2mmVOLTAGE=1.05V

PP1V05_S0_CK505_FMIN_LINE_WIDTH=0.5mm

PP1V5_S0_CK505_R=PP1V05_S0_CK505

CK505_XTAL_OUT

26 OF 110

11.1.0

051-8115

26 OF 98

90

18 26 91

6

6 95

91

97

90

18 26 90

18 26 90

18 26 90

18 26 90

18 26 90

18 26 90

91

95

95 95 6

91

www.vinafix.vn

OUT

NCNC

OUT

OUT

IN

OUT

IN

IN

NCNC

NCNC

OUT

OUT

OUT

OUT

IN

OUTIN

OUT

OUT

IN

OUT

OUT

OUT

OUT

NC

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

OPEN-DRAIN BUFFER

MAY NEED TO MOVE LONGER TRACE ONES TO BUFFERED

Platform Reset Connections

PCH 25MHZ CRYSTAL

PGOOD PROVIDES RSMRST_L ASSERTION TIMING REQUIREMENTS UPON AN UN-EXPECTED EXIT FROM S5 (POWER LOSS)

SMC MAY FORCE A RSMRST_L ASSERTION WITHOUT AN S5 POWER TRANSITION IN SOME ERROR CASES

SMC PROVIDES RSMRST_L DE-ASSERTION DELAY UPON ENTRY TO S5

Coin-Cell HolderUnbuffered

PLACE THIS ON THE BOTTOM SIDE

Reset Button

Buffered

SMC PROVIDES RSMRST_L ASSERTION TIMING REQUIREMENTS UPON EXPECTED EXIT FROM S5

VTT VOLTAGE DIVIDER AND PU ON CPU PAGE

RTC Power Sources

fault protection for RTC battery.

NOTE: R2800 and D2800 form the double-511-0054

PCH RTC Crystal

19 25 46 97

12

R2800

1/16W

402MF-LF

5%

1K

21

C2810

50V

402

12pF

5%

CERM

PLACE C2810 CLOSE TO Y2810

21

C2811

CERM


12pF

5%50V

402

31

42

Y2810

CRITICAL

SM-2

PLACE Y2810 CLOSE TO U1800

32.768K

3

6

4

1

D2800

SOT-363BAT54DW-X-G

21

R288133

1/16W5%

402MF-LF

21

R289033

MF-LF402

1/16W5%

48 97

9 97

18 91

18 91

20 97

21

R282633PLACEMENT_NOTE=Place close to U1800

5%

MF-LF1/16W

402

21

R282533PLACEMENT_NOTE=Place close to U1800

1/16WMF-LF

5%

402

20 91

39 97 21

R2892

402MF-LF1/16W5%

33

48 91

46 91

11 97

20 91

18 91 21

R2827PLACEMENT_NOTE=Place close to U1800 33

402MF-LF1/16W5%

20 91

2

1C2880

20%10V

402CERM

0.1UF

2

1R2880

402

5%100K

1/16WMF-LF

36 97 21

R288233

402

5%

MF-LF1/16W

1

2

J2800BB10201-C1403-7HSM

2

1R2897

1/16W

402MF-LF

5%4.7K

2

1R2811

402MF-LF1/16W

5%10M

5

4

1

2

3

U2880

SOT23-5-HFMC74VHC1G08

2

1C28900.1UF

10V20%

CERM402

21

R2810

MF-LF

5%

0

402

1/16W25 97 21

R2899

1/16WMF-LF402

1K

5%

XDP

21

C2815

50V5%

402CERM

22pF

PLACE C2815 CLOSE TO Y2815DEVELOPMENT

21

C2816

CERM402

50V5%

22pF


DEVELOPMENT

21

R2815NOSTUFF

5%

MF-LF402

1/16W

0

2

1R2816

5%1/16W

402

1M

MF-LF

DEVELOPMENT

18 91

18 79 91

21

Y2815

8X4.5MM-SM3

25.0000M

CRITICAL

PLACE Y2815 CLOSE TO U1800

DEVELOPMENT

43

21

SW2800NTC020-CC1J-B260T

SM

SILK_PART=SYS RESET

DEVELOPMENT

2

1 C2899

NONENONE

OMIT

603

NONENOSTUFF

21

R2850

NOSTUFF

402

1/16WMF-LF

5%

0

33 97 21

R2888

1/16WMF-LF

5%

33

402

80 97 21

R2855

MF-LF402

33

5%1/16W

T29

46 97 21

R2883

5%

402

1/16W

33

MF-LF

4

5

3

2

U289074LVC1G07SC70

21

R2898XDP

MF-LF402

5%1/16W

1K25 91 21

R2870

1/16WMF-LF402

5%

0

21

R28720

5%

402MF-LF1/16W

NOSTUFF

5

4

1

2

3

U2870

MC74VHC1G08SOT23-5-HF

2

1C2870

20%10V

402CERM

0.1UF

21

R2884

402

33

5%

MF-LF1/16W

44 97

CHIPSET SUPPORTSYNC_DATE=01/06/2011SYNC_MASTER=K62

PCH_CLK25M_XTALIN_R

PCH_CLK32K_RTCX2

PCH_CLK32K_RTCX1

PCH_CLK32K_RTCX2_R

PM_PGOOD_P3V3_S5_REG

PM_RSMRST_L

PM_RSMRST_PCH_L

=PP3V3_S5_RSTBUF

FW_RESET_L

ENET_RESET_L

PM_SYSRST_L

PCH_CLK33M_PCIOUT

LPC_CLK33M_SMC_R

LPC_CLK33M_LPCPLUS_R

PCH_CLK33M_PCIIN

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

XDPCPU_PLTRST_L

PEG_RESET_L

RTC_RESET_L=PP3V3_G3H_RTC_D


VOLTAGE=3.3V

PPVBATT_G3_RTC_R

=PP3V3_S0_RSTBUF

DEBUG_RESET_L

PPVBATT_G3_RTCMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

PCH_CLK32K_RTCX1_R

=PP3V3_S0_PCH_PM

PCH_CLK25M_XTALOUT_RPCH_CLK25M_XTALOUT

PCH_CLK25M_XTALIN

SMC_LRESET_L

T29_RESET_L

MINI_RESET_L

XDPPCH_PLTRST_L

CPU_RESET_L

=PP3V3_S0_RSTBUF

PLT_RESET_LMAKE_BASE=TRUE

NC_U2890_P1NO_TEST=TRUE

PLT_RST_BUF_L

SDCARD_PLT_RST_L

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mmPP3V3_G3H_RTC


28 OF 110

11.1.0

051-8115

27 OF 98

25

1

91

91

64 70 97

46 97

19 97

6

18 97 6

95

6 11 27

95

91

6

91

6 11 27

91

18 19 22 95

www.vinafix.vn

IN

BI

OUT

OUTSCL RH

RW

VDD

SDAGND

SCL RH

RW

VDD

SDAGND

IN

IN

OUT

OUT

OUT

OUT

BI

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

R2956 change to NOSTUFF if use VREFMARGIN_DIMMB_DQ

353S2369

to drive both VREFCA_A and VREFCA_B

PLACE IT CLOSE TO DIMM CONNECTOR PIN

PLACEMENT NOTE:

PLACE R2968, R2969 and C2961 near CPU

CPU VREF

353S2370

353S1961

PLACEMENT NOTE:

I2C ADDR = 0X5C (WRITE)

PLACEMENT NOTE:

EMPTY ONE SET OF OP-AMP & POT WHEN R2960 IS STUFF

PLACEMENT NOTE:

PLACE R2978, R2979 and C2991 close to DIMM PIN

PLACEMENT NOTE:

DIMM VREFDQ

I2C ADDR = 0X5D (READ)

353S1961

DIMM VREFCA

I2C ADDR = 0X7D (READ)

I2C ADDR = 0X7C (WRITE)




5

2

4

1

3

U2901VREFMRGN_A

LM321SOT23-5

2

1R2975

402

1%1/16WMF-LF

1K

2

1 C2951NOSTUFF

10%

X5R402

16V

0.1UF

2

1R2976

1/16W1%

402

1K

MF-LF

21

R2956

MF-LF1/16W5%

402

VREFMRGN_B

0

2

1 C2912

6.3V

1UF10%

402CERM

VREFMRGN_B

2

1R29031%

MF-LF

12.1K1/16W

402

VREFMRGN_A

21

R2914

MF-LF402

2.2

5%1/16W

VREFMRGN_B

2

1 C2911

X5R

0.1UF16V10%

VREFMRGN_B

402

2

1R2915VREFMRGN_B

402MF-LF1/16W1%1K

21

R2919VREFMRGN_B

402

10

1%

MF-LF1/16W

5

2

4

1

3

U2911VREFMRGN_B

SOT23-5LM321

2

1R2913

1/16W

402

12.1K1%

VREFMRGN_B

MF-LF

21

R2902VREFMRGN_A

12.1K

1/16WMF-LF402

1%

21

R2912

MF-LF402

1/16W1%

VREFMRGN_B

12.1K

2

1 C29100.1UF

402

16VX5R

10%

VREFMRGN_B

21

R2910

MF-LF

5%

402

0

1/16W

VREFMRGN_B

21

R2911

1/16W

0

5%

402

VREFMRGN_B

MF-LF

49

49

28 30 95

28 31 95

1

4

3

5

62

U2910SC-70

ISL90728WIE627ZTK

VREFMRGN_B

1

4

3

5

6

2

U2900SC-70

ISL90727WIE627ZTK

VREFMRGN_A

28 89

28 89

30 95

31 95

11 89

2

1 C2961

X5R

10%

402

16V

0.1UF

2

1R2968

402

1/16W1%

MF-LF

100

2

1R2969

402

1%

MF-LF1/16W

100

21

R2960

MF-LF1/16W5%

0

402

NOSTUFF

28 89

2

1 C2902VREFMRGN_A

CERM402

10%6.3V

1UF

2

1 C2900

402

10%

X5R16V

0.1UF

VREFMRGN_A

21

R2900

MF-LF402

5%

VREFMRGN_A

0

1/16W

21

R2901VREFMRGN_A

MF-LF402

1/16W

0

5%

49

49

21

R2904

MF-LF

5%

2.2

402

VREFMRGN_A

1/16W

2

1R2988

MF-LF

1%1/16W

402

1K

2

1 C2921

X5R

10%0.1UF

402

16V

NOSTUFF

2

1R29891K1/16WMF-LF

1%

402

2

1R2905VREFMRGN_A

402

1/16W1%

MF-LF

1K

21

R2995

5%

0

402

1/16W

NOSTUFF

MF-LF

2

1 C2901VREFMRGN_A

0.1UF16V10%

402X5R

2

1R29781K

MF-LF

1%1/16W

402

2

1 C299110%

402X5R16V

NOSTUFF

0.1UF

2

1R29791K

402

1%1/16WMF-LF

21

R2996NOSTUFF

1/16W5%

0

402MF-LF

2

1 C2950

16V

402

10%

X5R

0.1UF

NOSTUFF

2

1R29701K1/16W1%

402MF-LF

2

1R2971

402

1%

MF-LF1/16W

1K

21

R2958

402MF-LF1/16W5%

0

VREFMRGN_A

21

R2909VREFMRGN_A

1/16W

402

1%

10

MF-LF


DDR3 VREF MARGINING

=PP3V3_S3_VREFMRGN

=PP5V_S3_VREFMRGN

VREFMARGIN_DIMMA_DACOUT

VREFMARGIN_DIMMB_OPFB

=PP5V_S3_VREFMRGN

VREFMARGIN_DIMMB_DACOUT

PP5V_S3_VREFMRGN_B=PP1V5_S3_MEM_B

=PP1V5_S0_CPU_MEM

=PP1V5_S3_MEM_A

=PP1V5_S3_MEM_B

PP0V75_S3_MEM_VREFCA_B

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_B

=PP1V5_S3_MEM_A

VREFMARGIN_DIMMB_DQ PP0V75_S3_MEM_VREFCA_A

CPU_DDR_VREF

I2C_VREFMRGN_DIMMB_SDA

=I2C_VREFMRGN_B_SDA

I2C_VREFMRGN_DIMMB_SCL

=I2C_VREFMRGN_B_SCL

I2C_VREFMRGN_DIMMA_SDA

=I2C_VREFMRGN_A_SDA

=I2C_VREFMRGN_A_SCL

I2C_VREFMRGN_DIMMA_SCL

=PP3V3_S3_VREFMRGN

=PP1V5_S3_MEM_B

VREFMARGIN_DIMMB_DQ

VREFMARGIN_DIMMB_DQ

=PP1V5_S3_MEM_A

VREFMARGIN_DIMMA_DQ

VREFMARGIN_DIMMA_OPFB

PP5V_S3_VREFMRGN_A

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFDQ_B

29 OF 110

11.1.0

051-8115

28 OF 98

6 28

6 28

89

89

6 28

89

95

6 28 29 31

6 11 13 16 29

6 28 29 30

6 28 29 31

28 30 95 28 31 95

6 28 29 30

94

94

94

94

6 28

6 28 29 31

6 28 29 30

89

89

95

www.vinafix.vn




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

DECOUPLING CAPS FOR 1V5_S3_MEM AT CHANNEL A DIMM CONNECTOR

EXTRA DECOUPLING CAPS FOR 1V5_CPU_MEM RAIL

DECOUPLING CAPS FOR 1V5_S3_MEM AT CHANNEL B DIMM CONNECTOR

DIMM A (CLOSER TO CPU) DIMM B (FURTHER FROM CPU)CAPS TO STITCH 1V5_CPU_MEM TO GND NEAR DIMM

2

1 C3058

CERM

10%1UF6.3V

4022

1 C3057

402CERM

10%1UF6.3V

2

1 C3056

402CERM

10%1UF6.3V

2

1 C3055

402CERM

10%1UF6.3V

2

1 C3054

402

1UF

CERM

10%6.3V

2

1 C3053

402CERM

1UF6.3V10%

2

1 C3052

6.3V

1UF

CERM

10%

4022

1 C3051

20%

X5R6.3V

10UF

603

2

1 C3050

20%

603

6.3VX5R

10UF

2

1 C3085

6.3V

1UF10%

CERM402

2

1 C3084

6.3V

1UF10%

CERM402

2

1 C3083

6.3V

1UF10%

CERM402

2

1 C3082

6.3V

1UF10%

CERM402

2

1 C3081

402CERM

10%1UF

6.3V2

1 C3080

402CERM

10%1UF

6.3V2

1 C3079

402CERM

10%1UF

6.3V2

1 C3078

402CERM

10%1UF

6.3V2

1 C3077

402CERM

10%1UF

6.3V2

1 C3076

402CERM

10%1UF

6.3V2

1 C3075

402CERM

10%1UF

6.3V2

1 C3074

402CERM

10%1UF

6.3V2

1 C3073

402CERM

1UF

6.3V10%

2

1 C3072

6.3V

1UF

CERM

10%

4022

1 C3071

20%

X5R6.3V

10UF

603

2

1 C3070

20%6.3VX5R603

10UF

2

1 C3094

6.3V

1UF10%

CERM402

2

1 C3093

6.3V

1UF10%

CERM402

2

1 C309210%

CERM6.3V

402

1UF

2

1 C3091

6.3V

402CERM

10%1UF

2

1 C3090

6.3V

402CERM

10%1UF

2

1 C3049

6.3V

402CERM

10%1UF

2

1 C30481UF6.3V

402CERM

10%2

1 C3047

CERM

1UF6.3V

402

10%2

1 C3045

6.3V

1UF10%

CERM402

2

1 C3043

402

10%1UF

CERM6.3V

2

1 C3040

6.3VCERM

10%

402

1UF

2

1 C30A41UF6.3VCERM402

10%2

1 C30A31UF6.3V10%

402CERM2

1 C30A210%6.3V

402CERM

1UF

2

1 C30A110%

402CERM

1UF6.3V

2

1 C30A0

6.3VCERM

10%

402

1UF

2

1 C30AE

402CERM

1UF6.3V10%

2

1 C30AD10%

402CERM

1UF6.3V

2

1 C30AC

402

10%1UF

CERM6.3V

2

1 C30AB10%

402

1UF6.3VCERM2

1 C30AA

CERM402

10%1UF6.3V

2

1 C30A9

CERM402

10%1UF6.3V

2

1 C30A81UF

CERM

10%

402

6.3V2

1 C30A7

402CERM

10%1UF6.3V

2

1 C30A610%

402CERM

1UF6.3V

2

1 C30A51UF6.3VCERM402

10%

2

1 C30661UF6.3V10%

CERM402

2

1 C3067

6.3V10%1UF

402CERM 2

1 C3068

6.3V

1UF10%

CERM402

2

1 C3069

402CERM

10%1UF6.3V

2

1 C3089

402CERM

10%1UF

6.3V2

1 C3088

402CERM

10%1UF

6.3V2

1 C3087

402CERM

10%1UF

6.3V2

1 C3086

402CERM

10%1UF

6.3V

2

1 C3016

402CERM

10%1UF6.3V

2

1 C3017

402CERM

10%1UF6.3V

2

1 C3018

402CERM

10%6.3V

1UF

2

1 C3019

402CERM

1UF6.3V10%

2

1 C3010

CERM

10%1UF6.3V

4022

1 C3025

6.3V

1UF10%

CERM402

2

1 C3026

6.3V

1UF10%

CERM402

2

1 C3027

6.3V

1UF10%

CERM402

2

1 C3028

6.3V

1UF10%

CERM402

2

1 C3029

402CERM

10%1UF6.3V

2

1 C302010%6.3V

1UF

CERM402

2

1 C3021

6.3V

1UF10%

CERM402

2

1 C3022

6.3V

1UF10%

CERM402

2

1 C3023

6.3V

1UF10%

CERM402

2

1 C3014

6.3V

1UF10%

CERM402

2

1 C3030

402

6.3V

1UF10%

CERM 2

1 C3031

402

6.3V

1UF10%

CERM 2

1 C3032

6.3V

1UF10%

CERM402

2

1 C3033

402CERM

10%1UF6.3V

2

1 C304110%

CERM6.3V

1UF

4022

1 C3042

402

10%

CERM6.3V

1UF

2

1 C3044

402

10%

CERM6.3V

1UF

2

1 C304610%1UF6.3VCERM402

2

1 C3096

402CERM

10%1UF6.3V

2

1 C3095

402CERM

10%1UF6.3V

2

1 C30AG

402CERM

10%1UF6.3V

2

1 C30AF

402CERM

10%1UF6.3V

2

1 C3039

6.3V

1UF10%

CERM402

2

1 C3038

6.3V

1UF10%

CERM402

2

1 C3037

6.3V

1UF10%

CERM402

2

1 C3036

6.3V

1UF10%

CERM402

2

1 C3035

6.3V

1UF10%

CERM402

2

1 C303410%6.3V

1UF

CERM402

2

1 C3015

6.3V

402CERM

10%1UF

2

1 C3065

402CERM

10%1UF6.3V

2

1 C3064

402CERM

10%1UF6.3V

2

1 C3063

6.3V

402CERM

10%1UF

2

1 C3062

CERM402

10%1UF6.3V

2

1 C3061

402CERM

10%1UF6.3V

2

1 C3060

402CERM

10%1UF6.3V

2

1 C3059

402CERM

10%1UF6.3V


MEMORY CAPS

=PP1V5_S3_MEM_A

=PP1V5_S0_CPU_MEM

=PP1V5_S0_CPU_MEM

=PP1V5_S3_MEM_B

=PP1V5_S0_CPU_MEM

30 OF 110

11.1.0

051-8115

29 OF 98

6 28 30

6 11 13 16 28 29

6 11 13 16 28 29

6 28 31

6 11 13 16 28 29

www.vinafix.vn

S1*

A13

VDD_14

CAS*

VDD_12

BA0

A10_AP

WE*

A3

DQ54

DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQS0*

DQ5

DQ4

DQ6

DQ7

VREFDQ

VSS_1

VSS_3

DQ0

DQ1

DM0

VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

RESET*

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

DQS3*

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30

DQ31

VSS_25

VDD_1

CKE1

A15

A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2

A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

RAS*

VDD_11

CK1*

BA1

S0*

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

DQS5*

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

VTT_1

DQS7*

DQS7

EVENT*

VSS_51

DQ63

DQ62

VSS_49

SDA

SCL

DQ2

DQ3

VSS_6

DQ8

DQ9

VSS_8

DQS1*

DQS1

VSS_10

DQ16

VSS_12

DQ11

DQ10

DQ17

DQ18

DQS2

VSS_17

DQS2*

VSS_14

VSS_21

DQ24

DQ25

DQ19

VSS_19

VSS_24

DQ27

DQ26

DM3

VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

CK0*

DQ33

VSS_26

VDD_16

TEST

DQ32

DQ34

VSS_31

DQS4

DQS4*

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6*

DQS6

VSS_40

DQ49

DQ50

VSS_45

DQ56

DQ57

VSS_47

DM7

DQ58

VSS_48

DQ59

SA0

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ51

VTT_0

SA1

VDDSPD

MTG PIN MTG PIN

KEY

(1 OF 2)

DQ3

VSS_10

VSS_19

DQ9

VSS_8

DQS1*

DQS1

VSS_21

DQ26

CKE0

BA2

A9

A8

VDD_6

VDD_8

CK0*

A10_AP

BA0

SA0

VTT_0

SA1

VDDSPD

VSS_50

VSS_47

DM7

DQ58

DQ59

DQ57

DQ56

VSS_45

DQ51

DQ50

DQS6

VSS_43

DQS6*

VSS_40

DQ49

DQ48

VSS_38

DQ43

DQ42

VSS_36

DM5

VSS_35

DQ41

DQ40

DQ35

DQ34

VSS_31

DQS4

DQS4*

VSS_28

VSS_26

DQ32

DQ33

TEST

VDD_16

S1*

A13

CAS*

VDD_14

WE*

VDD_12

VDD_10

CK0

A1

A3

A5

VDD_4

A12/BC*

VDD_2

VDD_0

NC_0

DQ11

DQ16

VSS_12

DQ10

DQ8

DM0

VSS_4

VSS_6

DQ2

VREFDQ

DQ0

VSS_3

DQ1

VSS_1

SCL

SDA

VTT_1

VSS_51

VSS_49

DQ63

DQS7

DQS7*

EVENT*

DQ62

DM6

DQ60

VSS_46

VSS_41

DQ53

DQ55

VSS_44

DQ54

VSS_42

DQ61

DQ52

DQ44

VSS_34

DQS5*

VSS_37

DQ46

DQ47

VSS_39

DQ45

DQS5

VSS_32

DM4

VSS_27

VSS_29

DQ36

VREFCA

VDD_17

DQ37

DQ38

DQ39

VSS_30

BA1

NC_1

VDD_13

VDD_11

VDD_15

ODT0

CK1

A0

A2

A6

A4

A7

A11

VDD_9

VDD_7

VDD_5

VDD_3

A15

A14

CKE1

VDD_1

DM1

DQ15

DQ14

DQ13

VSS_11

VSS_9

RESET*

VSS_13

DQ20

DQ12

DQ7

DQ6

DQ5

DQ4

VSS_7

DQS0*

VSS_2

VSS_0

DQS0

VSS_5

DQ21

VSS_15

DM2

VSS_16

DQ22

VSS_18

DQ23

DQ28

VSS_20

DQ29

DQS3

VSS_23

DQS3*

DQ30

DQ31

VSS_25

VSS_14

DQ17

DQS2*

VSS_17

DQS2

DQ18

DQ19

DQ25

DQ24

DM3

VSS_22

DQ27

VSS_24

CK1*

RAS*

S0*

ODT1

VSS_33

VSS_48

KEY

(2 OF 2)




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

DIMM0

(Section A)

(Section B)

DIMM2

BOM options provided by this page:

Signal aliases required by this page:

(NONE)

- =I2C_SODIMMA_SDA

- =I2C_SODIMMA_SCL

Page Notes

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

- =PP1V5_S0_MEM_A

- =PP0V75_S0_MEM_VTT_A

- =PP1V5_S3_MEM_A

TO FACILITATE BITSWAPS WITH ALIASES- ALL DQ, DQS, DM SIGNALS;

DIMM0 SPD ADDR=0XA0(WR)/0XA1(RD)

DIMM 0

DIMM 2

DIMM2 SPD ADDR=0XA2(WR)/0XA3(RD)

STACKED SO-DIMM CONN.

Power aliases required by this page:

CPU - MEM Ch. A

2

1 C3131

402

10V

0.1UF20%

CERM2

1 C3130

CERM402-LF

20%2.2UF

6.3V

2

1 C3136

10V20%0.1UF

402CERM2

1 C3135

402-LF

20%

CERM6.3V

2.2UF

2

1 C31512.2UF

CERM402-LF

6.3V20%

2

1 C3150

6.3V20%

CERM402-LF

2.2UF

2

1R3141

MF-LF

5%10K

1/16W

4022

1R3140

5%10K

1/16W

402MF-LF

2

1 C3140

402-LF

6.3VCERM

20%2.2UF

2

1R3142

MF-LF

10K5%

402

1/16W

2

1R314310K

402

5%1/16WMF-LF

113A

204A203A

26A25A

20A19A

14A

196A195A

13A

190A189A

185A

184A

179A

178A

173A

172A

168A167A

9A

162A161A

156A155A

151A

150A

145A

144A

139A

138A

8A

134A133A

128A127A

72A71A

66A65A

61A

60A

3A

55A

54A

49A

48A

44A43A

38A37A

32A31A

2A1A

126A

199A

100A99A

94A93A

88A87A

82A81A

76A

124A123A

118A117A

112A111A

106A105A

75A

125A

200A

202A201A

197A

121A

114A

30A

110A

120A

116A

122A

77A

410409

198A

186A

188A

169A

171A

152A

154A

135A

137A

62A

64A

45A

47A

27A

29A

10A

12A

23A

21A

18A

16A

194A

192A

182A

180A

6A

193A

191A

183A

181A

176A

174A

166A

164A

177A

175A

4A

165A

163A

160A

158A

148A

146A

159A

157A

149A

147A

17A

142A

140A

132A

130A

143A

141A

131A

129A

70A

68A

15A

58A

56A

69A

67A

59A

57A

52A

50A

42A

40A

7A

53A

51A

41A

39A

36A

34A

24A

22A

35A

33A

5A

187A

170A

153A

136A

63A

46A

28A

11A

74A73A

104A

102A

103A

101A

115A

79A

108A

109A

85A

89A

86A

90A

91A 92A

95A 96A

97A

78A

80A

119A

83A 84A

107A

98A

J3100

DDR3-SODIMM-DUAL

F-RT-TH

CRITICAL

113B

204B203B

26B25B

20B19B

14B

196B195B

13B

190B189B

185B

184B

179B

178B

173B

172B

168B167B

9B

162B161B

156B155B

151B

150B

145B

144B

139B

138B

8B

134B133B

128B127B

72B71B

66B65B

61B

60B

3B

55B

54B

49B

48B

44B43B

38B37B

32B31B

2B1B

126B

199B

100B99B

94B93B

88B87B

82B81B

76B

124B123B

118B117B

112B111B

106B105B

75B

125B

200B

202B201B

197B

121B

114B

30B

110B

120B

116B

122B

77B

198B

186B

188B

169B

171B

152B

154B

135B

137B

62B

64B

45B

47B

27B

29B

10B

12B

23B

21B

18B

16B

194B

192B

182B

180B

6B

193B

191B

183B

181B

176B

174B

166B

164B

177B

175B

4B

165B

163B

160B

158B

148B

146B

159B

157B

149B

147B

17B

142B

140B

132B

130B

143B

141B

131B

129B

70B

68B

15B

58B

56B

69B

67B

59B

57B

52B

50B

42B

40B

7B

53B

51B

41B

39B

36B

34B

24B

22B

35B

33B

5B

187B

170B

153B

136B

63B

46B

28B

11B

74B73B

104B

102B

103B

101B

115B

79B

108B

109B

85B

89B

86B

90B

91B 92B

95B 96B

97B

78B

80B

119B

83B 84B

107B

98B

J3100F-RT-TH

DDR3-SODIMM-DUAL

CRITICAL

DDR3 SO-DIMM 0 & 2SYNC_DATE=01/06/2011SYNC_MASTER=K62

=I2C_SODIMMA_SDA

=MEM_A_DQ<62>

=MEM_A_DQ<52>

MEM_A_ODT<0>

MEM_A_CS_L<0>

=MEM_A_DQS_P<2>

=MEM_A_DQS_P<1>

=MEM_A_DQ<8>

=MEM_A_DQ<20>

=MEM_A_DQ<14>

=MEM_A_DQ<8>

=MEM_A_DQ<2>

=MEM_A_DQ<10>

=MEM_A_DQ<31>

=PP1V5_S3_MEM_A

=MEM_A_DQS_N<2>

=MEM_A_DQS_N<6>

MEM_DIMM2_SA<0>

=PPSPD_S0_MEM_A

MEM_DIMM0_SA<0>

=PPSPD_S0_MEM_A

MEM_DIMM0_SA<1>


=MEM_A_DQ<58>

=MEM_A_DQ<51>

=MEM_A_DQ<44>

=MEM_A_DQ<45>

MEM_A_A<7>

MEM_A_A<15>

MEM_A_CKE<1>

=MEM_A_DQ<19>

=MEM_A_DQS_P<2>

=MEM_A_DQ<29>

MEM_A_CAS_LMEM_A_ODT<2>

PP0V75_S3_MEM_VREFCA_A

=MEM_A_CLK_P<2>

=MEM_A_CLK_N<2>

=MEM_A_DQ<27>

MEM_A_CKE<0>

=MEM_A_DQ<22>

=MEM_A_DQ<3> =MEM_A_DQ<7>

=MEM_A_DQ<17>

=MEM_A_DQ<16>

=MEM_A_DQ<60>

=MEM_A_DQS_N<1>


=MEM_A_DQS_P<1>

=PP1V5_S3_MEM_A

MEM_A_A<4>

MEM_A_A<6>

MEM_A_RAS_L


=MEM_A_DQ<9>=MEM_A_DQ<13>

=MEM_A_DQ<0>

=MEM_A_DQ<1>

MEM_A_A<14>

=PPSPD_S0_MEM_A

=MEM_A_DQ<9>

=MEM_A_DQ<2>

=MEM_A_DQ<1>

=MEM_A_DQ<50>

=MEM_A_DQ<43>

=MEM_A_DQ<42>

=MEM_A_DQ<41>

=MEM_A_DQ<34>

=MEM_A_DQS_N<4>

MEM_A_WE_L

MEM_A_A<10>

MEM_A_A<5>

MEM_A_A<12>

MEM_A_A<9>

MEM_A_A<8>

=MEM_A_DQ<36>

=PP1V5_S3_MEM_A

=MEM_A_DQ<0>

=MEM_A_DQ<24>

=MEM_A_DQ<25>

=MEM_A_DQ<16>

=MEM_A_DQ<7>

=MEM_A_DQS_N<0>

=MEM_A_DQ<32>

MEM_A_ODT<3>

=MEM_A_DQ<10>

=MEM_A_DQ<3>

=MEM_A_DQ<28>

=MEM_A_DQS_N<3>

=MEM_A_DQ<61>

=MEM_A_DQ<49>

=MEM_A_DQ<48>

MEM_A_ODT<1>

MEM_A_CKE<2>

=MEM_A_DQ<38>


=MEM_A_DQ<14>

MEM_RESET_L

=MEM_A_DQ<30>

=MEM_A_DQ<11>

=MEM_A_DQ<6>

=MEM_A_DQ<11>

MEM_A_CKE<3>

MEM_A_A<7>

MEM_A_A<0>

=MEM_A_DQ<24>

=MEM_A_DQ<12>

MEM_A_A<13>

=MEM_A_CLK_N<0>

=MEM_A_DQ<29>

=MEM_A_DQ<18>

=MEM_A_DQ<28>

=MEM_A_DQ<23>

MEM_A_A<6>

=MEM_A_DQ<23>

=MEM_A_DQS_P<3>

=MEM_A_DQ<44>

=MEM_A_DQ<52>

=MEM_A_DQ<49>

MEM_A_A<2>MEM_A_A<2>

=MEM_A_CLK_P<1>

MEM_A_A<0>

MEM_A_A<4>

MEM_A_A<11>

MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_WE_L

MEM_A_CS_L<1>

=MEM_A_DQ<32>

=MEM_A_DQ<34>

=MEM_A_DQ<41>

=MEM_A_DQ<38>

=MEM_A_DQ<26>

=MEM_A_DQS_P<6>

=MEM_A_DQS_N<1>

MEM_A_A<12>

=MEM_A_DQ<22>

=MEM_A_DQ<25>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_A<1>

=MEM_A_CLK_P<3>

MEM_A_A<14>

=MEM_A_DQ<30>=MEM_A_DQ<26>

=MEM_A_DQ<27>

MEM_A_A<1>

=MEM_A_DQS_P<6>

=MEM_A_DQ<5>

=MEM_A_DQS_N<5>

=MEM_A_DQS_P<5>

=MEM_A_DQ<17>

=MEM_A_DQ<39>

=MEM_A_DQ<21>

=MEM_A_DQS_P<7>

=MEM_A_DQ<63>

MEM_EVENT_L

=I2C_SODIMMA_SCL

=PPSPD_S0_MEM_A

=MEM_A_DQ<43>

MEM_A_A<15>

=MEM_A_DQ<19>

=MEM_A_DQ<18>

MEM_A_BA<0>

MEM_DIMM0_SA<0>

MEM_DIMM0_SA<1>

MEM_DIMM2_SA<0>

MEM_DIMM2_SA<1>

MEM_DIMM2_SA<1>


=MEM_A_DQ<51>

MEM_A_BA<2>

=MEM_A_DQ<59>

=MEM_A_DQ<58>

=MEM_A_DQ<57>

=MEM_A_DQ<56>

=MEM_A_DQ<48>

=MEM_A_DQ<40>

=MEM_A_DQ<35>

=MEM_A_DQS_P<4>

=MEM_A_DQ<33>

=MEM_A_DQS_N<7>


=MEM_A_DQ<53>

=MEM_A_DQ<60>

=MEM_A_DQ<45>

=MEM_A_DQ<46>

=MEM_A_DQ<47>


=MEM_A_DQ<36>

=MEM_A_DQ<37>

=MEM_A_DQ<39>

MEM_A_CS_L<2>

MEM_A_BA<1>

=MEM_A_CLK_N<3>

MEM_A_RAS_L

=MEM_A_DQ<6>

=MEM_A_DQ<55>

=MEM_A_DQ<54>

MEM_A_CAS_L

MEM_A_A<13>

MEM_A_CS_L<3>

=MEM_A_CLK_N<1>

=MEM_A_DQS_N<2>

=MEM_A_DQ<21>

=MEM_A_DQ<4>

=MEM_A_DQ<20>

=MEM_A_DQ<15>

MEM_A_A<11>

=MEM_A_DQS_P<5>

=MEM_A_DQ<47>

=MEM_A_DQ<46>

=MEM_A_DQ<61>

=MEM_A_DQ<54>

=MEM_A_DQ<53>

=MEM_A_DQ<62>

MEM_EVENT_L

=MEM_A_DQS_N<7>

=MEM_A_DQS_P<7>

=MEM_A_DQ<63>


=I2C_SODIMMA_SDA

=I2C_SODIMMA_SCL

=MEM_A_CLK_P<0>

=MEM_A_DQ<33>

=MEM_A_DQS_N<4>

=MEM_A_DQS_P<4>

=MEM_A_DQ<35>

=MEM_A_DQ<40>

=MEM_A_DQ<42>

=MEM_A_DQS_N<6>

=MEM_A_DQ<50>

=MEM_A_DQ<56>

=MEM_A_DQ<57>

=MEM_A_DQ<59>

MEM_A_A<10>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<3>

=MEM_A_DQ<37>

MEM_A_BA<1>

=MEM_A_DQ<55>

=MEM_A_DQS_N<5>

=MEM_A_DQ<15>

=MEM_A_DQ<4>

=MEM_A_DQ<5>

=MEM_A_DQ<13>

=MEM_A_DQS_P<0>

=MEM_A_DQS_N<0>

MEM_RESET_L

=MEM_A_DQ<12>

=MEM_A_DQS_P<0>

=MEM_A_DQS_N<3>

=MEM_A_DQS_P<3>

=MEM_A_DQ<31>

=PP1V5_S3_MEM_A



31 OF 110

11.1.0

051-8115

30 OF 98

30 49

30 32

30 32

12 89

12 89

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

6 28 29 30

30 32

30 32

30

6 30 47

30

6 30 47

30

6 30

30 32

30 32

30 32

30 32

12 30 89

12 30 89

12 89

30 32

30 32

30 32

12 30 89 12 89

28 30 95

32

32

30 32

12 89

30 32

30 32 30 32

30 32

30 32

30 32

30 32

28 30 95

30 32

6 28 29 30

12 30 89

12 30 89

12 30 89

28 30 95

30 32 30 32

30 32

30 32

12 30 89

6 30 47

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

12 30 89

12 30 89

12 30 89

12 30 89

12 30 89

12 30 89

30 32

6 28 29 30

30 32

30 32

30 32

30 32

30 32

30 32

30 32

12 89

30 32

30 32

30 32

30 32

30 32

30 32

30 32

12 89

12 89

30 32

28 30 95

30 32

30 31 32 89 97

30 32

30 32

30 32

30 32

12 89

12 30 89

12 30 89

30 32

30 32

12 30 89

32

30 32

30 32

30 32

30 32

12 30 89

30 32

30 32

30 32

30 32

30 32

12 30 89 12 30 89

32

12 30 89

12 30 89

12 30 89

12 30 89

12 30 89

12 30 89

12 89

30 32

30 32

30 32

30 32

30 32

30 32

30 32

12 30 89

30 32

30 32

12 30 89

12 30 89

12 30 89

32

12 30 89

30 32 30 32

30 32

12 30 89

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 31 47

30 49

6 30 47

30 32

12 30 89

30 32

30 32

12 30 89

30

30

30

30

30

6 30

30 32

12 30 89

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

6 30

30 32

30 32

30 32

30 32

30 32

28 30 95

30 32

30 32

30 32

12 89

12 30 89

32

12 30 89

30 32

30 32

30 32

12 30 89

12 30 89

12 89

32

30 32

30 32

30 32

30 32

30 32

12 30 89

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 31 47

30 32

30 32

30 32

6 30

30 49

30 49

32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

12 30 89

12 30 89

12 30 89

12 30 89

30 32

12 30 89

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 32

30 31 32 89 97

30 32

30 32

30 32

30 32

30 32

6 28 29 30

6 30

28 30 95

www.vinafix.vn

S1*

A13

VDD_14

CAS*

VDD_12

BA0

A10_AP

WE*

A3

DQ54

DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQS0*

DQ5

DQ4

DQ6

DQ7

VREFDQ

VSS_1

VSS_3

DQ0

DQ1

DM0

VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

RESET*

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

DQS3*

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30

DQ31

VSS_25

VDD_1

CKE1

A15

A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2

A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

RAS*

VDD_11

CK1*

BA1

S0*

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

DQS5*

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

VTT_1

DQS7*

DQS7

EVENT*

VSS_51

DQ63

DQ62

VSS_49

SDA

SCL

DQ2

DQ3

VSS_6

DQ8

DQ9

VSS_8

DQS1*

DQS1

VSS_10

DQ16

VSS_12

DQ11

DQ10

DQ17

DQ18

DQS2

VSS_17

DQS2*

VSS_14

VSS_21

DQ24

DQ25

DQ19

VSS_19

VSS_24

DQ27

DQ26

DM3

VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

CK0*

DQ33

VSS_26

VDD_16

TEST

DQ32

DQ34

VSS_31

DQS4

DQS4*

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6*

DQS6

VSS_40

DQ49

DQ50

VSS_45

DQ56

DQ57

VSS_47

DM7

DQ58

VSS_48

DQ59

SA0

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ51

VTT_0

SA1

VDDSPD

MTG PIN MTG PIN

KEY

(1 OF 2)

DQ3

VSS_10

VSS_19

DQ9

VSS_8

DQS1*

DQS1

VSS_21

DQ26

CKE0

BA2

A9

A8

VDD_6

VDD_8

CK0*

A10_AP

BA0

SA0

VTT_0

SA1

VDDSPD

VSS_50

VSS_47

DM7

DQ58

DQ59

DQ57

DQ56

VSS_45

DQ51

DQ50

DQS6

VSS_43

DQS6*

VSS_40

DQ49

DQ48

VSS_38

DQ43

DQ42

VSS_36

DM5

VSS_35

DQ41

DQ40

DQ35

DQ34

VSS_31

DQS4

DQS4*

VSS_28

VSS_26

DQ32

DQ33

TEST

VDD_16

S1*

A13

CAS*

VDD_14

WE*

VDD_12

VDD_10

CK0

A1

A3

A5

VDD_4

A12/BC*

VDD_2

VDD_0

NC_0

DQ11

DQ16

VSS_12

DQ10

DQ8

DM0

VSS_4

VSS_6

DQ2

VREFDQ

DQ0

VSS_3

DQ1

VSS_1

SCL

SDA

VTT_1

VSS_51

VSS_49

DQ63

DQS7

DQS7*

EVENT*

DQ62

DM6

DQ60

VSS_46

VSS_41

DQ53

DQ55

VSS_44

DQ54

VSS_42

DQ61

DQ52

DQ44

VSS_34

DQS5*

VSS_37

DQ46

DQ47

VSS_39

DQ45

DQS5

VSS_32

DM4

VSS_27

VSS_29

DQ36

VREFCA

VDD_17

DQ37

DQ38

DQ39

VSS_30

BA1

NC_1

VDD_13

VDD_11

VDD_15

ODT0

CK1

A0

A2

A6

A4

A7

A11

VDD_9

VDD_7

VDD_5

VDD_3

A15

A14

CKE1

VDD_1

DM1

DQ15

DQ14

DQ13

VSS_11

VSS_9

RESET*

VSS_13

DQ20

DQ12

DQ7

DQ6

DQ5

DQ4

VSS_7

DQS0*

VSS_2

VSS_0

DQS0

VSS_5

DQ21

VSS_15

DM2

VSS_16

DQ22

VSS_18

DQ23

DQ28

VSS_20

DQ29

DQS3

VSS_23

DQS3*

DQ30

DQ31

VSS_25

VSS_14

DQ17

DQS2*

VSS_17

DQS2

DQ18

DQ19

DQ25

DQ24

DM3

VSS_22

DQ27

VSS_24

CK1*

RAS*

S0*

ODT1

VSS_33

VSS_48

KEY

(2 OF 2)




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

CPU - MEM Ch. B

STACKED SO-DIMM CONN.

- =PP1V5_S3_MEM_B

(Section A)

DIMM3

DIMM1

(Section B)


- =PP1V5_S0_MEM_B

DIMM1 SPD ADDR=0XA4(WR)/0XA5(RD) DIMM3 SPD ADDR=0XA6(WR)/0XA7(RD)

(NONE)

- =I2C_SODIMMB_SCL

- =PP0V75_S0_MEM_VTT_B

- =I2C_SODIMMB_SDA


- =PPSPD_S0_MEM_B (2.5 - 3.3V)

Page Notes

- ALL DQ, DQS, DM SIGNALS;


TO FACILITATE BITSWAPS WITH ALIASES

DIMM 3

DIMM 1

2

1 C32310.1UF20%10VCERM402

2

1 C3230

CERM

2.2UF20%6.3V

402-LF

2

1 C3236

10V20%0.1UF

402CERM2

1 C32352.2UF

402-LF

20%

CERM6.3V

2

1 C3251

CERM6.3V20%

402-LF

2.2UF

2

1 C3250

6.3V20%

CERM402-LF

2.2UF

2

1R3243

402

5%1/16WMF-LF

10K

2

1R3242

MF-LF1/16W5%

402

10K

2

1 C3240

20%2.2UF

6.3V

402-LFCERM

2

1R324010K5%

402

1/16WMF-LF

2

1R3241

MF-LF1/16W5%

402

10K

113A

204A203A

26A25A

20A19A

14A

196A195A

13A

190A189A

185A

184A

179A

178A

173A

172A

168A167A

9A

162A161A

156A155A

151A

150A

145A

144A

139A

138A

8A

134A133A

128A127A

72A71A

66A65A

61A

60A

3A

55A

54A

49A

48A

44A43A

38A37A

32A31A

2A1A

126A

199A

100A99A

94A93A

88A87A

82A81A

76A

124A123A

118A117A

112A111A

106A105A

75A

125A

200A

202A201A

197A

121A

114A

30A

110A

120A

116A

122A

77A

410409

198A

186A

188A

169A

171A

152A

154A

135A

137A

62A

64A

45A

47A

27A

29A

10A

12A

23A

21A

18A

16A

194A

192A

182A

180A

6A

193A

191A

183A

181A

176A

174A

166A

164A

177A

175A

4A

165A

163A

160A

158A

148A

146A

159A

157A

149A

147A

17A

142A

140A

132A

130A

143A

141A

131A

129A

70A

68A

15A

58A

56A

69A

67A

59A

57A

52A

50A

42A

40A

7A

53A

51A

41A

39A

36A

34A

24A

22A

35A

33A

5A

187A

170A

153A

136A

63A

46A

28A

11A

74A73A

104A

102A

103A

101A

115A

79A

108A

109A

85A

89A

86A

90A

91A 92A

95A 96A

97A

78A

80A

119A

83A 84A

107A

98A

J3200F-RT-TH

CRITICAL

DDR3-SODIMM-DUAL

113B

204B203B

26B25B

20B19B

14B

196B195B

13B

190B189B

185B

184B

179B

178B

173B

172B

168B167B

9B

162B161B

156B155B

151B

150B

145B

144B

139B

138B

8B

134B133B

128B127B

72B71B

66B65B

61B

60B

3B

55B

54B

49B

48B

44B43B

38B37B

32B31B

2B1B

126B

199B

100B99B

94B93B

88B87B

82B81B

76B

124B123B

118B117B

112B111B

106B105B

75B

125B

200B

202B201B

197B

121B

114B

30B

110B

120B

116B

122B

77B

198B

186B

188B

169B

171B

152B

154B

135B

137B

62B

64B

45B

47B

27B

29B

10B

12B

23B

21B

18B

16B

194B

192B

182B

180B

6B

193B

191B

183B

181B

176B

174B

166B

164B

177B

175B

4B

165B

163B

160B

158B

148B

146B

159B

157B

149B

147B

17B

142B

140B

132B

130B

143B

141B

131B

129B

70B

68B

15B

58B

56B

69B

67B

59B

57B

52B

50B

42B

40B

7B

53B

51B

41B

39B

36B

34B

24B

22B

35B

33B

5B

187B

170B

153B

136B

63B

46B

28B

11B

74B73B

104B

102B

103B

101B

115B

79B

108B

109B

85B

89B

86B

90B

91B 92B

95B 96B

97B

78B

80B

119B

83B 84B

107B

98B

J3200CRITICAL

F-RT-TH

DDR3-SODIMM-DUAL

DDR3 SO-DIMM 1 & 3SYNC_MASTER=K62 SYNC_DATE=01/06/2011

=MEM_B_DQS_P<4>

MEM_B_A<2>

=MEM_B_CLK_N<1>

MEM_B_BA<1>

MEM_B_A<0>

=MEM_B_DQS_P<2>

MEM_B_A<11>

=PP1V5_S3_MEM_B


MEM_B_CKE<0>

=MEM_B_DQ<2>

=MEM_B_DQ<34>

=MEM_B_DQ<35>

=PP1V5_S3_MEM_B

=MEM_B_DQ<10>


=MEM_B_DQ<0>

=MEM_B_DQ<1>

=MEM_B_DQ<7>

=MEM_B_DQ<12>

MEM_B_A<13>

=MEM_B_DQ<32>


=MEM_B_DQ<31>

=MEM_B_DQ<13>

MEM_B_WE_L

=MEM_B_DQ<27>

MEM_B_A<9>

MEM_B_A<12>

=PPSPD_S0_MEM_B

MEM_DIMM3_SA<1>


MEM_DIMM3_SA<0>

=MEM_B_DQ<59>

=MEM_B_DQ<58>

=MEM_B_DQ<57>

=MEM_B_DQ<49>

=MEM_B_DQS_N<6>

=MEM_B_DQ<42>

=MEM_B_DQ<43>

=MEM_B_DQ<40>

=MEM_B_DQ<41>

=MEM_B_DQS_N<4>

=MEM_B_DQ<33>

=MEM_B_CLK_P<2>

=MEM_B_DQ<26>

=MEM_B_DQ<11>

=MEM_B_DQ<16>

=MEM_B_DQS_P<1>

=MEM_B_DQ<9>

=MEM_B_DQ<8>

=MEM_B_DQ<3>

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

=MEM_B_DQ<62>

=MEM_B_DQ<63>

=MEM_B_DQS_P<7>

=MEM_B_DQS_N<7>


=MEM_B_DQ<53>

=MEM_B_DQ<60>

=MEM_B_DQ<47>

=MEM_B_DQ<37>

=MEM_B_DQ<38>

MEM_B_CS_L<2>

MEM_B_BA<1>

=MEM_B_CLK_N<3>

MEM_B_RAS_L

MEM_B_ODT<2>

MEM_B_ODT<3>

=MEM_B_CLK_P<3>

MEM_B_A<0>

MEM_B_A<2>

MEM_B_CKE<3>

=MEM_B_DQ<30>

=MEM_B_DQS_P<3>

=MEM_B_DQ<29>

=MEM_B_DQ<28>

=MEM_B_DQ<23>

=MEM_B_DQ<21>

=MEM_B_DQ<14>

=MEM_B_DQ<15>

=MEM_B_DQ<20>

=MEM_B_DQ<6>

=MEM_B_DQ<4>

=MEM_B_DQS_P<0>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

MEM_B_A<3>

MEM_B_CS_L<3>

=MEM_B_DQ<27>

=MEM_B_DQ<24>

=MEM_B_DQ<25>

=MEM_B_DQ<19>

=MEM_B_DQ<18>

=MEM_B_DQS_P<2>

=MEM_B_DQS_N<2>

=MEM_B_DQ<17>

=MEM_B_DQS_N<3>

=MEM_B_DQS_P<3>

=MEM_B_DQ<28>

=MEM_B_DQ<23>

=MEM_B_DQ<22>

=MEM_B_DQ<21>

=MEM_B_DQS_P<0>

=MEM_B_DQS_N<0>

=MEM_B_DQ<4>

=MEM_B_DQ<5>

=MEM_B_DQ<13>

=MEM_B_DQ<14>

MEM_B_CKE<1>

MEM_B_A<14>

=MEM_B_DQ<38>

=MEM_B_DQ<37>

=MEM_B_DQ<36>

=MEM_B_DQS_P<5>

=MEM_B_DQ<47>

=MEM_B_DQ<46>

=MEM_B_DQS_N<5>

=MEM_B_DQ<44>

=MEM_B_DQ<52>

=MEM_B_DQ<61>

=MEM_B_DQ<53>

=MEM_B_DQ<60>

=MEM_B_DQ<62>

MEM_EVENT_L

=MEM_B_DQS_N<7>

=MEM_B_DQS_P<7>

=MEM_B_DQ<63>


=MEM_B_DQ<1>

=MEM_B_DQ<0>


=MEM_B_DQ<8>

=MEM_B_DQ<10>

=MEM_B_DQ<16>

=MEM_B_DQ<11>

MEM_B_A<12>

MEM_B_A<5>

MEM_B_A<3>

MEM_B_A<1>

=MEM_B_CLK_P<0>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_A<13>

MEM_B_CS_L<1>

=MEM_B_DQ<33>

=MEM_B_DQ<32>

=MEM_B_DQS_N<4>

=MEM_B_DQS_P<4>

=MEM_B_DQ<34>

=MEM_B_DQ<35>

=MEM_B_DQ<41>

=MEM_B_DQ<42>

=MEM_B_DQ<43>

=MEM_B_DQ<48>

=MEM_B_DQ<49>

=MEM_B_DQS_N<6>

=MEM_B_DQS_P<6>

=MEM_B_DQ<50>

=MEM_B_DQ<51>

=MEM_B_DQ<56>

MEM_B_BA<0>

MEM_B_A<10>

=MEM_B_CLK_N<0>

MEM_B_A<8>

MEM_B_A<9>

=MEM_B_DQ<26>

=MEM_B_DQS_P<1>

=MEM_B_DQS_N<1>

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_CS_L<0>

=MEM_B_CLK_P<1>

=MEM_B_DQ<22>

=MEM_B_DQS_N<3>

MEM_B_A<10>

MEM_B_A<1>

MEM_B_A<5>

MEM_B_A<8>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<14>

MEM_B_A<15>

=MEM_B_DQ<2>

=MEM_B_DQ<15>

=MEM_B_DQ<46>

=MEM_B_DQ<52>=MEM_B_DQ<48>

=MEM_B_DQS_P<6>

=MEM_B_DQ<40>

=MEM_B_DQ<3>

=MEM_B_DQ<12>

=MEM_B_DQ<7>

=MEM_B_DQ<6>

=MEM_B_DQS_P<5>

=MEM_B_DQ<45>

=MEM_B_DQ<44>

=MEM_B_DQ<39>

MEM_B_CAS_L

=MEM_B_DQ<17>

=MEM_B_DQ<25>

MEM_B_CKE<2>

MEM_B_BA<2>

=PP1V5_S3_MEM_B

=MEM_B_DQ<39>

=MEM_B_DQ<51>

=I2C_SODIMMB_SDA

=I2C_SODIMMB_SCL

MEM_B_A<15>

=MEM_B_DQ<9>

=MEM_B_DQS_N<0>

=MEM_B_DQ<20>

=MEM_B_DQ<31>

=MEM_B_DQ<30>

MEM_B_A<4>

MEM_B_A<6>

=PP1V5_S3_MEM_B

MEM_B_A<7>

MEM_B_A<11>

MEM_B_BA<2>

=MEM_B_DQS_N<2>

=MEM_B_DQS_N<1>

=MEM_B_DQ<19>

=MEM_B_DQ<18>

=MEM_B_DQ<24>

MEM_B_A<7>

MEM_DIMM1_SA<1>


=MEM_B_DQ<36>

=MEM_B_DQ<57>

=MEM_B_DQ<58>

=MEM_B_DQ<59>

=PPSPD_S0_MEM_B

=MEM_B_DQS_N<5>

MEM_B_BA<0>

=MEM_B_CLK_N<2>

MEM_EVENT_L MEM_DIMM1_SA<0>

MEM_B_RAS_L

MEM_RESET_L

=MEM_B_DQ<29>

MEM_DIMM3_SA<0>

=PPSPD_S0_MEM_B

MEM_DIMM3_SA<1>MEM_DIMM1_SA<1>

MEM_DIMM1_SA<0>

=PPSPD_S0_MEM_B =PPSPD_S0_MEM_B



=MEM_B_DQ<54>

=MEM_B_DQ<55>

MEM_RESET_L

=MEM_B_DQ<45>

=MEM_B_DQ<61>

=MEM_B_DQ<5>

=MEM_B_DQ<50>

=MEM_B_DQ<56>


32 OF 110

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051-8115

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31

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32

30 31 47 31

12 31 89

30 31 32 89 97

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www.vinafix.vn

G S

D

G

D

S

DS

G

G

D

SG

D

S

PAD

VCC

THRMGND

1RD*

1Q

2SD*

2D

2CP

2RD*

2Q

2Q*

1CP

1D 1Q*

1SD*

G

D

S

G S

D

G

SD




36

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SHEET

PAGE TITLE

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Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

CPU CHANNEL B DQS 0 -> DIMM B DQS 7

CPU CHANNEL A DQS 6 -> DIMM A DQS 1 CPU CHANNEL B DQS 6 -> DIMM B DQS 1

CPU CHANNEL A DQS 3 -> DIMM A DQS 4











CPU CHANNEL B DQS 7 -> DIMM B DQS 0CPU CHANNEL A DQS 7 -> DIMM A DQS 0

MEMORY CLOCK ALIASING

0 0 1.5V

0 3.3V 0

1.5V 3.3V 1.5V

0 3.3V 0

1.5V 3.3V 1.5V

0 3.3V 0

CPU_RESET_L ISOLATE_L MEM_RESET_L

H H POSEDGE H H L

L L X X H H

H L X X L H

L H X X H L

H H POSEDGE L L H

S R CLK D Q QB

S0

S5

S0

S3

S0

S5

SNB? CANNOT CONTROL THIS SIGNAL DIRECTLY SINCE IT MUST BE HIGH IN SLEEP AND CPU MEM RAILS ARE NOT POWERED IN SLEEP.

DDR3 RESET SUPPORT

2

1R3353

402MF-LF

5%1/16W

20K

2

1C3353

402

10%

CERM

0.0022UF50V

2

1R3382MEM_RESET_HW

10K

MF-LF1/16W

402

5%

2

1

3

Q3350MEM_RESET_HW

2N7002SOT23-HF1

2

1R3381

5%

402

1/16WMF-LF

10K

MEM_RESET_HW

2

1R3384

1/16WMF-LF402

5%20K

2

3

1 Q3360SOT23-HF

MEM_RESET_HW

2N3904

4

5

3

Q3370

SOT-3632N7002DW-X-G

21

R3355NOSTUFF

1/16WMF-LF

0

5%

402

2

1

3

Q33042N7002SOT23-HF1

2

1R3352

5%20K

1/16W

402MF-LF

4

5

3

Q33062N7002DW-X-GSOT-363

2

1R335120K5%1/16W

402MF-LF

2

1R3350

1/16W5%

402MF-LF

20K

1

2

6

Q3306

SOT-3632N7002DW-X-G

21

R3380

MF-LF

MEM_RESET_HW

402

5%1/16W

10K

21

R3385

5%

0

1/16WMF-LF402

21

R3383

402MF-LF

5%

0

1/16W

NOSTUFF

2

1R3387

5%

402MF-LF1/16W

20K

21

R3393

402

5%

0

MF-LF1/16W

NOSTUFF

21

R33940

402MF-LF1/16W5%

2

1C3300MEM_RESET_HW

402

0.1UF20%

CERM10V

14

15

10

4

13

1

8

6

9

5

7

12

2

11

3

U3300

MEM_RESET_HW

DHVQFN74LVC74ABQ

2

1C3390NOSTUFF

CERM

20%10V

0.1UF

402

5

4

1

2

3

U3390

SOT23-5-HF

NOSTUFFMC74VHC1G08

1

2

6

Q33702N7002DW-X-GSOT-363

21

R3391

1/16WMF-LF402

NOSTUFF

5%

0

21

R33860

5%1/16WMF-LF402

NOSTUFF

2

1R3388

402

5%

MF-LF

10

1/16W

2

1

3

Q33802N7002SOT23-HF1

3

2

1

4

5

Q3375POWER33

FDMC8296

2

1R3340

402

5%

MF-LF1/16W

100K

21

R33900

5%

NOSTUFF

MF-LF1/16W

402

DDR3 SUPPORT AND BITSWAPSSYNC_MASTER=K62 SYNC_DATE=01/06/2011

=MEM_B_DQS_N<4>

=MEM_B_DQS_P<4>

=MEM_B_DQ<32>

=MEM_B_DQ<39>

PM_EN_DDRVTT_S0_REG

=MEM_B_DQ<29>

=MEM_B_DQ<30>

=MEM_B_DQ<31>

=MEM_B_DQ<28>

=MEM_B_DQS_N<3>

=MEM_B_DQS_P<3>

=MEM_B_DQ<59>

PPVTT_S0_DDR_FET

CPU_MEM_RESET3V3_L

PM_SLP_S3_L

PM_SYS_PWRGD

=MEM_B_DQ<45>

=MEM_B_DQS_P<5>

=MEM_B_DQS_N<5>

TP_PM_SLP_S4_DPM_SLP_S4_L

=PP3V3_S3_MEMRESET

PM_SLP_S4_D_L

PM_SLP_S4_D_L

=PP3V3_S3_MEMRESET

SLP_S3_CTL_L

CPU_MEM_RESET_R_LCPU_MEM_RESET_L

ISOLATE_CPU_MEM_L

=PP3V3_S5_MEMRESET

=PP5V_S3_MEMRESET

CPU_MEM_RESET3V3

=PP3V3_S5_MEMRESET

ISOLATE_CPU_MEM_L_R1

=PP5V_S3_MEMRESET

MEM_RESET_L

CPU_MEM_RESET_L

=PP1V5_S3_MEMRESET

PM_SLP_S3_5V_L

CPU_MEM_RESET3V3_L

=PP3V3_S3_MEMRESET

MAKE_BASE=TRUEMEM_B_CLK_P<2>

NO_TEST=TRUE=MEM_B_CLK_P<2>

MAKE_BASE=TRUEMEM_B_CLK_N<1>

NO_TEST=TRUE=MEM_B_CLK_N<1>







MAKE_BASE=TRUEMEM_A_CLK_N<3>

NO_TEST=TRUE=MEM_A_CLK_N<3>

MEM_B_CLK_P<0>MAKE_BASE=TRUE NO_TEST=TRUE

=MEM_B_CLK_P<0>



MEM_B_CLK_N<0>MAKE_BASE=TRUE NO_TEST=TRUE

=MEM_B_CLK_N<0>

MAKE_BASE=TRUEMEM_A_CLK_P<1>

NO_TEST=TRUE=MEM_A_CLK_P<1>











MEM_A_CLK_P<0>MAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUEMEM_A_DQ<56>

MAKE_BASE=TRUEMEM_A_DQ<57> =MEM_A_DQ<7>




MEM_A_DQ<61>MAKE_BASE=TRUE








=MEM_A_DQ<10>

=MEM_A_DQ<13>

=MEM_A_DQ<12>

=MEM_A_DQS_P<1>MAKE_BASE=TRUE

MEM_A_DQS_N<6>NO_TEST=TRUE

=MEM_A_DQS_N<1>

=MEM_A_DQ<20>

=MEM_A_DQ<22>

MEM_A_DQS_P<5>MAKE_BASE=TRUE NO_TEST=TRUE

=MEM_A_DQ<30>

=MEM_A_DQ<24>



MAKE_BASE=TRUEMEM_A_DQS_P<4>

NO_TEST=TRUE

MAKE_BASE=TRUEMEM_A_DQS_N<4>

NO_TEST=TRUE=MEM_A_DQS_N<3>




=MEM_A_DQ<34>MAKE_BASE=TRUE

MEM_A_DQ<29>



MEM_A_DQ<31>

=MEM_A_DQS_P<4>

=MEM_A_DQS_N<4>


MEM_A_DQ<17> =MEM_A_DQ<43>


=MEM_A_DQ<44>

=MEM_A_DQ<41>


=MEM_A_DQ<47>


=MEM_A_DQ<46>

=MEM_A_DQ<40>



=MEM_A_DQS_P<5>

=MEM_A_DQS_N<5>

=MEM_A_DQ<55>

=MEM_A_DQ<54>

MEM_B_DQ<56>MAKE_BASE=TRUE

=MEM_B_DQ<0>


=MEM_B_DQ<6>


=MEM_B_DQ<4>

MAKE_BASE=TRUEMEM_B_DQ<58> =MEM_B_DQ<5>





MAKE_BASE=TRUEMEM_B_DQS_P<7>

NO_TEST=TRUE=MEM_B_DQS_P<0>

MEM_B_DQS_N<7>MAKE_BASE=TRUE NO_TEST=TRUE

=MEM_B_DQS_N<0>


=MEM_B_DQ<13>


=MEM_B_DQ<12>MAKE_BASE=TRUE

MEM_B_DQ<50> =MEM_B_DQ<15>







=MEM_B_DQ<8>


NO_TEST=TRUE=MEM_B_DQS_P<1>

=MEM_B_DQS_N<1>

=MEM_B_DQ<17>


=MEM_B_DQ<16>








=MEM_B_DQ<18>

MEM_B_DQS_P<5>MAKE_BASE=TRUE NO_TEST=TRUE

=MEM_B_DQS_P<2>

MEM_B_DQS_N<5>MAKE_BASE=TRUE NO_TEST=TRUE

=MEM_B_DQS_N<2>





=MEM_B_DQ<25>




=MEM_B_DQ<24>



MAKE_BASE=TRUEMEM_B_DQS_N<4>

NO_TEST=TRUE







=MEM_B_DQ<37>


MAKE_BASE=TRUEMEM_B_DQ<31>


NO_TEST=TRUE


NO_TEST=TRUE


=MEM_B_DQ<43>


=MEM_B_DQ<41>



=MEM_B_DQ<44>






NO_TEST=TRUE



=MEM_A_DQ<48>


=MEM_A_DQS_P<6>MAKE_BASE=TRUE

MEM_A_DQS_N<1>NO_TEST=TRUE

=MEM_A_DQS_N<6>



MEM_A_DQ<4>

=MEM_A_DQ<58>

=MEM_A_DQ<57>





=MEM_B_DQ<52>



=MEM_B_DQS_N<6>


=MEM_B_DQS_P<6>



=MEM_B_DQ<58>


=MEM_B_DQ<57>


=MEM_B_DQ<63>

=MEM_B_DQ<56>


=MEM_B_DQ<62>


=MEM_B_DQ<60>

=MEM_B_DQ<61>


=MEM_B_DQS_P<7>

=MEM_B_DQS_N<7>

ISOLATE_CPU_MEM

PM_SLP_S3_5V

=MEM_B_DQ<55>


MEM_B_DQ<10>=MEM_A_DQ<53>

PM_SLP_S3_5V_L

VTT_R

=PP0V75_S0_MEM_VTT_S0FET

PM_SLP_S3_5V

=MEM_B_DQ<40>

ISOLATE_CPU_MEM_L_R1

ISOLATE_CPU_MEM_5V_L

TP_ISOLATE_CPU

ISOLATE_CPU_MEMHW_L

PM_SLP_S3_L

=PP3V3_S5_MEMRESET

PM_SLP_S3_5V_R2

DDRSYS_EN

ALL_SYS_PWRGD_R


=MEM_A_DQ<32>




=MEM_A_DQ<59>


=MEM_A_DQ<62>



=MEM_A_DQ<56>

=MEM_A_DQS_P<7>

=MEM_A_DQ<50>


=MEM_A_DQS_N<7>


NO_TEST=TRUE






=MEM_A_DQ<63>

=MEM_A_DQ<61>




=MEM_A_DQ<49>

=MEM_A_DQ<51>

=MEM_A_DQ<52>

=MEM_A_DQ<39>

=MEM_A_DQ<35>





=MEM_A_DQ<45>


=MEM_B_DQ<10>


NO_TEST=TRUE


NO_TEST=TRUE





NO_TEST=TRUE

=MEM_A_DQS_N<2>

=MEM_A_DQ<26>

=MEM_A_DQ<31>

=MEM_A_DQ<27>

=MEM_A_DQ<29>

=MEM_A_DQ<28>

=MEM_A_DQ<25>



NO_TEST=TRUE




=MEM_A_DQ<19>




=MEM_A_DQS_P<2>

=MEM_A_DQ<16>

=MEM_A_DQ<37>



MEM_A_DQS_N<3>MAKE_BASE=TRUE NO_TEST=TRUE

=MEM_A_DQ<38>

=MEM_A_DQ<17>

=MEM_A_DQ<18>





=MEM_A_DQ<23>

=MEM_A_DQ<21>



=MEM_A_DQ<5>

=MEM_A_DQS_P<0>

=MEM_A_DQS_N<0>

=MEM_A_DQ<6>

=MEM_A_DQ<0>

=MEM_A_DQ<1>

=MEM_A_DQ<2>

=MEM_A_DQ<3>

=MEM_A_DQ<4>


NO_TEST=TRUE

=MEM_A_DQ<8>

=MEM_A_DQ<14>

=MEM_A_DQ<15>


NO_TEST=TRUE

=MEM_A_CLK_P<0>


NO_TEST=TRUE

MEM_A_DQS_N<0>MAKE_BASE=TRUE NO_TEST=TRUE

MEM_A_DQS_N<2>MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE

MEM_B_DQS_N<2>NO_TEST=TRUE


NO_TEST=TRUE


=MEM_A_DQS_P<3>


33 OF 110

11.1.0

051-8115

32 OF 98

31

31

31

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63 71 97

31

31

31

31

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32

5 19 26 32 36 46 47 63 82 97

19 64 97

31

31

31

5 19 46 47 63 97

6 32

32 97

32 97

6 32

11 32 97

21 25 97

6 32

6 32

6 32

32

6 32

30 31 89 97

11 32 97

6

32 97

32

6 32

12 89 31

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30

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30

30

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30

30

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30

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30

30

30

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30

12 89 30

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30

12 89

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30

30

30

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31

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30

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31

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31

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31

32 97

31

31

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32 97

6

32 97

31

32

5 19 26 32 36 46 47 63 82 97

6 32

97

5 64 97

12 89

30

12 89

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30

12 89

30

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30

30

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12 89

30

12 89

12 89

12 89

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30

30

12 89

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30

30

30

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30

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12 89

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30

30

30

30

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30

12 89

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12 89

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30

30

30

12 89

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30

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12 89

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30

12 89

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30

30

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30

30

30

30

30

12 89

30

30

30

12 89

30

12 89

12 89

12 89 12 89

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12 89

30

12 89

www.vinafix.vn

IN

KEY

IN

IN

OUT

OUT

IN

IN

G

D S

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

RESET*

OUT

EN

MR*

GNDTHRM

IN

VDD

SENSE +-

PAD

(OD)

0.7V

DLY

IN

IN

OUT

OUT

IN

D

GS

OUT

OUT

D

GS




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: CURRENT DATA PER APR 5,2010 PCIE MINI CEM ECN

AP WAKE# ISOLATION

RESET HAS 100MS DELAY ONCE ENABLE IS HIGH

AP PWR EN ISOLATION

516S0457

NC

RESERVED

NC

| MAX CONT. 1100MA 190MA || 3.3V S3 CURRENT D0-D2,D3HOT D3COLD |

NC

| |

NCNCNC

NCNC

NCNC

NC

NC

NCNC

| 1.5V CURRENT || MAX CONT. N/U N/U || MAX PEAK N/U N/U |-----------------------------------------

| MAX PEAK 2750MA 2750MA |

-----------------------------------------

RESERVED

NO AVAILALBLE USB ON THIS PLATFORM

TARGET CARDS DO NOT USE IT

NC

21R3491

MF-LF

0

5%1/16W

402

NOSTUFF

33 97

9

87

6

5251

50

5

49

4847

4645

4443

4241

40

4

39

3837

3635

3433

3231

30

3

29

2827

2625

2423

2221

20

2

19

1817

1615

1413

1211

10

1

54

53

J3400F-RT-SM

CRITICAL

AS0B226-S40N-7F

18 90

18 90

21

R3400

5%1/16W

402MF-LF

0

NOSTUFF

21

R3401

MF-LF

5%

402

1/16W

0

NOSTUFF

21

C34310.1uF

10%16V

402X5R

PLACEMENT_NOTE=PLACE CLOSE TO U1800.

21

C3430PLACEMENT_NOTE=PLACE CLOSE TO U1800.

X5R

0.1uF

10%16V

402

18 90

18 90

18 90

18 90

2

1 C346110%16VX5R

0.1UF

402

1

4

5

Q3403CRITICAL

PQFN

IRFH3702TRPBF

1

9

6

8

2

4

7

5

U3404

CRITICAL

SLG5AP001TDFN

1

9

2

4

8

3

7

5

6

Q3406SLG4AP016V

TDFN

2

1C3408

402

16VX5R

0.1UF10%

2

1R341010K

MF-LF1/16W5%

402

27 97

33

15 97

2

1R3412

402

1/16WMF-LF

1%100K

33 97

33

2

1R3470

1/16WMF-LF

5%10K

402

21

3

Q3470

SOD-VESM-HF

SSM3K15FV

33

19 36 78 97

2

1R3471

MF-LF

5%10K

402

1/16W

21

3

Q3471 AP

SOD-VESM-HF

SSM3K15FV

2

1C3421

X5R603

6.3V20%

10uF

2

1C340120%

X5R603

10uF6.3V

NOSTUFF

2

1C3420

402

20%

CERM10V

0.1uF

2

1C3410

402

0.1uF20%10V

CERM

2

1C340020%10V

402CERM

0.1uF

NOSTUFF

21R3490

402

0

5%1/16WMF-LF

NOSTUFF


PCI-E Wireless ConnectorAP_PWR_EN

PCIE_MINI_R2D_PPCIE_MINI_R2D_N

=PP1V5_S0_MINI

AP_MINI_RESET_L

RSVD_MINI_BT_ACTIVEAP_MINI_CLKREQ_L

SMB_MINI_SDA

PCIE_MINI_R2D_C_P

PCIE_MINI_D2R_P

SMB_MINI_SCL

MINI_RESET_L

MINI_CLKREQ_L

=PP3V3_S3_MINI_CONN

=PP3V3_S3_MINI

TP_USB_MININ

PCIE_MINI_R2D_C_N

TP_USB_MINIP

=SMB_MINI_SCL

=SMB_MINI_SDA

P3V3_S0_MINI_EN_G

AP_MINI_RESET_L

AP_MINI_CLKREQ_L

PCIE_CLK100M_MINI_NPCIE_CLK100M_MINI_P

RSVD_MINI_WLAN_ACTIVE

=PP3V3_S3_MINIAP_PWR_EN_FET

=PP3V3_S3_MINI

AP_PWR_EN_FET

PM_PGOOD_MINI

PP3V3_S3_MINI_CONN

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMVOLTAGE=3.3V

=PP12V_S5_PWRCTL

=PP3V3_S3_MINI_CONN

=PP3V3_S3_MINI_CONN

AP_WAKE_LPCIE_WAKE_L

PCIE_MINI_D2R_N

=PP3V3_S3_MINI_CONN

=PP3V3_S3_MINI

PM_PGOOD_MINI

34 OF 110

11.1.0

051-8115

33 OF 98

3

20 25 97

90

90

6

33

6 33

49

49

6 33

33

6 33

33 97

95

6 64 73

33

33

33

6 33

33 97

www.vinafix.vn

IN

IN

IN

SCL

THRM_PAD

E0

E1

E2VSS

SDA

VCC

WC*

G

D

SG

D

S

TEST

RESET*

USBDM_DN1/PRT_DIS_M1

USBDP_DN1/PRT_DIS_P1







PRTPWR2/BC_EN2*

PRTPWR1/BC_EN1*

PRTPWR4/BC_EN4*

PRTPWR3/BC_EN3*

OCS2*

OCS1*

OSC3*

OSC4*

RBIAS

USBDP_UP

USBDM_UP

VBUS_DET

THRM_PAD

XTALIN/CLKIN

XTALOUT

SUSP_IND/LOCAL_PWR/NON_REM0

SDA/SMBDATA/NON_REM1

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

CRFILT

PLLFILT

VDD33

TABLE_5_ITEM




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_5_ITEM



DEFAULT K23F ==>

SEL1 SEL0 DESCRIPTION

DEFAULT K23F ==>

0 0 Internal Default with Self powered Operation

1 1 EEPROM Supported

0 1 SMBUS Slave Config

0 0 All ports are Non removable

0 1 Port1 is non removable

1 0 Port 1 and 2 are non removable

1 1 Port1,2 and 3 are non Removable

USB HUB-1

1 0 Internal Default with Bus powered Operation

NON_REM1 NON_REM0 DESCRIPTION

BOM TABLE

21

Y3500CRITICAL

5X3.2X1.4-SM

24.000M-60PPM-16PF

2

1 C3520

50V5%

CERM402

18PF21

R3591

5%1/16W

1M

MF-LF402

2

1 C351918PF

402

5%

CERM50V

2

1 C3534

402

0.1UF

X5R16V10%

2

1R3599

402

100K5%

1/16WMF-LF

NOSTUFF

2

1 C3537

402

50V5%

CERM

100PF

2

1 C3543

402CERM50V

100PF5%

2

1R3597NOSTUFF

10K5%

1/16WMF-LF

402

2

1 C3539

16V

402

10%

X7R-CERM

0.1UF

2

1 C354510%

402

16VX7R-CERM

0.1UF

2

1 C3546

16V

402X7R-CERM

10%0.1UF

2

1 C35470.1UF10%16VX7R-CERM402

2

1 C3525

402X7R-CERM

10%16V

0.1UF

2

1 C35230.1UF16V

402

10%

X7R-CERM

2

1 C3524

X7R-CERM

0.1UF16V10%

4022

1 C3528

16VX7R-CERM

10%

402

0.1UF

2

1 C35360.01UF10%16VCERM402

2

1 C354210%16V

402

0.01UF

CERM

2

1 C35290.01UF10%

402

16VCERM2

1 C352610%

CERM16V

0.01UF

402

20 92

20 92

34 35

21

R350012K

MF

1%

402

1/16W

2

1 C351820%

603

6.3V

10UF

X5R

21

L3559

0402

FERR-120-OHM-1.5A

2

1R3598

MF-LF1/16W

10K5%

4022

1R359210K

5%1/16W

402MF-LF

2

1R3594

5%1/16W

402MF-LF

10K

NOSTUFF

2

1R3504

MF-LF1/16W

10K5%

402 2

1R3550

MF-LF

5%

402

1/16W

10K

2

1R3580

402MF-LF1/16W5%10K

2

1R3581

MF-LF1/16W5%

402

10K

2

1R3565

5%

MF-LF402

1/16W

10K

2

1R3566

MF-LF

5%10K

402

1/16W

NOSTUFF

2

1R3567

1/16W5%

MF-LF

10K

402

2

1R3501

5%

402MF-LF1/16W

10K

7

4

89

5

6

3

2

1

U3514MLP8

NOSTUFF

CRITICAL

M24C02

21

R3755

1/16W

402

0

5%

MF-LF

2

1R3741

MF-LF

5%1/16W

402

10K

2

1R374020K

1/16W5%

402MF-LF

2

1C37415%

402

NOSTUFF

100PF50V

CERM

4

5

3

Q3740

SOT-3632N7002DW-X-G

21

R3745

MF-LF

0

1/16W5%

402

1

2

6Q37402N7002DW-X-GSOT-363

2

1 C3740

CERM-X5R

0.47UF10%

402

6.3V

NOSTUFF

2

1 C35301UF

402X5R16V10%

2

1 C3527

402X5R

1UF16V10%

2

1 C353820%

603

6.3VX5R

10UF

2

1 C3544

603

6.3V20%10UF

X5R

21

L3558

0402

FERR-120-OHM-1.5A

32

33

36

29

23

15

10

5

27

31

9

7

4

2

30

8

6

3

1

37

11

28

22

24

26

35

20

18

16

12

34

21

19

17

13

25

14

U3500USB2514-AEZG

QFN

OMIT

CKPLUS_WAIVE=NDIFPR_BADTERM

2 HUB_USX2061338S0721 CRITICALU3500,U3600SMSC USX2061-AEZG


USB HUB 1SYNC_MASTER=K62

SMSC USB2514B338S0824 HUB_USB2514BU3500,U36002 CRITICAL

USB_EXTA_OC_L

USB_HUB1_SMBDATA

USB_HUB1_UP_N

USB_HUB1_UP_P


USB_HUB1_VBUS_DET

USB_HUB1_RBIAS

USB_EXTC_OC_L

=PP3V3_S3_USB_HUB

TP_USB_HUB1_PRTPWR1

TP_USB_HUB1_OCS1_L

TP_USB_HUB1_PRTPWR4

TP_USB_HUB1_PRTPWR3

TP_USB_HUB1_OCS2_L

USB_SDCARD_P

USB_SDCARD_N

=PP3V3_S3_USB_HUB


USB_HUB1_VDDPLL3V3


=PP3V3_S3_USB_HUB

=PP3V3_S3_USB_HUB

USB_HUB1_LOCAL_PWR


USB_HUB1_VDD1V8

=PP3V3_S3_USB_HUB

USB_HUB1_XTAL1

USB_HUB1_XTAL2

USB_HUB1_CFG_SEL1


USB_HUB1_VDD1V8PLL

USB_HUB_RESET_L

USB_EXTC_P

USB_IR_N

USB_IR_P

USB_EXTA_N

USB_EXTA_P

USB_EXTC_N

USB_HUB1_TEST

USB_HUB1_VDDA3V3MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM

WP_HUB1

USB_HUB1_SMBCLK

=PP3V3_S3_USB_HUB=PP3V3_S5_USB_HUB

USB_PON_RESET_LUSB_PON_RESET


USB_HUB_RESET_L

TP_USB_HUB1_PRTPWR2

35 OF 110

11.1.0

051-8115

34 OF 98

43

91

43

6 34 35

44 92

44 92

6 34 35

20 25 97

95

6 34 35

6 34 35

95

6 34 35

91

91

95

43 92

44 92

44 92

43 92

43 92

43 92

95

6 34 35 6

73 97

34 35

www.vinafix.vn

IN

IN

IN

SCL

THRM_PAD

E0

E1

E2VSS

SDA

VCC

WC*

TEST

RESET*









PRTPWR2/BC_EN2*

PRTPWR1/BC_EN1*

PRTPWR4/BC_EN4*

PRTPWR3/BC_EN3*

OCS2*

OCS1*

OSC3*

OSC4*

RBIAS

USBDP_UP

USBDM_UP

VBUS_DET

THRM_PAD

XTALIN/CLKIN

XTALOUT

SUSP_IND/LOCAL_PWR/NON_REM0

SDA/SMBDATA/NON_REM1

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

CRFILT

PLLFILT

VDD33




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

USB HUB-2

21

1

Y3600

5X3.2X1.4-SM

CRITICAL

24.000M-60PPM-16PF

2

1 C3620

CERM50V5%

402

18PF21

R3691

MF-LF

5%1/16W

402

1M2

1 C3619

CERM50V

18PF5%

402

2

1 C3637

402CERM

5%50V

100PF

2

1 C3643

50V5%

402CERM

100PF

2

1 C3639

16V

402

10%0.1UF

X7R-CERM

2

1 C3645

X7R-CERM16V10%0.1UF

4022

1 C3646

402

0.1UF10%

X7R-CERM16V

2

1 C3647

402

16V10%0.1UF

X7R-CERM

2

1 C362510%

402

0.1UF

X7R-CERM16V2

1 C3623

16V10%

402

0.1UF

X7R-CERM

2

1 C3624

402

10%16V

0.1UF

X7R-CERM 2

1 C36280.1UF

X7R-CERM

10%

402

16V

2

1 C3636

CERM16V10%

402

0.01UF

2

1 C36420.01UF

402

16V10%

CERM

2

1 C3629

16VCERM402

0.01UF10%

2

1 C362610%16VCERM402

0.01UF

20 92

20 92

34

2

1 C361820%

603X5R

10UF6.3V

2

1R3697NOSTUFF

MF-LF402

10K5%

1/16W

2

1R3698

1/16W

10K5%

402MF-LF

2

1R36995%

402

1/16WMF-LF

100K

NOSTUFF

21

L3629

0402

FERR-120-OHM-1.5A

2

1R3692

402MF-LF

5%10K

1/16W

2

1R369410K

402MF-LF1/16W5%

NOSTUFF

2

1R3682

MF-LF

10K

1/16W

402

5%

2

1R3680

402

1/16W5%

MF-LF

10K

2

1R3681

402

1/16W5%

MF-LF

10K

2

1R366610K

402

5%

MF-LF1/16W

2

1R3665

402

10K

MF-LF1/16W5%

NOSTUFF

2

1R3667

1/16WMF-LF402

5%10K

2

1R3601

MF-LF402

10K5%

1/16W

2

1R3604

1/16WMF-LF

5%10K

402

2

1 C3634

X5R402

16V10%0.1UF

7

4

89

5

6

3

2

1

U3614M24C02

NOSTUFF

MLP8

CRITICAL

2

1R3660

402

1/16W5%

MF-LF

10K

2

1R366110K

MF-LF

5%1/16W

402

2

1 C3630

402X5R16V10%1UF

2

1 C362710%

402

16VX5R

1UF

2

1 C3638

603

6.3V

10UF

X5R

20%

2

1 C364420%

603X5R6.3V

10UF

21

L3658

0402

FERR-120-OHM-1.5A

21

R3600

1%

12K

MF402

1/16W

32

33

36

29

23

15

10

5

27

31

9

7

4

2

30

8

6

3

1

37

11

28

22

24

26

35

20

18

16

12

34

21

19

17

13

25

14

U3600USB2514-AEZG

QFN

OMIT



USB HUB 2SYNC_MASTER=K62

USB_HUB2_VBUS_DET

USB_EXTD_OC_L

USB_HUB2_RBIAS

USB_HUB2_UP_P

USB_EXTB_OC_L

TP_USB_HUB2_OCS2

=PP3V3_S3_USB_HUB

=PP3V3_S3_USB_HUB



USB_HUB2_VDDPLL3V3

USB_HUB2UNUSED_P

USB_HUB2UNUSED_N

USB_BT_P

=PP3V3_S3_USB_HUB

USB_HUB2_XTAL2

=PP3V3_S3_USB_HUB

USB_BT_N

USB_EXTD_N

USB_HUB2_UP_N

TP_USB_HUB2_PRTPWR2

TP_USB_HUB2_PRTPWR1

USB_EXTB_P

TP_USB_HUB2_OCS1

TP_USB_HUB2_PRTPWR4

TP_USB_HUB2_PRTPWR3

USB_EXTD_P

USB_HUB2_XTAL1


USB_HUB2_VDD1V8PLL


USB_HUB2_CFG_SEL1

USB_HUB_RESET_L

=PP3V3_S3_USB_HUB

WP_HUB2

USB_HUB2_SMBDATA

USB_HUB2_VDD1V8MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MM

USB_HUB2_SMBCLK

USB_HUB2_LOCAL_PWR

MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM USB_HUB2_VDDA3V3 =PP3V3_S3_USB_HUB

USB_EXTB_N

USB_HUB2_TEST

36 OF 110

11.1.0

051-8115

35 OF 98

43

91

43

6 34 35

6 34 35

95

92

92

44 92

6 34 35

91

6 34 35

44 92

43 92

43 92

43 92

91

95

6 34 35

95

95 6 34 35

43 92

www.vinafix.vn

D

GS

IN

S

G

D

IN

OUT

IN

IN OUT

IN

D

GS

G

D

S

G

D

S

IN

IN

OUT

INOUT

OUT IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

CAESAR IV SW RESET GATING

CAESAR IV CLKREQ ISOLATION

CAESAR IV WAKE# ISOLATION

CAESAR IV RESET CONNECTION

FROM PCH GPIO ->

3V3_ENET_PHY_FET = S0 || (S3 POWER && ENET_PWR_EN)

CAESAR IV POWER ENABLE CIRCUIT CAESAR IV ACTIVITY LED

SILKSCREEN:ENET ACT

197S0177

CAESAR IV 1.2V INT.VR CMPTS

CAESAR IV 25MHZ XTAL

CAESAR IV STRAPS (NONE)

K

A

LED3800DEVELOPMENT


2

1R3815

402MF-LF1/16W5%330

DEVELOPMENT

21

3

Q3870SSM3K15FVSOD-VESM-HF 2

1R3870

402

1/16W

10K5%

MF-LF

21

L3800

PCAA031B-SM

4.7UH-0.8A

PLACEMENT_NOTE=PLACE L3800 CLOSE TO U3900

2

1 C3826

X5R

0.1UF10%

402

16V

PLACEMENT_NOTE=PLACE CLOSE TO L3800

2

1 C3825

PLACEMENT_NOTE=PLACE CLOSE TO L3800

6.3V20%10UF

603-2X5R

21

C3850NOSTUFF

27pF

50V5%

402CERM

21

R3850NOSTUFF

200

MF-LF402

1/16W1%

37 92

21

C3851NOSTUFF

402

5%

27pF

50VCERM

31

42

Y3850

NOSTUFF

25.0000MSM-3.2X2.5MM

CRITICAL

2

1R3851NOSTUFF

1/16W

402

5%

MF-LF

10M

21

C3852

16VX5R10%

0.1UF

402

21

R3856

805

1/8W

0

5%

NOSTUFF

MF-LF

4

3

65

21

Q3850FDC606P_G

SOT-6

2

1 C3853

402X7R-CERM

10%16V

0.1UF

2

1R3853

MF-LF402

5%10K1/16W

NOSTUFF

21

R3852

1/16W

100K

402MF-LF

5%

2

1R3855

1/16W

402

5%

MF-LF

10K

20 25 97 21

R3801

402MF-LF1/16W

0

5%

2

1 C38270.1UF10%

X5R402

16V2

1 C38280.1UF10%

X5R402

16V2

1 C38290.1UF10%

X5R402

16V2

1 C38300.1UF

X5R

10%16V

4022

1 C38310.1UF10%

X5R402

16V

21

R3854NOSTUFF

1/16W

402

0

5%

MF-LF

37 92

21

R3857PLACEMENT_NOTE=PLACE CLOSE TO U3900

1/16W

402

0

5%

MF-LF

79 96

36 91 37

37

2

1R3872

402

1/16W

10K5%

MF-LF

21

3

Q3872SSM3K15FVSOD-VESM-HF

1

2

6

Q3852SOT-3632N7002DW-X-G

4

5

3

Q38522N7002DW-X-GSOT-36321

R3802

402MF-LF

5%1/16W

0

5

4

1

2

3

U3880SOT23-5-HF

MC74VHC1G0827 97

15 21 91

2

1C388020%10V

402CERM

0.1UF

36 91

37 19 33 78 97

15 18 91 37 91

21

R3829

MF-LF

5%

0

402

1/16W


CAESAR IV SUPPORT

ENET_PWR_EN_L

PM_SLP_S3_L PM_SLP_S3_R3802_L

=PP3V3_S3_ENET_PHY_FET

ENET_CLK25M_XTALI

ENET_CLK25M_XTALO_R

ENET_CLK25M_XTALI_R

ENET_CLK25M_XTALI_OSC

ENET_CLK25M_XTALO



VOLTAGE=1.2V

DIDT=TRUE

ENET_SR_LX


SWITCH_NODE=TRUE

MAKE_BASE=TRUEMIN_LINE_WIDTH=1.0MM

PP1V2_S3_ENET_INTREG

MIN_NECK_WIDTH=0.2MMVOLTAGE=1.2V



ENET_ACT

VOLTAGE=3.3V

MAKE_BASE=TRUE

NET_SPACING_TYPE=SWITCHNODE

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=1.0 MM

PP3V3_S3_ENET_PHY_FET=PP3V3_S3_ENET_PHY

ENET_LED_ACT_LMAKE_BASE=TRUE

ENET_TRAFFICLED_L

ENET_PWR_ENABLE_L

=PP1V2_S3_ENET_PHY

MIN_LINE_WIDTH=1.0MMENET_SR_VFB

VOLTAGE=1.2VMIN_NECK_WIDTH=0.2MM

ENET_PWR_EN

ENET_CLKREQ_FET_L

=ENET_WAKE_L

ENET_CLKREQ_L

ENET_PWR_EN_R

=PP3V3_S0_ENET_PHY

ENET_RESET_L

ENET_SW_RESET_L

ENET_RESET_LOGIC_L ENET_RESET_LOGIC_R_L

ENET_RESET_LOGIC_L

ENET_WAKE_LMAKE_BASE=TRUE

PCIE_WAKE_L

38 OF 110

11.1.0

051-8115

36 OF 98

5 19 26 32

46 47

63 82

97

36 37 79

92

36 37 79

37 95

95

36 37 79

36 37 79

95 6

37

37 95

6 37

www.vinafix.vn

IN

IN

IN

OUT

IN

IN

OUT

OUT

OUT

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

NC

BI

BI

BI

OUT

IN

IN

IN

OUT

VDDC

SR_LX

PCIE_PLLVDDL

SR_VFB

SR_VDDP

SR_VDD

SCLK

SI/LINKLED*

CS*

SO

SPD100LED*/SERIAL_DO

TRAFFICLED*/SERIAL_DI

TRD0_P

TRD1_P

TRD0_N

TRD1_N

TRD2_N

TRD2_P

TRD3_N

TRD3_P

GPIO_1/CR_BUS_PWR

GPIO_0

RE*/GPIO_2

VMAIN_PRSNT

PCIE_TXD_N

PCIE_TXD_P

PCIE_RXD_N

PCIE_RXD_P

PCIE_REFCLK_N

PCIE_REFCLK_P

PERST*

CLKREQ*

WAKE*

LOW_PWR

SD_DETECT/WE*

CR_CMD/CLE

CR_CLK/RY_BY*

CR_DATA0

CR_DATA1

CR_DATA3

CR_DATA2

CR_DATA4

CR_DATA5

CR_DATA6

CE*/MS_INS*

CR_DATA7

CR_LED/ALE

XD_DETECTTHRM_PAD

XTALI

XTALO

RDAC

GPHY_PLLVDDL

AVDDH VDDO

XTALVDDH

BIASVDDH

AVDDL

SMD_DATA

SMB_CLK

CR_WP*/XD_WP*

OUT

IN

IN

OUT

IN

OUT

BI

BI

BI

IN

BI

BI

BI

BI

BI

IN

SI

WP*SO

SCK

CS*

RESET*

VCC

GND




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PHY Non-Volatile MemoryROM contains MAC address, PCIe config

Avoids need for EFI to program at startup.

LimitingCurrent

LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for

the card reader on-chip I/O.

BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.

If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.

If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.

(IPD)

(IPD-ENETM)

(OD)

VDD for Card Reader I/O

(IPU-ENET)

If ENET switching regulator is

SD_DETECT can only be used active low due to errata.

Resistor

=ENET_WAKE_L to PCIE_WAKE_L.

WAKE#

(See note)

Must isolate from PCIe WAKE# if PHY

(See note)

ENET supports both active-levels for WP.

info as well as code for Bonjour proxy.

(Required ROM size 1 Mbit)

used, this pin can float (alias to

TP_). If not used, must be pulled

to 3.3V ENET via 1K resistor (not

Atmel AT45DB011D (1Mbit) ROM. If a different

(OD)

o(IPU-ENET)

(OD)

(IPU-ENET)

(OD)

BCM requests SD CR[0:7], CMD, CLK termination.

ENET_SR_DISABLE

ENET_CR Signals

Internal 1.2V Switching Regulator pins.

(IPD-ENET)

other 3 SPI pins configures ENET for the

ROM is used then the straps must change.

NOTE: Pull-down on SO plus internal pull-ups on

NOTE: ENETM requires SI pull-down instead of SO.

Special Star routing needed on these pins. Decoupling on Pg 37.

(IPx-ENET)

provided on this page).

(IPU)

(IPD)

NOTE: "IPx" == Programmable pull-up/down

(IPD)

(IPU-ENET)

281mA (1000base-T max power, Caesar IV)

Connect only to U3900 pin 20.

Control signal to light LED or control SD bus power.No MS (Memory Stick) Insert feature needed.

(IPU-ENET)

If PHY is always powered then alias

N-channel FET isolation suggested.

is powered-down in S3/S5. Standard

396mA (1000base-T, Caesar II)

MUST DO: REMOVE C/R3959 AFTER PROTO 2

ENET 1.2V SR IS ENABLED IF FLOATING.

(NO IPU OR IPD-ENET)

2

1C3921

402

16V10%

X7R-CERM

0.1UF

2

1 C3935

X5R

10%

805

6.3V

10UF

2

1 C39254.7UF

6.3V10%

603X5R-CERM

21

L3925

SM

FERR-600-OHM-0.5A

CRITICAL2

1 C3920

10%6.3V

603X5R-CERM

4.7UF

21

L3920

SM

FERR-600-OHM-0.5A

CRITICAL

21

L3900CRITICAL

SM

FERR-600-OHM-0.5A

21

L3905FERR-600-OHM-0.5A

SM

CRITICAL

2

1R39421K

MF-LF1/16W

402

5%

18 90

18 90

36

36 91

15 21 97

36 92

36 92

21

C3951

10%16V

402

0.1uF

X5R

21

C39500.1uF

16V10%

X5R402

21

C39560.1uF

402X5R

10%16V

21

C39550.1uF

10%16VX5R402

2

1R3965

MF-LF

1%

402

1/16W

1.24K

18 92

18 92

18 92

18 92

38 92

38 92

38 92

38 92

38 92

38 92

38 92

38 92

2

1R3941

402

5%1/16WMF-LF

4.7K

2

1R3940

1/16W

4.7K5%

402MF-LF

21R3978

PLACEMENT_NOTE=PLACE R3978 NEAR U3900

4025% MF-LF1/16W

33 DEVELOPMENT45 92

21R3977MF-LF 4025% 1/16W


33 DEVELOPMENT21R3976


5% 1/16W MF-LF 402

33 DEVELOPMENT21R3975

1/16W MF-LF5%


402

33 DEVELOPMENT

45 92

45 92

45 92

21R3961MF-LF5%


1/16W 402PLACEMENT_NOTE=PLACE NEAR U3900

33 DEVELOPMENT

21R3960402

05% MF-LF1/16W

DEVELOPMENT

45

21

R3943

5%

MF-LF1/16W

402

0

21

R39000

402

1/16W5%

MF-LF

2

1R3990NOSTUFF

MF-LF1/16W5%

402

4.7K

45 92

45

2

1 C3970

603X5R-CERM6.3V10%4.7UF

DEVELOPMENT

2

1 C3971

16VX7R-CERM

10%

402

0.1UF

DEVELOPMENT

2

1 C3972

16V

0.1UF

X7R-CERM

10%

402

DEVELOPMENT

15 18 92

2

1R3910

1/16W5%

4.7K

MF-LF402

17

19

18

68

3

58

62

56

20

7 61

35

50

49

46

47

44

43

40

41

67

69

13

15

14

16

2

65

10

6

64

1

66

9

38

11

28

27

33

34

31

30

32

29

4

8

5

36

63

57

60

55

54

53

52

22

23

24

25

26

21

12

59

37

51

45

39

48

42

U3900

QFN-8X8

OMIT

BCM57765

21R3979402MF-LF1/16W


335%PLACEMENT_NOTE=PLACE NEAR U3900

DEVELOPMENT

21R3980 1K1/16W5% 402

NOSTUFFMF-LF

36

37

37

37

37

45

21

L3910CRITICAL

SM

FERR-600-OHM-0.5A

37

37

37

37

45 92

21R3971


402

331/16W5% MF-LF

DEVELOPMENT

45 92

45 92

2

1 C3910

402

10%16VX7R-CERM

0.1UF

45 92

45 92

21R3972402


335% MF-LF1/16W

DEVELOPMENT

21R3973


5% MF-LF

334021/16W

DEVELOPMENT

21R3974


MF-LF1/16W5%

33402

DEVELOPMENT

21

R3901

MF-LF

5%

402

0

1/16W

2

1R3992

MF-LF1/16W

5%

402

4.7K

2

1R39934.7K

402

5%1/16WMF-LF

21

R39040

1/16WMF-LF

4025%

21R39815% 1/16W 402

1KMF-LF

2

1 C39180.1UF

402

16VX7R-CERM

10%

2

1 C3917

10%

402

16VX7R-CERM

0.1UF

36

2

1R3959

1/16W

402

5%150

MF-LF

NOSTUFF

2

1 C3980

402

10%

X5R16V

0.1UF

2

1 C39110.1UF10%16VX7R-CERM402

2

1 C397920%6.3VCERM

4.7UF

603

2

1 C39810.1UF16VX5R

10%

402

2

1 C395910PF

CERM50V5%

NOSTUFF

402

5

6

8

12

3

7

4

U3990

OMIT_TABLE

SOIC-8S1AT45DB021D

2

1 C39900.1UF

X7R-CERM402

16V10%

2

1C39000.1UF

16V

402

10%

X7R-CERM

2

1 C3905

10%0.1UF

16VX7R-CERM402

2

1 C39304.7UF10%6.3VX5R-CERM603

2

1C3931

16V10%

0.1UF

402X7R-CERM

21

L3930

SM

FERR-600-OHM-0.5A

CRITICAL

2

1C3915

603

6.3V

4.7UF10%

X5R-CERM 2

1 C3916

10%

402

16VX7R-CERM

0.1UF

2

1R3997

1/16W

4.7K

MF-LF402

5%

2

1C3936

X7R-CERM

0.1UF10%

402

16V

2

1C3926

16V10%

X7R-CERM

0.1UF

402

ETHERNET PHY (CAESAR IV)SYNC_MASTER=K62 SYNC_DATE=01/06/2011

ENET_WAKE_R_L

ENET_LOW_PWR

ENET_SMB_CLK

ENET_SMB_DATA

ENET_MISO

ENET_MOSI

ENET_CS_L

TP_ENET_SPD100LED_L

PCIE_ENET_D2R_C_P

PCIE_ENET_R2D_P

PCIE_ENET_R2D_N

PCIE_CLK100M_ENET_P

ENET_VMAIN_PRSNT



VOLTAGE=1.8VMIN_NECK_WIDTH=0.2 mm

PP3V3R1V8_ENET_LR_OUT_REG

ENET_MEDIA_SENSE

ENET_SD_DETECT_L

PCIE_ENET_D2R_P

PCIE_CLK100M_ENET_N

ENET_RESET_LOGIC_R_L

ENETCONN_MDI_P<3>

PCIE_ENET_D2R_C_N

SDCONN_DETECT_L

SDCONN_CMD

VOLTAGE=1.2VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mmPP1V2_S3_ENET_PHY_AVDDL

ENET_3V3_S3_SR_IN

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 MM

SWITCH_NODE=TRUEDIDT=TRUE

MIN_LINE_WIDTH=0.4 MMNET_SPACING_TYPE=SWITCHNODE

NO_TEST=TRUENC_ENET_CE_L_MS_INS_L

ENET_CR_DATA<7>

ENET_CR_DATA<6>

ENET_CR_DATA<4>

ENET_CR_DATA<3>

ENET_CR_DATA<2>

ENET_CR_DATA<1>

ENET_CR_DATA<0> SDCONN_DATA<0>

SDCONN_DATA<1>

SDCONN_DATA<3>

SDCONN_DATA<2>

ENET_CR_DATA<5>

SDCONN_DATA<4>


=PP3V3R1V8_ENET_LR_OUT

=PP3V3R1V8_ENET_LR_OUT

VOLTAGE=1.2VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mmPP1V2_S3_ENET_PHY_GPHYPLL

MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

PP3V3_S3_ENET_PHY_AVDDH

PP1V2_S3_ENET_PHY_PCIEPLLMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.2V

ENET_SR_VFB

ENETCONN_MDI_N<1>

ENET_SCLK

ENET_SR_LX

SDCONN_DATA<7>

SDCONN_DATA<6>

SDCONN_CLK

ENET_SD_CMD

ENET_CR_PWREN

ENET_SR_DISABLE

ENET_SCLK

ENET_TRAFFICLED_L

ENET_CLK25M_XTALI

PCIE_ENET_D2R_N

PCIE_ENET_R2D_C_P

=ENET_WAKE_L

ENET_CLKREQ_FET_L

ENETCONN_MDI_N<0>

SDCONN_DATA<5>

SDCONN_WP

ENETCONN_MDI_P<1>

ENETCONN_MDI_N<2>

ENETCONN_MDI_P<2>

MIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

ENET_XTALVDDHMIN_LINE_WIDTH=0.4 mm


PP3V3_S3_ENET_PHY_XTALVDDHMIN_LINE_WIDTH=0.4 mm


PP3V3_S3_ENET_PHY_BIASVDDH

VOLTAGE=3.3V


ENETCONN_MDI_P<0>

ENETCONN_MDI_N<3>

PCIE_ENET_R2D_C_N

=PP1V2_S3_ENET_PHY

ENET_SD_CLK

=PP3V3_S0_ENET_PHY

ENET_CLK25M_XTALO

ENET_RDAC


ENET_SRESET_L

ENET_CS_L

ENET_SCLK_R

ENET_MISOENET_SWP_L

ENET_MOSI

37 OF 98

051-8115

11.1.0

39 OF 110

92

92

92

36 37 79

95

92

92

95

95

92

92

92

92

92

92

92

92

36 37 79

37

37

95

95

95

36 95

36 95

92

95 95

95

36

92

6 36

92

36 37 79

www.vinafix.vn

TD4-

TCT4

TD4+

TD3-

TCT3

TD3+

TD2-

TD2+

TD1-

TCT2

TCT1

TD1+

MX4-

MX4+

MCT4

MX3-

MX3+

MCT3

MX2-

MX2+

MCT2

MX1-

MX1+

MCT1

1CT:1CT

1CT:1CT

1CT:1CT

1CT:1CT

ENET_MDITRAN_P0

TRAN_N0

TRAN_P1

TRAN_P2

TRAN_N2

TRAN_N1

TRAN_P3

TRAN_N3

PINSSHIELD

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NO PAIR AND PIN POLARITY SWAPS

514-0767

NOTE: BOB SMITH TERMINATION FOR EMC.

NOTE: Check with PHY and Magnetics MFR to determine what to do with center taps.

PLACE ONE CAP PER TCT PIN

157S0071

THIS PAGE DIFFERENT BETWEEN K60 and K62.

2

1R4000755%

MF-LF1/16W

402

PLACE_NEAR=T4000.15:6 mm

2

1R4001

MF-LF

755%1/16W

402


2

1R4002751/16WMF-LF402

5%


2

1R4003

MF-LF402

1/16W5%75PLACE_NEAR=T4000.24:6 mm

2

1 C4000

1206

10%

NOSTUFF

2KV

1000PF

CERM

2

1 C4001

CERM10V20%

402

0.1UF

2

1 C4002

CERM10V

0.1UF20%

4022

1 C4003

10VCERM

0.1UF20%

4022

1 C4004

CERM10V

0.1UF20%

402

11

12

8

9

5

6

2

3

10

7

4

1

14

13

17

16

20

19

23

22

15

18

21

24

T4000

CKPLUS_WAIVE=NDIFFPR_BADTERM

SOILFE9249APF

CRITICAL





7

4

3

1

8

5

6

2

9

10

J4000CRITICAL

F-ANG-THRJ45-K60K62

38 92

38 92

38 92

38 92

38 92

38 92

38 92

38 92

37 92

37 92

37 92

37 92

37 92

37 92

37 92

37 92

38 92

38 92

38 92

38 92

38 92

38 92

38 92

38 92

SYNC_MASTER=K60_MARK

Ethernet ConnectorSYNC_DATE=01/06/2011

ENETCONN_MDI_P<1>

ENETCONN_MDI_P<0>

ENETCONN_MDI_P<2>

ENETCONN_MCT2

ESD_HOT=TRUEENETCONN_MDI_T_P<3>

ENETCONN_MDI_T_P<0>

ENETCONN_MDI_T_P<1>

ENETCONN_MDI_T_P<2>

ENETCONN_MDI_T_N<2>

ENETCONN_MDI_T_N<3>

ENETCONN_MDI_P<3>

ENETCONN_MDI_N<3>

ENETCONN_MDI_N<2>

MIN_LINE_WIDTH=0.4 MMENETCONN_MCT_BS


ENETCONN_MDI_T_N<0>

ENETCONN_MDI_T_N<1>

ENETCONN_MDI_T_P<3>

ENETCONN_MDI_N<0>

ENETCONN_MDI_T_P<2>ESD_HOT=TRUE

ENETCONN_MCT3

ENETCONN_TCT

ENETCONN_MDI_N<1>

ENETCONN_MDI_T_N<3>ESD_HOT=TRUE

ESD_HOT=TRUEENETCONN_MDI_T_N<1>

ENETCONN_MDI_T_N<2>ESD_HOT=TRUE


ESD_HOT=TRUEENETCONN_MDI_T_N<0>


ENETCONN_MCT0

ENETCONN_MCT1

40 OF 110

11.1.0

051-8115

38 OF 98

www.vinafix.vn

DS2

ATBUSH

ATBUSN

VP25

OCR_CTL_V10

VAUX_DETECT

TMS

TCK

REFCLKN

PCIE_TXD0P

TRST*

ATBUSB

TDI

DS1

TPA0N

TPA0P

AVREG

CE

CLKREQN

FW_RESET*

FW620*

JASI_EN

MODE_A

NAND_TREE

OCR_CTL_V12

PCIE_RXD0N

PCIE_RXD0P

PCIE_TXD0N

PERST*

R0

REFCLKP

REGCLT

REXT

SCIFCLK

SCIFDAIN

SCIFDOUT

SCIFMC

SCL

SDA

SE

SM

TDO

TPA1N

TPA2N

TPA2P

TPB0N

TPB0P

TPB1N

TPB1P

TPB2N

TPB2P

TPBIAS0

TPBIAS1

TPBIAS2

TPCPS

VAUX_DISABLE

VBUF

VDDH VP VREG_PWR

WAKE*

XI

XO

DS0

TPA1P

VDD33VDD10

VREG_VSSVSS

SERIAL EEPROM

MISCELLANEOUS

CONTROLLER

POWER MANAGEMENT

TEST CONTROLLER

PCI EXPRESS PHY

CHIP RESET

SCIF

1394 PHY

NCNCNC

NC

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

NCNC




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Per LSI, R4162 and C4162 can be NOSTUFF ->

NT-1 (IPU)

(IPD) NT-21

(IPU)

NT-9

APN: 338S0753 ->

NT-2 (IPU)

NT-12 (IPD)

NT-10 (IPD)

NT-16 (IPD)

FIXME!!! - TYPO IN SYMBOL REGCTL

FIXME!!! - TYPO IN SYMBOL VAUX_ENABLE

NT-13

NT-5

NOTE: NT-xx notes show

NAND tree order.

114 mA FireWire PHY

17 mA PCIe SerDes

NT-3 (IPU)

NT-4 (IPU)

(IPU)

(IPD)

(Reserved)

NT-14 (IPD)

NT-6

NT-7

(OD)

135 mA25 mA PCIe SerDes

0 mA VReg PWR

7 mA I/O

(IPD)

(IPD)

(IPU) NT-8

110 mA Digital Core

138 mA

NT-OUTNT-17

NT-15 (IPD)

(IPD) NT-18

(IPD) NT-11

(IPD) NT-19

(IPD) NT-20

External power-on reset (IPU 100K):

K18 has 0.475-ohm upstream of L4110

2

1R4170

402MF-LF1/16W1%191

2

1 C4162

10%

402

6.3V

0.33UF

CERM-X5R2

1R4162

402

5%1/16WMF-LF

470K

F13

G13

C2

F6

F4

E9

E5

E4

D10

K10

K6

L7

K9

K8

D9

K7

K5

K4

J10

J9

J5

J4

H10

H8

H7

D7

H6

H4

G10

G8

G7

G6

G4

F10

F8

F7

D4

B2

L12

K12

L9

L6

L10

L5

D8

D6

D5

A12

M2

L11

L3

J1

G12

F1

C12

C1

L1

K2

H12

H2

E10

E2

C13

B12

N11

N3

M12

B1

A1

H13

D2

E1

N1

B10

A2

C3

B7

A4

B4

A6

B6

A9

B9

A3

B3

A5

B5

A8

B8

M3

M1

N2

M4

N13

M13

M11

N12

F2

H1

G1

G2

L8

D13

N10

N9

B11

N4

N6

N5

N7

N8

J13

J12

K1

J2

D1

K13

D12

E13

E12

F12

L2

L13

A10

A11

A13

B13

U4100

FW643

OMIT

CRITICAL

BGA

21

C415122PF

50V

402

5%

CERM

21

C4150

50VCERM

5%

402

22PF

2

1R4160

402

PLACEMENT_NOTE=Place close to U4100.B10

MF-LF1/16W

1%200K

21

R4150

MF-LF

412

1%1/16W

402

2

1R4163

402

1/16WMF-LF

10K5%

2

1R4164

5%1/16WMF-LF

10K

402

2

1R4165

402

10K

MF-LF

5%1/16W

NOSTUFF

21C4176 16V

X5R 4020.1UF10%

PLACEMENT_NOTE=PLACE C4176 CLOSE TO U4100

21C4175402

16V

0.1UF10%

PLACEMENT_NOTE=PLACE C4175 CLOSE TO U4100

X5R

2

1R4166

MF-LF1/16W

10K5%

402

21C4171

PLACEMENT_NOTE=Place C4171 close to U1800

16V

X5R 4020.1UF10%

21C4170X5R 402

PLACEMENT_NOTE=Place C4170 close to U1800

16V

0.1UF10%

2

1C4130

402CERM6.3V10%1UF

2

1C4131

10%1UF

6.3VCERM402

2

1 C4100

CERM

1UF

6.3V

402

10%

2

1 C4101

10%1UF

402

6.3VCERM

2

1C4132

10%1UF

402

6.3VCERM

2

1 C4102

10%1UF

402CERM6.3V

2

1 C4103

10%1UF

402

6.3VCERM

2

1C4135

10%1UF

6.3VCERM402

2

1C4136

10%1UF

402

6.3VCERM

2

1 C4104

402

10%6.3VCERM

1UF

2

1 C4110

10%1UF

402

6.3VCERM

2

1 C4105

10%1UF

402

6.3VCERM 2

1 C41061UF

402

6.3VCERM

10%

2

1C4120

10%1UF

402

6.3VCERM 2

1C4121

10%1UF

402

6.3VCERM 2

1C4122

10%

402

6.3VCERM

1UF

2

1C4123

10%1UF

402

6.3VCERM 2

1C41241UF

402

6.3VCERM

10%

2

1C4141

402

10VCERM

0.1UF20%

2

1 C4111

10%1UF

402

6.3VCERM

2

1 C4140

402

10%1UF

6.3VCERM

18 90

18 90

18 90

18 90

18 90

18 90

15 21 97

15 97

2

1R4161

1/16W

402

2.94K1%

MF-LF

40

40

40

40

40

40 92

40 92

40 92

40 92

40

40

40 92

40 92

40 92

40 92

40

40

40

21

L4130

0402-LF

120-OHM-0.3A-EMI

21

L4135

0402-LF

120-OHM-0.3A-EMI

27 97

21

L4110120-OHM-0.3A-EMI

0402-LF

31

42

Y4150CRITICAL

24.576MHZSM-3.2X2.5MM

SYNC_MASTER=K60_ROSITA SYNC_DATE=01/06/2011

FireWire LLC/PHY (FW643)

FW_CLK24P576M_XO

=PP1V0_S0_FWPHY

FW_CLK24P576M_XI

TP_FW643_TCK

FW643_REXT

TP_FW643_NAND_TREE

TP_FW643_CE

TP_FW643_FW620_L

TP_FW643_SM

FW643_OCR10_CTL

PCIE_FW_D2R_P

=PP3V3_S0_FWPHY

FW_PHY_DS2

TP_FW643_SE

TP_FW643_MODE_A

FW_P0_TPB_N

FW_P1_TPB_N

FW_P1_TPB_P

FW_PHY_DS1

TP_FW643_VBUF

FW_P2_TPBIAS

FW_P0_TPBIAS

FW_P2_TPB_P

FW643_PU_RST_L

TP_FW643_SCIFDOUT

PCIE_FW_R2D_N

FW_P2_TPA_N

FW_P1_TPA_P

FW643_TRST_L

PCIE_FW_D2R_N

TP_FW643_TMS

TP_FW643_AVREG

TP_FW643_JASI_EN

TP_FW643_SDA

FW_P2_TPA_P

FW_P0_TPA_N

TP_FW643_TDO

PCIE_CLK100M_FW_N

PCIE_CLK100M_FW_P

PCIE_FW_D2R_C_N

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP3V3_FW_FWPHY_VP25

FW_P0_TPB_P

FW_CLK24P576M_XO_R

FW_P1_TPA_N

TP_FW643_SCIFDAIN

TP_FW643_SCIFCLK

FW643_REGCTL

FW_CLKREQ_L

TP_FW643_VAUX_ENABLE

PCIE_FW_R2D_P

TP_FW643_TDI

FW_RESET_L

FW643_SCL

TP_FW643_SCIFMC

FW_PME_L

FW_P0_TPA_P

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP1V0_FW_FWPHY_AVDD

VOLTAGE=1.0V

PCIE_FW_D2R_C_P

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 MM

PP3V3_FW_FWPHY_VDDAMIN_LINE_WIDTH=0.4 MM

FW643_VAUX_DETECT

PPVP_FW_PHY_CPS

FW_PHY_DS0

=PP3V3_S0_FWPHY

FW_P2_TPB_N

FW643_TPCPS

FW643_R0

FW_P1_TPBIAS

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40

92

40

6 39 40 41

90

90

95

92

90

95

90

95

41 95

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Apple Inc.

PAGE


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345678

D

B

8 7 5 4 2 1

1394 PHY DATA/STROBE OPTIONS

2ND & 3RD TPA/TPB PAIR UNUSED

NOTE: AGERE’S RECOMMENDATION FOR UNUSED PORTS

THERE ARE THREE FIREWIRE PORTS, BUT ONLY ONE IS USED.NO STUFF MEANS THAT

IT IS IN BILINGUL MODE PULL-UPS ASSERT/ENABLE DATA STROBE ONLY MODE, FW643

HAS INTERNAL 100K PULL-DOWNS, ONLY PULL-UPS NECESSARY.

Place close to FireWire PHYTermination

NOTE: Q4200 COLLECTOR CONNECT TO CAPS WITH 0.4 SQ-IN HEAT SINKNOTE: MULTIPLE VIAS TO DGND

FW643 1.0V GENERATION

2

1R4255

402

10K

MF-LF

5%1/16W

NOSTUFF

3 4

2

1

Q4200SOT223-4

CRITICAL

BCP6916DG

2

1 C4213

CERM

10UF20%

805-1

6.3V2

1 C4211

10V20%

402CERM

0.1UF

21

R4200

1/16W

75

5%

MF-LF402

2

1 C4200

CERM6.3V

2.2UF

402-LF

20%2

1 C4201

402-LF

6.3VCERM

2.2UF20%

2

1 C4212

805-1

20%

CERM6.3V

10UF

2

1 C42100.1UF20%

402CERM10V

2

1R4256

402MF-LF1/16W5%10K

2

1R425710K1/16W5%

402MF-LF

2

1 C4250

402

10%

CERM-X5R6.3V

0.33UF

2

1R425156.21%

402MF-LF1/16W

2

1R42501%

MF-LF402

1/16W

56.2

2

1R4253SIGNAL_MODEL=EMPTY

56.2

MF-LF402

1/16W1%

2


1%1/16W

56.2

MF-LF402

2

1R4254

MF-LF1/16W1%4.99K

4022

1C42545%

402

220PF

CERM25V

2

1R4258

1/16W5%

MF-LF402

10K

FireWire: 1394B MISCSYNC_MASTER=K62 SYNC_DATE=01/06/2011

NET_SPACING_TYPE=POWERPP1V0_S0_FW_VDD

MAX_NECK_LENGTH=3MM

VOLTAGE=1.0V


DIDT=TRUEMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.25MMNET_SPACING_TYPE=SWITCHNODE

FW643_OCR10_CTL

DIDT=TRUEMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.25MMNET_SPACING_TYPE=SWITCHNODE

FW_OCR10_CTL_R

FW_P0_TPB_N

VOLTAGE=1.86V


FW_P0_TPBIAS

FW_PORT0_TPB_PMAKE_BASE=TRUE

FW_PHY_DS0

FW_PHY_DS1

FW_PHY_DS2

FW_P0_TPA_PFW_P0_TPA_N

MAKE_BASE=TRUEFW_PORT0_TPB_N

FW_PORT0_TPA_NMAKE_BASE=TRUE

FW_PORT0_TPA_PMAKE_BASE=TRUE

FW_P0_TPA_C

=PP3V3_S0_FWPHY

=PP3V3_S0_FWPHY

FW_P0_TPB_P

NO_TEST=TRUEMAKE_BASE=TRUE

NC_FW_PORT1_TPBIASFW_P1_TPBIAS

NO_TEST=TRUEMAKE_BASE=TRUENC_FW_PORT1_TPA_PFW_P1_TPA_P

NO_TEST=TRUEMAKE_BASE=TRUENC_FW_PORT1_TPA_NFW_P1_TPA_N

NO_TEST=TRUEMAKE_BASE=TRUENC_FW_PORT1_TPB_PFW_P1_TPB_P

FW_P1_TPB_N

FW_P2_TPBIAS

NC_FW_PORT2_TPA_PNO_TEST=TRUEMAKE_BASE=TRUE

FW_P2_TPA_P

NC_FW_PORT2_TPA_NNO_TEST=TRUEMAKE_BASE=TRUE

NC_FW_PORT2_TPB_PMAKE_BASE=TRUENO_TEST=TRUE

FW_P2_TPB_P

NC_FW_PORT2_TPB_NNO_TEST=TRUEMAKE_BASE=TRUE

FW_P2_TPB_N

=PP1V0_S0_FWPHY

FW_P2_TPA_N

NC_FW_PORT2_TPBIASNO_TEST=TRUEMAKE_BASE=TRUE

NC_FW_PORT1_TPB_NNO_TEST=TRUEMAKE_BASE=TRUE

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39

39

41 92

39

39

39

39

39

41 92

41 92

41 92

6 39 40 41

6 39 40 41

39

39

39 92

39 92

39 92

39 92

39

39 92

39 92

39 92

39

39 92

www.vinafix.vn

V+

GND

SHIELDPINS

VGTPA-

TPA(R)

TPB- TPB(R)

TPB+ VP

TPA+

SC/NC

VCC

VCLMP

D1-

GNDD2-

D2+

D1+

FWPWR_EN

OUT

OUTIN

IN

BI

BI

BI

BI

IN

G S

D

BI

BI

BI

BI

OUT




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Apple Inc.

PAGE


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345678

D

B

8 7 5 4 2 1

POUR COPPER TO SINK HEAT

FAST NON-RESETABLE FUSE

THIS FUSE WILL NOT BLOW

beta-only device, there is no DC path

BREF should be hard-connected to logic

ground for speed signaling and connection

When a billingual device is connected to a

AREF needs to be isolated from all

SHOULD BE DONE AS A POWER STRIP(SUBPLANE)

ACTIVE "LATE VG" + ESD PROTECTION

12 VOLTS

PLACE CLOSE TO COMPARATOR

1394BPORT 0

5.1V

PLACE CLOSE TO COMPARATOR

5.1VNC

NC

INRUSH RESETABLE PTC

POUR COPPER TO SINK HEAT14 WATTS MAX PER PORT

IT IS HERE FOR SAFETY ONLY

between them (to avoid ground offset issue)

local grounds per 1394b spec

514-0769

21

L4300CRITICAL

FERR-250-OHM

SM

2

1C4332

50VCERM402

10%0.001UF

NOSTUFF

2

1 C43350.1UF

X7R50V

603-1

10%

2

1R4335

402

1%

MF-LF1/16W

1M

2

1 C4300

X7R603-1

50V10%0.01UF

3

1

D4301

SOT23

MMBZ5231BXG

21

F4301

SMD030F-SM

0.3AMP-60V

CRITICAL

4

3

65

21

Q4300CRITICAL

SSOT6

FDC610PZ21

R4300

MF1W5%

0.33

2512

2 3

1 Q4301

SOT2360V-600MAMMBT2907AXG

21

R4352

402MF-LF1/16W

51.1K

1%

21

D4300CRITICAL

SM

CRS08-1.5A-30V

2

1R4303

MF-LF1/16W5%20K

4022

1R430215K

603

5%

MF-LF1/10W

2

1R4307

MF-LF1/16W

402

5%20K

2

1 C43020.01UF

16VCERM

20%

402

2

1R430110K

MF-LF

5%

402

1/16W

2

3

1Q4302

SOT23MMBT2222A7F

31

D4302BAS40XG

SOT23

2

1 C4304

402

16V10%0.1UF

X7R-CERM

8

1

7

3

5

2

6

4

U4300LM393SOI-HF

21

R4304

5%1/16W

100K

MF-LF402

2

1R4306

402

5%

MF-LF1/16W

200K

2

1C4305

16V10%

603

2.2UF

X5R

3 1

D4303

MMBZ5231BXG

SOT23

21

R4305

MF-LF1/16W

100K

402

5%

21

F4300

603

3AMP-32V

CRITICAL

21XW4300PLACEMENT_NOTE=PLACE CLOSE TO F4300

SM

8

6

9

2

1

5

4

3

7

11

10

J4300FWB-PL-K60-K62

CRITICAL

F-ANG-TH

3

12

4

6

5

8

7

U4350

PLACEMENT_NOTE=PLACE U4350 CLOSE TO J4300

CRITICALLLP

TPD4S1394

2

1C435010%16V

X7R-CERM402

0.1UF

41

41 41

41

40 41 92

40 41 92

40 41 92

40 41 92

41

4

3

65

21

Q4350

SSOT6

CRITICAL

FDC610PZ

2

1

3

Q4351SOT23-HF12N7002

2

1R4350100K

402

5%

MF-LF

NOSTUFF

1/16W

40 41 92

40 41 92

40 41 92

40 41 92

2

1R4351

5%

402

1/16WMF-LF

1K

2

1C43510.001UF

NOSTUFF

402

50VCERM

20%

2

1R43551K

402MF-LF1/16W5%

39 95

3

1

D4305

SOT23

MMBD914XG

NOSTUFF

FIREWIRE CONNECTORSYNC_DATE=01/06/2011SYNC_MASTER=K62

NO_TEST=TRUEFW_PORT0_TPA_P

FW_TURN_ON_V

FW_CURRENT_LIMIT

FWPWR_ON_L

FW_PORT0_TPA_R

=PP12V_S0_FW

FW_CURRENT_LIMIT

FWPWR_EN_L


P12V_FW_RMIN_LINE_WIDTH=1.7MM

VOLTAGE=12V

=PP12V_S0_FW

FW_FET_LINEAR_LIMIT_OUT

TP_FW_LATEVG_VCLMP

FW_PORT0_TPB_PNO_TEST=TRUE

FW_FET_LINEAR_LIMIT_FB

MIN_NECK_WIDTH=0.5MMMIN_LINE_WIDTH=1.7MMFW_PORT0_VP

VOLTAGE=12V

FW_CURRENT_LIMIT_RD

FW_PORT0_VP_FMIN_LINE_WIDTH=1.7MM

VOLTAGE=12VMIN_NECK_WIDTH=0.5MM

FW_PORT0_TPB_P

FW_PORT0_TPA_P

=PP3V3_S0_FWPHY

FW_CURRENT_LIMIT_Q

FW_FET_LINEAR_LIMIT_IN

FW_FET_LINEAR_LIMIT_OUT

FW_FET_LINEAR_LIMIT_IN

FW_CURRENT_LIMIT_R

VOLTAGE=12VMIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MM

PPVP_FW_PHY_CPS



P12V_FW_D

VOLTAGE=12VMIN_NECK_WIDTH=0.5MMMIN_LINE_WIDTH=1.7MMP12V_FW_CL

PP12V_S0_VG_OKMIN_LINE_WIDTH=1.7MM


FW_PORT0_TPB_N

FW_PORT0_TPA_N

FWPWR_EN

NO_TEST=TRUEFW_PORT0_TPA_N

NO_TEST=TRUEFW_PORT0_TPB_N

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IN

IN

OUT

OUT

IN

IN

OUT

OUT

G

D S

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

NC

G S

DNC

NC

IN

IN

OUT

OUT




36

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8 7 5 4 2 1

SILKSCREEN:SATA1

SATA PORT A1 FOR SSD/ODD

ODD PWR CONTROL

SATA PORT A0 FOR HDD

K60E should stuff S_P1_ODD:YES because it has no SSD option.

ODD X

BOMOPTION OPTIONS FOR SATA PORT A1 AND A2

5V 1.4A/0.8A/ 0.032A

518S0812

SILKSCREEN:SATA0

SSD ODD X

518S0813

SSD Power

HDD Power

518S0792

12V 1.2Amp

518S0251

5V 1.7Amp

518S0251

518S0251

353S2499

On= 2-5V

SATA Activity LED

SATA PORT A2 FOR ODD

A1 A2 ODD_SATA:P1 ODD_SATA:P2

SILKSCREEN:SATA2

USE OF PORT A2 FOR SSD IS NOT INTENDED VIA BOMOPTION THOUGH MLB SUPPORTS IT.

7

6

5

4

3

2

1

J4510CRITICAL

EP00-081-91M-ST-SM

18 90

18 90

18 90

18 90

21C4530SSD

10%0.01UF CERM16V 402

21C4531

SSD10% 4020.01UF CERM16V

21C4532SSD

402CERM0.01UF 16V10%

21C4533

SSD40210% CERM0.01UF 16V

7

6

5

4

3

2

1

J4530

SSD

M-ST-SMEP00-081-91

CRITICAL

2

1R4503100K

5%

402MF-LF1/16W

21

R4550

5%

805

0

NOSTUFF

1/8WMF-LF

18 90

18 90

18 90

18 90

21C4520

0.01UF 402CERM10% 16V

ODD_SATA:P2

21C4521

0.01UF 10% 16V 402CERM

ODD_SATA:P2

21C4523CERM16V 4020.01UF 10%

ODD_SATA:P2

21C452216V CERM 4020.01UF 10%

ODD_SATA:P2

7

6

5

4

3

2

1

J4520EP00-081-91

M-ST-SM

CRITICAL

ODD_SATA:P2

5

4

3

2

1

J452150293-0057N-001

M-ST-SM

CRITICAL

32

1

4

5

Q4500CRITICAL

FDMC8298MLP3.3X3.3

1

9

6

8

2

4

7

5

Q4501

CRITICAL

TDFNSLG5AP0012

1 C45000.1UF10%16VX5R402

2

1 C451720%10UF

603X5R10V

2

1 C4537SSD10UF

10V20%

603X5R

2

1 C4527

10VX5R603

10UF20%

2

1 C4518

25VX5R

10%10UF

1206-1

4

3

2

1

J4531

SSD

50293-00471-H01M-ST-SM

CRITICAL

21

L4511FERR-220-OHM

0402

2

1R452033K1/16WMF-LF

402

5%

21

R4501

5%1/16W

0

402MF-LF

2

1

3

Q4502SOT23-HF12N7002

2

1 C45251UF10%

X5R402

10V

7

6

5

4

3

2

1

J451150293-00771-H01

M-ST-SM

CRITICAL

21C451016V0.01UF 10% 402CERM

21C451110% 16V0.01UF 402CERM

21C451540210%0.01UF 16V CERM

21C4516CERM0.01UF 16V 40210%

18 90

18 90

18 90

18 90

2

1R4599

1/10W

DEVELOPMENT

5%330

603MF-LF

K

A

DS4599DEVELOPMENT


SILK_PART=SATA ACTIVE

SYNC_DATE=01/06/2011SYNC_MASTER=K60_JERRY

SATA Connectors

SATA_ODD_R2D_P

SATA_HDD_D2R_C_N

SATA_SSD_R2D_P

SATA_HDD_D2R_C_P

SATA_SSD_R2D_C_N

SATA_SSD_D2R_C_P

SATA_ODD_D2R_C_P

SATA_ODD_D2R_C_N

SATA_SSD_R2D_N

=PP5V_S0_SATA

HDD_OOB_TEMP_FB

SMC_ODD_DETECT

ODD_PWR_GATE

ODD_PWR_EN_LD

ODD_PWR_EN_L

SATA_HDD_D2R_N

SATA_HDD_R2D_P

SATA_ODD_R2D_C_N

PCH_SATALED_LMAKE_BASE=TRUE

SATALED_L

SATALED_R_L

=PP3V3_S0_SATALED

HDD_OOB_TEMP_FILT

SATA_HDD_R2D_N

=PP5V_S0_SATANET_PHYSICAL_TYPE=POWER

NET_PHYSICAL_TYPE=POWER

=PP12V_S0_SATA

ODD_PWR_EN_L_R

=PP12V_S0_SATASATA_HDD_R2D_C_N

SATA_ODD_R2D_C_P

SATA_SSD_D2R_C_N

SATA_HDD_D2R_P

=PP3V3_S0_ODD

NET_PHYSICAL_TYPE=POWERVOLTAGE=5V

PP5V_S0_SATA_FET

SATA_SSD_D2R_P

SATA_SSD_D2R_N

SATA_ODD_D2R_N

SATA_ODD_D2R_P

SATA_ODD_R2D_N

=PP5V_S0_SATASATA_SSD_R2D_C_P

SATA_HDD_R2D_C_P

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051-8115

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3

90

90

90

90

90

90

90

90

6 42

94

46 98

15 21 97

90

18

6 18

51 94 98

90

6 42

6 42

6 42

90

6

95

90

6 42

www.vinafix.vn

IO

IO

NC

GND

VBUS

NC

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

VCC

GND

SELOE*

D+

D-

Y+

Y-

M+

M-

GNDTHRM

OUT2

OUT1

ILIM

IN_0

IN_1

EN2

FAULT1*

FAULT2*

EN1

PAD

GNDTHRM

OUT2

OUT1

ILIM

IN_0

IN_1

EN2

FAULT1*

FAULT2*

EN1

PAD

VBUS

DATA-

GND

DATA+

VBUS

DATA-

GND

DATA+

VBUS

DATA-

GND

DATA+

VBUS

DATA-

GND

DATA+

IO

IO

NC

GND

VBUS

NC

IO

IO

NC

GND

VBUS

NC

IO

IO

NC

GND

VBUS

NC




36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

ADDED AT EVT & SWITCH TO S5 RAILUSB/SMC DEBUG MUX

Current Limit at 2.1Amp (@ S3 & S0)

USB PORT POWER:

SOFTWARE WILL ALOW 500MA/PORT, PLUS 2700MA EXTRA POWER TO BE

WHEN CURRENT HITS LIMIT, TPS2561 BECOME CONSTANT CURRENT MODE

STATE MAX MIN ( WITHIN THE TOLERANCE) PORT 0

514-0770

Place R4600 very close to ILIM pin

(PUT CAP ON CONNECTOR SIDE)

Place R4620 very close to ILIM pin

PORT 1514-0768

514-0768

514-0770

155S0329

SEL=1: CHOOSE USB

155S0329

155S0329

PORT 2

PORT 3

SEL=0: CHOOSE SMC

(PUT CAP ON CONNECTOR SIDE)

TOTAL: 4700MA

EACH PORT IS HARDWARE Capable of :

PORT 4 - USB 2.0 500MA = 500MA

Port 3 - iPhone fast charging = 1000mA

Port 2 - Wired Keyboard = 1100mA

EXAMPLE: Port 1 - iPad fast charging = 2100mA

distributed to approved devices on a 1st-come, 1st-served basis.

AND STAY AT THE LIMIT LEVEL UNTIL THERMAL SHUTDOWN WHEN JUNCTION REACH 130C

S0, S3 2.7A 2.1A -- PER PORT

155S0329

2

1C4650 MOJOMUX:YES

20%10V

402CERM

0.1UF

21

R4651

MOJOMUX:NO

MF-LF1/16W

402

0

5%

21

R4652

MOJOMUX:NO

1/16W5%

402MF-LF

0

2

1 C4622330UF

CRITICAL

6.3VPOLY-TANT

20%

CASE-D3L-SM

2

1C46010.1UF

20%

CERM10V

402

2

1C4621

402

0.1UF10V20%

CERM

2

1C4623

402

20%10V

0.1UF

CERM

2

1C4603

CERM10V20%

402

0.1UF

6

45

1

D4630

CRITICAL

RCLAMP0502NSLP1210N6

2

1 C4602

POLY-TANT

330UF20%6.3V

CRITICAL

CASE-D3L-SM

2

1 C4624

402CERM

20%16V

0.01uF

4 3

21

L4601CRITICAL

120-OHM-90MADLP0NS

4 3

21

L4611CRITICAL

120-OHM-90MADLP0NS

4 3

21

L4621120-OHM-90MA

DLP0NS

CRITICAL

4 3

21

L4631DLP0NS

CRITICAL

120-OHM-90MA

1

2

9

108

5

4

3

7

6

U4650MOJOMUX:YES

PI3USB102ZLE

CRITICAL

TQFN

2

1C463320%

CERM10V

402

0.1UF

2

1 C460020%0.01uF

CERM402

16V

2

1 C4660

402CERM16V

0.01uF20%

2

1C4661

CERM10V20%

0.1UF

4022

1 C4630

16V

0.01uF20%

402CERM

2

1R460023.2K

MF-LF402

1/16W1%

2

1R4620

1/16W1%

23.2K

MF-LF402

11

8

9

3

2

7

1

6

10

5

4

U4600CRITICAL

SONTPS2561DR

11

8

9

3

2

7

16

10

5

4

U4620TPS2561DR

CRITICAL

SON

21


0603CRITICAL

21

L4660

0603

FERR-220-OHM-2.5A

CRITICAL

21


0603

CRITICAL

21

L4620

0603

FERR-220-OHM-2.5A

CRITICAL

1

6

5

4

3

2

J4630F-ANG-TH

USB-K60K62

1

6

5

4

3

2

J4620USB-K60K62

F-ANG-TH

1

6

5

4

3

2

J4610USB-MG6-K60-K62

F-ANG-TH

1

6

5

4

3

2

J4600USB-MG6-K60-K62

F-ANG-TH

21

R4654

MOJOMUX:YES

MF-LF1/16W5%

0

402

21

R4653NOSTUFF

MF-LF1/16W

402

0

5%

6

45

1

D4620

CRITICAL


6

45

1

D4610

CRITICAL


6

45

1

D4600SLP1210N6

RCLAMP0502N

CRITICAL

EXTERNAL USB CONNECTORSSYNC_DATE=01/06/2011SYNC_MASTER=K62

PM_EN_USB_PWR

USB_DEBUGPRT_EN_L

USB_D_MUXED_N

USB_D_MUXED_P

USB_EXTB_N

=PP5V_S3_USB

USB_EXTD_OC_L

ILIM_IN1USB_EXTC_OC_L

USB_EXTA_OC_L

USB_EXTB_OC_L

=PP5V_S3_USB

ILIM_IN2

USB_EXTD_P

SMC_TX_L

USB_EXTC_NUSB_EXTC_P

USB_EXTA_NUSB_EXTA_P

USB_EXTB_P

SMC_RX_L


PP5V_USB_PORT3VOLTAGE=5V



PP5V_USB_PORT0


VOLTAGE=5V

USB_EXTD_N




PP5V_USB_PORT0_FVOLTAGE=5V


VOLTAGE=5V

PP5V_USB_PORT2_F

USB_PORT0_N

USB_PORT0_P

USB_PORT2_N

USB_PORT2_P

USB_PORT3_N

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMVOLTAGE=5V

PP5V_USB_PORT1_F

USB_PORT1_N

USB_PORT1_P

USB_PORT3_P




VOLTAGE=5VPP5V_USB_PORT3_F

MIN_LINE_WIDTH=0.6MMPP3V3_SMCUSBMUX

=PP3V3_S5_SMCUSBMUX

=PP3V3_G3H_SMCUSBMUX

46 OF 110

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051-8115

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2 3

2 3

2 3

2 3

63 91

46 47

92

92

35 92

6 43

35

34

34

35

6 43

35 92

46 47 48

34 92

34 92

34 92

34 92

35 92

46 47 48

95

95

35 92

95

95

95

92

92

92

92

92

95

92

92

92

95

95

95

6

6

www.vinafix.vn

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

G

D

S

G

D

S




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

CAMERA/ALS & BLUETOOTH (K37A) CONNECTOR

SD Card Reader Board ( Lazarus )

Skin Temp sense at upper Left Screen corner

IR RECEIVER CONNECTOR

518S0667

518S0785

518S0751

4 3

21

L4702

IR

120-OHM-90MA

CRITICAL

DLP0NS

4

3

2

1

6

5

J4780

IR

M-RT-SM

CRITICAL

53261-8604

4 3

21

L4701

120-OHM-90MADLP0NS

CRITICAL

2

1C4701

402

0.1UF20%10V

CERM

4 3

21

L4720BT

DLP0NS120-OHM-90MA

CRITICAL

2

1 C4721BT

20%

CERM10V

402

0.1UF

2

1 C4720BT

CERM

10UF20%6.3V

805-1

9

8

7

6

5

4

3

2

13

12

11

10

1

15

14

J4700CRITICAL

50224-01311-001M-RT-SM

21

L4703

IRCRITICAL

220-OHM-1.4A

0603

21

L4721 BT

0603

220-OHM-1.4ACRITICAL

21

L4700CRITICAL

220-OHM-1.4A

0603

2

1C470020%

10UF

805X5R10V

2

1 C4781IR

603X5R

1UF10%16V

2

1C4750

10%1UF

6.3VCERM402

21

R4750

402MF-LF

10K

1%1/16W

4 3

21

L4750CRITICAL

120-OHM-90MADLP0NS

21

L4751FERR-250-OHM

SM

CRITICAL

1

2

6

Q4710SOT-3632N7002DW-X-G

2

1R4751

402

10K1%1/16WMF-LF

4

5

3

Q47102N7002DW-X-GSOT-363

6

5

4

3

2

1

8

7

J4750F-RT-SM

CRITICAL

SM06B-SRKS-G-TB-HF

SYNC_MASTER=K62

Internal USB ConnectionsSYNC_DATE=01/06/2011

SDCARD_RESET_L

USB_SDCARD_L_NUSB_SDCARD_L_P

PP3V3_S3_SDCARD_FLT


VOLTAGE=3.3V

=SMB_ALS_SCL

USB_CAMERA_NUSB_CAMERA_P USB_CAMERA_L_P

USB_BT_P

USB_BT_N


=PP5V_S3_CAMERA


VOLTAGE=5V

PP5V_S3_CAMERA_FLT


PP5V_S3_IR_FLT


VOLTAGE=5VMIN_LINE_WIDTH=0.6MM

USB_IR_L_P

USB_BT_L_N

=SMB_ALS_SDA

VOLTAGE=3.3V

PP3V3_S3_BT_FLT


SNS_SKIN_LEFT_NSNS_SKIN_LEFT_P

NET_PHYSICAL_TYPE=POWER=PP3V3_S3_BT

USB_SDCARD_N

USB_SDCARD_P


=PP3V3_S3_SDCARD

SDCARD_RESET

SDCARD_PLT_RST_R_L

SDCARD_PLT_RST_L

USB_IR_L_N

=PP5V_S3_IRNET_PHYSICAL_TYPE=POWER

USB_IR_P

USB_IR_N

USB_CAMERA_L_N

USB_BT_L_P

47 OF 110

11.1.0

051-8115

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97

92

92

95

49

20 92

20 92 92 98

35 92

35 92

6 95

95 98

92 98

92 98

49

95

52 94 98

52 94 98

6

34 92

34 92

6 45

15 21 97 98

27 97

92 98

6

34 92

34 92

92 98

92 98

www.vinafix.vn

OUT

BI

BI

OUT

BI

BI

BI

BI

BI

BI

OC*

OUT2

OUT1

OUT0

THRMGND

EN

IN1

IN0

PAD

NC

G S

D

IN OUT

OUT

IN




36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

SDCONN DETECT DEBOUNCE, INVERSION, AND DETECT-CHANGED PCH GPIO CIRCUIT

GENERATE A 1 PULSE ON

SD CARD 3.3V OVERCURRENT PROTECTION CHIP WITH ACTIVE LOAD DISCHARGE

-> FROM SD CONN

Vil = 0.8V

Vih = 2.0V

NCX

-> TO ENET CHIP

CARD INSERT OR REMOVAL

-> TO PCH GPIO

SD CARD CONNECTOR

(CARD INSERTED = OPEN)

353S0004

MAKES THE ACTIVE-HIGH CASE UNUSABLE.

SD SPEC REQUIRES 47 UFCAPACITANCE ON 3.3V INPUT.22 + 10 + 10 + 2.2 (FLEX)

CAESAR-IV CARD DETECT IS PROGRAMMABLE, BUT A SILICON BUG

998-3513

TPS2065-1 (1.0A LIMIT) HAS ACTIVE LOAD DISCHARGE SO R4800 IS NOSTUFF.

37 92

37 92

37 92

37

37 92

37 92

37 92

37 92

37 92

37 92

9

8

7

6

5

3

2

1

4

U4800TPS2065-1

DGN

CRITICALDEVELOPMENT

2

1 C4802DEVELOPMENT

6.3V20%

603

10UF

X5R 2

1 C48030.1UF

DEVELOPMENT

16V10%

402X7R-CERM

2

1R4800NOSTUFF

47K1/16WMF-LF402

5%

2

1 C480020%

603

6.3VX5R

10UF

DEVELOPMENT

2

1 C4801

X7R-CERM16V10%

402

0.1UF

DEVELOPMENT

21

R48020

1/16W

402MF-LF

5%

DEVELOPMENT 2

1R480110K

5%

402

1/16WMF-LF

DEVELOPMENT

6

4

2

1

3

U4810DEVELOPMENT

SOT89174LVC1G86GF

2

1R481010K

5%

402

1/16WMF-LF

DEVELOPMENT

21

R4812

DEVELOPMENT

MF-LF1/16W

402

5%

33K

2

1C4810

DEVELOPMENT

10V10%

402-1

1UF

X5R

2

1C48120.1UF

402

20%

CERM10V

DEVELOPMENT

21

R4811DEVELOPMENT

SDCONN_DETECT_SHORT_DLY

1/16WMF-LF402

5%

33K

2

1C4811

DEVELOPMENT20%

0.1UF

402CERM10V

2

1

3

Q48102N7002SOT23-HF1

NOSTUFF

45 20 25 97

37

21

R4814DEVELOPMENT

0

MF-LF1/16W5%

402

2

1 C4805

805-3CERM-X5R6.3V20%22UF

DEVELOPMENT

9

8

7

6

5

4

3

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

27

28

J4800F-RT-SM

50671-02641

CRITICALDEVELOPMENT

21

L4800DEVELOPMENT

FERR-10-OHM-500MA

SM

37 92


SD READER CONNECTOR

=PP3V3_S0_SDCARD

VOLTAGE=3.3V


PP3V3_S0_SW_SD_PWR


MAKE_BASE=TRUE

=PP3V3_S0_PCH_GPIO

ENET_CR_PWREN

SDCONN_OC_L_R TP_SDCONN_OC_L

=PP3V3_S0_SW_SD_PWR

SDCONN_DATA<5>

SDCONN_DATA<4>

SDCONN_DATA<2>

SDCONN_DATA<3>

=PP3V3_S0_SW_SD_PWR

SDCONN_CMD

SDCONN_DATA<6>

SDCONN_WP

SDCONN_DATA<7>

SDCONN_DATA<0>

SDCONN_DETECT

SDCONN_CLK_L

SDCONN_DATA<1>

=PP3V3_S3_SDCARD

SDCONN_DETECT_LONG_DLY

SDCONN_DETECT SDCONN_STATE_CHANGE

SDCONN_DETECT_L

SDCONN_DETECT_PULSESDCONN_CLK

48 OF 110

11.1.0

051-8115

45 OF 98

5

6 95

6 20

37

45

45

45

6 44

www.vinafix.vn

IN

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

BI

IN

IN

OUT

OUT

IN

IN

IN

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

BI

BI

BI

BI

BI

BI

OUT

OUT

IN

IN

OUT

ININ

BI

OUT

INOUT

OUT

OUT

OUT

OUTNC

NCNC

NCNCNC

NC

NC

NC

IN

OUT

NC

OUT

BI

IN

OUT

ININ

IN

OUT

NCNC

NC

IN

NCNC

IN

NC

NC

NCNC

NC

NC

NC

P82

P83

P35

P97

P96

P95

P94

P93

P92

P91

P90

P86

P85

P84

P81

P80

P77

P76

P75

P74

P73

P72

P71

P70

P67

P65

P64

P63

P62

P61

P60

P52

P51

P50

P47

P46

P45

P44

P43

P42

P41

P40

P37

P36

P34

P33

P32

P31

P30

P27

P26

P25

P24

P23

P22

P21

P20

P17

P11

P10

P66P16

P15

P14

P13

P12 (1 OF 4)

PE1*

PE2*

PE3*

PE4*

PC0

PC1

PB7

PB6

PB5

PB4

PB3

PA5

PA4

PA0

PA1

PA2

PA3

PA6

PA7

PB0

PB1

PB2

PC2

PC3

PC4

PC5

PC6

PC7

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PE0

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

PH0

PH1

PH2

PH3

PH4

PH5

(2 OF 4)

ETRST*

EXTAL

RES*

XTAL

NMI

VSS

VCLVCC

MD2

MD1

AVSS

AVREFAVCC

(3 OF 4)

PI6

PI7

PI4

PI5

PI1

PI2

PI3

PJ7

PI0

PJ5

PJ6

PJ2

PJ3

PJ4

PJ0

PJ1

VSS

VCC3

AVSS1

AVCC1

AVREF1

NC

(4 OF 4)

NCNCNCNCNCNCNCNC

NCNCNCNCNCNCNCNCOUT

IN

NC

NC

NC

OUT

NC

NC

NC

NC

IN

NC

OUT

BI

BI

BI

BI

IN

IN

IN

BI

IN

IN

BI

BI

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

338S0878

K62 PROTO-2:NEW

K62 NEW:NOT USE

K62 NEW:NOT USE

Peak/Ave/Standby= 2mA/1mA/5uA

K62 NEW:NOT USE,PULLED UP


(OC)

(OC)

K62 NEW:NOT USE

(IMON)

(OC)

(OC)

(IMON)

(OC)

(OC)

(OC)

SMS Interrupt can be active high or low, rename net accordingly.

If SMS interrupt is not used, pull up to SMC rail.

SMC PG1:

Otherwise, TP/NC okay (was ISENSE_CAL_EN)SMC_IG_THROTTLE_L for MG systems.SMC PB3:

those designated as inputs require pull-ups.

Peak/Ave/Sleep/Standby = 40mA/25mA/20mA/50uA

Peak/Ave/Standby = 2mA/1mA/5uA

(OC)

(OC)

(OC)

PEVSTP

NOTE: Unused pins have "SMC_Pxx" names. Unused

PEVref

(OC)

(OC)

(OC)

(IMON)

pins designed as outputs can be left floating,

K60 New Change

K60 New Change

PECI(IMON)

(OC)

(OC)

(IMON)

(IMON)

K62 P1 NOT USED, WAS OOB_TEMP



(See below)

(OC)

(OC)

PROTO-3, Change back to WAKE_SCI_L

PROTO-3:back to K75F

2

1C4902

805

22UF

CERM

20%6.3V

19 48 97

47 48 97

47 97

2

1C4907

PLACEMENT_NOTE=Place C4907 close to U4900 pin 13

402CERM-X5R

0.47UF

6.3V10%

2

1 C4903

402

10V

0.1UF

CERM

20%

2

1C4920

10V

402

0.1UF

CERM

20%

PLACEMENT_NOTE=Place C4920 close to U4900 pin 76

21

R49994.7

1/16WMF-LF402

5%

PLACEMENT_NOTE=Place R4999 close to U4900 pin 76

2

1 C4904

10V

402CERM

20%0.1UF

2 1

XW4900SM

19 25 97

47

2

1 C4905

10V

402CERM

20%0.1UF

27 97

64 97

64 97

47

2

1 C4906

20%

CERM

0.1UF

10V

402

50 94

50 94

50 94

50 94

50 94

50 94

50 94

50 94

47

43 46 47 48

43 46 47 48

49

2

1R4909

5%10K

1/16WMF-LF

402

48

48

2

1R490110K

MF-LF

5%1/16W

402

2

1R4902

402

10K5%

MF-LF1/16W

2

1R4903

402

1/16W5%

MF-LF

0

NOSTUFF

2

1R499810K

1/16WMF-LF402

5%

43 47

15 19 97

42 98

51 94

53

53

53

53

50 94

50 94

50 94

50 94

50 94

50 94

50 94

47 48

47

47 48

47 48

47 48

49

49

49

49

49

49

47 97

47

50 94

43 46 47 48

43 46 47 48

47 47

18 48

19 25 27 97

48 15 18 21 97

15 19 48 97

47

47

19 47 97

47

47

18 97

47

47

47

47 47

5 19 47 63 97

74 97

5 19 32 47 63 97

47

G2

H1

H2

J4

J3

J1

J2

K4

B6

A6

C6

D6

B7

A7

C7

P15

N13

R15

P14

R14

P13

R13

N12

J13

J12

K14

K13

K12

L15

L14

L13

F2

G4

G1

C1

D3

C2

B1

C3

D5

B5

A5

D7

A8

C8

D8

B9

A9

C9

D9

F14

E13

E15

E14

E12

D15

D14

D13

C15

D12

C14

B15

B14

A15

C13

B12U4900

LFBGA

OMIT

H8S2117

B3

D4

C4

K2

F3

E1

R7

P7

M8

R8

P8

N9

R9

P9

N5

P5

R5

M6

N6

R6

P6

M7

L2

L4

M1

M2

M3

M10

N10

R10

P10

N11

R11

P11

M11

H12

H13

H15

H14

G12

G13

G15

G14

D11

A12

C11

B11

A11

D10

A10B10

N1

M4

N2

R1

N3

R2

P3

R3U4900

OMIT

LFBGAH8S2117

A2

A4

B13

F12

P4

D2

F1

J15

P1

A1

E3

F4

K1

E2

B2

L1

R12

M14

N14

U4900H8S2117

OMIT

LFBGA

D1

B4

A13

F13

R4

P2

K15

J14

F15

A14

C12

C10

B8

C5

G3

H4

H3

K3

L3

M5

N7

N8

A3

L12

M13

M12

M9

N4

E4

P12

M15

N15

U4900

OMIT

LFBGAH8S2117

2

1 C49100.1UF

10V20%

CERM402

21

R49110

402 1/16W5%MF-LF

21R4910

1/16W5%0

402MF-LF

21R4912

MF-LF 1/16W5% 4020

54

54

21 47 97

47

83 97

18 48 91

18 48 91

18 48 91

18 48 91

18 48 91

27 97

27 91

49

5 19 26 32 36 47 63 82 97

9 91 97

49

49

47 97


SMC

LPC_CLK33M_SMC

SMC_SMS_INT

SMB_BSA_DATA

SMC_FAN_0_CTL

SMC_PE0

SMC_PB6

SMC_PB3

SMC_HDD_OOB_TEMP

PM_BATLOW_L

MEM_EVENT_B_L

MEM_EVENT_A_L

USB_DEBUGPRT_EN_L

PM_SYSRST_L

PM_PECI_PWRGD_R

PVCCIO_S0_SMC_RCPU_PECI_R

SMC_THRMTRIP

SMC_PROCHOT

SMB_B_S0_CLK

SMB_B_S0_DATA

SMB_A_S3_CLK

SMB_A_S3_DATA

SMC_DIMM_VSENSE

SMC_DIMM_ISENSE

SMC_GPU_VSENSE

SMC_GPU_ISENSE

SMC_PCH_1V05_VSENSE

SMC_PCH_1V05_ISENSE

SMC_1V05_VSENSE

SMC_1V05_ISENSE

SMC_FAN_3_TACH

SMC_FAN_1_TACH

SMC_FAN_0_TACH

SMC_FAN_3_CTL

SYS_ONEWIRE

SMC_GFX_OVERTEMP_L

SMC_FAN_1_CTL

SMC_RESET_L

GND_SMC_AVSS

SMC_MD1

SMC_XTAL

SMC_TRST_L

SMC_NMI

SMC_KBC_MDE

GND_SMC_AVSS

PP3V3_G3H_AVREF_SMC

PP3V3_G3H_AVREF_SMC

=PP3V3_G3H_SMC


PP3V3_G3H_SMC_AVCC

VOLTAGE=3.4V


=PP3V3_G3H_SMC

SMC_EXTAL

PP3V3_G3H_SMC_AVCC

PM_PECI_PWRGD

=PPVCCIO_S0_SMC

CPU_PECI

SMC_PA0

SPI_DESCRIPTOR_OVERRIDE_L

SMC_ODD_DETECT

SMC_RUNTIME_SCI_L

ALL_SYS_PWRGD_SMC

RSMRST_PWRGD

PM_RSMRST_L

CPUIMVP_VR_ON SMC_PROCHOT_3_3_L

SMC_EXCARD_PWR_EN

SMC_RSTGATE_L

PM_PWRBTN_L

LPC_AD<0>

LPC_AD<1>

LPC_AD<2>

LPC_AD<3>

LPC_FRAME_L

LPC_SERIRQ

SMB_MGMT_DATA

SMS_ONOFF_L

SMC_GFX_THROTTLE_L

SMC_TX_L

SMC_RX_L

SMB_0_S0_CLK

SMC_PM_G2_EN

SMC_ADAPTER_EN

SMC_BIL_BUTTON_L

SMC_VCORE_ISENSE

SMC_VCORE_VSENSE

SMC_CPU_1V5_ISENSE

SMC_CPU_1V5_VSENSE

SMC_VCCSA_ISENSE

SMC_VCCSA_VSENSE

SMC_VAXG_ISENSE

SMC_VAXG_VSENSE

SMC_WAKE_SCI_L

SMC_TX_L

SMC_RX_L

SMB_MGMT_CLK

SMC_ONOFF_L

SMC_BC_ACOK

PM_SLP_S3_L

PM_CLK32K_SUSCLK

SMB_0_S0_DATA

SMC_LRESET_L

LPC_PWRDWN_L

PM_CLKRUN_L

PM_SLP_S4_L

PM_SLP_S5_L

SMC_LID

SMC_SYS_LED

G3_POWERON_L

SMC_TMS

SMC_TDO

SMC_TDI

SMC_TCK

BDV_BKL_PWM

SMC_VCL

SMB_BSA_CLK

49 OF 110

11.1.0

051-8115

46 OF 98

97

97

46 47 50 94

47 94

46 47 50 94

46 47 95

46 47 95

6 46 47

46 95

6 46 47

47 94

46 95

64 97

6 47

11 21 97

47

www.vinafix.vn

G

D

SIN

OUT

G

D

S

OUT

IN

ING

D

S G

D

S

IN

OUT

REFOUT

MR1*

THRMGND

RESET*

DELAY

MR2*

VINV+

SN0903048

PAD

IN

BI

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

UNUSED PORT 7 ANALOG SENSORS

MISC. SIGNAL ALIASESSMC Reset "Button", Supervisor & AVREF Supply

UNUSED TP/NC ALIASES

MEM_EVENT

518S0665

(IPU)NC

NC

POWER BUTTON

FROM DIMMS

TO/FROM SMC

TO SMC

To PCH

FROM MXM

FROM SMC

FROM CPU

TO SMC

SMC PROCHOT 3.3V LEVEL SHIFTING

Can be driven by VREG or CPU

FROM SMC

(IPU)

MR1* and MR2* must both be low to cause manual reset.

Used on mobiles to support SMC reset via keyboard.

NOTE: Internal pull-ups are to VIN, not V+.

SMC Crystal Circuit

SMC & MXM THERMTRIP LEVEL SHIFTING

4

5

3

Q5095SOT-3632N7002DW-X-G

21R50204025% MF-LF1/16W

10K

21R50211/16W

10K4025% MF-LF

21R5022MF-LF5% 4021/16W

100K

21R5023 2.0K4025% MF-LF1/16W

21R50245% 4021/16W MF-LF

10K

21R5025 10K5% 4021/16W MF-LF

21R5026 10K5% MF-LF 4021/16W

21R50274021/16W MF-LF5%

10K

21R5041MF-LF1/16W5% 402

100K

46 97

2

1 C5014

CERM

0.1UF

402

10V20%

21

R5012

402

1/16WMF-LF

5%

1K

1

6

2 Q5077SOT-363-LFMMDT3904-X-G

21

R5094

402

5%1/16WMF-LF

3.3K

4

3

5 Q5077MMDT3904-X-GSOT-363-LF

2

1R50773.3K

5%

MF-LF402

1/16W

2

1R5078

402

1/16WMF-LF

5%470

46 97

21R5042 100K5% 402MF-LF1/16W

21R5028 10K5% 1/16W 402MF-LF

21R5029 10K5% 1/16W 402MF-LF

21R5030402MF-LF1/16W5%

10K

21R5031402MF-LF1/16W5%

10K

1

2

6

Q5095

SOT-3632N7002DW-X-G

21 97

46

76

21

R5095

402

0

MF-LF1/16W5%

21R5035 10K5% 1/16W MF-LF 402

1

2

6

Q5096SOT-3632N7002DW-X-G 4

5

3

Q50962N7002DW-X-GSOT-363

2

1R5096

1/16WMF-LF402

5%3.3K

2

1R509710K

5%1/16WMF-LF

402

2

1

4

3

J5010

CRITICAL

M-RT-SM53261-8602

SILK_PART=PWR BTN

2

1R504010K1/16WMF-LF

5%

402

30 31

21R5034402MF-LF1/16W5%

10K

43

21

S5000SM

NTC020-CC1J-B260T

SILK_PART=SMC RESET

DEVELOPMENT

43

21

S5010DEVELOPMENT

SILK_PART=SYS POWER

NTC020-CC1J-B260TSM

21R5043 100K402MF-LF5% 1/16W

46 48 97

2

1R5010

MF-LF

1K

1/16W5%

402

2

1 C5013

10%

CERM

0.01UF

402

16V2

1C5012

X5R

10uF

6.3V

603

20%

31

9

5

8

7

6

2

4

U5010VREF-3.3V-VDET-3.0V

DFN

2

1C5010

CERM-X5R

0.47UF

402

6.3V10%

2

1C5011

10%

402

0.01UF

16VCERM

I581

2

1R50863.3K5%

402MF-LF1/16W

11 97

21

R50880

402

5%

MF-LF1/16W

2

1R5087

402MF-LF1/16W5%51

1

6

2 Q5086MMDT3904-X-GSOT-363-LF

4

3

5Q5086

C_THRMTRP1

MMDT3904-X-GSOT-363-LF

21

R50853.3K

MF-LF1/16W5%

402

21R50325%

10K402MF-LF1/16W

21R50335% MF-LF1/16W 402

10K

11 65 97

21R5037MF-LF 4021/16W5%

100K

21R5038 100K402MF-LF5% 1/16W

21R5036402MF-LF5% 1/16W

100K

2

1Y50205X3.2-SM

CRITICAL

20.00MHZ

21

C502015PF

5%50VCERM402

21

C502115PF

5%50VCERM402

21R5044402MF-LF1/16W5%

10K

46 47 97


SMC Support

SMC_PB6

SMC_LID

SMC_PA0

SMC_PE0MIN_NECK_WIDTH=0.1 mmVOLTAGE=0V

MIN_LINE_WIDTH=0.4 mmGND_SMC_AVSS

SMC_GFX_OVERTEMP_L

SMC_EXTAL

SMC_XTALMAKE_BASE=TRUETP_SMC_PB3

SMC_RX_L

SYS_ONEWIRE

G3_POWERON_L

SMC_GFX_OVERTEMP_LSMC_ONOFF_L

SMC_PROCHOT

CPU_PROCHOT_L

CPU_PROCHOT_BUF

=PP3V3_S0_SMC_LS

CPRCHOT_R

CPU_THRMTRIP_L

MXM_OVERT_L

C_THRMTRP_L

MXM_THRMTRIP_L

C_THRMTRP

MXM_THRMTRIP

=PP3V3_S0_SMC_LSPM_THRMTRIP_L

SMC_THRMTRIP

=PP3V3_S0_SMC_LS

=PPVCCIO_S0_SMC

SMC_TDI

SMC_TDO

SMC_TMS

TP_SMC_SYS_LEDMAKE_BASE=TRUE

SMS_ONOFF_L

SMC_EXCARD_PWR_EN

SMC_SYS_LED

SMC_PB3

SMC_RSTGATE_L

MEM_EVENT_B_L

MEM_EVENT_A_LMAKE_BASE=TRUE

MEM_EVENT_L

=PPSPD_S0_MEM_A

SMC_ONOFF_L

POWER_BUTTON_L

SMC_RESET_L

SMC_MANUAL_RST_L

MAKE_BASE=TRUETP_SMC_RSTGATE_L

TP_SMS_ONOFF_LMAKE_BASE=TRUE

SMC_PROCHOT_3_3_L

PM_SLP_S4_L

PM_SLP_S5_L

PM_SLP_S3_L

TP_SMC_EXCARD_PWR_ENMAKE_BASE=TRUE

SMC_ADAPTER_EN

SMC_TCK

SMC_BC_ACOK

USB_DEBUGPRT_EN_L

SMC_SMS_INT

SMC_TX_L

SMC_BIL_BUTTON_L

CPUIMVP_VR_ON

SMC_GFX_THROTTLE_L

MXM_ALERT_LMAKE_BASE=TRUE

MXM_PWR_LEVELMAKE_BASE=TRUE

SMC_DELAYED_PWRGDMAKE_BASE=TRUE

=PP3V3_S0_SMC_LS

SMC_RUNTIME_SCI_L

=PP3V3_G3H_SMC

=PP3V3_G3H_SMC

PP3V3_G3H_AVREF_SMCMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.1 mmVOLTAGE=3.3V

50 OF 110

11.1.0

051-8115

47 OF 98

46

46

46

46

46 50 94

46 47

46 94

46 94

43 46 48

46

46

46 47

46 47 97

6 47 51

6 47 51

6 47 51

6 46

46 48

46 48

46 48

46

46

46

46

46

46

46

6 30

97

97

5 19 32 46 63 97

5 19 46 63 97

5 19 26 32 36 46 63 82 97

19 46 97

46 48

46

43 46

46

43 46 48

46

46

46

76

76

64 97

6 47 51

21 46 97

6 46 47

6 46 47

46 95

www.vinafix.vn

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

IN

BI

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

IN

BI

IN

IN

OUT

BI

BI

IN

INOUT

INOUT

OUTIN

OUT

OUT

VER 1

VCC

A

1

0

B1

GND

B0

SEL




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Alternate SPI ROM Support

LPC+SPI Connector

Pull-up on debug card

516S0573

FRANK CONNECTOR

SPI Bus Series Resistance Option

2

1 C5144LPCPLUS:YES

CERM402

20%10V

0.1UF

21

R5145

MF-LF

LPCPLUS:YES

1/16W

0

5%

402

PLACEMENT_NOTE=Place near U1800

18 91

43 46 47

46

46 47

46

27 97

46 47

15 19 46 97

48 91

18 46 91

18 46 91

48 91

18 46 91

9

87

65

4

3433

3231

30

3

29

2827

2625

2423

2221

20

2

19

1817

1615

1413

1211

10

1

J5100LPCPLUS:YES

M-ST-SM

CRITICAL

55909-0374

21

43 46 47

46

46 47 97

46 47

46 47

19 46 97

18 46

48 91

48 91

21 48 91

18 46 91

18 46 91

27 91

18 55 91 21

R5156

LPCPLUS:YES

402

5%

MF-LF1/16W

PLACEMENT_NOTE=Place next to R6150

3348 91

18 55 91 21

R5157

LPCPLUS:YES


402MF-LF

5%1/16W

3348 91

18 55 91 21

R5158

LPCPLUS:YES

1/16W5%

MF-LF402


3348 91

2

1R5140100K

1/16W5%

402MF-LF

48 91

55 91

5

6

2

1

3 4

U5100

LPCPLUS:YES

PATH=I96

CRITICAL

SC70

NC7SB3157P6XG2

1R5144

1/16W5%

MF-LF402

20K

21

R5146LPCPLUS:NO

402

0

MF-LFPLACEMENT_NOTE=PLACE NEXT TO U5100

1/16W5%


LPC+SPI Debug ConnectorSYNC_MASTER=K62_AARON

SPI_MLB_CS_L

SPI_ALT_CLK

SPI_MISO

SPI_MOSI_R

SPI_ALT_MISO

SPI_ALT_MOSI

SPI_CLK_R

=PP3V3_S5_ROM

=PP5V_S0_LPCPLUS=PP3V3_G3H_LPCPLUS

LPC_CLK33M_LPCPLUS

LPC_AD<3>

SPIROM_USE_MLBSPI_ALT_CLKSPI_ALT_CS_LLPC_SERIRQ

SMC_TDI

SMC_RESET_LSMC_NMISMC_RX_LLPCPLUS_GPIO

SPI_CS0_L

LPC_AD<1>LPC_AD<0>

SPI_ALT_MOSISPI_ALT_MISO

DEBUG_RESET_LSMC_TMS

SMC_TDO

SMC_MD1SMC_TX_L

SPI_ALT_CS_L

SMC_TCK

LPC_PWRDWN_LPM_CLKRUN_LLPC_FRAME_L

SPI_CS0_R_L

LPC_AD<2>

SMC_TRST_L

=PP3V3_S5_LPCPLUS

=PP3V3_S5_LPCPLUS

SPIROM_USE_MLBMAKE_BASE=TRUE

51 OF 110

11.1.0

051-8115

48 OF 98

6 55

6

6

91

6 48

6 48

21 48 91

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OUT

BI




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

U9700

NOTE: O2Micro BLC HAS NO PU.

T29 I2C CONNECTIONS

T29 IC

(MASTER)

AC/DC PS POWERINA219: ACDC THRU J600

(WRITE: 0X80, READ: 0X81)

SMC "0" SMBUS CONNECTIONSUSES INTERNAL SMC CONTROLLER CHANNEL 0 ONLY

BLC MICRO

AND EDID ROM.

(WRITE: 0X9E READ: 0X9F)

SMC

(DIMM3: WRITE: 0XA6 READ: 0XA7)

NOTE: SPTX BLC HAS 4.7K PU.NOTE: DISPLAY TCON HAS 4.7K PU.

DISPLAY TCON TO SPTX OR O2M BLC

U4900

THIS PAGE DIFFERENT BETWEEN K60 AND K62.

MEMORY A DIMMS

PCH "SMBUS" CONNECTIONS

DISPLAY TCON

PCH "SML 0" CONNECTIONS

USES INTERNAL SMC CONTROLLER CHANNEL 1 ONLY

(SLAVE)PARADE ON TCON BOARD VIA J9002

(TBD WRITE: 0X1A READ: 0X1B)(TO READ VENDOR ID

DISPLAY TCON

(WRITE: 0X5C READ: 0X5D)

MASTER BUS TO LUT ROM

U9330

WHEN USB POWER (VBUS) IS VALID.

T29 PORT A MCU

(WRITE: 0X86 READ: 0X89)

PCH "SML 1" CONNECTIONS

DP SDRV "A"

THE PCH address is user programmable by SPI ROM


SPTX BLC MICRO

PCH (FOR TEMP)

EMC1402 ON AMD MXM CARD (WRITE: 0X98 READ: 0X99)

TMP421 ON TCON BOARD VIA J9002

PANEL TEMP SENSOR

SMC "MANAGEMENT" SMBUS (BUS 1)


PCH

U6806

XDP (PCH)

XDP (CPU)

J2550

J2500


(WRITE: 0XD2 READ: 0XD3)

MEM VREF MARGIN A

CK505

(WRITE: 0X7C READ: 0X7D)

U2910

MIKEY

U2900

U9310, PS8301

(WRITE: 0X94, READ: 0X95)

U1800

(SLAVE)

PCIE MINI-CARD

MEMORY B DIMMS

X18 WI-FI MODULETMP106: J3400

ALS

(MASTER) (DIMM0: WRITE: 0XA0 READ: 0XA1)

SMCU4900

(MASTER)

U4900

SMC

(SLAVE)

BUS A CAN USE EITHER INTERNAL SMC CHANNEL 0 OR 1, K74 CHOOSES 1

NOTE: SMC RMT BUS REMAINS POWERED AND MAY BE ACTIVE IN S3 STATE

SMC "A" SMBUS CONNECTIONS

U1800

PCH

(MASTER)

U4900

(MASTER)

U2600


SMC

U1800

USES INTERNAL SMC CONTROLLER CHANNEL 2 ONLY (NO CONNECTIONS, JUST PULLUP)

J3200-A/B

(SLAVE)

AND PANEL ID)

TCON ALSO HAS

(MASTER)

(MASTER)

(MASTER)

SMCU4900

EMC1428: U5500

GPU ON CARD - J8400

MXM TEMPAlso reserve 0x56 and 0x32 per spec

(WRITE: 0x92 READ:0x93)

PROD: AMB,L-SKIN,R-SKIN,ODD,

DEV: CPU D,CPU HTSK

LCD,CPU PROX,MXM TEMPS

NV INSIDE (WRITE: 0X9E READ: 0X9F)


VIA J602



SMC SLAVE SMBUS "2" CONNECTIONS

EMC1414: U5520

J3100-A/B

(SLAVE)VIA J9002

OUTPUT VOLTAGE, CURRENT, POWER


VIA J602

MEM VREF MARGIN B

I2C BUS PULL-UP RAIL MUST REFLECT


3 SENSE POINTS - PRIMARY, SECONDARY, AMB

SMC "B" SMBUS CONNECTIONSBUS B CAN USE EITHER INTERNAL SMC CHANNEL 0 OR 1, K60/62 CHOOSES 0

(WRITE: 0X98 OR 0X9A, READ: 0X99 OR 0X9B)EMC1403-[1,2] : ACDC THRU J600

AC/DC PS TEMPS

2

1R5280100K

MF-LF1/16W

5%

402 2

1R5281

MF-LF1/16W

100K

402

5%

2

1R5291

MF-LF402

1/16W5%2.2K

2

1R52905%

402MF-LF1/16W

2.2K

2

1R5261

MF-LF

5%1/16W

402

2.0K

2

1R52605%

402

1/16WMF-LF

2.0K

2

1R52512.2K

MF-LF1/16W

402

5%

2

1R52502.2K

1/16W

402

5%

MF-LF

2

1R5203

MF-LF402

1/16W5%8.2K

2

1R5202

1/16W5%

MF-LF402

8.2K

2

1R5204

MF-LF1/16W

402

5%

NOSTUFF

8.2K

2

1R5205

MF-LF1/16W

402

5%8.2K

NOSTUFF

21

R5206

402

1/16W

0

MF-LF

5%

21

R5207

402

5%

0

MF-LF1/16W

2

1R52704.7K

402

1/16WMF-LF

5%

2

1R5271

MF-LF

4.7K5%

402

1/16W

2

1R52082.2K

402

5%

MF-LF1/16W

2

1R5209

1/16WMF-LF

2.2K5%

402

2

1R52102.2K

5%

402

1/16WMF-LF

2

1R52115%

402

1/16WMF-LF

2.2K

6 81 94

6 81

94

2

1R5230T29

5%1/16W

402

4.7K

MF-LF

2

1R5231T29

MF-LF402

4.7K5%1/16W

SYNC_MASTER=K60_MARK

SMBUS CONNECTIONSSYNC_DATE=01/06/2011

MAKE_BASE=TRUESMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUESMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUESMBUS_SMC_A_S3_SDA

=I2C_VREFMRGN_A_SDA

=SMB_ACDC_SDA

SMB_0_S0_DATA

SMBUS_SMC_A_S3_SCLMAKE_BASE=TRUE

=SMB_ALS_SCL

MAKE_BASE=TRUESML_PCH_0_CLK

SMB_0_S0_CLK

=I2C_SODIMMA_SCL

SMBUS_SMC_0_S0_SDAMAKE_BASE=TRUE

=PP3V3_S0_SMBUS

=SMB_SNS1_SCL

=SMB_SNS1_SDA

=SMB_MXM_THRM_SDA

SMB_MGMT_CLK

=PP3V3_S0_SMBUS_SMC_MGMT

SMB_A_S3_DATA

=SMB_ACDC_SCL

SMB_BSA_CLK

MAKE_BASE=TRUESML_PCH_0_DATA

SMB_B_S0_DATA

=PP3V3_S3_SMBUS_SMC_A

SMB_BSA_DATA

=PP3V3_S0_SMBUS_SMC_B

SMB_A_S3_CLK

=SMB_MINI_SCL

=SMB_MINI_SDA

=I2C_SODIMMA_SDA

MAKE_BASE=TRUESMBUS_SMC_BSA_SDA

MAKE_BASE=TRUESMBUS_SMC_BSA_SCL

SMB_B_S0_CLK

=I2C_AUDIO_SDA

=I2C_SODIMMB_SDA

=SMBUS_CK505_SCL

SMBUS_SMC_MGMT_SCLMAKE_BASE=TRUE

=SMBUS_CK505_SDA

=I2C_AUDIO_SCL

=I2C_VREFMRGN_B_SDA

=I2C_VREFMRGN_A_SCL

=SMBUS_XDP_SCL

=SMBUS_XDP_SCL

=SMBUS_XDP_SDA

=SMBUS_XDP_SDA

=PP3V3_S0_SMBUS_SMC_0

=SMB_ALS_SDA

SMB_DP_TCON_SLA_SCL

=SMB_BLC_PCH_SCL

=SMB_BLC_PCH_SDA

SMBUS_SMC_MGMT_SDAMAKE_BASE=TRUE

=SMB_MXM_THRM_SCLMAKE_BASE=TRUESMBUS_SMC_0_S0_SCL

SML_PCH_1_DATAMAKE_BASE=TRUE

MAKE_BASE=TRUESML_PCH_1_CLK

=PP3V3_S0_SMBUS

=PP3V3_S0_SMBUS

=SMB_DP_TCON_SDAMAKE_BASE=TRUE

SMB_BLC_TCON_SDA

=PP3V3_S0_SMBUS

SMB_MGMT_DATA=PP3V3_S0_SMBUS_SMC_BSA

=I2C_VREFMRGN_B_SCL

SMB_DP_TCON_SLA_SDA

=I2C_T29AMCU_SDA

=I2C_T29AMCU_SCL

MAKE_BASE=TRUESMB_BLC_TCON_SCL

MAKE_BASE=TRUESMBUS_PCH_DATA

SMBUS_PCH_CLKMAKE_BASE=TRUE

=I2C_DPSDRVA_SCL

=I2C_DPSDRVA_SDA

=I2C_SODIMMB_SCL

=SMB_DP_TCON_SCL

MAKE_BASE=TRUEI2C_T29_SDA

MAKE_BASE=TRUEI2C_T29_SCL

=PP3V3_S0_T29I2C

52 OF 110

11.1.0

051-8115

49 OF 98

94

94

94

28

6

46

94 44 18 94

46

30

94

6 49

52

52

76

46

6

46

6

46

18 94

46

6

46

6

46

33

33

30

94

94

46

62

31

26

94

26

62

28

28

25 49

25 49

25 49

25 49

6

44

81

6

6

94

76 94

18 94

18 94

6 49

6 49

6 49

46 6

28

81

84

84

18 94

18 94

84

84

31

86 96

86 96

6

www.vinafix.vn

OUT

IN

V+

REFIN+

IN- OUT

GND

OUT

IN

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

V+

REFIN+

IN- OUT

GND

OUT

OUT

V+

REFIN+

IN- OUT

GND

OUT

OUT

V+

REFIN+

IN- OUT

GND

V+

REFIN+

IN- OUT

GND

OUT

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM



TABLE_5_ITEM





TABLE_5_ITEM



TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM



TABLE_5_ITEM

TABLE_5_ITEM




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_5_ITEM

TABLE_5_ITEM



DIMM VDD 1.5V (LIKELY DEVELOPMENT ONLY)

IMAX = 8.25A

IMAX = 8.25A

353S2073GAIN = 200V/V

353S2073GAIN = 200V/V

IMAX = 8.25A

IMAX = 8.25A

IMAX = 8.25A

353S2073GAIN = 200V/V

NO_CPU_VCCSA_SENSE, ANDTHE NO_1V05_PCH_SENSE,

NO_CPU_1V5_SENSEBOMOPTIONS SHOULD IDEALLYNEVER BE USED AS TOTAL CPU POWERSENSING REQUIRES ALL3 SENSORS.

IMAX = 2.79V

IMON MAX = 0.9V

353S2073GAIN = 200V/V

NOTE: TOTAL CPU POWER =+ VC5R*IC5R

VC0C*IC0C

+ VCSR*ICSR+ VC0G*IC0G+ VV1R*IC1R

whereIC1R = IV1R - IN1R - ICSR

SENSE RESISTOR CURRENT (ICSR) AND VOLTAGE (VCSR) SENSE

CPU VAXGIMON CURRENT (IC0G) AND VOLTAGE (VC0G) SENSE

IMON CURRENT (IC0C) AND VOLTAGE (VC0C) SENSEGPU MXM

SENSE RESISTOR CURRENT (IG0R) AND VOLTAGE (VG0R) SENSE

CPU VCCSA

IMON MAX = 0.9V

IMAX = 2.7V

PCH 1.05V

IMON MAX = 2.7V

CPU VDD 1.5VSENSE RESISTOR CURRENT (IC5R) AND VOLTAGE (VC5R) SENSE

SENSE RESISTOR CURRENT (IN1R) AND VOLTAGE (VN1R) SENSE

PLACE C CLOSE TO SMC

CPU VCC (VCORE)

SENSE RESISTOR CURRENT (IM0R) AND VOLTAGE (VM0R) SENSE

IMAX = 2.79V

IMON CURRENT (IV1R) AND VOLTAGE (VV1R) SENSE1.05V FOR CPU VCCIO, CPU VCCSA & PCH 1.05V

46 94

2

1 C5332

PLACEMENT_NOTE=PLACE C5332 NEAR SMC

10%

CERM-X5R6.3V

402

0.22UF

21

R5332

PLACEMENT_NOTE=PLACE R5332 NEAR SMC

402

5%

5.1K

1/16WMF-LF

21

C5331

402CERM

0.01UF

20%16V

21

R5331

1%1/16WMF-LF

9.31K

OMIT_TABLE

402

21

R5333

1/16WMF-LF402

10K

1%65 95

5

2

4

1

3

U5330

CRITICAL

SC70-5OPA348

2

1R533410K1%1/16W

402MF-LF

3

1

6

4

5

2

U5300

CPU_1V5_SENSE

INA210SC70

2

1 C5302


OMIT_TABLE

0.22UF

402X5R

20%6.3V

43

21

R5300

1/4W

1206

0.002

MF-LF

1%

OMIT_TABLE

21

R5302


1/16W

402MF-LF

1%

4.53K

CPU_1V5_SENSE

21

R5301

402

1/16WMF-LF

1%

4.53K

CPU_1V5_SENSE

PLACEMENT_NOTE=PLACE R5301 NEAR CPU 2

1 C5301OMIT_TABLE


0.22UF20%

402X5R6.3V

21

R536018.2K

1/16W1%

402MF-LF

PLACEMENT_NOTE=PLACE R5360 NEAR CPU

2

1 C5362


6.3V20%

X5R402

0.22UF

2

1R5362

402MF-LF1/16W1%6.04K

21

C5351

402

16VCERM

20%

0.01UF

46 94

2

1 C5352

CERM-X5R

0.22UF

402

10%6.3V


21

R5352

5%

MF-LF


402

1/16W

5.1K5

2

4

1

3

U5350

CRITICAL

OPA348SC70-5

21

R5353

1/16W

402

1K

5%

MF-LF

68 95

46 94

2

1 C5350

X5R

20%6.3V


402

0.22UF

21

R53504.53K

1/16W1%

MF-LF402


46 94

46 94

2

1 C5340OMIT_TABLE

6.3VPLACEMENT_NOTE=PLACE C5340 NEAR SMC X5R

0.22UF20%

402

21

R5340VAXG


1%

4.53K

402MF-LF1/16W

21

R5342

402

5.1K


VAXG

1/16WMF-LF

5%

21

C5341VAXG

16V

402

20%

0.01UF

CERM

21

R5341VAXG

1/16W

21K

MF-LF402

1%

5

2

4

1

3

U5340

CRITICAL

VAXG

SC70-5OPA348

2

1 C5342

CERM-X5R

0.22UF

OMIT_TABLE

402

10%


6.3V

21

R5343

1/16W

VAXG

1%

MF-LF402

10K65 95

2

1R5344

1/16W

VAXG

1%

402MF-LF

10K

46 94

46 94

46 94

46 94

21

C5300CPU_1V5_SENSE

20%6.3VX5R402

0.22UF

46 94

46 94

2

1 C5311


OMIT_TABLE

402

20%6.3V

0.22UF

X5R

21

R5311

402

1%

CPU_VCCSA_SENSE

1/16W


MF-LF

4.53K

2

1 C5312


402X5R

20%6.3V

0.22UF

OMIT_TABLE21

R5312

MF-LF402


1/16W

4.53K

1%

CPU_VCCSA_SENSE

3

1

6

4

5

2

U5310INA210

CPU_VCCSA_SENSE

SC70

21

C5310

20%6.3VX5R402

0.22UF

CPU_VCCSA_SENSE

46 94

46 94

21

R5321

402

1%


MF-LF1/16W

4.53K

1V05_PCH_SENSE

2

1 C5321OMIT_TABLE

20%

402X5R6.3V


0.22UF

2

1 C5322OMIT_TABLE

0.22UF20%6.3VX5R

PLACEMENT_NOTE=PLACE C5322 NEAR SMC 402

21

R5322

1%

402

1/16W

4.53K

1V05_PCH_SENSE


MF-LF

43

21

R5320OMIT_TABLE

1/4W1%

0.002

1206MF-LF

3

1

6

4

5

2

U5320

1V05_PCH_SENSE

SC70INA210

21

C53200.22UF

402X5R6.3V20%

1V05_PCH_SENSE

46 94

46 94

21

R5371


DIMM_1V5_SENSE

4.53K

1%

MF-LF402

1/16W

2

1 C5371


OMIT_TABLE

402X5R

0.22UF20%6.3V

21

R5372DIMM_1V5_SENSE

4.53K

1/16W

402

1%

MF-LF

2

1 C5372OMIT_TABLE

X5R6.3V

0.22UF20%

402

43

21

R5370

1206MF-LF1/4W

0.0021%

21

C5370

X5R402

DIMM_1V5_SENSE

0.22UF

6.3V20%

3

1

6

4

5

2

U5370SC70

INA210

DIMM_1V5_SENSE

43

21

R5310OMIT_TABLE

1/4WMF-LF1206

1%0.002

3

1

6

4

5

2

U5360

CRITICAL

INA210SC70

43

21

R53611%

MF-LF1/4W

0.002

CRITICAL

1206

2

1 C53600.22UF

402X5R6.3V20%

21

R5363

402MF-LF

1%1/16W

4.53K

2

1 C5363

402

20%0.22UF6.3VX5R

46 94 21

R5330

1%

MF-LF402

1/16W

4.53K

PLACEMENT_NOTE=PLACE R5330 NEAR CPU2

1 C5330

20%

X5R6.3V


0.22UF

402

116S0004 RES,0 OHM,402 NO_VAXG2 C5340,C5342

132S0080 CAP,0.22UF,402 VAXG2 C5340,C5342

CPU/PCH/GPU POWER SENSESYNC_MASTER=K62 SYNC_DATE=01/06/2011

R53101104S0018 RES,2 MILLIOHM,1206 CPU_VCCSA_SENSE

C5301,C5302132S0080 2 CAP,0.22UF,402 CPU_1V5_SENSE

1101S0414 R5320RES,0 OHM,1206,20 MILLIOHM MAX NO_1V05_PCH_SENSE

132S0080 2 CAP,0.22UF,402 C5321,C5322 1V05_PCH_SENSE

RES,0 OHM,1206,20 MILLIOHM MAX NO_CPU_1V5_SENSE101S0414 1 R5300

1104S0018 R5320RES,2 MILLIOHM,1206 1V05_PCH_SENSE

C5321,C53222 RES,0 OHM,402116S0004 NO_1V05_PCH_SENSE

R5331 CPUVCORE-3PH1114S0312 RES,MTL FILM,1/16W,9.31K,0402

RES,MTL FILM,1/16W,21K,0402 R53311 CPUVCORE-4PH114S0345

CPU_1V5_SENSERES,2 MILLIOHM,12061104S0018 R5300

NO_CPU_1V5_SENSERES,0 OHM,402116S0004 2 C5301,C5302

NO_CPU_VCCSA_SENSERES,0 OHM,1206,20 MILLIOHM MAX101S0414 1 R5310

C5311,C5312CAP,0.22UF,4022132S0080 CPU_VCCSA_SENSE

NO_CPU_VCCSA_SENSEC5311,C5312RES,0 OHM,402116S0004 2

132S0080 DIMM_1V5_SENSE2 CAP,0.22UF,402 C5371,C5372

PRODUCTION2116S0004 C5371,C5372RES,0 OHM,402

SMC_1V05_VSENSE

GND_SMC_AVSS

VR_ISNS_VAXG_N

SNS_PS_VAXG_ISNS

SMC_DIMM_VSENSE

SMC_DIMM_ISENSE

GND_SMC_AVSS

PP1V5_S0_CPU_MEM_SNS=PPVCORE_S0_CPU

SNS_CPU_1V5_P

GND_SMC_AVSS

VR_ISNS_N_1V05

P1V05_IMON VR_ISNS_P_1V05

=PP5V_S0_ISENSE

SMC_VCORE_ISENSE

=PPVCCSA_S0_CPU

PPVCCSA_S0_INPUT_SNS PP1V5_S3_MEM_SNS

=PP3V3_S0_SENSE

GND_SMC_AVSS

SMC_GPU_ISENSE

SNS_DIMM_1V5_N

=PP3V3_S0_SENSE

SNS_I_MXM_P

PP12V_S0_MXM_SNS

=PP12V_S0_MXM_PWR

SMC_PCH_1V05_VSENSE

GND_SMC_AVSS

GND_SMC_AVSS

PP1V05_S0_PCH_SNS

=PP1V5_S0_PWR

SMC_VCCSA_VSENSE

SNS_CPU_1V5_N SMC_CPU_1V5_ISENSE_R

SMC_VCCSA_ISENSE

GND_SMC_AVSS

SMC_DIMM_1V5_R

GND_SMC_AVSSGND_SMC_AVSS

SMC_GPU_VSENSE

SMC_CPU_1V5_VSENSE

GND_SMC_AVSS

SNS_1V05_PCH_R

SMC_VCCSA_ISENSE_R

=PPVCCSA_S0_INPUT_PWR

SMC_CPU_1V5_ISENSE

=PP3V3_S0_SENSE

SNS_1V05_PCH_N

SNS_VCCSA_N

SNS_VCCSA_P

GND_SMC_AVSS

SMC_PCH_1V05_ISENSE

=PP1V05_S0_PCH_PWR

SNS_DIMM_1V5_P

SNS_I_MXM_N

GND_SMC_AVSS

=PP1V05_S0_PWR

=PP1V5_S3_MEM_PWR

VR_ISNS_VCORE_PVR_CPU_IMON

SMC_VCORE_VSENSE

SMC_1V05_ISENSE

SMC_GPU_R

=PP5V_S0_ISENSE

SNS_1V05_PCH_P

=PP3V3_S0_SENSE

GND_SMC_AVSS

VR_ISNS_VCORE_N

GND_SMC_AVSSSNS_PS_VCORE_ISNS

GND_SMC_AVSS

GND_SMC_AVSS

=PP5V_S0_ISENSE

SMC_VAXG_VSENSE=PPVAXG_S0_CPU

VR_AXG_IMON VR_ISNS_VAXG_P

=PP3V3_S0_SENSE

SMC_VAXG_ISENSE

53 OF 110

11.1.0

051-8115

50 OF 98

46 47 50 94

94 95

46 47 50 94

6 6 13 16 65

94

46 47 50 94

6 50

6 13

6 6

6 50 52

46 47 50 94

94

6 50 52

94

6

6

46 47 50 94

46 47 50 94

6

6

94 94

46 47 50 94

94

46 47 50 94 46 47 50 94

46 47 50 94

94

6 69

6 50 52

94

94

94

46 47 50 94

6

94

94

46 47 50 94

6

6

94 95

6 50

94

6 50 52

46 47 50 94

46 47 50 94

46 47 50 94

46 47 50 94

6 50

6 13 17 65

6 50 52

www.vinafix.vn

IN

OUT

GND

V+IN

GND

V+




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

DRIVE ASLEEP = HDD DRIVES HDD_OOB_TEMP LOW

BOTH FUNCTIONS NOT USED.

NOTE: WILL BE CONNECTED TO SATA PWR CONNECTOR PIN 11THIS PIN IS ORIGINALLY INTENDED FOR HDD LED OUTPUT,AND ALSO FOR HDD STAGGERED PIN UP (FLOATING) OR IMMEDIATE SPIN-UP (GROUND).

DRIVE ACTIVE = VALID SIGNAL PROTOCOL BETWEEN 0-2.0V.

HIGH: 1.2V TO 2.0V

DRIVE ABSENT = OOB IS PULLED HIGH UNLESS PCH DETERMINES SSD PRESENT AND DRIVES USE_HDD_OOB_L LOW WHICH THEN PULLS HDD_OOB_TEMP LOW.

LOW: 0.0V TO 0.3VFROM DRIVE:

Pull up 1.5V.

1.5V

Trip point 1.0V.

HDD OOB TEMPERATURE SENSING

2

1R5405

MF-LF1/16W

1K

402

5%

2

1R5402

1/16W5%

MF-LF402

180K

2

1R5404150K

1/16W5%

MF-LF402

2

1 C5401

20%16VCERM603

0.1UF

42 94 98

2

1 C54000.1UF

16V20%

CERM603

46 94

8

7

5

6

4

U5400LM393

CRITICAL

SOI-HF21

R540710K

MF-LF402

5%1/16W

2

1R54060

1/16W

402MF-LF

5%

NOSTUFF

20 97

8

1

3

2

4

U5400SOI-HF

CRITICAL

LM393

2

1R5400

1%

402

1/16WMF-LF

110K

2

1R5401

402

1%10K

1/16WMF-LF

21

R5403

MF-LF402

5%1/16W

3.3K


HDD OOB SENSE

=PP12V_S0_SENSE

=PP3V3_S0_SMC_LS

SMC_HDD_OOB_TEMP

HDD_OOB_TEMP_FILT

USE_HDD_OOB_PD

USE_HDD_OOB_L_RUSE_HDD_OOB_L

HDD_OOB_1V00_REF

=PP3V3_S0_SMC_LS HDD_OOB_1V00_REF

HDD_OOB_TEMP_R

54 OF 110

11.1.0

051-8115

51 OF 98

6

6 47 51

51 97

6 47 51 51 97

94

www.vinafix.vn

ALERT*

THERM*/ADDRDP1

SMCLK

SMDATA

VDD

DN1

DP2/DN3

DN2/DP3GND

BI

IN

VDD

DP6/DN7

DN6/DP7

DN4/DP5

DP2/DN3

DN2/DP3

DP4/DN5

DN1

DP1

THRM_PADGND

NC

TRIP/SET

SMDATA

SMCLK

SYS_SHND*

ALERT*

BI

IN

NC




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

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8 7 5 4 2 1

ON K60 IT IS SHARED.AMBIENT TEMP SENSOR ON K62 GOES TO J5500.

ODD TEMP SENSOR

MXM HTSK TEMP SENSOR

CPU PROXIMITY TEMP SENSOR

Place Q5500 (CPU Proximity Sensor) at the solder side

CPU HTSK TEMP SENSOR

THIS PAGE DIFFERENT BETWEEN K60 AND K62.

EMC1414-A-AIZL: 33K PULL UP: I2C ADDRESS: WRITE: 0x78, READ: 0x79

SNS T1: PRODUCTION TEMP SENSOR IC

518S0665

SNS T2: DEVELOPMENT TEMP SENSOR IC

EMC1428-7: 6.8K PULL UP: I2C ADDRESS: WRITE: 0x92, READ: 0x93

MLB Prox 0 (Tm0p)

AMB (TA0p)

ODD (TO0p)

at edge near backer plate of CPU to replace HeatSink Temp Sensor

(TL2p)

MLB Prox 1 (Tm1p)

CPU HTSK (TC0h)

MXM HTSK (TG0h)

RIGHT SKIN (TS0p)

LEFT SKIN (TS2p)

CPU PROX (TC0p)

RIGHT SKIN TEMP SENSOR

LCD TEMP

CPU THERMAL DIODE(TC0D)

ONLY DP/N1 compatible with CPU thermal diode

518S0665

LEFT SKIN TEMP SENSOR

CONNECTOR COMBINED WITH CAMERA/BT

518S0678

Set trip point to 125 C.

518S0678518S0677

518S0698

AMBIENT TEMP SENSOR

Place Hsk sensor conn top side next MXM or CPU

2

1 C55210.0022UF50VCERM

10%

402

DEVELOPMENT

2

1C5520DEVELOPMENT

X5R

10%

402-1

1UF

6.3V

21

L5510FERR-220-OHM

0402

21

L5511FERR-220-OHM

0402

21

L5500FERR-220-OHM

0402

21

L5501

0402

FERR-220-OHM

21

L5540MXM

0402

FERR-220-OHM

21

L5541FERR-220-OHM

0402

MXM2

1

4

3

J5530

CRITICAL

53398-8602M-ST-SM

MXMSILK_PART=MXM HSK

21

L5520

0402

FERR-220-OHM

21

L5521FERR-220-OHM

0402

2

1

4

3

J552053261-8602

M-RT-SM

CRITICAL

SILK_PART=SKIN RIGHT TEMP

2

1R55201%

MF-LF402

1/16W

DEVELOPMENT

33.2K

2

1C550010%

X5R402-1

10V

1UF

2

1R5521

402

DEVELOPMENT

10K

MF-LF

5%1/16W1

7

9

10

6

4

2

5

3 8

U5520

DEVELOPMENT

MSOPEMC1414-A

2

1 C5504NOSTUFF

10%0.0022UF

50VCERM4022

3

1Q5500

SOT23MMBT3904G

2

1 C55500.0022UF

CERM

DEVELOPMENT

10%

402

50V

21

L5550

0402

FERR-220-OHM

DEVELOPMENT

21

L5551

0402

FERR-220-OHM

DEVELOPMENT

49 52

49 52

16

5

17

6

11

12

8

15

10

3

1

14

9

4

2

7

U5500

CRITICAL

QFNEMC1428-7

PLACEMENT_NOTE=PLACE U5500 UNDER MXM HTSK TO GET MXM PROX TEMP

2

1

XW5504 SM

OMIT 2

1

XW5505OMIT

SM

2

1

XW5503SM

OMIT2

1

XW5502 SM

OMIT

2

1

XW5501SM

OMIT2

1

XW5500 SM

OMIT

49 52

49 52

2

1R5501

402

5%10K

MF-LF1/16W

2

1R55001%6.81K

402

1/16WMF-LF

2

1R5502

1/16WMF-LF

20K5%

402

2 1

L5522FERR-220-OHM

0402

2 1

L5523FERR-220-OHM

0402

2

1 C552210%0.0022UF

CERM50V

402

2

1 C55010.0022UF

50VCERM

10%

402

2

1 C55110.0022UF

402

10%

CERM50V

2

1 C5512

402CERM50V10%0.0022UF

2

1 C55130.0022UF

402

10%

CERM50V

2

1 C5514MXM

0.0022UF

50VCERM

10%

402

2

1

4

3

J5510SILK_PART=ODD TEMP

CRITICAL

M-RT-SM53780-8602

21

L5530

0402

FERR-1000-OHM

21

L5531

0402

FERR-1000-OHM

2

1

4

3

J5521

CRITICAL

53398-8602M-ST-SM

SILK_PART=CPU HSK

2

1

4

3

J5550M-RT-SM

53261-8602

CRITICAL

SILK_PART=LCD TEMPDEVELOPMENT

SYNC_DATE=01/06/2011SYNC_MASTER=K60_MARK

TEMP SENSORS

SNS_T1_5_P

SNS_SKIN_LEFT_N

SNS_AMB_P

SNS_T1_1_N

SNS_SKIN_RIGHT_N

SNS_T1_3_N

SNS_T1_5_N

SNS_MXM_NSNS_MXM_P

SNS_SKIN_RIGHT_P

SNS_T1_3_N

SNS_T1_7_P

SNS_T1_5_P

SNS_T1_1_P

=SMB_SNS1_SDA

=SMB_SNS1_SCL

SNS_T1_2_P

SNS_T1_5_N

SNS_T1_7_N

SNS_T1_6_N

SNS_T1_4_P

SNS_T1_4_N

SNS_T1_TRIPSET

SNS_T1_6_N

SNS_T1_6_P

SNS_SKIN_LEFT_P

SNS_T1_7_N

SNS_LCD_H_PSNS_LCD_H_N

SNS_T1_2_P

SNS_T1_2_N

SNS_T1_3_P

SNS_CPU_H_N

SNS_T2_DP2

=SMB_SNS1_SCL

SNS_T2_ALERT_L

SNS_T2_ADDR

=SMB_SNS1_SDA

SNS_T1_3_P

SNS_T1_4_N

SNS_T1_2_N

SNS_ODD_N

SNS_T1_1_PSNS_T1_1_N

SNS_CPU_THERMD_P

SNS_CPU_THERMD_N

SNS_CPU_H_P

SNS_T1_6_P

SNS_T1_4_P

=PP3V3_S0_SENSE

SNS_T1_ADDR

=PP3V3_S0_SENSE

SNS_T1_ALERT_L

SNS_T2_DN2

SNS_ODD_P

SNS_AMB_N

SNS_T1_7_P

55 OF 110

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051-8115

52 OF 98

13

52 94

44 94 98

54 94 98

52 94

94 98

52 94

52 94

94

94

94 98

52 94

52 94

52 94

52 94

52 94

52 94

52 94

52 94

52 94

52 94

52 94

52 94

44 94 98

52 94

94

94

52 94

52 94

52 94

94

94

52 94

52 94

52 94

94 98

52 94

52 94

10 94

10 94

94

52 94

52 94

6 50 52

6 50 52

94

94 98

54 94 98

52 94

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8 7 5 4 2 1

HD FAN

ODD FAN

NOTE: ADDED TO PROTECT SMC

FAN 1

518S0730

12V DC

GND

FAN 0

TACH

MOTOR CONTROL

C5605 IS POLY-TANT BECAUSE IT MUST BE PLACED ON THE BOTTOM

12V DC

MOTOR CONTROL

TACH

GND

518S0730

2

1R5600

402MF-LF1/16W

10K5%

2

1R5601

402

1/16W

10K5%

MF-LF

2

1R5602

1206MF-LF1/4W

1.5K5%

5

4

876321

Q5600

1206A-03-HFNTHS5443T1H

CRITICAL2

1R56031.5K

MF-LF1/8W

5%

805

3

1

D5600

SOT23

MMBD914XG

2

1C5601

X7R

10%16V

805

0.47UF

21

R5605

805

1/8WMF-LF

3.9K

5%

2

1R56065%

402

10K1/16WMF-LF

5

4

876321

Q5603NTHS5443T1H1206A-03-HF

CRITICAL2

1R56071/8W

1.5K5%

MF-LF805

2

1C56030.47UF

10%

805X7R16V

21

R5609

805

5%1/8WMF-LF

3.9K

3

1

D5601

SOT23

MMBD914XG

2

1R56101/4W

1206

5%

MF-LF

1.5K

2

1R561110K

MF-LF402

5%1/16W

21

R5699

402

1/16W

47K

5%

MF-LF

21

R569847K

5%1/16WMF-LF402

2

1

3

Q56022N7002SOT23-HF1

2

1

3

Q56052N7002SOT23-HF1

2

1 C5602100UF

6.3X5.5-SM1-HFELEC16V

CRITICAL

20%

4

3

2

1

6

5

J5601M-RT-SM

53780-8604

CRITICAL

4

3

2

1

6

5

J5600CRITICAL

M-RT-SM53780-8604

2

1 C56070.01UF16VCERM

20%

4022

1 C560620%

CERM1206-1

16V

4.7UF

2

1 C560916V20%0.01UF

402CERM2

1C56082.2UF

16V10%

603X5R

21

L5600

0402

CRITICAL

FERR-220-OHM

21

L5601CRITICAL

0402

FERR-220-OHM

21

L5610220-OHM-1.4A

CRITICAL

0603

21

L5620220-OHM-1.4A

0603

CRITICAL

21

L5630

0603

220-OHM-1.4A

CRITICAL

21

L5640CRITICAL

0603

220-OHM-1.4A

2

1R5620

MF-LF1/10W5%0

603

PLACEMENT_NOTE=PLACE R5620 CLOSE TO J5600 Pin3

2

1R5630


5%1/10WMF-LF603

0

2

1 C5628

X5R603

2.2UF10%16V

2

1 C5605

TANT16V20%100UF

D-HF

CRITICAL


HD AND OD FAN

FAN_TACH1_L

VOLTAGE=12V

MIN_LINE_WIDTH=0.5MMPP12V_S0_FAN1_LMIN_NECK_WIDTH=0.25MM

MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MMFAN_1_GND


FAN_1_PWR_L

VOLTAGE=12V

MIN_LINE_WIDTH=0.5MMPP12V_S0_FAN0_L


FAN_TACH0_L

=PP3V3_S0_FANF0_GATESLOWDN

FAN_0_PWRMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM

F0_VOLTAGE8R5


FAN_0_PWR_L

FAN_0_GNDMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM

=PP3V3_S0_FAN

FAN_TACH0SMC_FAN_0_TACH

SMC_FAN_0_CTL


FAN_1_PWR

F1_GATESLOWDN

FAN_TACH1

=PP3V3_S0_FAN

SMC_FAN_1_TACH

=PP12V_S0_FAN

F1_VOLTAGE8R5

=PP12V_S0_FAN

SMC_FAN_1_CTL

=PP3V3_S0_FAN

56 OF 110

11.1.0

051-8115

53 OF 98

98

95 98

98

98

95 98

98

6 53 54

98

98

6 53 54

46

46

6 53 54

46

6 53 54

6 53 54

46

6 53 54

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PAGE


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C

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8 7 5 4 2 1

FAN 3 SMC CONTROL (UNUSED)

SMC’S FAN3 OUTPUT CONTROL FAN 2

12V DC

GND

TACH

MOTOR CONTROL

518S0778

CPU FAN

2

1

3

Q5702SOT23-HF12N7002

2

1 C5702100UF20%16VELEC6.3X5.5-SM1-HFCRITICAL

2

1 C5708

1206-1CERM16V20%4.7UF

2

1 C570920%16V

0.01UF

CERM402

21

L5701CRITICAL

FERR-220-OHM

0402

21

L5710

0603

220-OHM-1.4A

CRITICAL

21

L5720

0603

220-OHM-1.4A

CRITICAL

2

1 R5720

MF-LF

05%1/10W

603


6

5

4

3

2

1

8

7

J5700

CRITICAL

M-RT-SM53780-8606

2

1R57001/16WMF-LF402

5%10K

5

4

876321

Q5700NTHS5443T1H1206A-03-HF

CRITICAL

3

1

D5700SOT23

MMBD914XG

2

1R5701

1/8W

805

5%1.5K

MF-LF

2

1C57010.47UF

10%16VX7R805

21

R5703

1/8W5%

3.9K

MF-LF805

2

1R57045%1/4W

1.5K

1206MF-LF

2

1R5705

MF-LF

10K

402

5%1/16W

21

R579747K

5%1/16WMF-LF402

CPU FANSYNC_DATE=01/06/2011SYNC_MASTER=K60_JERRY

SNS_AMB_NSNS_AMB_P

FAN_2_PWR_L


FAN_TACH2_L

VOLTAGE=12V

PP12V_S0_FAN2_LMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM


FAN_2_GND

MIN_NECK_WIDTH=0.25MMFAN_TACH2

F2_GATESLOWDN

SMC_FAN_3_TACH

F2_VOLTAGE8R5

=PP12V_S0_FAN

FAN_2_PWRMIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MM

=PP3V3_S0_FAN

=PP3V3_S0_FAN

SMC_FAN_3_CTL

57 OF 110

11.1.0

051-8115

54 OF 98

52 94 98

52 94 98

98

98

95 98

98

46

6 53

6 53 54

6 53 54

46

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OUTIN

IN IN

WP*

SI

HOLD*VSS

SCK

CE*

VDD

SO




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8 7 5 4 2 1

2

1C6100

10%1UF

6.3V

402CERM

2

1R6101

5%

402

3.3K

1/16WMF-LF

2

1R6100

1/16W5%

MF-LF

3.3K

402

18 48 91 48 91

18 48 91 18 48 91

21

R610533

MF-LF

5%1/16W

402

21

R615233

402

1/16W5%

MF-LF

PLACEMENT_NOTE=PLACE CLOSE TO U6100

21

R6150

1/16W

402

5%

MF-LF

PLACEMENT_NOTE=PLACE CLOSE TO U6100

33

3

48

2

56

7

1

U6100

SOIC

CRITICAL

OMIT

64MBIT

SST25VF064C


SPI ROMSYNC_MASTER=K62

SPI_WP_L

SPI_HOLD_L

SPI_MOSI

SPI_MISO_R

SPI_CLKSPI_CLK_R SPI_MOSI_R

SPI_MISOSPI_MLB_CS_L

=PP3V3_S5_ROM

61 OF 110

11.1.0

051-8115

55 OF 98

91

91

91

6 48

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IN

IN

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

OUT

NR/FB

NC

IN

EN

GND

OUT

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

L2L1

IN

IN

OUT

GND

SHDN*/SS FB

SWIN

SYM VER 2

/SPDIF_OUT2

VL_HD

SENSE_A

GPIO1/DMIC_SDA2

GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REFVD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYC

FLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+

MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDI

SDO

VL_IF

BITCLK

MICIN_R-

MICIN_R+

VREF+_ADC

LINEOUT_L2+

LINEOUT_L2-

LINEOUT_R2+

TABLE_ALT_ITEM


TABLE_ALT_HEAD




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8 7 5 4 2 1

PLACE XWS 6202 & 6203 NEAR PINS 35 & 36

ISOLATED 5 V POWER SUPPLY FOR HP AMP

SE FSINPUT= 1.22VRMSDIFF FSINPUT= 2.45VRMS

APPLE P/N 353S2592AUDIO CODEC PLACE C6200 AS CLOSE TO PIN 9 AS POSSIBLE

APN 353S3080

4.5V POWER SUPPLY FOR CODEC

NC

HP AMP

APPLE P/N 353S2456

WOOFERS

TWEETERS

HP AMP/LINE OUT

VD MUST BE LESS THAN OR EQUAL TO VL_HD

NC

DAC1 FSOUTPUT= 1.34VRMSDAC2/3 FSOUTPUTDIFF= 2.67VRMSDAC2/3 FSOUTPUTSE= 1.34VRMS

APN 128S0271

APN 152S1314

PLACE TP FOR ALL HDA SIGNALS NEAR CODEC

SPEAKERS

NC

NC

NC

NC

PLACE XWS 6200 & 6201 NEAR PINS 38 & 40

2

1C6211

402-LF

6.3V20%

CERM

2.2UF

2

1 C62122.2UF

CERM402-LF

20%6.3V

18 91

18 91

18 91

15 18 91

18 91

61

58

59 62

58 62

57 62

57 62

59 62

58 62

57

57

62

62

57

21

L6210FERR-220-OHM

0402

2

1 C622110%

NOSTUFF

1UF10V

402-1X5R

2

1 C6204

402

0.47UF10VX5R

10%

2

1 C6200

402

0.47UF10%

X5R10V

2

1C62060.47UF

10%10VX5R402

2

1R6200

MF-LF

1%1/16W

2.67K

402

21

R6201

1/16W

22

5%

402MF-LF

2

1C6202

10V10%

X5R

0.47UF

402

2

1 C621410UF

CASE-B2-SM

16V

CRITICAL

20%

POLY-TANT

2

1 C6203

CASE-B2-SMPOLY-TANT16V20%10UF2

1C620810UF

20%

CASE-B2-SMPOLY-TANT

16V

6 56

6 56

56 61 95

56 61 95

56 61 95

6 58 59 60 61 62

56 95

2

1C620510%

402-1X5R10V

1UF

1

3

6

2

4

VR6201

CRITICAL

SONTPS71745

2

1C6223

402

0.1UF10%

X7R-CERM16V

21

R6202

1/16WMF-LF

22

402

5%

60 91

83 97

2

1R6203

MF-LF1/16W

402

1%100K

2

1 C62221UF

402-1

10%

X5R10V 2

1 C6224

10VX5R

10%1UF

402-1

2

1C621310%

CRITICAL

1UF20VTANT

CASE-P3-HF

56 95

2

1 C6207

0402-1

20%10UF

CERM-X5R6.3V

CRITICAL

21

XW6211

SM

21

R6210

MF-LF603

5%

0

1/10W

2

1C6250

603

20%

X5R10V

10UF

6 56

2

1R6252

402

12.4K

MF-LF1/16W1%

2

1C6253NOSTUFF

1UF10%

X5R10V

402-12

1C6252

X7R-CERM

10%0.1UF

16V

402

2

1R62501%

MF-LF402

1/16W

40.2K

2

1 C6251

X7R-CERM

0.1UF16V10%

402

2 1

D6251

BAT54XV2T1

SOD-523

2

1

D6250SOD-523BAT54XV2T1

5

6

1

Q6250DMMT3906W-7-F

CRITICAL

SOT-363

43

2

Q6250SOT-363

DMMT3906W-7-F

CRITICAL

2

1C62540.01UF

16VCERM

10%

4022

1C62550.001UF

50VX7R402

10%

21

R6212

402

1/16W5%

MF-LF

NOSTUFF

0

21

D6252DO222-SM

STPS1L30MF

2

1 C625910UF

603X5R10V20%

2

1C62570.1UF

X7R-CERM402

10%16V

2

1R62581%

MF-LF402

1/16W

1K

NOSTUFF

2

1R6255

1/10W1%

603

1.0K

MF-LF2

1C625610%1UF25VX5R402

CRITICAL

2

1R6254

603

1%20

1/10WMF-LF

2

1 C626110%0.001UF

NOSTUFF

402X7R50V

2

1R6259100K1%

NOSTUFF

1/16W

402MF-LF

2

1R6257

603

1/10W1%4.99K

MF-LF

21

R6260

1%

603MF-LF1/10W

10

2

1C62092.2UF6.3V20%

402-LFCERM 2

1 C6210

CERM6.3V20%

2.2UF

402-LF

57

21

L6212

0402

NOSTUFF

FERR-220-OHM

21

XW6200

SM

59 62

58 62 21

XW6201

SM

21

XW6203

SM

59 62

58 62

21

XW6202

SM

2

1R620505%1/16W

402MF-LF

57 62

57 62

4

3

2

1

T62501.8UH-1.6A-243MOHM

LPD3015-SM

CRITICAL

21

R6213

1/10WMF-LF603

0

5%

2

1C625820%

TANT6.3V

150UF-.025-OHM

CASE-B2-SM

CRITICAL

21

XW6212

SM

61 62

61 62

21

R6253

MF-LF1/16W

402

43.2K

1%

2

1R62513.40K1%

MF-LF402

1/16W

2

1R62561%1/16WMF-LF

49.9K

402

61

21

R62200

MF-LF

5%1/16W

402

2

1C6201

4VX5R-1

402

4.7UF20%

1

4

5

2

3

U6250

TSOT-23SC4503

CRITICAL

27

1

3

44

41

9

28

29

24

46

25

49

10

48

47

13

5

8

1119

20

18

17

16

32

33

36

37

31

30

35

34

23

21

22

39

40

38

15

14

12

2

45

42

43

4

7

6

26

U6201CS4206B

QFN

CRITICAL


AUDIO: CODEC/REGULATORSYNC_MASTER=K60_DAVID

353S2592 U6201 CS4206A353S3199

GND_AUDIO_CODEC

SC4503_FB_RDIV SC4503_FB_PNP SC4503_FB_FILT SC4503_SW_D

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MMAUD_XFRMR_SEC

GND_AUDIO_ISO

VOLTAGE=0VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.5MM

GND_AUDIO_ISO

PP5V_AUDIO_ISO




4V5_NR

AUD_LO2_L_N

GND_AUDIO_CODEC

PP4V5_AUDIO_ANALOGGND_AUDIO_HPAMP

HDA_SDIN0

AUD_HP_R_N

AUD_HP_L_N

GND_AUDIO_HPAMP

GND_AUDIO_HPAMP

AUD_SPDIF_OUT

VOLTAGE=4.5V

4V5_OUT



SC4503_SW_SNBR

PP5V_LAMP_VREG

=PP5V_S0_AUDIO

VOLTAGE=0VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.5MMGND_AUDIO_CODEC


PP5V_AUDIO_HPAMP


4V5_REG_IN PP4V5_AUDIO_ANALOGVOLTAGE=4.5V


4V5_REG_EN

=PP5V_S0_AUDIO

GND_AUDIO_HPAMPMIN_LINE_WIDTH=0.2MM


SC4503_SW

AUD_LO2_R_N

=PP5V_S0_AUDIO


SC4503_SW

SC4503_FB


SC4503_SHDN_L

SC4503_FB_DDROP

AUD_LO2_R_P

AUD_LO2_L_P

MIN_LINE_WIDTH=0.20MMCS4206_VREF_ADCMIN_NECK_WIDTH=0.15MM

AUD_MIC_INR_PAUD_MIC_INR_N

HDA_BIT_CLK

HDA_SDOUT

AUD_SDI_R

TP_CS4206_DMIC_SCL

HDA_SYNC

AUD_CODEC_MICBIAS

AUD_MIC_INN_LAUD_MIC_INP_L

AUD_LI_P_L

AUD_LI_P_R

GND_AUDIO_CODEC

MIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.20MMCS4206_VCOM

AUD_HP_R_PMIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.1MM

GND_AUDIO_HPAMP

AUD_LO1_L_P

AUD_SPDIF_IN_CODEC

CS4206_FLYN

CS4206_FLYC

AUD_LI_COM

AUD_SPDIF_CHIP

AUD_LO1_R_PAUD_LO1_R_N

CS4206_FN

AUD_GPIO_3

CS4206_FLYP

VBIAS_DAC

HDA_RST_L

AUD_GPIO_2

CS4206_FP

TP_AUD_DMIC_SDA1TP_AUD_GPIO_1

AUD_SENSE_A

=PP3V3_S0_AUDIO=PP1V5_S0_AUD_DIG

PP5V_AUDIO_HPAMP

PP4V5_AUDIO_ANALOG

MIN_NECK_WIDTH=0.1MM AUD_HP_L_PMIN_LINE_WIDTH=0.1MM

AUD_HP_PORT_REFMIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM

AUD_LO1_L_N

TP_AUD_LO2_N_L

TP_AUD_LO2_N_R

62 OF 110

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5

56 57 60 61 62

56 57 60 62

56 57 60 62

57 61

56 57 60 61 62

56

56

56

59 95

56 57 60 61 62

95

97

56

56

56

91

56 57 60 61 62

56

91

6

www.vinafix.vn

PGND

SGND

PVSS

THM_PAD

PVDD

SVDD

BIAS

OUTL

OUTR

C1P

C1N

SVDD2

INL-

INL+

INR-

INR+

SHDN*

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL

R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL

FC = 3.62 HZ

NET RIN = 18K OHMSVIN = 2VRMS, CODEC VIN = 1.14 VRMS

CODEC Nom SE RIN = 20K OHMS

2

1 C63541UF10%10VX5R402-1

2

1C6352

402-1X5R10V10%1UF

2

1 C6356

X5R10V10%1UF

402-12

1 C63551UF10%10VX5R402-1

2

1 C6351

10V20%10UF

603X5R2

1C6350

X7R-CERM402

16V10%

0.1UF

17

913

16

6 5

1

3

10

12

7

8

15

14

2

4

11U6350TQFN

CRITICAL

MAX97220AETE

21

L6350FERR-220-OHM

0402

2

1R6350

1/16WMF-LF

402

5%100K

56 62

56 62

56 62

56 62

57 62

57 62

57 62

57 62

56

57 62

57 62

57 60

57 62

57 62

57 60

57 60

57 60

2

1 C6353

10V10%1UF

X5R402-1

21

R63650

1/16W5%

402MF-LF

21

C6361CRITICAL

33UF

CASE-ATANT6.3V20%

21

C636333UF

CRITICAL

CASE-ATANT6.3V20%

21

C6373CRITICAL

20%6.3VTANTCASE-A

33UF

21

C6371

20%6.3VTANTCASE-A

33UF

CRITICAL

21

C6362SIGNAL_MODEL=EMPTY

220PF

402CERM25V5%

2

1 C6364SIGNAL_MODEL=EMPTY

220PF

402CERM25V5%

2


220PF

402CERM25V5%

21

C6372

SIGNAL_MODEL=EMPTY

220PF

402CERM25V5%

2 1

C6300

20%10VTANT

SM-HF-PL

22UF

CRITICAL

2 1

C6302

SM-HF-PL

20%10VTANT

22UF

CRITICAL

2 1

C6303CRITICAL

22UF

SM-HF-PLTANT10V20%

56

56

56

60

60

56 60 61 62

60

21

R6300

1/16WMF-LF402

1%

7.87K

2

1R6301

MF-LF402

1/16W1%

21.5K

2

1 C6301

402

10%50VCERM

NOSTUFF

820PF

2

1R63031%1/16WMF-LF

10

402

21

R6306

1%

7.87K

402

1/16WMF-LF

2

1 C6304

402

NOSTUFF

820PF10%50VCERM

2

1R6305

MF-LF1/16W

1%21.5K

402

21

R6361

1%

402

1/16WMF-LF

10K

21

R6363

1%

MF-LF402

10K

1/16W

21

R6373

1%1/16W

402MF-LF

10K

21

R6371

MF-LF1/16W

402

10K

1%

2


1%1/16W

402

7.87K

MF-LF

2


402MF-LF1/16W

1%7.87K

21

R6362

SIGNAL_MODEL=EMPTY

7.87K

1%

402

1/16WMF-LF

21

R6372

1%

402

1/16W

7.87K

MF-LF

SIGNAL_MODEL=EMPTY

AUDIO: FILTER/BUFFERSYNC_DATE=01/06/2011SYNC_MASTER=K60_DAVID

AUD_LI_P_R

MIN_NECK_WIDTH=.2MMMIN_LINE_WIDTH=.3MM


AUD_LI_RF


AUD_LI_COM


AUD_LI_GND

AUD_LI_P_L


AUD_LI_LF

MIN_LINE_WIDTH=.3MMMIN_NECK_WIDTH=.2MM


AUD_LI_R

MAX97220_SGND

MAX97220_INR_P

MAX97220_INL_P

MAX97220_INL_N

MAX97220_OUTL

MAX97220_INR_N

MAX97220_OUTR PP5V_AUDIO_ISO

MAX97220_INL_P

AUD_GPIO_2

MAX97220_INL_N

GND_AUDIO_ISO


MAX97220_OUTR

MAX97220_OUTLMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM

GND_AUDIO_ISO

MAX97220_C1NMIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.2MM

GND_AUDIO_CODEC


AUD_LI_L



MAX97220_PVSS

VOLTAGE=0V

MAX97220_INR_N

MIN_NECK_WIDTH=0.2MMMAX97220_C1P


GND_AUDIO_ISO

MAX97220_SHDN_L

MAX97220_INR_P


MAX97220_BIAS

AUD_LO1_R_C_NAUD_LO1_R_N

AUD_LO1_R_C_PAUD_LO1_R_P

AUD_LO1_L_C_PAUD_LO1_L_P

AUD_LO1_L_C_NAUD_LO1_L_N

GND_AUDIO_ISO

63 OF 110

11.1.0

051-8115

57 OF 98

56 61

56 57 60 62 56 57 60 62

56 57 60 62

62

62

62

62

56 57 60 62

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IN

REG_OUT

PLIMIT

FSEL

SD*

PVCCL

AGND

PGND

THRM

GAIN1

GAIN0

LINP

LINN

RINN

RINP

AVCC

NC

PVCCR

OUTNL

OUTPL

BSNL

BSPL

BSNR

OUTNR

OUTPR

BSPR

PBTL

PAD

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

FC_HPF, WOOFERS = ~22.5 HZ (0.068 UF)FC_HPF, TWEETERS = ~850 HZ (0.0018 UF)SPEAKER AMP RIN = 104K NOMINAL W/ +15.2 DB GAINSPEAKER AMP GAIN = +15.2 DBR6402 = HIGH = 400 KHZ

APPLE P/N 353S3069RIGHT CH SPEAKER AMP

21

R6400

MF-LF402

1/16W5%

0

6 59

21

L6404

SIGNAL_MODEL=EMPTY

CRITICAL

220-OHM-25%-2.5A

0603

21

L6405

SIGNAL_MODEL=EMPTY

0603

CRITICAL

220-OHM-25%-2.5A

21

L6406CRITICAL

SIGNAL_MODEL=EMPTY

220-OHM-25%-2.5A

0603

21

L6407

SIGNAL_MODEL=EMPTY

220-OHM-25%-2.5A

0603

CRITICAL

33

30

9

8

6

15

14

27

26

7

23

18

11

17

24

19

22

10

29

28

13

12

32

1

3

2

31

16

25

20

21

45

U6400

CRITICALQFN

TPA3117D2

2

1 C6421 SIGNAL_MODEL=EMPTY

NP0-C0G25V5%1000PF

CRITICAL

4022


25VNP0-C0G402

1000PF5%

CRITICAL

2

1C6420SIGNAL_MODEL=EMPTY

5%1000PF

402NP0-C0G

25V

CRITICAL

2

1C6422 SIGNAL_MODEL=EMPTY

5%1000PF

402NP0-C0G

25V

CRITICAL

2

1R6401

MF-LF1/16W

5%100K

4022

1 C64125%100PF

CERM50V

402

NOSTUFF

21

R6408

1%

MF-LF

10

1/16W

402

21

C6415

603

20%25VX5R

0.22UF

2

1 C641720%

402X5R-CERM10V

2.2UF

21

R6409

5%

402MF-LF1/16W

0

2

1R64101%

402MF-LF1/16W

10K

NOSTUFF

2

1C6406

16VTANTD-HF

20%

CRITICAL

100UF2

1 C640720%100UF

D-HFTANT16V

CRITICAL

56 62

56 62

2

1R640605%1/16WMF-LF402

2

1R6407NOSTUFF

05%1/16WMF-LF402

2

1R6404

402MF-LF1/16W

5%0

NOSTUFF

2

1R6405

402MF-LF1/16W

5%0

2

1R6402

MF-LF402

1/16W

05%

2

1R640305%1/16WMF-LF402

21

C64080.0018UF

50V

402

10%

CERM

21

C6409

CERM

0.0018UF

50V

402

10%

21

C6416

25VX5R

0.22UF

603

20%

21

C6411

X5R0402

25V10%

0.068UF

21

C6410

X5R25V10%

0402

0.068UF

21

C6413

25VX5R

20%

603

0.22UF

21

C6414

603X5R

0.22UF

20%25V

2

1 C64010.1UF10%

X5R25V

4022

1C6400

25VX5R

10%

805

10UF

21

L6400FERR-1000-OHM

0402

2

1C64040.1UF

402X5R

10%25V

21

L6401

0402

FERR-1000-OHM

21

L6402FERR-1000-OHM

0402

21

L6403

0402

FERR-1000-OHM

2

1C64020.1UF

10%

402X5R25V 2

1 C640310%

X5R25V

603-1

1UF

2

1 C6405

603-1

1UF10%

X5R25V

56 62

56 62

56

60 62

60 62

60 62

60 62

59

2

1 C641810%10VX5R402

1UF


AUDIO: SPEAKER AMP_1SYNC_MASTER=K60_DAVID


AUD_RAMP_OUTNLMIN_LINE_WIDTH=0.6MM

AUD_RAMP_OUTPL


AUD_RAMP_GAIN1


AUD_RAMP_RINC_P AUD_RAMP_RIN_P

AUD_RAMP_RINC_N AUD_RAMP_RIN_N

AUD_RAMP_LINC_N AUD_RAMP_LIN_N

AUD_RAMP_LINC_P AUD_RAMP_LIN_P

AUD_RAMP_FSEL

AUD_SPKR_RWFR_OUT_P

AUD_SPKR_RWFR_OUT_N

AUD_RAMP_BSPRMIN_LINE_WIDTH=0.20MMMIN_NECK_WIDTH=0.15MM

AUD_RAMP_GAIN0

AUD_RAMP_OUTPR


AUD_LO2_R_N

AUD_HP_R_N

AUD_LO2_R_P

AUD_SPKRAMP_MUTE_L

AUD_RAMP_PBTL


AUD_RAMP_REG_OUT

=PP3V3_S0_AUDIO

VOLTAGE=5VPP5V_RAMP_VREG

AUD_GPIO_3

AUD_SPKR_RTWT_OUT_N

MIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.20MMAUD_RAMP_BSPL

MIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.20MMAUD_RAMP_BSNL

AUD_SPKR_RTWT_OUT_PAUD_RAMP_PLIMIT

MIN_LINE_WIDTH=0.6MMAUD_RAMP_OUTNR


MIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.20MMAUD_RAMP_BSNR

AUD_HP_R_P

64 OF 110

11.1.0

051-8115

58 OF 98

62 62

62 62

62 62

62 62

6 56 59 60 61 62

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IN

REG_OUT

PLIMIT

FSEL

SD*

PVCCL

AGND

PGND

THRM

GAIN1

GAIN0

LINP

LINN

RINN

RINP

AVCC

NC

PVCCR

OUTNL

OUTPL

BSNL

BSPL

BSNR

OUTNR

OUTPR

BSPR

PBTL

PAD

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

LEFT CH SPEAKER AMPAPPLE P/N 353S3069

SPEAKER AMP RIN = 104K NOMINAL W/ +15.2 DB GAINSPEAKER AMP GAIN = +15.2 DBR6502 = LOW = 300 KHZ

FC_HPF, TWEETERS = ~850 HZ (0.0018 UF)FC_HPF, WOOFERS = ~22.5 HZ (0.068 UF)

21

L6501

0402

FERR-1000-OHM

21

L6500

0402

FERR-1000-OHM

2

1 C65172.2UF10V

402

20%

X5R-CERM

21

R65090

1/16WMF-LF

5%

402

2

1R6510

MF-LF

1%

402

10K1/16W

NOSTUFF

2

1 C6518

402X5R10V10%1UF

21

R650810

1%1/16WMF-LF402

6 58

2

1C650010UF

10%

805X5R25V 2

1 C65010.1UF25VX5R

10%

402

33

30

9

8

6

15

14

27

26

7

23

18

11

17

24

19

22

10

29

28

13

12

32

1

3

2

31

16

25

20

21

45

U6500

CRITICAL

TPA3117D2QFN

21

C65160.22UF

20%

X5R25V

603

21

C65150.22UF

X5R25V20%

603

21

C6514

25V

0.22UF

X5R603

20%

21

C6513

603

20%

X5R25V

0.22UF

21

L6506

0603

CRITICAL

220-OHM-25%-2.5A

SIGNAL_MODEL=EMPTY

56 62

21

L6507

0603

CRITICAL

SIGNAL_MODEL=EMPTY

220-OHM-25%-2.5A

2

1 C6519CRITICAL

5%1000PF

402NP0-C0G25V

SIGNAL_MODEL=EMPTY

21

L6504

0603

220-OHM-25%-2.5A

CRITICAL

SIGNAL_MODEL=EMPTY

21

L6505

0603

CRITICAL

220-OHM-25%-2.5A

SIGNAL_MODEL=EMPTY

2

1C6520CRITICAL

25VNP0-C0G

402

1000PF5%

SIGNAL_MODEL=EMPTY

2

1 C6521

402

CRITICAL

1000PF5%25VNP0-C0G

SIGNAL_MODEL=EMPTY

2

1C6522

25VNP0-C0G

402

1000PF5%

CRITICALSIGNAL_MODEL=EMPTY

2

1C6502

X5R

0.1UF25V

402

10%2

1 C6503

25VX5R

10%

603-1

1UF

2

1C6504

25V10%

X5R402

0.1UF

56 62

2

1 C6505

X5R25V10%1UF

603-1

60 62

60 62

60 62

60 62

58

2

1 C6507100UF

D-HFTANT16V

CRITICAL

20%2

1C650620%

100UF

D-HF

16V

CRITICAL

TANT

56 62

56 62

2

1R650305%1/16WMF-LF402

2

1R6507NOSTUFF

05%1/16W

402MF-LF

2

1R6505

402

5%0

1/16WMF-LF

2

1R650605%1/16WMF-LF4022

1R6504

402MF-LF1/16W

5%0

NOSTUFF

2

1R65025%

MF-LF402

01/16W

21

C65080.0018UF

402CERM50V10%

21

C6509

10%50VCERM402

0.0018UF

21

C6511

10%

0402X5R25V

0.068UF

21

C6510

0402

10%25V

0.068UF

X5R

21

L6503FERR-1000-OHM

0402

21

L6502FERR-1000-OHM

0402

SYNC_DATE=01/06/2011SYNC_MASTER=K60_DAVID

AUDIO: SPEAKER AMP

AUD_HP_L_P


AUD_LAMP_OUTPR

AUD_LO2_L_N

AUD_HP_L_N

AUD_LO2_L_P

AUD_LAMP_REG_OUT


MIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.20MMAUD_LAMP_BSPL

AUD_LAMP_GAIN1

=PP3V3_S0_AUDIO

AUD_LAMP_BSNRMIN_LINE_WIDTH=0.20MMMIN_NECK_WIDTH=0.15MM

AUD_LAMP_FSEL

AUD_SPKR_LTWT_OUT_N

AUD_SPKR_LTWT_OUT_P

AUD_SPKR_LWFR_OUT_N

AUD_SPKR_LWFR_OUT_P

AUD_LAMP_GAIN0



AUD_LAMP_OUTNR

AUD_LAMP_BSNLMIN_LINE_WIDTH=0.20MMMIN_NECK_WIDTH=0.15MM

AUD_LAMP_PBTL

AUD_LAMP_OUTPLMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.25MM

AUD_LAMP_OUTNL


AUD_LAMP_PLIMIT

AUD_SPKRAMP_MUTE_L

VOLTAGE=5VPP5V_LAMP_VREG

AUD_LAMP_LIN_PAUD_LAMP_LINC_P

AUD_LAMP_LINC_N

AUD_LAMP_RINC_N

AUD_LAMP_RINC_P

MIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.20MMAUD_LAMP_BSPR

AUD_LAMP_LIN_N

AUD_LAMP_RIN_N

AUD_LAMP_RIN_P

65 OF 110

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051-8115

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IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT




36

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DRAWING NUMBER SIZE

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PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

INTERNAL MIC CONAPPLE P/N 518S0677

WOOFER (BR)

TWEETER (FR)

APPLE P/N 518S0656APPLE P/N 518S0748

SPEAKER CABLE CONNECTORS

PROPERTIES FOR ALL SPKR NETS

APPLE P/N 518S0723

REMOTE I/O CONNECTOR

AUD_LI_GND_JACK

AUD_HP_GND_JACK

PP3V3_AUDIO_SPDIF_JACK

PROPERTIES FOR ALL SPKR NETS

WOOFER (BL)

TWEETER (FL)

NC

21

L6604

0402

FERR-1000-OHM

2

1

DZ66056.8V-100PF402

CRITICAL 2

1

DZ6609402

CRITICAL

6.8V-100PF

21

L6614

0402

FERR-1000-OHM

2

1

DZ66076.8V-100PF402

CRITICAL56 91

61

6 56 58 59 61 62

58 62

58 62

58 62

58 62

59 62

59 62

59 62

59 62

2

1 C6601

10VX5R

10%0.47UF

402

21

L6607

0402

FERR-1000-OHM

57

21

L6608

0402

FERR-1000-OHM

57

21

L6609

0402

FERR-1000-OHM

56 57 61 62

62

56 57 62

61 62

2

1

DZ66126.8V-100PF

402

CRITICAL2

1

DZ6610CRITICAL

4026.8V-100PF

2

1

DZ6603CRITICAL

6.8V-100PF402

2

1C6600

10VX5R

1UF10%

402-1

21

L6615

0402

FERR-1000-OHM

21

L6605FERR-1000-OHM

0402

21

R6601

1/16W

402MF-LF

22

5%

83 91 97

61

21

L6606FERR-1000-OHM

0402

21

L6612FERR-1000-OHM

0402

61

57

21

R6617

1/10W5%

0

603MF-LF

5

4

3

2

1

J6603M-RT-SM

78048-0573

CRITICAL

4

3

2

1

J6602M-RT-SM

78048-0473

CRITICAL

21

L661010-OHM-1A

0402

CRITICAL

2

1

DZ6606SOD882

CRITICAL

ESDALC5-1BM2

9

8

7

6

5

4

3

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J6600F-RT-SM

20143-020E-20F

CRITICAL

57

57

61 62

61 62

21

L6602FERR-1000-OHM

0402

2

1

DZ6600SIGNAL_MODEL=EMPTY

CRITICAL

4026.8V-100PF

2

1

DZ6601CRITICAL

SIGNAL_MODEL=EMPTY

6.8V-100PF402

2

1R66000

402

1/16WMF-LF

5%

3

2

1

5

4

J660153780-8603

CRITICAL

M-RT-SM

21

L6600FERR-1000-OHM

0402

21


0402

CRITICAL

21


CRITICAL

0402

2

1C6604

402CERM16V10%

0.01UF2

1C6608

CERM16V10%

0.01UF

402

2

1 C66110.01UF10%16VCERM402 2

1 C66130.01UF10%16VCERM402

2

1 C66150.01UF10%16VCERM402

2

1C6614

402CERM16V10%

0.01UF

SYNC_DATE=01/06/2011SYNC_MASTER=K60_DAVID

Audio: MLB to I/O Conn.

MAX97220_OUTR

MAX97220_OUTL

AUD_MIC1_IN_N AUD_SPKR_RWFR_OUT_N

AUD_SPKR_LWFR_OUT_P

AUD_SPKR_LWFR_OUT_N

NO_TEST NC_J6702_3AUD_SPKR_LTWT_OUT_P

AUD_SPKR_LTWT_OUT_N

AUD_SPKR_RTWT_OUT_P

AUD_SPKR_RWFR_OUT_P

AUD_SPDIF_IN

MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MMAUD_LI_GND

=PP3V3_S0_AUDIO

MIN_NECK_WIDTH=0.1MMAUD_IP_PERPH_DET


AUD_LI_TIP_DET

AUD_SPKR_RTWT_OUT_N

AUD_HP_TYPE


AUD_MIC1_IN_P

AUD_MIC_IN1_CONN_N

AUD_MIC_IN1_CONN_PVOLTAGE=0V

GND_AUDIO_MIC1_CONNMIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM

AUD_SPDIFIN_JACK

AUD_LI_R


HS_MIC_HI


AUD_HP_TIP_DET


GND_AUDIO_ISO

GND_AUDIO_CODEC


AUD_LI_L

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM AUD_LI_L_JACK

MIN_LINE_WIDTH=0.4MM VOLTAGE=3.3V PP3V3_AUDIO_SPDIF_JACKMIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM AUD_GND_DET_JACK

AUD_LI_DET_JACKMIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM AUD_LI_GND_JACK

AUD_HP_R_JACKMIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

AUD_HP_TIPDET_JACKMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM

AUD_HP_TYPEDET_JACKMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MMAUD_IP_PERPH_JACKMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM

AUD_LI_R_JACKMIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

AUD_HP_L_JACKMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM

AUD_SPDIF_OUT

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM AUD_HP_GND_JACKMIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM HS_MIC_HI_JACK

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98

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98

98

98

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G

S

D

G

S

D

G

S

D

OUT

IN

IN

IN

IN

IN

IN

G

S

D

IN

IN

G

S

D

G

S

D

IN

G

S

D

G

S

D

IN

ININ

IN

IN

OUT

OUT

IN

OUT

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(DETECT C)(DETECT D)Digital Out(DETECT B)

LI Insert Detect

IPHS HS Detect Debounce CKT

DP Audio Enable

NC

Headphone Out

NC

Internal Microphone Impedance Matching

1

2

6

Q6700SOT-563-HFNTZD3154NT1H

1

2

6

Q6702NTZD3154NT1HSOT-563-HF

4

5

3


2

1R67905%

MF-LF402

1/16W

10K

2

1R6795

1/16W5%

MF-LF402

100K2

1R6794

402MF1/16W0.1%

CRITICAL

20K

20 97 21

R6799

MF-LF

5%

0

402

1/16W

2

1 C6797

16V10%

402X5R

0.1UF

NOSTUFF

21

R6796

5%

402MF-LF1/16W

0

2

1R6701

402

1%10K

MF-LF1/16W

56 61

60

60

56 61

60

56 61

2

1R6798100K

MF-LF

5%1/16W

402

4

5

3


2

1R67975%1/16W

402MF-LF

10K

21

R6700

402

1/16W

17.4K

1%

MF-LF

2

1 C6740

16V

0.1UF10%

X5R402

60 62

2

1R6730

1/16W5%

MF-LF402

10K

56 61 95

1

2

6


4

5

3


2

1R6762

402

5%1/16WMF-LF

10K

61

2

1R6768100K

402MF-LF

5%1/16W

1

2

6


4

5

3

Q6703SOT-563-HFNTZD3154NT1H18 83 91

56 57 61

21

R6712

5%1/16W

0

MF-LF402

21

R6710

1/16WMF-LF

5%

402

0

21

R6711

MF-LF

5%1/16W

0

402

2

1R6744

MF-LF

1%1/16W

5.11K

402

2

1R67921%

MF-LF1/16W

SIGNAL_MODEL=EMPTY3.40K

402

21

XW6702SM

60 62

60 62

2

1C6750

402

25VX7R

10%0.0082UF

2

1R6791

MF-LF402

1/16W5%100K

2

1R6793

402MF-LF1/16W1%3.40K

SIGNAL_MODEL=EMPTY

21

C6796

402X5R

10%

0.1UF

16V

21

C6795

402

16VX5R

10%

0.1UF

2

1C6751

TANT603-HF

6.3V20%

4.7UF

CRITICAL

21

R67432.2K

5%

402MF-LF1/16W

56 62

56 62

56

21

L6700

0402

FERR-220-OHM

21

L6701

0402

FERR-220-OHM

NOSTUFF

2

1 C6700

X5R402

10%16V

0.1UF

61

61

AUDIO: Detects/GroundingSYNC_DATE=11/24/2010SYNC_MASTER=K60_DAVID

AUD_MIC1_IN_N

AUD_MIC1_IN_P

AUD_IP_PERIPHERAL_DET

AUD_HP_TYPE_INV

PP4V5_AUDIO_ANALOG

=PP3V3_S0_AUDIO

=PP3V3_S0_AUDIO

PP5V_AUDIO_ISO

GND_AUDIO_CODEC

GND_AUDIO_CODEC

AUD_HP_TYPE

AUD_MIC_INR_N

AUD_HP_TIP_DET

AUD_CODEC_MICBIAS

AUD_MIC_INR_P

AUD_INTMICBIAS

AUD_Q6701_D6

AUD_SENSE_A

JACK_DET_V_FILT

GND_AUDIO_CODEC JACK_L_RTN_2JACK_L_RTN_1

AUD_Q6702_D3

GND_AUDIO_CODEC

AUD_LI_TIP_DET_INV

AUD_IP_PERPH_DET_DB

DP_GPU_T29_SEL

GND_AUDIO_CODEC

AUD_MIC1_IN_G

JACK_DET_V_FILT



AUD_IP_PERPH_DET

GND_AUDIO_CODEC JACK_L_RTN_0

AUD_SENSE_A

PP4V5_AUDIO_ANALOG

AUD_IP_PERPH_DET_INV AUD_IP_PERPH_DET_R

AUD_LI_TIP_DET

AUD_HP_TIP_DET_INV

GND_AUDIO_CODEC

AUD_IP_PER_DEB

AUD_SENSE_A

JACK_DET_V_FILT

JACK_DET_V_FILT

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56 57 60 61 62

www.vinafix.vn

IN

BI

OUT

IN

IN

CS

HDET

AGND

DGND

ENABLE

AVDD

SDA

BYPASS

DETECT

MICBIAS

INT*

SCL

OUT

OUT

IN

2E

1E

1Y 1Z

2Z

GND

VCC

2Y

OUT

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM


PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD


TABLE_PHYSICAL_ASSIGNMENT_ITEM





36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

WRITE: 0X72 READ: 0X73

PHYSICAL

APN 353S2640

FHP = 80 HZFLP = 8.82 KHZ

PIN COMPLEX

ENABLE/CONTROL

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

LINE IN

SPDIF IN

INTERNAL MIC

EXTERNAL MIC

FUNCTION

SPDIF OUT

0X02 (2)

0X04 (4)

N/A

0X03 (3)

0X06 (6)

0X04 (4)

0X08 (8)

0X02 (2)

0X03 (3)

CONVERTER

0X06 (6)

0X05 (5)

0X0D (13,V22,B,LEFT)

0X0E (14,LEFT & RIGHT)

0x0F (15)

0X12 (12,C)

0X0A (10,D)

0X0B (11)

0x10 (16)

0X09 (09)

PIN COMPLEX

GPIO_3

N/A

N/A

N/A

N/A

COUGAR POINT GPIO 5 (RCVR INT)COUGAR POINT GPIO 3 (PERIPH DET)

DET ASSIGNMENT

0X0D (B)

DET ASSIGNMENT

N/A

N/A

0X12 (C)

N/A

N/A

0X0A (D)

FUNCTIONHP/LINE OUT

PRIMARY SPKRS (WFR)

COUGAR POINT GPIO 16

GPIO_3

GPIO_2

SHDN

CODEC INPUT SIGNAL PATHS

SECONDARY SPKRS (TWT)

CODEC OUTPUT SIGNAL PATHS

0X07 (7)

CONVERTER

VOLUME/MUTE

MIKEY RECEIVER CKT

21

L6800

0402

FERR-1000-OHM

21

R6802

402MF-LF1/16W

0

5%

21

R6803

5%1/16WMF-LF402

0

21

R6804

402MF-LF

5%1/16W

0

21

R68050

5%

MF-LF402

1/16W

49

49

20 97

21 97

2

1 C6803CRITICAL

4.7UF

603-HF

20%6.3VTANT

6 56 58 59 60 61

2

1R6812100K

MF-LF1/16W5%

402

21

R6810

MF-LF1/16W

402

5%

2.2K

2

1 C6806

402

25VX7R

10%0.0082UF

21

C6804

402

16VX5R

10%

0.1UF

21

C68050.1UF

10%

X5R402

16V

2

1R6806

MF-LF402

5%1/16W

10K2

1 C680010%

X5R

1UF10V

402

2

1 C680110%0.1UF

402X5R16V

2

1R6811

1/16WMF-LF

05%

402

B3

C3 C1

D3

A1

A3

C2

B1

B2

D1

A2

D2

U6806

CRITICAL

WCSPCD3282A1

56

56

60

8

4

65

3

21

7

U6807NX3L2G66GD

SOT996-2

2 1

R6814

402

5%

MF-LF1/16W

0

2

1C6810

402

10V

1UF10%

X5R 2

1 C68110.1UF

402

10%

X5R16V

I203

I204

I205

I206

I207

I208

I209

I210

I211

I212

I213

I214

I215

I216

I217

I218

I219

I220

I221

I222

I223

I224

I225

I226

I227

I228

I229

I230

2 1

R6815

402

5%

MF-LF1/16W

0

I232

I233

I234

I235

I236

I237

I238

I239

I240

I241

I242

I243

I244

I245

I246

I247

60 61

2

1R6807

402

5%1/16W

100K

MF-LF

2 1

R6816

5%1/16WMF-LF402

0

I252

I253

I254

I255

I256

I257

2

1R68092.2K5%

MF-LF1/16W

4022

1R68085%1/16WMF-LF

1K

402

2

1 C68020.01UF

402

10%25VX7R

SYNC_MASTER=K60_DAVID

AUDIO: MikeySYNC_DATE=01/06/2011

AUDIODIFF*AUDIODIFF

*SPKROUTDIFF SPKROUTDIFF

* Y 10 MM 0.2 MM0.25 MM0.6 MM 0.2 MMSPKROUTDIFF

AUDIODIFF Y* 0.1 MM 10 MM0.1 MM 0.1 MM0.1 MM

0.2 MMSPKROUT * ?

?AUDIO * 0.1 MM

HS_MIC_LO

MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.15MMVOLTAGE=0V

GND_AUDIO_CODEC

HS_MIC_LO_SW


GND_AUDIO_ISO


HS_MIC_HI

HS_RST

HS_SCL

AUDIO AUD_LO2_R_NAUDIODIFFAUDIO_DIFFPAIR

AUDIODIFF AUDIOAUDIO_DIFFPAIR AUD_MIC_IN1_CONN_P

AUDIOAUDIODIFFAUDIO_DIFFPAIR AUD_MIC_IN1_CONN_N

AUD_MIC1_IN_NAUDIODIFF AUDIOAUDIO_DIFFPAIR

SPKROUTDIFF SPKROUT AUD_SPKR_LTWT_OUT_NSPKROUT_DIFFPAIR

AUDIOAUDIODIFFAUDIO_DIFFPAIR AUD_MIC_INR_N

AUDIODIFF AUDIOAUDIO_DIFFPAIR AUD_MIC_INR_P


HS_MIC_BIASMIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.20MMMIN_NECK_WIDTH=0.15MMVOLTAGE=3.3VPP3V3_S0_HS_F

AUDIOAUDIODIFF MAX97220_INR_PAUDIO_DIFFPAIR

MAX97220_INR_NAUDIODIFF AUDIOAUDIO_DIFFPAIR

AUD_SPKR_RWFR_OUT_NSPKROUTSPKROUTDIFFSPKROUT_DIFFPAIR

SPKROUTDIFF SPKROUT AUD_SPKR_LTWT_OUT_PSPKROUT_DIFFPAIR

=I2C_AUDIO_SCL

HS_SDA

HS_INT_L

AUD_IPHS_SWITCH_EN

AUD_I2C_INT_L

AUD_IP_PERPH_DET

HS_HDET

=I2C_AUDIO_SDA

HS_SW_DET


AUD_RAMP_LINC_NAUDIODIFF AUDIOAUDIO_DIFFPAIR

AUD_RAMP_RINC_PAUDIODIFF AUDIOAUDIO_DIFFPAIR

AUD_LO2_L_PAUDIOAUDIODIFFAUDIO_DIFFPAIR

AUDIOAUDIODIFF AUD_LO1_R_PAUDIO_DIFFPAIR

AUD_RAMP_RINC_NAUDIODIFF AUDIOAUDIO_DIFFPAIR

AUD_LAMP_LINC_PAUDIODIFF AUDIOAUDIO_DIFFPAIR

AUD_LAMP_RINC_NAUDIODIFF AUDIOAUDIO_DIFFPAIR

AUD_LAMP_LIN_PAUDIODIFF AUDIOAUDIO_DIFFPAIR

AUDIODIFF AUD_LAMP_RIN_NAUDIOAUDIO_DIFFPAIR

AUDIODIFF AUD_LAMP_RIN_PAUDIOAUDIO_DIFFPAIR

AUDIODIFF AUDIO AUD_LO1_L_C_PAUDIO_DIFFPAIR

AUDIOAUDIODIFF AUD_LO1_R_C_PAUDIO_DIFFPAIR

AUD_LO1_L_C_NAUDIODIFF AUDIOAUDIO_DIFFPAIR

AUDIOAUDIODIFF MAX97220_INL_PAUDIO_DIFFPAIR

AUDIOAUDIODIFF AUD_LO1_R_C_NAUDIO_DIFFPAIR

AUDIOAUDIODIFF MAX97220_INL_NAUDIO_DIFFPAIR

AUD_SPKR_RTWT_OUT_NSPKROUTSPKROUT_DIFFPAIR SPKROUTDIFF

AUD_SPKR_RTWT_OUT_PSPKROUTSPKROUT_DIFFPAIR SPKROUTDIFF

AUD_SPKR_RWFR_OUT_PSPKROUTSPKROUTDIFFSPKROUT_DIFFPAIR

AUD_LAMP_LIN_NAUDIODIFF AUDIOAUDIO_DIFFPAIR

AUD_RAMP_RIN_PAUDIODIFF AUDIOAUDIO_DIFFPAIR

AUD_LAMP_LINC_NAUDIOAUDIODIFFAUDIO_DIFFPAIR

AUD_RAMP_LIN_NAUDIODIFF AUDIOAUDIO_DIFFPAIR

AUD_RAMP_LIN_PAUDIODIFF AUDIOAUDIO_DIFFPAIR

AUD_RAMP_LINC_PAUDIODIFF AUDIOAUDIO_DIFFPAIR

AUDIODIFF AUD_LO2_L_NAUDIOAUDIO_DIFFPAIR

AUDIO AUD_LO1_L_PAUDIODIFFAUDIO_DIFFPAIR

AUDIODIFF AUDIO AUD_HP_L_PAUDIO_DIFFPAIR

AUDIODIFF AUDIO AUD_LO1_L_NAUDIO_DIFFPAIR

AUD_LAMP_RINC_PAUDIODIFF AUDIOAUDIO_DIFFPAIR

AUD_RAMP_RIN_NAUDIODIFF AUDIOAUDIO_DIFFPAIR

AUDIODIFF AUDIO AUD_LO2_R_PAUDIO_DIFFPAIR

AUDIODIFF AUD_LO1_R_NAUDIOAUDIO_DIFFPAIR

AUDIOAUDIODIFF AUD_HP_R_NAUDIO_DIFFPAIR

AUDIOAUDIODIFF AUD_HP_L_NAUDIO_DIFFPAIR

AUDIOAUDIODIFF AUD_HP_R_PAUDIO_DIFFPAIR


AUD_MIC_INP_L



AUD_MIC_INN_L


HS_RX_BP


=PP3V3_S0_AUDIO

HS_RST

PP3V3_S0_HS_F

AUD_SW_SEL


HS_MIC_HI_SW


AUD_MIC_INF

GND_AUDIO_CODEC

SPKROUT AUD_SPKR_LWFR_OUT_NSPKROUT_DIFFPAIR SPKROUTDIFF

SPKROUT AUD_SPKR_LWFR_OUT_PSPKROUT_DIFFPAIR SPKROUTDIFF

AUD_MIC1_IN_PAUDIOAUDIODIFFAUDIO_DIFFPAIR

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57

57

58 60

59 60

58

58

56 59

56 57

58

59

59

59

59

59

57

57

57

57

57

57

58 60

58 60

58 60

59

58

59

58

58

58

56 59

56 57

56 59

56 57

59

58

56 58

56 57

56 58

56 59

56 58

62

62 95

56 57 60 61 62

59 60

59 60

60 61

www.vinafix.vn

08

08

G S

D

08

08

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

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PAGE


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D

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8 7 5 4 2 1

OPTION TO DELAY 1V05

OPTION TO DELAY 1V8

Enable regulator

PLACE TOP SIDEREWORK TO POWER UP WITH NO CPU

SLP_S4 ENABLES

OTHER RAILS ENABLED BY P3V3_S0 AND P5V_S0:

OPTIONAL SEQUENCE TO DELAY 3V,1V5

Enable FET

Enable regulator

SLP_S3 ENABLES

MEMVTT_EN SEQUENCE

NOTE: PM_PGOOD_P1V05_S0_REG ENABLES VCCSA REGULATOR CIRCUIT ON PAGE 70

Enable FET

Enable regulator

TO ENABLE OF CPU VCORE

CPUVTT VREG/

VCCSA REGULATOR

ENABLE REGULATOR

Enable FET

Enable FET

PCH CORE

PP1V8_S0 VREG (CPU PLL)

21

R6946

MF-LF402

33

5%1/16W

NOSTUFF

2

1R6916

MF-LF

5%100K

402

1/16W 2

1R6915

402

10K

MF-LF1/16W5%

14

8

9

10

7

U6900

TSSOP-HF74LVC08

14

3

2

1

7

U6900

74LVC08TSSOP-HF

2

1R691710K1/16W

402MF-LF

NOSTUFF

5%

2

1 C6944

NOSTUFF

402

0.47UF

6.3V

CERM-X5R

10%

2

1

R6944

33 1/16W

MF-LF

5%

402

NOSTUFF

2 1

C69100.1UF

CERM402

10V20%

2

1 C6921

6.3V

NOSTUFF

0.47UF

CERM-X5R

402

10%

2

1 C6920

10%

6.3V

402

CERM-X5R

0.47UF

NOSTUFF

2

1 C6946NOSTUFF

10%

6.3V

CERM-X5R

402

0.47UF

2

1 C6945NOSTUFF

0.47UF

6.3V

CERM-X5R

10%

402

2

1 C69240.47UF10%

6.3V

402

CERM-X5R

NOSTUFF

2

1 C6947

CERM-X5R

NOSTUFF

10%

6.3V

402

0.47UF

2

1 C6952NOSTUFF

6.3V10%

402

0.47UF

CERM-X5R

1

6

2Q6911

MMDT3904-X-GSOT-363-LF

2

1 C6951NOSTUFF

5%

402CERM

100PF50V

2

1R695110K

402

1/16WMF-LF

5%

4

3

5Q6911MMDT3904-X-GSOT-363-LF

2

1 C695310%

X5R402

16V

NOSTUFF

0.1UF

21

R6950

5%1/16WMF-LF402

10K

2

1R695210K

402

1/16WMF-LF

5%

2

1

3

Q69102N7002SOT23-HF1

21

R6990

1/16W5%

33

402MF-LF

NOSTUFF

2

1 C6994NOSTUFF

CERM-X5R

6.3V

10%

402

0.47UF

2

1 C6942NOSTUFF

402

CERM

6.3V

10%

1UF

21

R6942

1/16W5%

33

402MF-LF

NOSTUFF

21

R6972NOSTUFF

5%1/16WMF-LF402

0

21

R6971

MF-LF1/16W5%

402

0

14

6

5

4

7

U6900

TSSOP-HF74LVC08

14

11

12

13

7

U6900

74LVC08TSSOP-HF

21

R69700

1/16W5%

MF-LF402

21

R6955

1/16W5%

402

10K

MF-LF

21

R6930

1/16W5%

33

402MF-LF

21

R6931NOSTUFF

1/16W5%

33

402MF-LF

21

R6932

1/16WMF-LF402

33

5%

21

R6933

MF-LF402

5%1/16W

33

2

1R6934

MF-LF402

1/16W5%82K

2

1R693533K5%

MF-LF1/16W

402

21

R6936

1/16WMF-LF402

33

5%

73 97

63 73 97

2

1

R6941

1/16W5%

402

10K

MF-LF

NOSTUFF

2

1 C69410.47UF

NOSTUFF

10%

402

CERM-X5R

6.3V

21

R6911

1/16W

33

402MF-LF

5%

21

R6912

402

5%

MF-LF

33

1/16W

21

R6947

MF-LF402

33

5%1/16W

POWER SEQUENCING ENABLESSYNC_MASTER=K62 SYNC_DATE=01/06/2011

PM_EN_P1V5_S0_FET

PM_EN_P12V_S0_FET

=PP3V3_S0_PWRCTL

=PP3V3_S5_PWRCTL

PM_EN_DDR1V5_S3_REG

PM_EN_P3V3_S0_FET

PM_EN_DDRVTT_S0_REG

PM_SLP_S4_L

PM_PGOOD_P5V_S3_REG

PM_SLP_S4_1_L_R

PM_SLP_S5_L

CPU_SKTOCC

S4_ENABLES

PM_EN_P5V_S3_REG


PM_SLP_S4_L

=PP3V3_S5_PWRCTL

CPUVTT_REG_PGOOD_R

CPU_SKTOCC_L

VTT_REG_PGOOD_L

PM_PGOOD_PVCCSA_S0_REGMAKE_BASE=TRUE

PM_PGOOD_P1V05_S0_REGMAKE_BASE=TRUE

P3V3_S5_PWRCTL_U6900_R

=PM_EN_VCCSA_S0_CPU

PM_EN_PVCORE_CPU

PM_SLP_S3_BUF_L

PM_PGOOD_P5V_S0_FET

=PP3V3_S5_PWRCTL

PM_EN_DDRVTT_S0_REG

PM_PGOOD_P5V_S0_FET

=PP12V_S0_PWRCTL

=PP3V3_S5_PWRCTL


PM_SLP_S3_L

PM_EN_USB_PWRPM_PGOOD_P5V_S3_REG

PM_EN_P3V3_S0_FET

PM_EN_P5V_S0_FET

PM_PGOOD_P5V_S0_FET PM_EN_P1V5_S0_FET

PM_PGOOD_P3V3_S0_FET PM_EN_P1V5_S0_FET

PM_EN_P3V3_S3_FET

=PP3V3_S5_PWRCTL


PM_PGOOD_P5V_S0_FET

PM_EN_P1V05_S0_REG

PM_EN_P1V8_S0_REG


PGOOD_P12V_S0

69 OF 110

11.1.0

051-8115

63 OF 98

63 73 97

6 97

6 64 73 80

6 11 63 64

71 97

63 73 97

32 63 71 97

5 19 32 46 47 63 97

63 70 82 97

97

5 19 46 47 97

91

97

70 97

63 64 68 97

5 19 32 46 47 63 97

6 11 63 64

97

11 97

64 97

63 64 68 97

65 97

97

63 64 73 97

6 11 63 64

32 63 71 97

63 64 73 97

6 64 80

6 11 63 64

5 71 97

5 19 26 32 36 46 47 82 97

43 91 63 70 82 97

63 64 73 97 63 73 97

63 64 73 97 63 73 97

73 97

6 11 63 64

63 64 73 97

63 64 73 97

68 97

71 97

63 64 73 97

64 97

www.vinafix.vn

OUT

OUT

08

08

08

08

08

GND

V+G

D

S

G

D

S

GND

V+

08

08

G S

D

08




36

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DRAWING NUMBER SIZE

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Apple Inc.

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8 7 5 4 2 1

SMC

OPTION FOR SMC TO OUPUT

DELAYED PWRGD (BY 99MS)

VCCSA POWERGOOD

PGOOD COMPARATORS FOR PP1V8_S0 AND PP12V_S0

PULL-UP ON MXM PAGE

TO BE DRIVEN BY SAME SIGNALOPTION FOR PCH PWROK AND SYSPWROK

ALL_SYS_PWRGD CIRCUIT

VCCSA ENABLE SIGNAL

DELAY IS ABOUT 200MS

To SMC (2)

WHICH GOES INTO RSMRST_L OF PCHFROM THIS SMC GENERATES PM_RSMRST_L

(1.67V/1.22V; 132mV Hysteresis)

(9V/9.58V; 580mV Hysteresis)

S0 RAILS PGOOD

46 97

2

1 C7022

20%

CERM

0.1UF

10V

402

2

1R7050

1/16W

402

5%

MF-LF

1K

NOSTUFF

2

1 C705910%0.1UF

402X5R16V

NOSTUFF

2

1R7007

1%49.9K

402

1/16WMF-LF

21

R702233

5%1/16WMF-LF402

NOSTUFF

21

R7023

1/16W5%

33

402MF-LF

5 32 97

2

1R7020

1%

402

1/16WMF-LF

64.9K

2

1R7021

1%10K

1/16WMF-LF402

21

R7002

1%1/16W

402

2.0K

MF-LF

2

1R7017

402

10K5%1/16WMF-LF

2

1R70185%1/16WMF-LF402

10K

14

6

5

4

7

U7000TSSOP-HF74LVC08

14

8

9

10

7

U7050

74LVC08TSSOP-HF

14

11

12

13

7

U7000

TSSOP-HF74LVC08

14

3

2

1

7

U7050

TSSOP-HF74LVC08

21

R7054

402

5%

MF-LF1/16W

0

4

3

5Q7011

SOT-363-LFMMDT3904-X-G

1

6


21

R702833

1/16WMF-LF402

5%

2

1 C702310%

NOSTUFF

0.47UF

CERM-X5R6.3V

4022

1R7031100K5%

MF-LF402

1/16W

2

1R7061

MF-LF402

1/16W

10K5%

21

R7060

MF-LF

5%

0

402

1/16W

14

11

12

13

7

U7050

TSSOP-HF74LVC08

21

R7029

MF-LF402

0

5%1/16W

21

R7032

MF-LF

5%1/16W

402

33

2

1 C7080

603CERM16V20%0.1UF

2

1R7086

1/16W

10K

MF-LF402

5%

2

1R7084

MF-LF402

10K1/16W5%

2

1R7083

1%

402MF-LF1/16W

49.9K

8

1

3

2

4

U7080SOI-HF

CRITICAL

LM393

2

1R7080

1/16WMF-LF

33.2K1%

402

2

1R7081

402

1%

MF-LF

100K

1/16W

21

R7082

1%

MF-LF402

2.0K

1/16W

1

2

6

Q7080

SOT-3632N7002DW-X-G 4

5

3

Q7080

SOT-3632N7002DW-X-G

8

7

5

6

4

U7080LM393

CRITICAL

SOI-HF

14

3

2

1

7

U7000

74LVC08TSSOP-HF

21

R7063

MF-LF

33

5%

402

1/16W

2

1 C706610%

NOSTUFF

X5R16V

402

0.1UF

2

1R7092

MF-LF1/16W

10K5%

402

4

3

5Q7090

SOT-363-LFMMDT3904-X-G

21

R7093

MF-LF1/16W5%

402

10K

2

1R7091

1/16WMF-LF

10K5%

402

1

6


2

1 C7091

16V

402

NOSTUFF

X5R

10%0.1UF

21

R70901K

1/16WMF-LF

5%

402

21

R707833

MF-LF402

1/16W5%

21

R7079

MF-LF402

5%1/16W

33

2

1 C7050

CERM

20%10V

402

0.1UF

14

8

9

10

7

U7000

74LVC08TSSOP-HF

2

1

3

Q7010SOT23-HF12N7002

2

1 C70610.1UF16VX5R402

NOSTUFF

10%

21

R7094

5%

MF-LF1/16W

33

402

21

R709933

402

1/16WMF-LF

5%

NOSTUFF

14

6

5

4

7

U7050

74LVC08TSSOP-HF

21

R703533

1/16W5%

MF-LF402

21

R7066

402

1/16WMF-LF

5%

0

2

1R7067

10K

1/16W

402

5%

MF-LF

2

1 C705510%

NOSTUFF

0.47UF

CERM-X5R6.3V

402

2

1 C7056

402

6.3V

0.47UF

NOSTUFF

10%

CERM-X5R

21

R7024

402

5%

MF-LF1/16W

0

NOSTUFF

21

R70300

1/16WMF-LF

5%

402

21

R705233

5%

402MF-LF1/16W

NOSTUFF

21

R705333

1/16W5%

MF-LF402

NOSTUFF

POWER SEQUENCING PGOODSYNC_MASTER=K62 SYNC_DATE=01/06/2011

=PP3V3_S5_PWRCTL

=PP3V3_S0_PWRCTL


PM_PGOOD_P5V_S0_FET

PGOOD_CPU_UNCORE

PGOOD_CPU_S0


PM_PGOOD_PVCORE_CPU

PGOOD_P1V8_S0

=PP3V3_S0_PWRCTL

=PP3V3_S0_PWRCTL


PM_PGOOD_CK505


=PP3V3_S0_PWRCTL

=PP12V_S5_PWRCTL

PGOOD_1V8_S0_G2

=PP12V_S0_PWRCTL

PGOOD_1V8_S0_G1

VCCSAPG_1

PVCCSA_L

PVCCSA_R_L

PGOOD_12V_S0_G1

=PP3V3_S0_PWRCTL

=PP12V_S0_PWRCTL

1V60_COMP_REF

PVCCSA_EN_L

=PP12V_S5_PWRCTL

PGOOD_12V_S0_G2

=PP3V3_S0_PWRCTL

=PPVCCSA_S0_PWRCTL

PGOOD_P12V_S0

=PP1V8_S0_PWRCTL

=PP3V3_S0_PWRCTL

9V_COMP_REF

12V_COMP_REF

=PM_EN_VCCSA_S0_CPU

PGOOD_5V_1V05_3V3

PM_PGOOD_PVCCSA_S0_REG


PGOOD_3V3_1V05

1V80_COMP_REF

PM_PGOOD_PVCCSA_S0_REG

=PP3V3_S0_PWRCTL

=PP3V3_S3_PWRCTL

=PP3V3_S0_PWRCTL

PM_EN_PVCCSA_S0_REG_L

VTTS3PG_1

=PP3V3_S0_PWRCTL

=PP3V3_S5_PWRCTL

RSMRST_PWRGDPM_PGOOD_P3V3_S5_REG

PM_ASW_PWRGD

PM_PCH_PWRGDPM_PCH_PWRGD_RPGOOD_PCH_S0_R

PGOOD_PCH_S0_R

SMC_DELAYED_PWRGD

PM_SYS_PWRGD

ALL_SYS_PWRGD_R

PM_ASW_PWRGD

PGOOD_PCH_S0 ALL_SYS_PWRGD_SMCPM_MXM_PGOOD

ALL_SYS_PWRGD

=PP3V3_S0_PWRCTL

=PM_MXM_PGOOD_PULLUP=PP3V3_S0_MXM


PGOOD_PCH_S0

PM_MXM_EN

PGOOD_SYSPWROKALL_SYS_PWRGD_SMC

PM_PECI_PWRGD

PGOOD_SYSPWROK_R

SMC_DELAYED_PWRGD

70 OF 110

11.1.0

051-8115

64 OF 98

6 11 63 64

6 63 64 73 80

63 64 68 97

63 73 97

91 97

97

71 97

5 25 65 97

97

6 63 64 73 80

6 63 64 73 80

63 73 97

26

11 64 73 97

6 63 64 73 80

6 33 64 73

6 63 64 80

6 63 64 73 80

6 63 64 80

6 33 64 73 6 63 64 73 80

6

63 97

6

6 63 64 73 80

97

97

63

91 97

63 64 97

11 64 73 97

91 97

63 64 97

6 63 64 73 80

6 73 82

6 63 64 73 80

97

6 63 64 73 80

6 11 63 64

27 70 97

19 64 97

19 21 97 97 64 91 97

64 91 97

47 64 97

19 32 97

19 64 97

5 64 97 46 64 97 76 97

91 97

6 63 64 73 80

76 6 21 75 76

63 64 68 97

5 64 97

76 97

97

46 64 97

46 97

97

47 64 97

www.vinafix.vn

OUT

IN

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

OUT

IN

OUT

OUT

BI

IN

IN

IN

IN

IN

VR_RDYS

IMONS

FS_DRP

VCC

ISEN1+

PWM1

ISEN1-

PWM2

ISEN2+

ISEN2-

PWM3

ISEN3-

ISEN3+

TMS

ISEN4-

ISEN4+

PWM4

FSS_DRPS

EN_VTT

RSET

VSENS

RAMP_ADJ

FBS

RGNDS

VR_RDY

COMPS

SVCLK

SVDATA

SVALERT*

VSEN

FB

RGND

PSICOMP

COMP

IMON

VR_HOT*

TMTHRM

ISENS-

ISENS+

PWMS

HFCOMPS/DVCS

EN_PWR

ADDR_IMAXS_TMAX

NPSI_DE_IMAX

BT_FDVID_TCOMP

BTS_DES_TCOMPS

SICI

HFCOMP

PAD




36

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Apple Inc.

PAGE


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C

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D

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8 7 5 4 2 1

CPU CORE/AXG REG 1.1V/75A O/P= PPVCORE_S0_CPU_REG

1.25 mOhm loadline

LOCAL 5V

1.25 mOhm loadline

CPU CORE INPUT FILTER

AVG = 55A

CPU VCORE

PEAK = 75AVOUT = VCORE

67 95

67 95

67 95 2

1 C7101

X5R

10%

402

16V

0.1UF

VAXG

66 95

66 95 2 1R71104025%

01/16W MF-LF

50 95

21

R7109

MF-LF4021/16W1%

1.02K

VAXG

2

1 C7103220PF

X7R-CERM50V10%

402

21

R7108110

1%

MF-LF1/16W

402

VAXG

2

1 C7104

16V

402X5R

10%0.1UF

2

1 C710010%220PF

X7R-CERM50V

402

VAXG2

1R710001/16WMF-LF402

5%

NO_VAXG

2

1 C7102

X7R-CERM402

220PF10%50V

VAXG

2

1R7107

402

05%1/16WMF-LF

VAXG

2

1R7103

402MF-LF

NOSTUFF

01/16W5%

2

1R71040

MF-LF1/16W5%

NOSTUFF

402

2

1R7105

1/16W5%

NOSTUFF

0

402MF-LF

2

1R710605%1/16WMF-LF402

66 95

66 95

2

1 C7106

16VX5R

10%0.1UF

402

2 1R7112 05% MF-LF 4021/16W

2

1 C7105

X7R-CERM

220PF50V10%

402

66 95

66 95 2 1R7114 0402MF-LF5%1/16W

2

1 C7108

16V

402X5R

0.1UF10%

2

1 C7107220PF

X7R-CERM50V

402

10%

66 95

66 95

66 95

2

1R7102NOSTUFF

1/16W

05%

MF-LF402

2

1R7155

402MF-LF1/16W1%105K

2

1 C71110.1UF

X5R16V

402

10%2

1R71251K

402MF-LF

5%1/16W

2

1R712613.7K1%1/16WMF-LF402

2

1R7101NOSTUFF

MF-LF

05%1/16W

402

2

1R7120

1/16W1%

124K

402MF-LF

50 95

2

1R7118

1/16W

1.18M1%

MF402

2

1 C7112

402X5R16V10%0.1UF

PP12V_S0_CPU_FLTRD2

1R7122100K

MF-LF1/16W5%

402

2

1R7123

402

2.74K1/16W1%

MF-LF

2

1R71246.65K1/16W

402

1%

MF-LF

63 97

2

1R711911K

1/16W

402

1%

MF-LF

2

1 C71130.1UF

X5R402

16V10%

2

1 C71150.01UF20%16VCERM402

NOSTUFF

21R7141 1.21K402MF-LF1/16W1%

21

C7117

0402

10%

3900PF

X7R50V

21

C711839PF

50V5%

402CERM

21

R71329.09K

1%1/16W

402MF-LF

21

R7130

402

309

1/16W1%

MF-LF

21

R7129499

1%

402MF-LF1/16W

21

R7128

1%1/16WMF-LF

249

402

21

R7131

402

10

1/16W5%

MF-LF

5 25 64 97

21R7140 953K4021% 1/16W MF-LF

21R7156 953KMF-LF1% 4021/16W

2

1R7151255K

MF-LF402

1/16W1%

2

1R715017.8K1/16WMF-LF

402

1%

21R7143 15.0K1/16W MF-LF1% 402

2

1R714930.1K

1%1/16WMF-LF

402

2

1R7146110

MF-LF1/16W

5%

402

13 95

13 95

13 95

2

1R7147

MF-LF1/16W

NOSTUFF

402

1%90.9

2

1R7148

1/16W1%

402MF-LF

54.9

2

1 C71260.1UF16VX5R

10%

402

21

R7136215

MF-LF1/16W

402

1%

21

R7133402

402

1/16W1%

MF-LF

21

R71351.3K

1/16WMF-LF402

1%

21

C7120

10%50VCERM402

390PF

21

C7122

50VCERM402

5%

82PF

21

R7134249

402MF-LF

1%1/16W

21R7144MF-LF2.32K

4021% 1/16W

2

1 C71240.01UF16V

402CERM

20%

21

R7121

5% MF-LF1/16W

10402

21

R7145

1/16W1%

402

4.99K

MF-LF

2

1 C712710%

402

10VX5R

27.0NF2

1R715305%

402

1/16WMF-LF

2

1R715411K

MF-LF

1%

402

1/16W

2

1R7152

MF-LF402

5%1/16W

0

2

1 C7132

X5R16V10%0.1UF

402

21R71111/16W 402MF-LF1%

1.02K

21R7113MF-LF1% 1/16W 4021.02K

21R7115402MF-LF1% 1/16W

1.02K

2

1R7158255K

402

1/16W1%

MF-LF

21

L7100

TH-VERT-HF

1UH-20A-4.5MOHM

21R7199MF-LF0

4025% 1/16W

2

1 C7155

SIGNAL_MODEL=EMPTY

NOSTUFF

402CERM50V10%0.0022UF

21

R716210

1/16W5%

MF-LF402

21

R7160

1/16W

402

5%

1K

MF-LF

21

R71610

MF-LF402

1/16W5%

21

XW7120

SM

OMIT

13 95

13 95

2

1 C7157

402

50VCERM

10%0.0022UF

2

1 C7156

402

0.0022UF10%50VCERM

21

R7164

MF-LF1/16W5%

10

402

21

R7165

5%

402

1K

1/16WMF-LF

21

R7163

1/16W5%

MF-LF

0

402

21

XW7130SM

OMIT

2

1 C7158

SIGNAL_MODEL=EMPTY

NOSTUFF

0.0022UF

402CERM50V10%

21

R716710

1/16W5%

MF-LF402

21

R7166

402

5%

MF-LF1/16W

1K

21

R7168

1/16W5%

402MF-LF

0

21

XW7123

SM

OMIT

13 95

13 95

2

1 C7160

402

50VCERM

10%0.0022UF

2

1 C71590.0022UF

402

50VCERM

10%

21

R7170

MF-LF1/16W5%

10

402

21

R71711K

5%1/16WMF-LF402

21

R7169

402

1/16W5%

MF-LF

0

21

XW7133

OMIT

SM

2

1R719510K1/16WMF-LF402

5%

2

1R71891K1/16W5%

MF-LF402

21

RT7104

6.8K

0603

2

1R7159

5%1K

402

1/16WMF-LF

21

RT7103

6.8K

0603

2

1R7157

MF-LF1/16W

402

5%1K

2

1R7179100K

5%

402

1/16WMF-LF

NOSTUFF

2

1R7180

MF-LF1/16W

402

5%

NOSTUFF

100K

2

1R718110K

MF-LF1/16W

402

5%

NOSTUFF

21

C7116

50VCERM402

0.001UF

10%

21

C71194700PF

100V

402

10%

CERM

21

C7123

10%50VCERM402

0.0012UF

21R7142MF-LF23.2K

4021%1/16W

21XW7101

SM

OMIT

20

4

17

13

15

35

23

31

49

10

12

11

32

33

21

3

2

26

37

39

36

38

6

28

24

25

44

43

48

47

42

41

46

45

14

9

16

5

22

34

19

7

40

1

18

8

30

29

27

U7100ISL6364

QFN

2 1

R7127

MF-LF

2.2

1/8W

805

5%

2

1 C711410%25V

805

10UF

X5R


VREG: PPVCORE_S0_CPUSYNC_DATE=N/A

VR_AXG_PWM

PP5V_S0_CPU_VCORE_VCC


VOLTAGE=5V

MAX_NECK_LENGTH=3MM


VR_CPU_SW_FREQ

VR_CPU_ISNS3_R_N

VR_CPU_RAMP_ADJ

VR_CPU_PWM2

VR_CPU_VSEN

VR_CPU_RGND

CPU_VIDALERT_L

VR_CPU_FB

CPU_VIDSCLK

VR_CPU_IMON

VR_CPU_TM

VR_CPU_SUTH

VR_AXG_VSEN

VR_CPU_N_PSI

VR_AXG_FB

VR_AXG_RGND

CPU_VIDSOUT

PM_PGOOD_PVCORE_CPU

VR_AXG_SW_FREQ

VR_CPU_PSICOMP1

VR_CPU_VSNS_XW_PVOLTAGE=1.1VNET_PHYSICAL_TYPE=SNS_DIFF

AGND_CPUVR_AXG_COMP_RC

NET_PHYSICAL_TYPE=SNS_DIFFVOLTAGE=1.1VVR_AXG_VSNS_XW_P

VR_AXG_VSNS_R_P

VR_SEN_R1

VR_SEN_R3

VR_CPU_PSICOMP2

AGND_CPUMAX_NECK_LENGTH=3MMMIN_NECK_WIDTH=0.3MMMIN_LINE_WIDTH=0.6MMVOLTAGE=0V

VR_AXG_IMON

VR_AXG_TM

=PP3V3_S0_VRD

VR_AXG_HFREQ_COMP

VR_RSET

AGND_CPU

AGND_CPU

=PPVAXG_S0_CPU

CPU_VAXG_SENSE_P

VOLTAGE=12VNET_PHYSICAL_TYPE=POWERPP12V_S0_CPU_FLTRD

VR_CPU_FB2

VR_AXG_VSNS_R_N


VR_CPU_IMON_R

CPU_PROCHOT_L

=PPVCORE_S0_CPU

VR_EN_PWR_OVP_R

VR_CPU_ISNS1_NDIFFERENTIAL_PAIR=VR_CPU_ISNS1

AGND_CPU

AGND_CPU

AGND_CPU

VR_CPU_ISNS3_NDIFFERENTIAL_PAIR=VR_CPU_ISNS3

VR_CPU_PWM1

VR_AXG_IMON_R

=PP12V_S0_VRD

CPU_VCC_SENSE_P

CPU_VCC_SENSE_N

AGND_CPU

VR_CPU_VSNS_R_N

NET_PHYSICAL_TYPE=SNS_DIFF

VR_CPU_VSNS_XW_NVOLTAGE=0V

VR_CPU_VSNS_R_P

DIFFERENTIAL_PAIR=VR_CPU_ISNS2VR_CPU_ISNS2_N

CPU_VAXG_SENSE_N

VR_AXG_VSNS_XW_NVOLTAGE=0VNET_PHYSICAL_TYPE=SNS_DIFF


VR_CPU_PWM3

AGND_CPU

AGND_CPU

AGND_CPU

AGND_CPU

DIFFERENTIAL_PAIR=VR_AXG_ISNS

VR_AXG_ISNS_P

AGND_CPU

AGND_CPU

VR_AXG_PWM_R

VR_AXG_ISNS_R_N

VR_HOT_L

PM_EN_PVCORE_CPU

VR_CPU_PWM4_R

DIFFERENTIAL_PAIR=VR_CPU_ISNS3VR_CPU_ISNS3_P

VR_CPU_PWM3_R

VR_CPU_ISNS2_R_N

VR_CPU_PWM2_R

VR_CPU_ISNS1_R_N

VR_CPU_PWM1_R

PM_PGOOD_PVAXG

AGND_CPU

VR_SEN_R2

AGND_CPU

VR_AXG_COMP


VR_CPU_COMP

=PPVCCIO_S0_CPU

=PP5V_S0_VRD

AGND_CPU

VR_CPU_ISNS1_PDIFFERENTIAL_PAIR=VR_CPU_ISNS1

VR_CPU_ISNS2_PDIFFERENTIAL_PAIR=VR_CPU_ISNS2

VR_AXG_TCOMP

VR_CPU_FDVID

VR_CPU_IAUTO

VR_CPU_PSICOMP

VR_CPU_HFREQ_COMP

VR_EN_PWR_OVP


VR_CPU_FB_R

VR_CPU_FB_RC

DIFFERENTIAL_PAIR=VR_AXG_ISNS

VR_AXG_ISNS_N

VR_AXG_ISNS_R_P

=PP3V3_S0_VRD

71 OF 110

11.1.0

051-8115

65 OF 98

65 66 67 95

65 95

95

95

95

95

95

95

95

95

95

95

95

95

95

95

65 95

95

95

95

95

65

95

6 65 68

95

95

65

65

6 13 17 50

65 66 67 95

95

65 95

95

11 47

97

6 13 16 50

95

65

65

65

95

6

65

95

95

65 95

65

65

65

65

65

95

95

95

95

95

95

95

95

65

95

65

95

65 95

95

6 10 11 13 16

6 67

65

95

95

95

95

95

95

65 95

95

95

95

6 65 68

www.vinafix.vn

OUT

IN

IN

OUT

OUT

OUT

OUT

BOOT

UGATE

PHASENC

NC

GND

LGATE

VCC PVCC

THRML

PWM

PAD

BOOT

UGATE

PHASENC

NC

GND

LGATE

VCC PVCC

THRML

PWM

PAD

S

G

D

D

G

S

S

G

D

S

G

D

D

G

S

D

G

S

IN

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GND THRML

PHASE

LVCCUVCC

PAD

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

THESE TWO CAPS ARE FOR EMC


PHASE 3

PHASE 2

OUTPUT BULK DECOUPLING:

PHASE 1

376S0771

152-0118

376S0771

376S0772

376S0771

75A MAX

152-0118

376S0772

128S0209

376S0772


65 95

2

1 C7282

X5R

10%

603

16V

1UF

2

1 C7226CRITICAL

0805

10%16V

10UF

X5R-CERM

2

1R7226

MF-LF1/8W

NOSTUFF

805

2.25%

2

1 C7206CRITICAL

16V

10UF10%

0805X5R-CERM

2

1 C72280.001UF

402

50V10%

CERM

NOSTUFF

2

1 C7223

603

0.22UF

X7R16V10%

2

1R72240

1/10W

603MF-LF

5%2

1 C7221

16V

1UF

603

10%

X5R

2

1R7221

1/10W

10

603MF-LF

5%

2

1R7225

1/10W

603

NOSTUFF

MF-LF

5%0

2

1R722210

MF-LF603

5%1/10W

2

1 C7220

603X5R

1UF16V10%

NOSTUFF

2

1C7222

16V

1UF10%

X5R603

2

1R7227

MF-LF603

NOSTUFF

05%1/10W

65 95

2

1 C728310%1UF16VX5R603

2

1 C7246CRITICAL

10UF16V10%

0805X5R-CERM

2

1R7206NOSTUFF

2.2

MF-LF805

5%1/8W

2

1R72465%

1/8WMF-LF

2.2

805

NOSTUFF

2

1 C7248

50V

0.001UF10%

402CERM

NOSTUFF

2

1 C7243

16V10%

X7R603

0.22UF

2

1R724405%

603

1/10WMF-LF

2

1 C72411UF16V

603X5R

10%

2

1 C7208

50VCERM402

10%0.001UF

NOSTUFF

2

1R7241

MF-LF603

1/10W5%10

2

1R724505%

MF-LF

NOSTUFF

603

1/10W

2

1R7242105%

603MF-LF1/10W

2

1 C7240

603X5R

1UF16V10%

NOSTUFF

2

1C7242

16VX5R

1UF10%

603

2

1R7247

MF-LF

0

603

1/10W5%

NOSTUFF

65 95

2

1 C72071UF10%16V

603X5R 2

1 C721110%

402

1UF25VX5R

2

1 C721510%

X5R-CERM0805

16V

10UF

CRITICAL

2

1 C7229

16VX5R-CERM

CRITICAL

10%

0805

10UF

2

1 C7249CRITICAL

X5R-CERM0805

10%16V

10UF

43

21

R72080.0005

MF1W1%

0612

CRITICAL

43

21

R7228

0612MF1W

0.00051%

CRITICAL

65 95

65 95

65 95

65 95

43

21

R72481%

0.0005CRITICAL

MF1W

0612

2

1 C7270CRITICAL

220UF

ALUM-POLY8X7-TH

16V20%

2

1 C7271

ALUM-POLY8X7-TH

20%16V

220UF

CRITICAL

2

1 C72030.22UF10%16VX7R603

2

1 C7205220UF20%16V

CRITICAL

ALUM-POLY8X7-TH

2

1 C7225

16V20%

ALUM-POLY8X7-TH

220UF

CRITICAL

2

1 C724520%16V

CRITICAL

ALUM-POLY8X7-TH

220UF

7

1

11

4

9

10

8

3

6

5

2

U7221

CRITICAL

QFN1ISL6612

7

1

11

4

9

10

8

3

6

5

2

U7241QFN1

ISL6612

CRITICAL

2

1 C72100.001UF50V10%

402X7R

2

1 C723010%

402

50VX7R

0.001UF

2

1 C7231

402

10%1UF25VX5R

2

1 C725010%

X7R50V

402

0.001UF

2

1 C725110%

402

1UF25VX5R

2

1 C7263330UF-0.0045OHM20%2VPOLYCASE-D2-SM

2

1 C7264

POLY2V20%330UF-0.0045OHM

CASE-D2-SM

2

1 C7262

CASE-D2-SM

330UF-0.0045OHM20%2VPOLY

2

1 C7260

CASE-D2-SM


2

1 C7261

CASE-D2-SM


3

4 6

5

2

1

Q7201CRITICAL

S1IRF6710

43

5

7621

Q7202IRF6795DIRECTFET-MX

CRITICAL

3

4 6

5

2

1

Q7221IRF6710

CRITICAL

S1

3

4 6

5

2

1

Q7241IRF6710

S1

CRITICAL

2

1R72040

603MF-LF1/10W

5%

43

5

7621

Q7222DIRECTFET-MXIRF6795

CRITICAL

43

5

7621


CRITICAL

21

L72010.24UH+/-20%-0.00042OHM-40A

SDP1108M-TH

CRITICAL

21

L7221CRITICAL

SDP1108M-TH

0.24UH+/-20%-0.00042OHM-40A

21

L7241CRITICAL

0.24UH+/-20%-0.00042OHM-40A

SDP1108M-TH

2

1 C7265

CASE-D2-SM


2

1 C7272220UF

8X7-THALUM-POLY16V

CRITICAL

20%

2

1 C7281

X5R603

16V10%1UF

2

1 C722710%

603

16VX5R

1UF

2

1 C7247

603X5R16V

1UF10%

65 95

9 8

1

11

4

10

7

6

5

3 2

U7201ISL6622

CRITICAL

DFN

2

1C7202

16V

603X5R

10%1UF

65 95

2

1 C7201

X5R16V

603

10%1UF

2

1

R7201

MF-LF

5%

NOSTUFF

603

1/10W

10

2

1R72025%

603MF-LF1/10W

10

2

1R72075%1/10WMF-LF603

0

NOSTUFF

2

1R7205

MF-LF1/10W

5%

603

0

2

1 C7200

16VX5R603

1UF10%


VREG: CPU CORE - PHASES 1-3

SYNC_MASTER=K62

PP12V_S0_CPU_FLTRDNET_SPACING_TYPE=POWER

PPVCORE_S0_CPU_REG

NET_SPACING_TYPE=VR_CONTROLNET_PHYSICAL_TYPE=VR_CTL_PHYVR_CPU_DRV2_LGATE

DIDT=TRUENO_TEST=TRUE

VR_CPU_BOOT1_RCNET_PHYSICAL_TYPE=VR_CTL_PHYNET_SPACING_TYPE=VR_CONTROL


NET_SPACING_TYPE=VR_CONTROLDIDT=TRUEVR_CPU_DRV1_UGATE

NET_PHYSICAL_TYPE=VR_CTL_PHYNO_TEST=TRUE

NET_PHYSICAL_TYPE=POWERNO_TEST=TRUE

VR_CPU_DRV1_VCC

VR_CPU_ISNS3_N

PPVCORE_S0_CPU_REGNET_SPACING_TYPE=VR_CONTROLDIDT=TRUENO_TEST=TRUE

VR_CPU_BOOT3_RCNET_PHYSICAL_TYPE=VR_CTL_PHY

NET_SPACING_TYPE=VR_CONTROLVR_CPU_DRV1_BOOT

DIDT=TRUENET_PHYSICAL_TYPE=VR_CTL_PHYNO_TEST=TRUE

NET_SPACING_TYPE=VR_CONTROLVR_CPU_DRV1_LGATE

NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUENO_TEST=TRUE

NET_SPACING_TYPE=VR_CONTROLNET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUEVR_CPU_DRV2_UGATE

NO_TEST=TRUE

NET_SPACING_TYPE=VR_CONTROLVR_CPU_DRV3_BOOT

DIDT=TRUE

NO_TEST=TRUE

NET_PHYSICAL_TYPE=VR_CTL_PHY

NET_SPACING_TYPE=VR_CONTROLDIDT=TRUE

VR_CPU_DRV3_LGATE

NO_TEST=TRUENET_PHYSICAL_TYPE=VR_CTL_PHY

DIDT=TRUE NET_SPACING_TYPE=VR_CONTROLVR_CPU_DRV3_UGATE NO_TEST=TRUE


NET_SPACING_TYPE=SWITCHNODEVR_CPU_PHASE3

NET_PHYSICAL_TYPE=POWER DIDT=TRUE

SWITCH_NODE=TRUE

VR_CPU_PHASE2NET_PHYSICAL_TYPE=POWER DIDT=TRUE NET_SPACING_TYPE=SWITCHNODE

SWITCH_NODE=TRUE

VR_CPU_DRV3_GDSEL

VR_CPU_PWM3

VR_CPU_DRV1_GDSEL

PPVCORE_S0_CPU_REG2

PPVCORE_S0_CPU_REG1

VR_CPU_PWM2

VR_CPU_ISNS2_P

VR_CPU_ISNS1_P

PPVCORE_S0_CPU_REG

VR_CPU_DRV2_GDSEL

VR_CPU_ISNS1_N

PPVCORE_S0_CPU_REG3

VR_CPU_PH3_SNUB


NET_PHYSICAL_TYPE=VR_CTL_PHYDIDT=TRUE

VR_CPU_PH2_SNUB

NET_SPACING_TYPE=SWITCHNODEDIDT=TRUE


VR_CPU_PH1_SNUB



VR_CPU_DRV3_VCCNO_TEST=TRUE NET_PHYSICAL_TYPE=POWER

NET_PHYSICAL_TYPE=POWERVR_CPU_DRV3_UVCC

VR_CPU_DRV3_PVCC

NO_TEST=TRUENET_PHYSICAL_TYPE=POWER

VR_CPU_DRV2_VCC


VR_CPU_DRV2_UVCCNET_PHYSICAL_TYPE=POWER

NO_TEST=TRUE

VR_CPU_DRV1_PVCC



VR_CPU_BOOT2_RC

NET_SPACING_TYPE=VR_CONTROL


VR_CPU_DRV2_PVCC


VR_CPU_PWM1

NO_TEST=TRUEVR_CPU_DRV2_BOOTNET_SPACING_TYPE=VR_CONTROLDIDT=TRUENET_PHYSICAL_TYPE=VR_CTL_PHY

VR_CPU_PHASE1NET_SPACING_TYPE=SWITCHNODEDIDT=TRUENET_PHYSICAL_TYPE=POWER

SWITCH_NODE=TRUE

VR_CPU_ISNS2_N

VR_CPU_ISNS3_P

VR_CPU_DRV1_UVCC


PPVCORE_S0_CPU_REG

72 OF 110

11.1.0

051-8115

66 OF 98

65 67 95

6 66

95

95

95

95

6 66

95

95

95

95

95

95

95

95

95

95

95

95

6 66

95

95

95

95

95

95

95

95

95

95

95

95

95

95

95

95 6 66

www.vinafix.vn

IN

VSW

PGND

TGR

TG

BG

VIN

THRML

VCC

LGATE

GND

NC

NCPHASE

UGATE

BOOTPWM

EN

PAD

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1


376S0906

AXG PHASE (MAX 15A)

152S1268

65 95

2

1 C7322VAXG

10V

10UF20%

X5R603

2

1 C7323VAXG

603X5R

20%10UF10V

8

7

6

1

4

3

9

5

Q7301

VAXG

SON5X6CSD58864Q5D

CRITICAL

7

1

11

4

10

8

3

65

9

2

U7301

VAXG

QFNISL6620

CRITICAL2 1

R7305VAXG

1

5%

603MF-LF1/10W

2

1 C7320VAXG

CASE-D2-SM


2

1 C7321VAXG

CASE-D2-SMPOLY2V20%330UF-0.0045OHM

2

1 C7310VAXG

1UF10%16VX5R603

2

1 C7307VAXG

603X5R16V10%1UF

2

1 C731510UF10%

X5R-CERM

VAXG

16V

CRITICAL

0805

43

21

R7308VAXG

1WMF0612

CRITICAL

1%0.0005

21

L73010.68UH-7.6MOHM-12A

VAXG

PIC0504H-SM

CRITICAL

2

1R7306

MF-LF805

5%1/8WNOSTUFF2.2

65 95

65 95

2

1 C7308

402

50VCERM

10%0.001UF

NOSTUFF

2

1 C7303VAXG

0.22UF16V10%

X7R603

2

1R7304VAXG

603

1/10W5%

MF-LF

1

2

1 C7301VAXG

1UF16VX5R603

10%

2

1

R7301VAXG

MF-LF603

1/10W5%0

VREG:AXG PHASE/CORE - CAPSSYNC_MASTER=K60_AARON SYNC_DATE=N/A

PP12V_S0_CPU_FLTRD

MIN_LINE_WIDTH=0.6MMVOLTAGE=12V


VR_AXG_DRV1_PVCCNET_PHYSICAL_TYPE=POWER

VR_AXG_DRV1_BOOTNET_PHYSICAL_TYPE=VR_CTL_PHYNET_SPACING_TYPE=VR_CONTROL

DIDT=TRUE

PPVCORE_S0_AXG_REGOUT

VR_AXG_ISNS_P

VR_AXG_ISNS_N



VR_AXG_PH1_SNUB

PPVCORE_S0_AXG_REG1

NET_PHYSICAL_TYPE=VR_CTL_PHY NET_SPACING_TYPE=VR_CONTROLVR_AXG_DRV1_LGATE

DIDT=TRUE

VR_AXG_DRV1_UGATEDIDT=TRUE

VR_CONTROLNET_PHYSICAL_TYPE=VR_CTL_PHY NET_PHYSICAL_TYPE=VR_CTL_PHY

VR_CTLDIDT=TRUE

VR_AXG_DRV1_UGATE_R

=PP5V_S0_VRD

VR_AXG_PWM

DIDT=TRUENET_SPACING_TYPE=VR_CONTROL

VR_AXG_BOOT1_RCNET_PHYSICAL_TYPE=VR_CTL_PHY

NET_SPACING_TYPE=SWITCHNODEVR_AXG_PHASE1

DIDT=TRUE



PPVAXG_S0_REG

73 OF 110

11.1.0

051-8115

67 OF 98

65 66 95

95

95

95

95

95

95 95

6 65

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D

G

S

NC

OUT

OUT

IN

SOFT

RBIAS VIN

UGATE

VW

VSS

VSEN

VR_ON

VO

VID1

VID0

THRM_PAD

RTN

PVCC

PHASEPGOOD

PGND

FDE

FB

BOOT

VDD

VID2

VID3

IMON

AF_EN

VDIFF

COMP

LGATE

ICOMP

ISN

OCSET

ISP

NC

S

G

D




36

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345678

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8 7 5 4 2 1

1.05V DEFAULT, OTHER VALUES TBD

(P1V05S0_PHASE)

(P1V05S0_LGATE)

(PP1V05S0_UGATE)

(P1V05S0_V0)

(P1V05S0_ICOMP)

(P1V05S0_ISN)

(P1V05S0_ISP)

(P1V05S0_VO)

(P1V05S0_VDIFF)

(P1V05S0_FB)

(P1V05S0_COMP)

(P1V05S0_VW)

(P1V05S0_RTN)

(P1V05S0_VSEN)

OUTPUT BULK DECOUPLING

376S0771

376S0772

0000 +1.100V 0011 +1.050V

VID<3:0> Voltage

1V05 REGULATOR for CPU & PCH VCCIO O/P= PP1V05_S0_REG


2

1 C7429

CERM-X5R6.3V20%22UF

805

2

1R749120.0K

MF-LF402

1%1/16W

2

1R7492

MF-LF1/16W1%

NOSTUFF

20.0K

4022

1R7490

MF-LF1/16W

20.0K

402

1%

43

5

7621


2

1R7493NOSTUFF

1%

MF-LF1/16W

20.0K

402 2

1R7494

MF-LF

NOSTUFF

1%1/16W

20.0K

402 2

1R749520.0K1%1/16WMF-LF402

2

1R7476

1%6.65K

1/16WMF-LF402

21

R7477150K

1%1/16WMF-LF402

21

C748033PF

5%50VCERM402

21

C74810.001UF

402CERM50V10%

2

1R7475

MF-LF

1%45.3K

1/16W

402

2

1R7484

MF-LF

20.0K

NOSTUFF

1/16W1%

402

50 95

63 64 97

2

1 C74301UF

402

16VX5R

10%

21

R7480

603MF-LF1/10W5%

2.2

2

1C74651UF

X5R16V

402

10%

NOSTUFF

21

R7467

MF-LF1/10W

2.2

5%

603

2

1 C7426CRITICAL

20%

8X7-TH

16VALUM-POLY

220UF

2

1 C7420

16V

CRITICAL

20%

ALUM-POLY8X7-TH

220UF

2

1 C7427CRITICAL

20%16VPOLY6.3X6-TH

100UF

2

1 C7445

CASE-D2-SM

20%2VPOLY

330UF-0.0045OHM

2

1R741110K

402MF-LF1/16W5%

43

21

R7420

MF1W1%

0612

0.0005

2

1 C7424

X5R

10%1UF

603

16V2

1 C7425

16V

603

1UF10%

X5R

2

1R7462

603

1/10W

0.499

MF

1%

NOSTUFF

2

1 C74630.0022UF

CERM402

10%50V

NOSTUFF

2

1R7464

402

1K1%

MF-LF1/16W

2

1R7470

1/16W

NOSTUFF

MF-LF

1%10K

402

2

1 C7478

X5R25V

0.1UF10%

402

2

1 C74730.01UF50V

402X7R

10%

2

1 C7477

X5R25V10%0.1UF

402

21

R74602.2

5%1/10WMF-LF603

21

C74640.22UF

X7R16V60310%

2

1R74699.31K1%

MF-LF402

1/16W

2

1 C7462

10%

X5R16V

402

1UF

21

R7474

MF-LF1/10W5%

0

603

2

1R7473

MF-LF1/16W

10K1%

402

21

XW7461

OMIT

SM

2

1C7461

16VX5R402

10%1UF

2

1R7461

1/16WMF-LF402

1K5%

63 97

2

1R7463

MF-LF

1%

402

100

1/16W

2

1 C74700.001UF10%

X7R402

50V

21

R746620

402

1/16WMF-LF

1%

21

R7468

1/16W

402MF-LF

1%

20

2

1C7476

X7R-CERM

0.1UF

402

10%16V

2

1R7472150K

402

1%

MF-LF1/16W

2

1R7471

1%1/16W

402

100

MF-LF

2

1C7479

50V10%

X7R402

0.001UF

21

C74820.001UF

10%50VCERM402

21

R7478200

1/16W

402MF-LF

1%

21

R7479

1%

402MF-LF

2.21K

1/16W

2

1R7483

MF-LF

20.0K

1/16W1%

402

4

15

8

29

12

14

27

26

25

24

7

16

18

33

2

9

1

22

1931

20

3

21

13

11

28

10

32

6

5

17

30

U7401

CRITICAL

ISL9563A

QFN

2

1 C7423

16V

603

1UF10%

X5R2

1 C7422CRITICAL

0805

16V10%10UF

X5R-CERM2

1 C7421

0805X5R-CERM

CRITICAL

10%16V

10UF

3

4 6

5

2

1

Q7420S1

IRF6710

21

L7420CRITICAL

0.36UH-45A-0.76MOHM

MSQ1211R36LF-TH

2

1 C7443


2

1 C7444


2

1 C7446


2

1 C7428

CERM-X5R6.3V20%22UF

805


1V05 REGULATORSYNC_MASTER=K62

P1V05S0_VO

P1V05S0_OCSET

P1V05S0_ISP

P1V05S0_VW

PP1V05_S0_REG

CPU_VCCIO_SENSE_P

DIDT=TRUE=PP12V_S0_P1V05_VREG


0.25 MM0.2 MM

P1V05S0_BOOT

DIDT=TRUE

NET_SPACING_TYPE=VR_CTL

0.2 MMDIDT=TRUE

0.25 MMP1V05S0_BOOT_R


DIDT=TRUE

P1V05S0_LGATE



GATE_NODE=TRUEMIN_NECK_WIDTH=0.2 MM

P1V05S0_UGATE

DIDT=TRUEGATE_NODE=TRUEMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM


P1V05_REG_VID0

P1V05S0_VDIF_C

CPU_VCCIO_SENSE_N

P1V05S0_COMP_C

P1V05S0_RTN

P1V05S0_VSEN

P1V05_REG_VID2

P1V05S0_FDE

P1V05_REG_VID3

=PP3V3_S0_P1V05_VREG

DIDT=TRUEMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MMP1V05S0_PHASE_L PP1V05_S0_REG

P1V05S0_ISP_R

=PP5V_S0_P1V05_VREG

0.6 mmVOLTAGE=5V

0.2 MM

5V_S0_P1V05REG_VDD

P1V05_REG_VID1

PM_EN_P1V05_S0_REG


VOLTAGE=5V0.6 mm0.2 MM

5V_S0_P1V05REG_VIN

=PP3V3_S0_VRD

GND_P1V05S0_AGND

VOLTAGE=12V0.6 mm0.2 MM

PP12V_S0_P1V05_VREG_VIN

P1V05_IMON

P1V05S0_SNUBBER


DIDT=TRUE


P1V05S0_RBIAS

P1V05S0_SOFT

P1V05S0_PHASE



SWITCH_NODE=TRUEDIDT=TRUE


PP1V05_S0_REG

P1V05S0_FB

P1V05S0_COMP

P1V05_S0_VDIFF

GND_P1V05S0_AGND


VOLTAGE=0VMIN_LINE_WIDTH=0.6 mm

P1V05S0_ICOMP

P1V05S0_ISN

74 OF 110

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051-8115

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95

95

95

6 68

13 95

6

95

95

95

13 95

95

95

6

95 6 68

95

6

95

6 65

68

95

95

95

6 68

95

95

95

68

95

95

www.vinafix.vn

G

D

S

VIN VOUT

GND




36

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SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1



CPU VCCSA 0.925V (8.8A MAX)

NOTE: THIS POWER RAIL IS BEFORE THE SENSE RES R5310

NOTE: THIS RAIL IS COMING FROM PPVCCSA_S0_INPUT_SNS AFTER SENSE RES

376S0910

4

8

1

3

2 U7501LM358-SOI-HF

21

R75030

5%

402

1/16WMF-LF

2

1 C7502

603-1

10%1UF25VX5R

2

1 C7501

CERM402

5%50V

100PF

21

R75075.49K

1%1/16W

402MF-LF

21

R7506

402

5%

MF-LF1/16W

1K

NOSTUFF

21

R7505

MF-LF

5%1/16W

0

402

2

1 C750710%

X5R6.3V

10UF

805

Place C7507 inside cavity

2

1 C750810UF

805X5R6.3V10%

Place C7508 inside cavity

2

1R7504

MF-LF

5%2.2

1/10W

603

2

1 C7509

CASE-D2E-SM

6V20%

POLY-TANT

220UF-25MOHM

OMIT_TABLE

2

1 C7510

CASE-D2E-SM

220UF-25MOHM6V20%

POLY-TANT

OMIT_TABLE

1

4

5

Q7500IRFH3702TRPBFPQFN

4

8

7

5

6 U7501LM358-SOI-HF

2

1R7533

402MF-LF

10K

1/16W1%

21

C7512NOSTUFF

5%50V

10PF

402CERM

21

R7535

402

1/16WMF-LF

5%

22

2

1 C7505

402

10VCERM

20%0.1UF

2

1 C7504

402

6.3VX5R-CERM1

20%4.7UF

2

1 C7506

CASE-D2-HF

20%

POLY2V

CRITICAL

330UF-0.009OHM

21

R7550

1%

MF-LF402

1/16W

49.9K 21

C7550

10%

560PF

CERM50V

402

21

C755110PF

CERM50V5%

402

21

C7552

25VNP0-C0G

402

5%

1000PF21

R7552

MF-LF1/16W5%

402

1K

21

3

U7505CRITICAL

ISL21070SOT23-3

21

R7531

402

5%1/16WMF-LF

100

2

1 C751510%1UF

10VX5R402

2

1 C751610%10V

1UF

X5R402

128S0330 2 POLYTANT,6V,220UF,25MOHM C7509,C7510


CPU VCCSA REGULATORSYNC_MASTER=K62

VCCSA_CNTRL_INPUT2_R

VCCSA_CRL

NET_SPACING_TYPE=VR_CTLDIDT=TRUE

VCCSA_OUTNET_PHYSICAL_TYPE=VR_CTL_PHY

VCCSA_FIL

VCCSA_GATEDIDT=TRUENET_SPACING_TYPE=VR_CTL


VCCSA_CNTRL_INPUT2

VCCSA_PWR_RC

=PPVCCSA_S0_INPUT_PWR

=PPVCCIO_S0_CPU_VCCSA

=PP12V_S0_CPU_VCCSA

CPU_VCCSA_SENSE

VCCSA_REF=PP3V3_S5_CPU_VCCSA

VCCSA_CNTRL_INPUT1

DIDT=TRUENET_SPACING_TYPE=POWER


PPVCCSA_S0_FET

75 OF 110

11.1.0

051-8115

69 OF 98

95

95

95

95

6 50

6

6

13 95

6

95 6

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OUT

D1

G1

S2

G2

S1/D2

G

D

S

G

D

S

PGOOD2

FCCM

VIN

FB1

FSET1

EN2

FSET2

BOOT2

THRMPGND

EN1

FB2

VOUT2VOUT1

ISEN2ISEN1

OCSET1 OCSET2

LGATE1 LGATE2

PHASE2

BOOT1

UGATE1

LDO5

PGOOD1

VCC1

VCC2

UGATE2

PHASE1

PAD




36

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DR


SHEET

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C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

3V3 S5 REGULATOR


376S0875

PLACE AT L7750.2


5V S3 REGULATOR

RB

(P3V3S5_PHASE)

RATO LPLACE CLOSEEMC CAPS

<Ra>

5V OUTPUT

Power Rating ?

<Rb>

EMC CAPS

(P3V3S5_LGATE)

PLACE CLOSE TO FET

(P3V3S5_UGATE)

EMC: C7763,C7764

PLACE AT Q7330

376S0917

Vout = 0.6V * (1 + Ra / Rb)

128S0237

376S0801

EMC: C7754,C77553V3 OUTPUT

2

1 C7762330UF

POLY-TANTCASE-D3L-SM

CRITICAL

20%6.3V

2

1R7747

402MF-LF1/16W1%16.5K

2

1 C774710%16VCERM402

0.01UF

2

1 C77770.001UF

402

10%50VCERM

NOSTUFF

2

1C7757NOSTUFF

50V10%

0.001UF

402CERM

2

1C7721CRITICAL

6.3VPOLY-TANT

330UF20%

CASE-D3L-SM

2

1R7723

MF-LF

5%33K

402

1/16W

2

1R7722

402MF-LF1/16W

68K5%

63 82 97

2

1R7724976

1%

402MF-LF1/16W

2

1R7759976

MF-LF

1%1/16W

4022

1R775575K

1%1/16WMF-LF

402

5 4 3

7

6

1

2

Q7710RJK0384DPA

WPAK

321

4

5

Q7750CRITICAL

FDMS0346POWER56

2

1C776410%

X7R50V

402

0.001UF

2

1C7718

6.3X6-THPOLY16V20%

100UF

2

1C7763

10%

X7R50V

0.001UF

402

21

L7750CRITICAL

2.2UH+/-20%-0.0069OHM-16A

PIC1005H-SM

2

1 C7760

CERM

10UF

20% 6.3V805-1

321

4

5

Q7751FDMS0355S

POWER56

CRITICAL

2

1C7719

6.3X6-THPOLY16V

100UF20%

2

1C7766100UF

16V20%

POLY6.3X6-TH

2

1C7767

6.3X6-TH

100UF

16VPOLY

20%2

1C7768

6.3X6-THPOLY

100UF20%16V

2

1R7741

MF-LF

5%1/8W

805

1

2

1 C7743

603

16V10%

X5R

1UF

2

1R7725

NOSTUFF

1/16W

20K5%

402MF-LF

2

1R77265%1/16W

20K

MF-LF402

2

1

XW7751OMITSM

2 1

R7776

1/4W

0.002

MF-LF1%

1206

2 1

R7775

MF-LF

0.002

12061/4W1%

21

C777027.0NF

402X5R10V10%

2

1 C775410%16V

1UF

X5R603

2

1 C7755

603X5R

1UF16V10%

2

1 C771110%16V

1UF

X5R603

2

1 C772210%16V

1UF

X5R603

2

1C7761

CASE-D3L-SM

330UF20%

6.3VPOLY-TANT

CRITICAL

2

1 C7769

CERM20%

805-16.3V

10UF

2

1C7759

25V

402

5%1000PF

NP0-C0G

2

1 R7756

402MF-LF1/16W1%10K

2 1

C7756

25V10%

X5R402

0.1UF

2

1C776510UF

16V10%

X5R-CERM0805

2

1R7752

MF 603NOSTUFF

1/10W1%

0.499

2 1

R7750

1/10W

603

5%

MF-LF

0

2

1C7758

X5R-CERM16V10%

10UF

0805

2

1C7710

X5R-CERM

10%16V

0805

10UF

2 1

XW7716SM

OMIT

PLACEMENT_NOTE=PLACE NEXT TO C7716

2

1C7720

NP0-C0G

1000PF

402

5%25V

2

1R772045.3K

1/16W

402

1%

MF-LF

2

1R7721

1/16W0.5%

402MF

10.0K

2

1C7712

16VX5R-CERM

10%

0805

10UF

2

1C7717

0805

16VX5R-CERM

10UF10%

2

1C771510UF

X5R-CERM0805

16V10%

279

17

45

2214

29

2313

17

19

2511

2016

18

2610

26

3

288

2412

2115

U7700ISL62383

CRITICALQFN

2

1 C77160.1UF

603

20%16VCERM2

1 C77230.1UF

16VCERM603

20%

21

C7790

10%

16V

402

CERM

0.01UF

2

1R7791

1/16W

402

1%

MF-LF

15.8K

2

1 C77301000PF

25VNP0-C0G402

5%

NOSTUFF

2

1R7730

1/10WMF

1%

NOSTUFF

603

0.499

21

C7714

0.1UF

603-150V

10% X7R21

R7710

1/10W

603

5%

0

MF-LF

21

R7790

1/16WMF-LF

1%

402

15.8K

2 1

R77709.76K

402 MF-LF1/16W1%

2

1R77719.76K

MF-LF402

1/16W1%

21

L7710

MMD06CZ-SM

CRITICAL

2.2UH-14A

2

1C77401UF

X5R

10%

603

16V2

1 C774110%16V

1UF

X5R603

2

1R7740

1/8W

2.25%

MF-LF805

2

1 C7742

6.3VCERM

20%

603

4.7UF

2

1 C77010.01UF10%16VCERM402

2

1R7701

402MF-LF1/16W1%16.5K

SYNC_MASTER=K62

5V_S3 / 3V3_S5 VREGSSYNC_DATE=01/06/2011

P3V3S5_REG_VOUT1

PP5V_S3_REG_RNET_PHYSICAL_TYPE=POWER

P5VS3_REG_UGATEDIDT=TRUE




P3V3S5_REG_UGATEDIDT=TRUE

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMGATE_NODE=TRUE


P3V3S5_REG_LGATEDIDT=TRUE


GATE_NODE=TRUENET_SPACING_TYPE=VR_CONTROL


DIDT=TRUE

=PP12V_S5_P5VS3_VREGNET_SPACING_TYPE=POWER

NET_PHYSICAL_TYPE=POWERDIDT=TRUE

PP3V3_S5_REG_RNET_PHYSICAL_TYPE=POWER

=PP12V_S5_P5VS3_VREG

PM_PGOOD_P5V_S3_REG

P5VS3_REG_VOUT2

P3V3S5_REG_OCSET

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6MM


P5VS3_REG_BOOTDIDT=TRUE


MIN_LINE_WIDTH=0.6MMNET_SPACING_TYPE=VR_CONTROL

P5VS3_REG_LGATEDIDT=TRUE

P3V3S5_REG_SNUB

DIDT=TRUE


P5VS3_REG_FB

P3V3S5_REG_PHASEDIDT=TRUEMIN_NECK_WIDTH=0.2MM




DIDT=TRUE


VIN_5V_S5_REG_RC

P5VS3_REG_BOOT_R



DIDT=TRUE


DIDT=TRUEP3V3S5_REG_BOOT



P3V3S5_REG_FSET1

PP5V_S3_REG

=PP3V3_S5_VRD

P3V3S5_REG_BOOT_R

DIDT=TRUEMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM


P5V_S5_LDO_R

P3V3S5_REG_FB

P3V3S5_REG_FB_R

P5VS5_REG_FB_R

TP_P5VS3_REG_FCCM

PM_EN_P3V3_S5_REG

P5VS3_REG_FSET2

PP3V3_S5_REG

PM_EN_P5V_S3_REG

5V_SNUBBER



DIDT=TRUE


P3V3S5_REG_ISEN

P5V_S5_VCC1


P5VS3_REG_ISEN

P5VS3_REG_PHASEDIDT=TRUE

MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2 MM

NET_SPACING_TYPE=SWITCHNODENET_PHYSICAL_TYPE=POWERDIDT=TRUE

P5VS3_REG_OCSET


PP5V_S5_LDO

77 OF 110

11.1.0

051-8115

70 OF 98

95

95 95

95

6 70

95

6 70

95

95

95

95

95

95

95

95

95

6

6

95

95

97

95

6

63 97

95

27 64 97

95

95

95

6

www.vinafix.vn

MODE

VDDQSNSCOMP

NC0

NC1

VTTSNS

VTT

VTTREF

PGOOD

S3

S5

VTTGND THRM_PAD GND CS_GNDPGND

CS

LL

DRVL

DRVH

VDDQSET

VBST

VLDOINV5FILTV5IN

SYM (2 OF 2)

NCNC

IN

IN

OUT

NC

VFB

LX2

LX1

LX0

SYNCH

PG

SGND PGND THRM_PAD

VINVDD

EN

VSW

PGND

TGR

TG

BG

VIN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(DDRREG_DRVH)

<Ra>

VTTREF

Vout = VTTREF

1.8 V SUPPLY

(DDRREG_FB)

(DDRREG_VDDQSNS)

VDDQ/VTTREF Enable


PPDDR_S3_REG

PEAK = 11A

Vout = 0.75V * (1 + Ra / Rb)

1A Average current

VDDQ PGOOD

S5

<Ra>

<Rb>

AVG = 6.7A

EMC CAPSPLACE CLOSE TO L7830

<Rb>

LO

S0

S5S3

STATEHIHILO

LO

HI

OFF

ON

OFFON ON

ON ONOFF

VDDQ VTT

(DDRREG_CSGND)

FEEDBACK THROUGH SHORTSHOULD NOT NEED TP

Vout = VDDQSNS/2

Vo=0.8*(1+ Ra/Rb)

10mA max load

(NOT USED)

OFF

CONTINUOUS MODE

Vo=0.8*(1+ 59/47)=1.804V

VOUT = 1.5V

S3

1.5 V DDR SUPPLY

(DDRREG_DRVL)

(DDRREG_LL)

PLACE CLOSE TO FETEMC CAPS

VTT Enable

2

1 C7837

X5R

10UF20%6.3V

603

2

1C78411000PF

25V5%

402NP0-C0G

NOSTUFF

2

1 C7832

16V

0805

10%10UF

X5R-CERM

2

1R7831NOSTUFF

0.499

603MF1/10W1%

21

XW7831SM

OMITPLACEMENT_NOTE=PLACE NEXT TO Q7831

21

C7840

25V

603

0.1UF

CERM

20%

21

R7840

MF-LF

5%

0

603

1/10W

2

1 C7815

6.3VX5R

20%

603

10UF

2

1 C7839

50VX7R402

0.001UF10%

2

1R78103.57K

1%1/16WMF-LF

402

2

5

1

24

23

8

9

22

15

14

25

11

10

13

18

12

7

4

20

3

19

21

17

16

6

U7800

QFN

CRITICAL

TPS51116

2

1

XW7801OMITSM

2

1

XW7800SM

OMIT

2

1C7801

10%1UF

10VX5R402

21

R7801

402MF-LF1/16W5%

4.7

2

1C7805

10%0.033UF

402X5R16V

2

1C7800

603CERM6.3V

4.7UF20%

21

XW7803OMIT

SM

2

1 C780322UF

CERM-X5R805-3

CRITICAL

20%6.3V2

1C7804

CERM-X5R805-3

22UF20%

6.3V

CRITICAL

32 63 97

63 97

2

1 R7854

MF-LF402

1/16W5%100K

2

1

XW7830

PLACEMENT_NOTE=PLACE NEXT TO L7830

OMIT

SM

21

L7850CRITICAL

MMD04BZ-SM

1.5UH-4A

2

1R7851

1/16W 1%402

47.0K

MF-LF

2

1R7850

1/16W4021%

MF-LF

59.0K

2

1

C7850 5%

CERM

50V

402

47PF

2

1R783215.0K

MF-LF1/16W1%

402

5 63 97

2

1C7820100PF

402CERM

5%50V

NOSTUFF

2

1C7830

8X9-TH1

270UF16V

ELEC

20%

CRITICAL

2

1C7831

8X9-TH1

270UF20%16V

ELEC

CRITICAL

2

1 C783520%

CRITICAL

2.5VPOLY-TANT

330UF

CASE-D2E-SM32

1 C783620%

CRITICAL

2.5VPOLY-TANT

330UF

CASE-D2E-SM3

21

8

317

4

109

12

11

7

16

6

15

14

13

5

U7850QFN

ISL8013A

CRITICAL

2

1 R7853

402

5%1/16WMF-LF

100K

8

7

6

1

4

3

9

5

Q7830CRITICAL

SON5X6CSD58864Q5D

2

1R7833

1/16W

402

15.0K1%

MF-LF

2

1 C7854

X5R-CERM-1

22UF

603

6.3V20%

2

1 C7855

X5R-CERM-1603

20%22UF6.3V

2

1 C7852

6.3V20%22UF

603X5R-CERM-1 2

1 C7853

603

22UF6.3V20%

X5R-CERM-1

2

1R7820

MF-LF

10K5%

1/16W

402

2

1 R7860

5%1/16WMF-LF

100K

NOSTUFF

402

21

R7841

1/10W

603MF-LF

5%

4.7

21

L7830CRITICAL

1.5UH-15%-22A-3.3MOHM

SDP1182M-TH

2

1 C7833

603

1UF10%16VX5R 2

1 C7834

X5R16V10%1UF

603

2

1 C7838

50VX7R402

0.001UF10%


1.5V / 1.8V VREGS

NET_PHYSICAL_TYPE=POWERMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmPP5V_S3_DDR_REG_V5FILT

VOLTAGE=5V

PP1V5_S3_REGNET_PHYSICAL_TYPE=POWER


DDR_REG_CS

DDR_REG_UGATE_R

DIDT=TRUEMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

VR_CTL


DDR_REG_PHASEDIDT=TRUE



NET_SPACING_TYPE=VR_CONTROLDDR_REG_UGATE

DIDT=TRUE

DDR_REG_VDDQSNS


AGND_DDR_REG


VOLTAGE=0VMIN_NECK_WIDTH=0.2 mm


=PP5V_S3_DDR_VREGNET_PHYSICAL_TYPE=POWER

=PP12V_S5_DDR_VREG


DIDT=TRUE

1V5_SNUBBER


DIDT=TRUE



DIDT=TRUE


DDR_REG_PHASE_R


DDR_REG_LGATE

MIN_NECK_WIDTH=0.2 mmNET_SPACING_TYPE=VR_CONTROL DIDT=TRUEMIN_LINE_WIDTH=0.6 mm


DDR_REG_BOOT


DIDT=TRUE

TP_PPVTT_S3_DDR_BUF


PP1V8_S0_REGPM_EN_P1V8_S0_REG



=PP3V3_S3_VRD

DDR_REG_VTTSNSNO_TEST=TRUE


DDR_REG_PGND

DIDT=TRUE


DDR_REG_BOOT_R


P1V8_REG_SYNC

=PP5V_S0_P1V8_REG

SWITCHNODEDIDT=TRUE

P1V8_REG_PHASE


P1V8_REG_VFB

DDR_REG_FB

PM_EN_DDRVTT_S0_REGPM_EN_DDR1V5_S3_REG

PPVTT_S0_DDR_LDO

DDR_REG_CSGND


78 OF 110

11.1.0

051-8115

71 OF 98

95

6

95

95

95

95

6

6

95

95

95

95

6 63 97

64 97

6

95

95

95

95

6

95

95

95

6

95

www.vinafix.vn

SW

BOOSTVIN

BIAS

SHDN*

GND

NC

FB

PADTHRM

NC




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Vout = 1.25V * (1 + Ra / Rb)

353S2171

(Switcher limit)

Vout = 3.425

<Rb>

250mA max output

<Ra>

Supply needs to guarantee 3.31V delivered to SMC VRef generator

3.425V "G3Hot" Supply

2

1C791010UF

X5R

10%25V

805

6

9

48

5

1

3

2

U7900DFN

LT3470A

CRITICAL

2

1C7900

6.3V20%

402X5R

0.22UF

21

L7900

CDPH4D19FHF-SM

33UH

CRITICAL

2

1R7901

402MF-LF1/16W

1%200K

2

1C790122pF

50V

402

5%

CERM2

1R7900348K

402

1%1/16WMF-LF

2

1 C790222UF6.3V20%

603X5R-CERM-1

2

1 C7911

402

25VNP0-C0G

1000PF5%

2

1R79106.98K

MF-LF1/16W

1%

402

2

1R79111%

MF-LF1/16W

402

2.1K

SYNC_MASTER=K62

3.42 G3HOT SUPPLYSYNC_DATE=01/06/2011

3V42G3H_SHDN_L

NET_SPACING_TYPE=POWER=PP12V_G3H_3V42

PP3V42_G3H_REG

P3V42G3H_FB

DIDT=TRUE

P3V42G3H_SW

SWITCH_NODE=TRUE




P3V42G3H_BOOST

79 OF 110

11.1.0

051-8115

72 OF 98

7

97

6

6

95

95

95

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G

D S

G

D S

G

D S

G

D S

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

IN

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

IN

IN

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

3.3V S0 FET (2.9APK / 2.0A AVG) 3.3V S3 FET (3.4A PK / 1.6A AVG)

1.5V S0 FET (4.8A PK / 4.8A AVG)

5V S0 FET (6.6A PK/3.1A AVG)

2

1 C8050

402

0.1UF10%

X5R16V

1

4

5

Q8000IRFH3702TRPBF

PQFN

CRITICAL

1

4

5

Q8053CRITICAL

PQFN

IRFH3702TRPBF

1

4

5

Q8050IRFH3702TRPBF

PQFN

CRITICAL

1

4

5

Q8025IRFH3702TRPBF

PQFN

CRITICAL

1

9

6

8

2

4

7

5

U8053SLG5AP001

CRITICAL

TDFN

63 97

2

1 C80000.1UF10%16VX5R402

1

9

6

8

2

4

7

5

U8000SLG5AP001

TDFN

CRITICAL

2

1 C8025

402

10%

X5R16V

0.1UF

1

9

6

8

2

4

7

5

U8025TDFN

CRITICAL

SLG5AP001

63 97

63 97

2

1 C80530.1UF

402

10%

X5R16V

1

9

6

8

2

4

7

5

U8050SLG5AP001

TDFN

CRITICAL

2

1R8000NOSTUFF

402

5%1/16W

10K

MF-LF

2

1R805010K

402

5%1/16WMF-LF

2

1R8051

MF-LF1/16W5%

402

10K

2

1R8020

402MF-LF

10K1/16W5%

63 97


S3+S0 FETSSYNC_MASTER=K62

=PP3V3_S0_PWRCTL

PM_PGOOD_P5V_S0_FET

=PP1V5_S3_S0FET PP1V5_S0_FET

P1V5_S0_EN_G

P3V3_S3_EN_G

PP3V3_S3_FET

=PP3V3_S5_S3FET

PP3V3_S0_FET

P3V3_S0_EN_G

=PP3V3_S5_S0FET

=PP5V_S3_S0FET

PP5V_S0_FET

P5V_S0_EN_G

=PP12V_S5_PWRCTL


=PP12V_S5_PWRCTL

=PP3V3_S0_PWRCTL

PM_EN_P1V5_S0_FET


PM_EN_P3V3_S0_FET

PM_EN_P5V_S0_FET

=PP3V3_S3_PWRCTL

=PP12V_S5_PWRCTL

=PP12V_S5_PWRCTL

=PP3V3_S0_PWRCTL

PM_EN_P3V3_S3_FET


80 OF 110

11.1.0

051-8115

73 OF 98

3

3

3

3

6 63 64 73 80

63 64 97

6 6

6

6

6

6

6

6

6 33 64 73

11 64 97

6 33 64 73

6 63 64 73 80

63 64 97

6 64 82

6 33 64 73

6 33 64 73

6 63 64 73 80

34 97

www.vinafix.vn

NC

NC

G S

D

G

DS




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Proto-3:Add C8111

376S0933P-CH MOSFET 376S0933 4.6-MOHM 20A (WHEN USED W/Q8112)

10Amp-7Amp

Short R8132 BEFORE DVT

(2.4-5.5V)High=3.3V

43

21

R8132

MF1W

2512

0.0051%

2

1 C8110

X7R805-1

0.47UF10%16V

21

R8111

1/16W5%

MF-LF402

10K

2

1R811010K1/16W

5%

MF-LF402

2

1

3

Q8112SOT23-HF12N7002

2

1R8112

402MF-LF1/16W

5%10K

21

R8113

MF-LF1/16W

402

0

5%

1

4

5

Q8110

CRITICALPQFNIRFH9310PBF

2

1R8115

1/16W

402

5%100K

MF-LF

2

1C8111

805

2.2UF10%16V

X7R-CERM


12V_S0 & 12V_S5 switchSYNC_MASTER=K60_JERRY

PP12V_S5_FETMIN_LINE_WIDTH=1mmMIN_NECK_WIDTH=0.5mm

NET_PHYSICAL_TYPE=POWERVOLTAGE=12V

PP12V_S5_RSN

SMC_PM_G2_EN SMC_PM_G2_EN_R

S5_DG_1

SMC_PM_G2_EN_L

S5_MSFT_G1

=PP12V_G3H_S5_FET

81 OF 110

11.1.0

051-8115

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6 95 95

46 97 97

97

97

97

6

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3V3

5V

PWR_SRC

(4 OF 4)

PCI-E

DP

(2 OF 4)

PEX_TX15*

DP_A_AUX*

PEX_TX1*

PEX_TX13

PEX_TX11*

PEX_TX7*

PEX_TX8*

PEX_TX9

PEX_TX10

PEX_STD_SW*

PEX_TX15

PEX_TX14*

PEX_TX14

PEX_TX13*

PEX_TX12*

PEX_TX12

PEX_TX11

PEX_TX10*

PEX_TX9*

PEX_TX8

PEX_TX7

PEX_TX6*

PEX_TX6

PEX_TX5*

PEX_TX5

PEX_TX4*

PEX_TX4

PEX_TX3*

PEX_TX3

PEX_TX2*

PEX_TX2

PEX_TX1

PEX_TX0*

PEX_TX0

PEX_REFCLK*

PEX_REFCLK

PEX_RST*

DP_C_HPD

DP_D_HPD

DP_B_HPD

DP_A_HPD

PEX_RX15*

PEX_RX15

PEX_RX14*

PEX_RX14

PEX_RX13*

PEX_RX13

PEX_RX12*

PEX_RX12

PEX_RX11*

PEX_RX11

PEX_RX10*

PEX_RX10

PEX_RX9*

PEX_RX9

PEX_RX8*

PEX_RX8

PEX_RX7*

PEX_RX7

PEX_RX6*

PEX_RX6

PEX_RX5*

PEX_RX5

PEX_RX4*

PEX_RX4

PEX_RX3*

PEX_RX3

PEX_RX2*

PEX_RX2

PEX_RX1*

PEX_RX1

PEX_RX0*

PEX_RX0

CLK_REQ*

DP_C_L0*

DP_C_L0

DP_C_L1*

DP_D_L0*

DP_C_L1

DP_D_L0

DP_C_L2*

DP_D_L1*

DP_C_L2

DP_D_L1

DP_C_L3*

DP_D_L2*

DP_C_L3

DP_D_L2

DP_D_L3*

DP_D_L3

DP_B_L0*

DP_B_L0

DP_B_L1*

DP_A_L0*

DP_B_L1

DP_A_L0

DP_B_L2*

DP_A_L1*

DP_B_L2

DP_A_L1

DP_B_L3*

DP_A_L2*

DP_B_L3

DP_A_L2

DP_A_L3*

DP_A_L3

DP_C_AUX*

DP_C_AUX

DP_D_AUX*

DP_D_AUX

DP_B_AUX*

DP_B_AUX

DP_A_AUX




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Page Notes

VOLTAGE CURRENT POWER


- MXM

- =PPV_S0_MXM_PWRSRC


(NONE)

- =PP3V3_S0_MXM


(NOT NECESSARILY THE SAME FOR EVERY MODULE)

MXM SPEC POWER REQUIREMENTS

5V

3V3

PWR (7-20V) UP TO 10 A

2.5 A

1.0 A 3.3 W

12.5 W

PLATFORM DEPENDENT

DP B

DP C

DP D

DP E EXT DP2

INT DPINT DP

DP A EXT DP1

T29 DP1 T29 DP1

T29 DP2 T29 DP2

EXT DP1

K62 K60

MXM DP PORT ROUTING

- =PP5V_S0_MXM

APPLE P/N: 516S0699

2

1C840022UF

35VELEC

6.3X5.5-SM1

20%

MXM

2

1 C8401

805-3CERM-X5R

MXM

6.3V20%22UF

2

1C8410

50V

402X7R

10%

MXM

0.001UF

2

1 C84120.001UF50V

402

10%

X7R

MXM

2

1 C84130.001UF50V10%

X7R402

MXM

2

1 C84140.001UF50V

402

10%

X7R

MXM

2

1R8400MXM

MF-LF1/16W

402

100K5%

2

1 C8416

805-3CERM-X5R

MXM

6.3V20%22UF

2

1 C841510%

X7R402

50V

0.001UF

MXM

E2

E1

9

7

5

3

1

280

278

J8400F-RT-SM

B35P101-0121

MXM

84

86

90

92

96

98

102

104

108

110

114

116

120

122

136

138

48

50

54

56

60

62

66

68

72

74

78

80

142

144

148

150

19

85

87

91

93

97

99

103

105

109

111

115

117

121

123

135

137

49

51

55

57

61

63

67

69

73

75

79

81

141

143

147

149

156

153

155

224

226

218

220

212

214

206

208

236

230

232

217

219

211

213

205

207

199

201

234

223

225

264

266

258

260

252

254

246

248

274

270

272

271

273

265

267

259

261

253

255

276

277

279

154

J8400F-RT-SM

B35P101-0121

MXM

CRITICAL

SYNC_MASTER=K62

MXM PCIe, DP & PowerSYNC_DATE=01/06/2011

MXM_DP_A_ML_N<2>

MXM_DP_A_ML_P<1>

MXM_DP_A_ML_P<0>

MXM_DP_A_ML_N<0>

MXM_RESET_L

MXM_DP_C_ML_N<0>

MXM_DP_C_ML_P<0>

MXM_DP_C_ML_P<1>

MXM_DP_C_ML_N<3>

MXM_DP_D_ML_N<1>

MXM_PCIE_STD_SWING_L

MXM_PCIE_D2R_P<1>

MXM_PCIE_D2R_N<6>

MXM_PCIE_D2R_N<10>

MXM_PCIE_D2R_N<11>

MXM_DP_A_ML_N<1>

MXM_DP_A_ML_P<2>

MXM_PCIE_D2R_N<2>

MXM_PCIE_D2R_N<9>

MXM_PCIE_D2R_P<7>

MXM_PCIE_D2R_P<5>

MXM_PCIE_D2R_N<5>

MXM_PCIE_D2R_P<6>

MXM_PCIE_D2R_P<12>

MXM_PCIE_D2R_N<12>

MXM_PCIE_D2R_N<13>

MXM_PCIE_D2R_P<15>

MXM_PCIE_D2R_P<10>

MXM_PCIE_D2R_P<9>

MXM_PCIE_D2R_N<8>

MXM_PCIE_D2R_P<4>

MXM_PCIE_D2R_N<7>

MXM_PCIE_D2R_P<11>

MXM_PCIE_D2R_P<13>

MXM_PCIE_D2R_N<14>

MXM_PCIE_D2R_P<14>

MXM_PCIE_D2R_N<15>

MXM_PCIE_D2R_P<8>

MXM_PCIE_D2R_P<3>

MXM_PCIE_D2R_N<4>

MXM_PCIE_D2R_P<2>

MXM_PCIE_D2R_N<1>

MXM_PCIE_D2R_P<0>

MXM_PCIE_D2R_N<0>

MXM_PCIE_R2D_N<2>

MXM_PCIE_R2D_P<2>

MXM_PCIE_R2D_P<3>

MXM_PCIE_R2D_N<3>

MXM_PCIE_R2D_N<4>

MXM_PCIE_R2D_N<5>

MXM_PCIE_R2D_P<5>

MXM_PCIE_R2D_N<6>

MXM_PCIE_R2D_P<8>

MXM_PCIE_R2D_N<1>

MXM_PCIE_R2D_P<10>

MXM_PCIE_R2D_N<10>

MXM_PCIE_R2D_N<9>

MXM_PCIE_R2D_N<8>

MXM_PCIE_R2D_P<6>

MXM_PCIE_R2D_P<0>

MXM_PCIE_R2D_N<11>

MXM_PCIE_R2D_P<12>

MXM_PCIE_R2D_P<13>

MXM_PCIE_R2D_P<14>

MXM_PCIE_R2D_N<14>

MXM_PCIE_R2D_P<15>

MXM_PCIE_R2D_N<15>

MXM_PCIE_R2D_P<7>

MXM_PCIE_R2D_P<11>

MXM_PCIE_R2D_N<13>

MXM_PCIE_R2D_N<12>

MXM_PCIE_R2D_P<9>

MXM_PCIE_R2D_P<1>

MXM_PCIE_R2D_P<4>

MXM_PCIE_R2D_N<7>

MXM_PCIE_R2D_N<0>

MXM_DP_C_AUX_P

MXM_DP_B_ML_N<0>

MXM_CLKREQ_L

MXM_DP_B_AUX_P

MXM_DP_B_HPD

MXM_DP_B_ML_P<0>

CLK_100M_MXM_N

CLK_100M_MXM_P

MXM_DP_C_HPD

MXM_DP_D_HPD

MXM_DP_A_HPD

MXM_DP_C_ML_N<1>

MXM_DP_D_ML_N<0>

MXM_DP_D_ML_P<0>

MXM_DP_C_ML_N<2>

MXM_DP_C_ML_P<2>

MXM_DP_D_ML_P<1>

MXM_DP_D_ML_N<2>

MXM_DP_C_ML_P<3>

MXM_DP_D_ML_P<2>

MXM_DP_D_ML_N<3>

MXM_DP_D_ML_P<3>

MXM_DP_B_ML_N<1>

MXM_DP_B_ML_P<1>

MXM_DP_B_ML_N<2>

MXM_DP_B_ML_P<2>

MXM_DP_B_ML_N<3>

MXM_DP_B_ML_P<3>

MXM_DP_C_AUX_N

MXM_DP_D_AUX_N

MXM_DP_D_AUX_P

MXM_DP_B_AUX_N

=PP3V3_S0_MXM

MXM_DP_A_AUX_N

MXM_DP_A_AUX_P

MXM_PCIE_D2R_N<3>

MXM_DP_A_ML_N<3>

MXM_DP_A_ML_P<3>

=PP3V3_S0_MXM

=PP12V_S0_MXM

=PP5V_S0_MXM

84 OF 110

11.1.0

051-8115

75 OF 98

78

78

78

78

9

83 93

83 93

83 93

83 93

78 93

76

77 90

77 90

77 90

77 90

78

78

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

77 90

83 93

78 93

9 97

78 93

78

78 93

9

9

83

78

78

83 93

78 93

78 93

83 93

83 93

78 93

78 93

83 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

83 93

78 93

78 93

78 93

6 21 64 75 76

78

78

77 90

78

78

6 21 64 75 76

6

6

www.vinafix.vn

GPIO0

VGA_DISABLE*

TH_OVERT*

TH_PWM

LVDS_DDC_CLK

LVDS_UTX1

LVDS_UTX2*

RSVD1

PNL_PWR_EN

LVDS_UTX1*

RSVD2

LVDS_UTX2

LVDS_UTX3*

LVDS_LCLK

PRSNT_R*

LVDS_LTX3

DVI_HPD

PWR_EN

SMB_CLK

LVDS_LTX0

LVDS_LTX0*

LVDS_LTX1

LVDS_LTX2

LVDS_LTX2*

LVDS_LTX3*

LVDS_UTX0

LVDS_UTX0*

LVDS_UTX3

PNL_BL_EN

PRSNT_L*

PWRGOOD

VGA_BLUE

VGA_GREEN

VGA_HSYNC

VGA_RED

VGA_VSYNC

VGA_DDC_DAT

GPIO1

GPIO2

HDMI_CEC

OEM0

OEM1

OEM2

OEM3

OEM4

OEM5

OEM7

VGA_DDC_CLK

RSVD3

RSVD4

RSVD5

RSVD7

RSVD8

RSVD9

RSVD10

RSVD11

RSVD12

RSVD13

RSVD14

RSVD15

RSVD16

RSVD17

RSVD18

RSVD19

RSVD21

SMB_DAT

TH_ALERT*

LVDS_UCLK*

LVDS_UCLK

RSVD20

LVDS_LCLK*

LVDS_LTX1*

RSVD6

RSVD0

RSVD22

RSVD23

PWR_LEVEL

LVDS_DDC_DAT

PNL_BL_PWM

OEM6

WAKE*

SYSTEM MANAGEMENT

(1 OF 4)

LVDS

ANALOG DISPLAY

POWER/THERMAL

MANAGEMENT

GNDGND

(3 OF 4)

SCL

THRM_PAD

E0

E1

E2VSS

SDA

VCC

WC*




36

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DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

I2C ADDRESS: A8

- =PP3V3_S0_MXM

STUFF FOR WRITE PROTECT

PLACE CLOSE TO J8400

FLOAT = LOW SWINGGND = HIGH SWING


Page NotesPower aliases required by this page:

- =PM_MXM_PGOOD_PULLUP

PULLED TO GROUND ON MXMWE DON’T USE CARD DETECT

OR ANOTHER OPEN-DRAIN PGOOD SIGNAL DEPENDING ON DESIRED BEHAVIOR

SYSTEM INTEGRATOR MUST ALIAS THIS EITHER TO A VOLTAGE RAIL,

- =SMB_MXM_THRM_DATA PULLUPS & PULLDOWNS AT MXM CONNECTOR

FLOAT = NORMAL VGA MODEGND = SECONDARY DISPLAY CARD


- =SMB_MXM_THRM_CLK

MXM SYSTEM INFORMATION ROM

2

1R8570

1/16W5%

NOSTUFF

0

MF-LF402

2

1 C85700.1UF

402CERM

20%10V

MXM

21

R8500100K

1/16W5%402

MF-LF

21

R8501100K

5%MF-LF 1/16W402

2 1

R8503

402

MF-LF 5%

10K

1/16W

4

162

168

164

170

21

158

160

172

24

20

22

32

34

231

229

227

167

165

163

161

16

14

249

247

12

245

243

242

241

240

239

238

237

235

233

159

10

6

18

8

2

281

23

27

25

45

44

43

42

41

40

39

38

175

177

181

183

187

189

193

195

169

171

182

184

188

190

194

196

200

202

176

178

33

35

29

30

28

2631

J8400B35P101-0121

MXM

F-RT-SM

53

52

283

282

E4

275

269

268

263

47

262

257

256

251

250

E3

244

228

222

221

46

216

215

210

209

204

203

198

197

192

191

37

186

185

180

179

174

173

166

157

152

151

36

146

145

140

139

134

133

125

124

119

118

17

113

112

107

106

101

100

95

94

89

88

15

83

82

77

76

71

70

65

64

59

58

13

11

J8400F-RT-SM

MXM

B35P101-0121

2 1

R8504MXM

0

402

5%MF-LF 1/16W

2 1

R8510NOSTUFF

0

5%

402

MF-LF 1/16W

7

4

89

5

6

3

2

1

U8570

OMIT

M24C02MLP8

CRITICAL

2

1R85754.7K

MF-LF1/16W

5%

4022

1R8576

402

5%1/16WMF-LF

4.7K

2

1R85794.7K

402MF-LF

NOSTUFF

5%1/16W

2

1R8580

1/16W5%

4.7K

MF-LF

NOSTUFF

402

SYNC_MASTER=K60_MASTER

MXM I/OSYNC_DATE=N/A

=PP3V3_S0_MXM

MXM_PNL_PWR_EN

TP_MXM_N_TDI

TP_MXM_N_TCK

TP_MXM_N_TMS

MXM_A_TESTEN

TP_MXM_A_TDO

TP_MXM_A_TRST_L

MXM_PNL_BL_PWM

TP_MXM_A_TCK

TP_MXM_N_TRST_L

=PP3V3_S0_MXM

TP_MXM_VGA_DDC_DAT

TP_MXM_N_TDO

=PP3V3_S0_MXM

TP_MXM_A_TDI

TP_MXM_A_TMS

MXM_LVDS_A_CLK_P

MXM_PNL_BL_EN

TP_MXM_HDMI_CEC

MXM_VGA_DISABLE_L

TP_MXM_GPIO0

MXM_LVDS_DDC_DAT

MXM_DETECT_L

TP_MXM_WAKE_L

PM_MXM_PGOOD

MXM_VGA_DISABLE_L

MXM_PCIE_STD_SWING_L

MXM_DETECT_R

MXM_LVDS_A_DATA_N<0>

MXM_LVDS_A_DATA_P<0>

MXM_DETECT_L

PM_MXM_EN

MXM_PWR_LEVEL

=SMB_MXM_THRM_SCL

=SMB_MXM_THRM_SDA






MXM_LVDS_B_CLK_P

MXM_LVDS_B_CLK_N

MXM_LVDS_B_DATA_P<3>

MXM_LVDS_B_DATA_N<3>







PM_MXM_PGOOD


TP_MXM_VGA_BLUE

TP_MXM_VGA_RED

TP_MXM_VGA_DDC_CLK

MXM_LVDS_A_CLK_N

TP_MXM_DVI_HPD

MXM_LVDS_DDC_DAT

MXM_LVDS_DDC_CLK

TP_MXM_GPIO1

TP_MXM_GPIO2

=PM_MXM_PGOOD_PULLUP

MXM_ALERT_L

MXM_OVERT_L

TP_MXM_VGA_VSYNC

TP_MXM_VGA_HSYNC

TP_MXM_TH_PWM

TP_MXM_VGA_GREEN

MXM_DETECT_R

MXM_ROM_WP

MXM_LVDS_DDC_CLK

85 OF 110

11.1.0

051-8115

76 OF 98

6 21 64 75 76

78

83 97

6 21 64 75 76

6 21 64 75 76

78 93

78

76

76

76

64 76 97

76

75

76

78 93

78 93

76

64 97

47

49

49

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

78 93

64 76 97

78 93

78 93

76

76

64

47

47

76

76

www.vinafix.vn

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

MXM TX CAPS MXM RX CAPS

9 90

21C8636 10% X5R0.1UF 40216VMXM

75 90

75 90

21C8600 40216V0.1UF X5R10%MXM

21C8602 402X5R10% 16V0.1UFMXM

21C8601 0.1UF 16V X5R10% 402MXM

21C8604 10%0.1UF X5R 40216VMXM

21C8603 0.1UF 402X5R10% 16VMXM

9 90

9 90

9 90

75 90

9 90

9 90

21C8605 10% 4020.1UF X5R16VMXM75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

21C8606 10% 16V 4020.1UF X5RMXM

21C8607 X5R10% 16V0.1UF 402MXM

21C8608MXM 16V X5R 4020.1UF 10%

21C8609 10% 16V X5R 4020.1UFMXM

21C8610 0.1UF 16V10% X5R 402MXM

21C8611 0.1UF 10% 16V X5R 402MXM

21C8612 10% X5R0.1UF 40216VMXM

21C8613 10% 16V X5R 4020.1UFMXM

21C8614 16V10% X5R 4020.1UFMXM

21C8615 16V10% X5R 4020.1UFMXM

75 90

21C8616 0.1UF 16V10% X5R 402MXM

21C8618 16V10% X5R 4020.1UFMXM

21C8617 16V10% X5R 4020.1UFMXM

21C8620 16V10% X5R 4020.1UFMXM

21C8619 10% X5R 4020.1UFMXM 16V

21C8622 0.1UF 402X5R10% 16VMXM

21C8621 16V10% X5R 4020.1UFMXM

9 90

9 90

9 90

21C8637 10%0.1UF X5R 40216VMXM

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

21C8623 0.1UF 402X5R10% 16VMXM

21C8624 16V10% X5R 4020.1UFMXM

21C8625 16V10% X5R 4020.1UFMXM

21C8626 0.1UF 402X5R10% 16VMXM

21C8628 402X5R10% 16V0.1UFMXM

9 90

21C8627 0.1UF 402X5R10% 16VMXM

21C8630 0.1UF 402X5R10% 16VMXM

21C8629 0.1UF 402X5R10% 16VMXM

21C8631 0.1UF 402X5R10% 16VMXM

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

9 90

21C8638 0.1UF X5R10% 40216VMXM

21C8639 0.1UF 402X5R10% 16VMXM

21C8641 0.1UF 16V 402X5R10%MXM

21C8640 0.1UF 40210% X5R16VMXM

21C8642 0.1UF 402X5R10% 16VMXM

21C8643 402X5R10% 16V0.1UFMXM

9 90

21C8644 0.1UF 402X5R10% 16VMXM

21C8645 402X5R10% 16V0.1UFMXM

21C8646 0.1UF 402X5R10% 16VMXM

21C8647 0.1UF 10% 16V 402X5RMXM

21C8648 0.1UF 16V10% X5R 402MXM

21C8649 40216V10% X5R0.1UFMXM

21C8652 16V10% X5R 4020.1UFMXM

21C8653 16V10% X5R 4020.1UFMXM

21C8651 0.1UF 16V10% X5R 402MXM

21C8650 0.1UF 16V10% X5R 402MXM

21C8632 0.1UF 40210% 16V X5RMXM

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

21C8633 0.1UF 40210% 16V X5RMXM

75 90

75 90

75 90

75 90

75 90

75 90

75 90

21C8654 16V10% X5R0.1UF 402MXM

21C8655 16V10% X5R0.1UF 402MXM

21C8657 16V X5R 4020.1UF 10%MXM

21C8635 16V10% 4020.1UF X5RMXM

21C8656 10% X5R 4020.1UF 16VMXM

21C8658MXM 16V10% X5R 4020.1UF

21C8662 16V X5R10% 402MXM 0.1UF

21C8663 16V10% X5R 4020.1UFMXM

21C8660 16V X5R 40210%0.1UFMXM

21C8659 16V10% X5R 4020.1UFMXM

21C8661 16V10% X5R 4020.1UFMXM

75 90

75 90

75 90

21C8634 16V 40210%0.1UF X5RMXM

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

75 90

SYNC_MASTER=K62

MXM PCIE CAPSSYNC_DATE=01/06/2011

PEG_R2D_C_N<1>

PEG_R2D_C_N<2>

PEG_R2D_C_P<3>

MXM_PCIE_R2D_P<9>

MXM_PCIE_R2D_P<8>

MXM_PCIE_D2R_P<3>

MXM_PCIE_D2R_N<3>

MXM_PCIE_D2R_P<2>

PEG_D2R_P<14>

MXM_PCIE_D2R_N<5>

PEG_R2D_C_P<4>

MXM_PCIE_R2D_N<14>

PEG_R2D_C_P<11>

PEG_R2D_C_N<13>

PEG_R2D_C_N<15>

MXM_PCIE_R2D_P<11>

MXM_PCIE_R2D_N<11>

MXM_PCIE_D2R_N<15>

PEG_D2R_N<0>

PEG_D2R_N<3>

PEG_D2R_N<12>

PEG_D2R_N<10>

PEG_R2D_C_N<5>

MXM_PCIE_D2R_P<4>

MXM_PCIE_D2R_N<1>

MXM_PCIE_D2R_P<0>

MXM_PCIE_D2R_N<0>

MXM_PCIE_D2R_P<1>

MXM_PCIE_D2R_P<13>

MXM_PCIE_D2R_N<13>

MXM_PCIE_D2R_P<12>

MXM_PCIE_D2R_N<12>

PEG_R2D_C_N<0>

MXM_PCIE_R2D_P<14>

MXM_PCIE_R2D_N<10>

PEG_R2D_C_P<13>

PEG_R2D_C_P<14>

PEG_R2D_C_N<14>

PEG_R2D_C_P<15>

MXM_PCIE_R2D_P<15>

MXM_PCIE_R2D_N<12>

MXM_PCIE_D2R_N<14>

MXM_PCIE_D2R_P<14>

MXM_PCIE_R2D_P<10>

PEG_R2D_C_P<10>

MXM_PCIE_R2D_P<5>

PEG_D2R_P<4>

PEG_R2D_C_N<12>

PEG_R2D_C_P<12>

PEG_R2D_C_N<10>

PEG_R2D_C_P<5>

PEG_R2D_C_P<6>

PEG_R2D_C_N<6>

PEG_R2D_C_P<7>

PEG_R2D_C_P<8>

PEG_R2D_C_N<8>

PEG_R2D_C_N<11>

PEG_R2D_C_N<9>

PEG_R2D_C_P<9>

PEG_R2D_C_N<7>

MXM_PCIE_R2D_N<5>

MXM_PCIE_R2D_P<4>

MXM_PCIE_R2D_N<4>

MXM_PCIE_R2D_P<3>

MXM_PCIE_R2D_P<2>

MXM_PCIE_R2D_N<2>

MXM_PCIE_R2D_N<1>

MXM_PCIE_R2D_N<0>

MXM_PCIE_R2D_N<9>

MXM_PCIE_R2D_N<8>

MXM_PCIE_R2D_P<7>

MXM_PCIE_R2D_N<7>

MXM_PCIE_R2D_P<0>

MXM_PCIE_D2R_P<8>

MXM_PCIE_D2R_P<7>

MXM_PCIE_D2R_P<5>

MXM_PCIE_D2R_N<8>

MXM_PCIE_D2R_N<9>

MXM_PCIE_D2R_P<9>

MXM_PCIE_D2R_N<10>

MXM_PCIE_D2R_P<10>

MXM_PCIE_D2R_N<11>

MXM_PCIE_D2R_P<11>

PEG_D2R_P<7>

PEG_D2R_P<12>

PEG_D2R_N<6>

PEG_D2R_N<7>

PEG_D2R_P<10>

PEG_D2R_N<4>

PEG_D2R_N<9>

PEG_D2R_P<9>

PEG_D2R_N<11>

PEG_D2R_P<13>

PEG_D2R_N<13>

PEG_D2R_P<15>

PEG_D2R_N<15>

PEG_D2R_P<5>

PEG_D2R_N<5>

PEG_D2R_P<11>

PEG_D2R_P<6>

PEG_D2R_P<2>

PEG_D2R_N<2>

MXM_PCIE_R2D_N<13>

PEG_D2R_P<3>

MXM_PCIE_D2R_N<4>

MXM_PCIE_D2R_P<15>

PEG_D2R_P<1>

PEG_D2R_N<1>

PEG_D2R_P<0>

MXM_PCIE_D2R_N<7>

MXM_PCIE_D2R_N<6>

MXM_PCIE_D2R_P<6>

PEG_D2R_P<8>

PEG_D2R_N<8>

PEG_R2D_C_P<0>

PEG_R2D_C_N<4>

PEG_R2D_C_N<3>

PEG_R2D_C_P<2>

PEG_R2D_C_P<1>

MXM_PCIE_R2D_P<1>

MXM_PCIE_R2D_N<3>

MXM_PCIE_R2D_N<6>

MXM_PCIE_R2D_P<6>

MXM_PCIE_R2D_N<15>

MXM_PCIE_R2D_P<13>

MXM_PCIE_R2D_P<12>

MXM_PCIE_D2R_N<2>

PEG_D2R_N<14>

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Unused T29 InterfacesUNUSED MXM CONTROL SIGNALS

T29 MXM DP ALIAS

T29 CONN POWER CONTROL ALIAS

Unused MXM Interfaces

MXM ALIAS



(NONE)


(NONE)

Page Notes

DDC/AUX ALIAS


DP ALIAS AND CONTROLSYNC_DATE=07/18/2010

DP_EXTA_AUXCH_C_PMAKE_BASE=TRUE

DP_EXTA_DDC_DATADP_EXTA_AUXCH_C_NMAKE_BASE=TRUE

DP_EXTA_DDC_CLK

NC_MXM_LVDS_A_DATA_N<3..0>NO_TEST=TRUEMAKE_BASE=TRUE

NC_MXM_LVDS_B_DATA_N<3..0>NO_TEST=TRUEMAKE_BASE=TRUE

NC_MXM_LVDS_B_DATA_P<3..0>NO_TEST=TRUEMAKE_BASE=TRUE

NC_MXM_PNL_PWR_ENMAKE_BASE=TRUE NO_TEST=TRUE

NO_TEST=TRUENC_MXM_PNL_BL_ENMAKE_BASE=TRUE

MXM_DP_A_HPD

MXM_DP_A_AUX_N

MXM_DP_A_AUX_P

MXM_DP_A_ML_N<0..3>

MXM_DP_A_ML_P<0..3>

MAKE_BASE=TRUEDP_EXTA_AUXCH_C_N

NO_TEST=TRUE

DP_EXTA_ML_C_P<0..3>MAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUEDP_EXTA_ML_C_N<0..3>

NO_TEST=TRUE

MAKE_BASE=TRUEDP_EXTA_AUXCH_C_P

NO_TEST=TRUE=T29_WAKE_LPCIE_WAKE_L

MAKE_BASE=TRUE NO_TEST=TRUEDP_T29SNK0_AUXCH_C_N

DP_T29SNK0_ML_C_P<0..3>MAKE_BASE=TRUE NO_TEST=TRUE

DP_T29SNK0_AUXCH_C_PMAKE_BASE=TRUE NO_TEST=TRUE

DP_T29SNK0_HPDMAKE_BASE=TRUE NO_TEST=TRUE

DP_T29SNK1_HPDNO_TEST=TRUEMAKE_BASE=TRUE

DP_T29SNK1_AUXCH_C_PMAKE_BASE=TRUE NO_TEST=TRUE

DP_T29SNK1_ML_C_N<0..3>NO_TEST=TRUEMAKE_BASE=TRUE

DP_T29SNK1_ML_C_P<0..3>NO_TEST=TRUEMAKE_BASE=TRUE

MXM_DP_B_ML_P<0..3>

MXM_DP_B_ML_N<0..3>

MXM_DP_B_AUX_P

MXM_DP_B_AUX_N

MXM_DP_B_HPD

DP_EXTA_HPDMAKE_BASE=TRUE NO_TEST=TRUE

MXM_LVDS_B_DATA_N<3..0>

MXM_LVDS_B_DATA_P<3..0>

NC_MXM_LVDS_A_DATA_P<3..0>MAKE_BASE=TRUE NO_TEST=TRUE

MXM_LVDS_A_DATA_P<3..0>

T29_D2R_N<2..3>

T29_D2R_P<2..3>

MXM_LVDS_B_CLK_N

MXM_LVDS_B_CLK_P NC_MXM_LVDS_B_CLK_PMAKE_BASE=TRUE NO_TEST=TRUE

NC_MXM_LVDS_A_CLK_PMAKE_BASE=TRUE NO_TEST=TRUE

NC_MXM_LVDS_A_CLK_NMAKE_BASE=TRUE NO_TEST=TRUE

MXM_LVDS_A_CLK_P

MXM_LVDS_A_CLK_N

NC_MXM_LVDS_B_CLK_NNO_TEST=TRUEMAKE_BASE=TRUE

MXM_LVDS_A_DATA_N<3..0>

MXM_PNL_BL_EN

MXM_PNL_PWR_ENNO_TEST=TRUE

NC_T29_R2D_C_P<2..3>MAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_T29_D2R_N<2..3>

T29_LSEO<2>

T29_R2D_C_N<2..3>

T29_LSEO<3> T29_LSOE<3>

T29_R2D_C_P<2..3>

PP3V3_SW_DPAPWR =PP3V3_SW_DPAPWR

MXM_DP_D_AUX_N

MXM_DP_D_HPD

DP_T29SNK0_ML_C_N<0..3>MAKE_BASE=TRUE NO_TEST=TRUE

NO_TEST=TRUEMAKE_BASE=TRUEDP_T29SNK1_AUXCH_C_N

MXM_DP_D_AUX_P

MXM_DP_D_ML_N<0..3>

MXM_DP_D_ML_P<0..3>

T29_LSOE<2>MAKE_BASE=TRUET29_LSEO_LSEO2

NO_TEST=TRUE

MAKE_BASE=TRUET29_LSEO_LSOE3

NO_TEST=TRUE

NO_TEST=TRUENC_T29_R2D_C_N<2..3>MAKE_BASE=TRUE

NC_T29_D2R_P<2..3>NO_TEST=TRUEMAKE_BASE=TRUE

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84 19 33 36 97

86 96

86 96

86 96

86

86

86 96

86 96

86 96 75 93

75 93

75 93

75 93

75

84

76 93

76 93

76 93

86 96

86 96

76 93

76 93

76 93

76 93

76 93

76

76

86

86 96

86 86

86 96

84 95 6

75 93

75

86 96

86 96

75 93

75 93

75 93

86

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NCNC

OUT

OUT

OUT

PAD

+3.42V

VDD_25M

+V3.3A

VDDIO_25M_C

VDDIO_25M_B

VDDIO_25M_A

25MHZ_C

25MHZ_B

25MHZ_A

X1

X2

VDD_RTC_OUT

THRMGND

32KHZ_A




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For SB RTC Power

For Caesar-IV (BCM57765): VDDIO = XTALVDDH (3.3V), Vclk = 3.3V Max. No Divider Necessary

VDD_25M: 3.3V matching ’highest’ VDDIO power state (ENET)

VDDIO_25M_A: SB power rail for XTAL circuit.

VDDIO_25M_C: T29 power rail for XTAL circuit.

VBAT: Alias as appropriate (see note below & Desktop Example)

System RTC Power Source & 32kHz / 25MHz Clock Generator

For Cougar Point Mobile: VDDIO = VCCVRM (1.5V), Vclk = 1.1V Max, Divider: 332 / 1000

GreenCLK Implementation Notes:

VDDIO_25M_B: Ethernet power rail for XTAL circuit.

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

For Cougar Point Desktop: VDDIO = VCCVRM (1.8V), Vclk = 1.1V Max, Divider: 604 / 1000

(1.1V)

+V3.3A should be first

(3.3V)

+V3.3A: Alias as appropriate (see note below)

Coin-Cell & G3Hot: 3.42V G3Hot

Coin-Cell & No G3Hot: 3.3V S5

internally ORed to

to reduce VBAT draw.

available ~3.3V power

(1.8V)

VBAT and +V3.3A are

create VDD_RTC_OUT.

No Coin-Cell: 3.3V S5

No bypass necessary

NOTE: 30 PPM crystal required

2

1R8816

1/16W

1M

402

5%

MF-LF

NOSTUFF

2

1 C8802

10%6.3VCERM402

1UF

2

1 C8810

CERM6.3V10%

402

1UF

21

C8806

402

50V5%

12PF

CERM

2 1

C880512PF

CERM

5%50V

402

2

1C8824T29

CERM402

20%10V

0.1UF

2

1C8822

CERM402

0.1UF20%10V

2

1C8820

402CERM

20%10V

0.1UF

31

42 Y8805

CRITICAL

SM-3.2X2.5MM

25.000MHZ-12PF-20PPM

2

1R8826

1%

MF-LF402

1/16W

140

21

R882540.2

MF-LF

1%

402

1/16W

18 27 91

86 96

21

R884333

MF-LF1/16W

402

5%

36 96

2

1R8808

402MF-LF1/16W5%10K

21R8806

1/16W

402MF-LF

5%

NOSTUFF0

21R8807

402MF-LF

5%

0

1/16W

21R8810

T29

1/16W5%

0

402MF-LF

21R88095%

MF-LF

0 NOSTUFF

402

1/16W

21R8812

402

0

1/16WMF-LF

5%

21

R8815

402

0

1/16W5%

MF-LF

3

4

14

6

11

1

5

17

2 13

16

10

7

12

15

8

9

U8800

TQFNCRITICAL

SLG3NB148V

21

R8845

T29

5%

402

1/16WMF-LF

47

GREEN CLOCK


SYSCLK_CLK25M_X2_R

SYSCLK_CLK25M_X1

=PP3V3_S3_SYSCLK

PPVBAT_G3_SYSCLK_RMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mm

PPVDDIO_25M_A

=PP3V3_T29_RTR


PPVDDIO_25M_C


PPVDDIO_25M_BMIN_LINE_WIDTH=0.3 mm

ENET_CLK25M_XTALI_OSC


SYSCLK_CLK25M_SB

PCH_CLK25M_XTALIN

TP_SYSCLK_CLK32K_RTC

SYSCLK_CLK25M_T29_CLK SYSCLK_CLK25M_T29SYSCLK_CLK25M_X2




TP_PPVRTC_G3_OUT

SYSCLK_CLK25M_ENET

=PP1V05_S0_PCH

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95

6 80 86 87 95

95

36 37 79

96

96 96

6 24 79

36 37 79

6 24 79

96

6 18 24

www.vinafix.vn

GND

VOUT

ON

VIN

OUT

IN

IN

RESET*

OUT

EN

MR*

GNDTHRM

IN

VDD

SENSE+-

PAD

(OD)

0.7V

DLY

IN

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

IN

D

GS

OUT

D SG




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Max Output: 2A

R(on)

TPS22924C

3.3V T29 Switch

T29 CLKREQ# ISOLATION

- =PP3V3_T29_P3V3T29FET (3.3V FET Input)

- =PP1V05_T29_FET (1.05V FET Output)

1.05V T29 Switch

DLY = 60 ms +/- 20%

- T29_RESET_L


- =PP3V3_T29_FET (3.3V FET Output)

- =PP3V3_S0_T29PWRCTL

- =PP1V05_T29_P1V05T29FET (1.05V FET Input)

Page NotesPower aliases required by this page:

Pull-up provided by SB page.

Platform (PCIe) Reset

18 mOhm Typ


Open-Drain GPIO

Max Current = 1.7A (85C)

Supervisor & CLKREQ# Isolation

(NONE)

- =T29_CLKREQ_L

Load Switch

50 mOhm Max

U8910Part

Type

B1

A1

B2

A2

C2

C1

U8910

T29CRITICAL

CSPTPS22924

86 97

1

2R8903

1/16W5%

10K

402MF-LF

2

1 C8900T29

0.1UF

25VX5R

10%

402

27 97

86

2

1C8910T29

402CERM6.3V10%1UF

1

9

2

4

8

3

7

5

6

U8900SLG4AP016V

T29CRITICAL

TDFN

2

1R8907T29

MF-LF

100K

1/16W

402

5%

15 21 91

2

1R8906

1/16W

10K

402

5%

MF-LF

2

1 C8930T29

402X5R16V10%0.1UF

2

1R8930T29

MF-LF

10K1/16W5%

402

1

9

6

8

2

4

7

5

U8930

T29

CRITICAL

TDFNSLG5AP001

18 97

21

3

Q8950T29

SOD-VESM-HF

SSM3K15FV

15 21 91

1

2R8904T29

MF-LF402

10K5%

1/16W

32

1

4

5

Q8930

T29

BSZ035N03MSGP-TSDSON-8

CRITICAL


T29 POWER

PM_PGOOD_P1V05_S0_T29_FET

PP3V3_T29_FET

T29_RESET_RTR_L

=PP3V3_T29_RTR

=PP12V_S0_PWRCTL

=PP3V3_S0_PWRCTL


T29_SW_RESET_L

=PP1V05_T29

T29_RESET_L

=PP3V3_S0_T29PWRCTL

T29_CLKREQ_ISOL_LMAKE_BASE=TRUE

=T29_CLKREQ_LT29_CLKREQ_L

=PP3V3_T29_RTR

T29_PWR_EN

P1V05_S0_T29_EN

PP1V05_T29_FET=PP1V05_S0_P1V05T29FET

T29_CLKREQ_FET_L

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6 79 80 86 87

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IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

BI

BI

OUT

BI

OUT

OUT

OUT

BI

IN




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used by diag LED

I2C MASTER ON TCON

BACKLIGHT CONTROL SUPPORTonly on when Panel has valid video

guarantee backlight is

- =PP12V_S0_LCD

- =PP3V3_S0_VIDEO

I2C SLAVE ON TCON

518S0787

INTERNAL DP POWER

518S0778IG, MXM, MLB_PNL_PWR, LCD_PNL_PWR


(NONE)


Page Notes

INTERNAL DP INTERFACE


21

R9050

1/16W5%

402MF-LF

0

21

R9051

1/16WMF-LF402

0

5%

83 93

2

1 C9001

CERM

0.001uF

402

20%50V

83 93

83 93

83 93

83 93

83 93

83 93

83 93

2

1 C9020

X5R-CERM0805

10%10UF

16V

31

D9000SOT23

BAT54XG

21

R900919.1K

402

1%1/16WMF-LF

21

R901147

1/16WMF-LF402

5%

6 97

2

1 C9005

805

20%22UF

CERM6.3V

4

5

2

3

U900074AUP2G14GMSOT886

5

21

R9010

5%

603

0

MF-LF1/10W

83 93

83 93

6 49 94

6 49 94

6

5

2

1

U900074AUP2G14GMSOT886

2

1 C9006

402

10V

0.1UF

CERM

20%

83 97

81 97

83 97

9

8

7

6

5

41

40

4

39

38

37

36

35

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J9002CABLINE-CA

CRITICAL

F-RT-SM

6

5

4

3

2

1

8

7

J900153780-8606

M-RT-SM

CRITICAL

49

49

2

1 C9010NOSTUFF

5%47PF

50VCERM402

2

1 C9011NOSTUFF

5%47PF

50VCERM402

21

L9000

SM

FERR-250-OHM


Display: Int DP ConnectorSYNC_MASTER=K62

NO_TESTDP_INTPNL_ML_P<1>

SMB_BLC_TCON_SDA

I2C_TCON_SDA

SMB_BLC_TCON_SCL

DP_INTPNL_AUX_P

DP_INT_SPDIF_AUDIO

TP_OPTION1

DP_INTPNL_AUX_N

TP_OPTION2

=PP3V3_S0_DP

BL_EN

PP12V_LCDVOLTAGE=12VMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM

=PP12V_S0_LCD

SMB_DP_TCON_SLA_SCL

SMB_DP_TCON_SLA_SDA

LCD_BKL_ON_DLYVIDEO_ON

=PP3V3_S0_DP

VIDEO_ON

DP_INTPNL_HPD

VIDEO_ON_L_DLY

VIDEO_ON_L


NO_TESTDP_INTPNL_ML_N<1>

VSYNC_DP_CONN

NO_TESTDP_INTPNL_ML_N<3>

NO_TESTDP_INTPNL_ML_N<2>NO_TESTDP_INTPNL_ML_P<2>

VSYNC_DP

DP_INTPNL_ML_N<0> NO_TEST


I2C_TCON_SCL

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SS

ENABLE

GNDTHRM

VIN

PG

VOUT

ADJ

ISETPAD

CT

EN*

RTRY*

VIN

THRMGND

IFLT

ILIM

FLT*

VOUT

PAD

G

D

S

G

D

S

D

G S

IN




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8 7 5 4 2 1

VO=3.304V

<RB2>

2V9 measured at CDR

(IPU-Weak!)

TSD = CCT * 100000

ILIM = 201K / RLIM = 1.155A.

IFLT = 200K / RFLT = 2A

TFLT = CCT * 38900

<CT>

HI: 2V9 FOR T29

<RB1>

LO: 3V3 FOR DP

TSD 470ms 235ms 724ms

<RFLT>

12V T29 PORTA SUPPLY3V3(DP)/2V9(T29) PORTA SUPPLY

<RA>

12 WATTS MAX PER PORT

12 VOLTS

<RLIM>

(*) U9410 tolerance unknown

TFLT 18.3ms 13.4ms 26.7ms

ILIM 935mA 925mA 944mA (*)

IFLT 885mA 876mA 894mA (*)

Nominal Min Max

NEED TO UPDATE TABLE BELOW LATER

VO=0.5*(1+ RA/RB)

2

1R91501/10WMF-LF

5%603

2.2K

21

D9105DSN2

NSR20F20NXT5G

T29

5

4

1

2

3

U9120

MC74VHC1G08SOT23-5-HF

T29

2

1 C915010%16V

402X5R

0.1UF

T29

2

1 C9124

16V10%10UF

X5R-CERM0805

2

1R9112

MF-LF1/16W

402

5%0

T2931

D9103SOT23

MMBZ5227BLT1H

CRITICALT29

2

1R911713K

NOSTUFF

1/16W5%

402MF-LF

21

R91280

402

5%

MF-LF1/16W

NO_T29

2

1

10

9

11

64

8

5

7 3

U9101

CRITICAL

DFNISL80101A

2

1R912411.5K1/16WMF-LF

1%402

12

11

10

4

3

2

1

17

6 7

8

14

135

1516

9

U9110

T29CRITICAL

SN1010017QFN

2

1C9123330PF

50V10%

402 CERM2

1 C9120

X5R-CERM

10%

0805

16V

10UF

2

1 C9121

CERM-X5R16V

0.022UF10%

402

2

1 C9125NOSTUFF

0805

16V10%10UF

X5R-CERM2

1 C912210UF

0805

10%

X5R-CERM16V

2

1R9121

4025%1/16W

20KMF-LF

2

1R91232.05K1/16WMF-LF 402

1%

4

5

3

Q9120

SOT-3632N7002DW-X-G

NOSTUFF

2

1R9126NOSTUFF

402MF-LF1/16W5%10K

1

2

6

Q9120NOSTUFF

2N7002DW-X-GSOT-363

2

1R9125NOSTUFF

4021%1/16W

MF-LF

15.0K2

1R9122

MF-LF1/16W 5%100K

402

21

D9101POWERDI-123

DFLS260

2

1R91301%1/16W

25.5KMF-LF 402

2

1 C9111

X7R

0.1UF10%50V

603-1

T29

2

1C91100.1UF

10%

X7R50V

603-1

T292

1R9116

1/16W5%

402MF-LF

15K

T29

2

1R9111174K1%

402

1/16WMF-LF

T29

2

1R9110100K

1%1/16W

402MF-LF

T29

21

3

Q9115SSM3K15FV

SOD-VESM-HF

T29

84 97


2V9/3V3/12V POWER SWITCH

=PP5V_S3_P3V3R2V9_REG_A

DPAPWRSW_HVEN_L_R

DPAPWRSW_CT

=PP12V_S5_T29_A

DPAPWRSW_IFLT

DPAPWRSW_ILIM

TP_DPAPWRSW_FLT_L


VOLTAGE=12V

PP3V3R12V_SW_DPAPWR_D

3V3R2V9_SS_AT29_DP_PORTA_PWR_EN_REG

PM_PGOOD_P3V3_2V9_A

NET_PHYSICAL_TYPE=POWERMIN_LINE_WIDTH=0.6MM

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2MM

PP3V3R2V9_DPAPWR_D

3V3R2V9_DPAPWR_ADJ

80101A1_ISET

DP_A_PWRDWN_FET_R

T29_A_BIAS

PP3V3R12V_SW_DPAPWR

VOLTAGE=12VMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MM

=PP3V3_S3_PWRCTL

T29_A_HV_EN

NET_PHYSICAL_TYPE=POWERMIN_LINE_WIDTH=0.38 MMVOLTAGE=12V

PP3V3R12V_SW_DPAPWR


=PP3V3_S5_P3V3R2V9_A

PM_SLP_S3_L

PM_PGOOD_P5V_S3_REG

=PP3V3_S3_P3V3R2V9_REG_A

DP_A_PWRDWN_INV

T29_DP_PORTA_PWR_ENT29_DP_PORTA_PWR_EN_REG

91 OF 110

11.1.0

051-8115

82 OF 98

6

97

97

6

97

97

95

82 97 95 97

84 85 96

82 85

6 64 73

82 85

6

5 19 26 32 36 46

47 63 97

63 70

97

6

97

20 25

91

97 82 97

www.vinafix.vn

S GND

OUTPUT

MUXSELECTOR

I1

I0Y

VCC

IN

IN

IN

OUT

IN

DDC_DAT2

XSD*

GPU_SEL

HPD_2

DDC_CLK2

DIN2_3-

DIN2_3+

DIN2_2-

DIN2_2+

DIN2_1-

DIN2_1+

DAUX2+

DAUX2-

DIN2_0+

DIN2_0-

DDC_DAT1

DDC_CLK1

HPD_1

DAUX1-

DAUX1+

DIN1_0-

DIN1_1+

DIN1_3-

DIN1_1-

DIN1_2+

DIN1_0+

DIN1_2-

DIN1_3+

TST0

DDC_AUX_SEL

HPDIN

AUX+

AUX-

DOUT_3-

DOUT_3+

DOUT_1-

DOUT_2-

DOUT_2+

DOUT_1+

DOUT_0+

DOUT_0-

GND

VDD

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

OUT

NCNC

OUT

NCNC

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

S GND

OUTPUT

MUXSELECTOR

I1

I0Y

VCC

IN

IN

IN

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(For each pair)

4

5

6

1

3

2

U9220SOT48774LVC1G157

T29

46 97

76 97

18 61 83 91

2 1

R9222

1/16W5%

402

47

MF-LF

21

L9201

0402

FERR-220-OHM

6 97

2

1R9227NOSTUFF

MF-LF

5%1/16W

100K

402

2

1R9230NOSTUFF

MF-LF402

10K5%

1/16W

2

1R923710K

1/16W5%

402MF-LF

81 97

21C9211402X5R

10% 16V0.1uF

T29

21C92120.1uF 402

16V10%X5R

T29

B7

J4

A2

G2

J1

H3

J2

A1

H7

H4

G8

C8

B3

F2

F1

E2

E1

D2

D1

B2

B1

F8

F9

E8

E9

D8

D9

B8

B9

A8

A9

B6

A6

B5

A5

B4

A4

J5

J8

H5

H8

C2

H6

J6

H9

J9

H2

H1

U9200

TFBGACBTL06142CEEG

CRITICAL

21C92130.1uF X5R

10% 16V402

21C92144020.1uF X5R

10% 16V

2

1R9240

402

5%1/16WMF-LF

470K

2

1 R9242

1/16WMF-LF402

5%470K

2

1 R9245

402MF-LF1/16W5%

470K

T29

2

1R9244

402

5%1/16W

470K

MF-LF

T29

2

1 R9249100K5%1/16WMF-LF4022

1R9248470K

1/16WMF-LF

5%

402

NOSTUFF

2

1R9250100K

MF-LF402

5%1/16W

2

1 R9251470K

5%1/16W

402MF-LF

NOSTUFF

81 93

81 93

21C921010% 16VX5R 4020.1uF21C9215

0.1uF X5R10% 16V

402

21C9250402X5R16V10%

0.1uF T29

21C925110% 16VX5R 4020.1uF T29

21C9252X5R

16V10%4020.1uF T29

21C925310% 16VX5R 4020.1uF T29

21C9254X5R

16V10%4020.1uF T29

21C925510% 16VX5R 4020.1uF T29

21C9256X5R

16V10%4020.1uF T29

21C925710% 16VX5R 4020.1uF T29

2

1R9261

MF-LF402

5%1/16W

470K

T29

2

1R9263

MF-LF

470K

1/16W5%

402

T29

2

1R9265

1/16WMF-LF

5%

402

470K

T29

2

1R9267

1/16WMF-LF

5%

402

470K

T29

2

1R9266

402

5%

MF-LF1/16W

470K

T29

2

1R9264

MF-LF

5%

402

470K

1/16W

T29

2

1R9262470K

1/16WMF-LF

402

5%

T29

2

1R9260

402

5%

MF-LF1/16W

470K

T29

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

83 96

83 96

83 96

83 96

83 96

83 96

83 96

83 96

2

1 C9209

10%1UF

10VX5R402-1

2

1R9228100K

1/16W5%

MF-LF402

2 1

R9223

5%

MF-LF1/16W

0

402

2

1 C9273

10%16VX5R402

0.1uF

NOSTUFF

2 1

R9225NO_T29

402

5%

MF-LF1/16W

0

2 1

R9226NO_T29

1/16WMF-LF

5%

402

0

83 96

83 96

83 96

83 96

83 96

83 96

83 96

83 96

86 96

86 96

86

75

2

1 C9269

402

10%16VX5R

0.1uF

2

1C9268

X5R16V

402

10%0.1uF

18 61 83 91

75 93

75 93

75 93

75 93

75 93

75 93

75 93

75 93

75 93

75 93

21C920710% 16VX5R 4020.1uF21C9208

0.1uF X5R16V402

10%

21C92050.1uF X5R 402

16V10%

21C92060.1uF

16V402

10%X5R

21C9203X5R 402

16V10%0.1uF

21C9204402

10% 16VX5R0.1uF

21C9201X5R

16V10%4020.1uF

21C920210% 16VX5R 4020.1uF

81 93

81 93

81 93

81 93

81 93

81 93

81 93

81 93

2

1R9220

402MF-LF1/16W

5%10K

4

5

6

1

3

2

U921074LVC1G157SOT487

T29 2

1 C9272

402

0.1uF10%16VX5R

T29

60 91 97

81 97

18 61 83 91

56 97

2

1 C92700.1uF

16V10%

402X5R

T29


Internal DP MUXingSYNC_DATE=N/A

PP1V5_S0_DP_R

=PP1V5_S0_DP

MXM_DP_C_ML_P<1>

DP_INTMUX_XSD

PP1V5_S0_DP_R

=PP3V3_S0_INTDPMUX

PP1V5_S0_DP_R

MXM_DP_C_HPD

DP_T29SRC_AUXCH_R_C_N

=PP3V3_S0_INTDPMUX

DP_T29SRC_ML_C_P<0>

DP_T29SRC_ML_C_N<0>

DP_T29SRC_ML_C_P<1>

MXM_DP_C_AUX_P

MXM_DP_C_ML_N<2>

DP_INTCONN_ML_C_N<3>

MXM_DP_C_ML_N<0>

DP_T29SRC_ML_C_N<3>

DP_T29SRC_ML_C_P<3>

DP_T29SRC_ML_N<0>

DP_T29SRC_ML_P<1>

DP_T29SRC_ML_N<1>

DP_T29SRC_ML_P<2>

DP_T29SRC_ML_N<2>

DP_T29SRC_ML_P<3>

DP_T29SRC_ML_P<0>

DP_T29SRC_ML_C_P<0>DP_T29SRC_ML_C_N<0>

DP_T29SRC_ML_C_N<1>DP_T29SRC_ML_C_P<1>

DP_T29SRC_ML_C_P<2>

DP_T29SRC_ML_C_P<3>DP_T29SRC_ML_C_N<3>

DP_INTCONN_ML_C_N<0>MXM_DP_C_ML_N<3>

DP_INTPNL_AUX_NDP_INTPNL_AUX_P

MXM_DP_C_ML_P<2>

=PP3V3_S0_INTDPMUX

DP_INTPNL_HPD

MXM_DP_C_ML_P<0>

MXM_DP_C_ML_N<1>

DP_T29SRC_AUXCH_C_N

=PP3V3_S0_INTDPMUX

BL_PWMLCD_BL_FILTBDV_BKL_PWM

DP_GPU_T29_SEL

DP_INTPNL_ML_N<3>DP_INTPNL_ML_P<3>

DP_INTCONN_ML_C_P<1>



DP_INTPNL_ML_N<2>

DP_INTPNL_ML_P<1>

DP_INTPNL_ML_P<2>

DP_INTPNL_ML_N<1>

DP_INTPNL_ML_N<0>

DP_T29SRC_AUXCH_C_P

DP_T29SRC_HPD

MXM_DP_C_AUX_N



DP_T29SRC_ML_C_N<2>

DP_T29SRC_ML_C_P<2>

DP_T29SRC_ML_C_N<2>

DP_INTCONN_ML_C_P<0> DP_INTPNL_ML_P<0>MXM_DP_C_ML_P<3>

MXM_DP_C_AUX_R_PMXM_DP_C_AUX_R_N

DP_T29SRC_ML_C_N<1>

DP_T29SRC_AUXCH_R_C_P

MIN_LINE_WIDTH=0.4MMVOLTAGE=1.5VPP1V5_S0_DP_R


DP_T29SRC_ML_N<3>

=PP3V3_S0_INTDPMUX

DP_INT_SPDIF_AUDIOAUD_SPDIF_IN

AUD_SPDIF_IN_CODEC

MXM_PNL_BL_PWMLCD_BL_PWM

=PP3V3_S0_INTDPMUX

DP_GPU_T29_SEL

DP_GPU_T29_SEL

DP_INTCONN_AUXCH_C_PDP_INTCONN_AUXCH_C_N

92 OF 110

11.1.0

051-8115

83 OF 98

83 95

6

83 95

6 83

83 95

96

6 83

93

93

6 83

6 83

97

93

93

93

93

93

93

93

93

96

83 95

6 83

97

6 83

93

93

www.vinafix.vn

OUT

OUT

BI

OUT

OUT

IN

IN

IN

IN

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

NC

IN

BI

THMPADGND

VDD

OUT_D0P

OUT_D0N

OUT_D1P

OUT_D2P

OUT_D1N

OUT_D3P

OUT_D2N

OUT_D3N

AC_AUXP

AC_AUXN

OUT_HPD

CEXT

IN_D0P

IN_D0N

IN_D1N

IN_D2N

IN_D3P

IN_SDA

IN_AUXP

IN_AUXN

IN_HPD

I2C_CTL_EN

I2C_ADDR0

I2C_ADDR1

SCL_CTL

SDA_CTL

REXT

AUXDDC_OFF

PD

CA_DET

IN_SCL

IN_D3N

IN_D2P

IN_D1P

OUT_AUXN_SDA

OUT_AUXP_SCL

BI

BI

IN

BI

OUT

IN

OUT

OUT

OUT

VDD

PIO1_8/CT16B1_CAP0

PIO1_7/TXD

XTALIN

PIO1_4/AD5/WAKEUP

PIO1_6/RXD

SWDIO/PIO1_3/AD4

R/PIO1_2/AD3

R/PIO1_1/AD2

R/PIO1_0/AD1RESET#/PIO0_0

PIO0_1/CLKOUT

SWCLK/PIO0_10/SCK/CT16B0_MAT2

PIO0_9/MOSI/CT16B0_MAT1

PIO0_8/MISO/CT16B0_MAT0

PIO0_2/SSEL/CT16B0_CAP0

R/PIO0_11/AD0

PIO0_7/CTS#

PIO0_6/SCK

PIO0_4/SCL

PIO0_5/SDA

VSSTHRMPAD

BI

OUT

OUT

IN

IN

IN

IN

IN

IN

AUX-

AUX+

DOUT_1+

DOUT_1-

NC

GNDTHMPAD

GPU_SEL

HPD_2

AUX2-

AUX2+

DIN2_1-

DIN2_1+

DIN2_0-

HPD_1

AUX1-

AUX1+

DIN1_1-

DOUT_0-

DIN1_0+

DIN1_0-

DIN1_1+

HPD_IN

DOUT_0+

DIN2_0+

VDD

AUX_SEL

OUT

IN

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(P2R = PLUG TO RECEPTACLE)

pin 10 for ML and pin 11 for HPD.

similar pinouts. NXP uses pinfootprint-compatible parts with

HI=Port B

DP/T29 A Low-Speed MUX

pull-ups on ML<3>. U9390 AUX defaults to DP mode because 100-ohm pull-downs would defeat DP Sink’s detection of DP Source.

CBTL04DP081 (353S3151) and

10 for ML and HPD, Pericom uses

Note: U9390 ML/HPD defaults to T29 mode so that DP/T29

Must be 3.3V DP A port power

Port A MCU

~150K pull-down on PDpin. Okay to drive thispin even when VCC=0V perParade (pin is 5V-tolerant).

(R2P = RECEPTACLE TO PLUG)

LO=Port A

(OD)

R9330 provides pads for programming/debug of MCU, please make accessible.

Display can detect host T29 support using I2C

(All 4 L’s)

T29 A High-Speed Signals(C9370/C9371)

(Both L’s)

P/N-swapped after AC

(DP_SDRVA_AUXCH_P)

(IPU)

(OD)

T29 signals are

R9308/R9309 maintain bias on C9308/C9309

transitions from high to low.

caps to improve layout.

AUXCH Snoop Port,

high while Vcc = 0V.

DP A Super-Driver

and DDC, alias nets together at GPU.If GPU uses common pins for AUX_CH

(D9360/D9361)

(D9382/D9383)

(C9380/C9381)

(C9372.2)

PS8301 I2C Addresses:

T29: TX_1

Both R’s:

(D9361.2)

(IPD)

If project has space for 10-pin programming header it should be used.

PS8301 has internal

(OD)

during training.used by PS8301

=T29_WAKE_L:

SWDIO

SWCLK

(OD)

T29: LSX_A_R2P/P2R (P/N)

T29: Unused

T29: RX_1 Bias Sink

(IPU)

(IPD)

1 0 0x94/0x95

0 0 0x96/0x97 0 1 0xB6/0xB7

Note: Other Paradedevices use 96/B6,

(D9365.2)

(DP_SDRVA_HPD)

(DP_SDRVA_AUXCH_N)

A1 A0 Addr (W/R)

1 1 0xB4/0xB5

so only 94/B4 are

(IPD)

used for this part.

(IPD)

Biasing

(D9364.2)

DP Path Biasing

T29: TX_0

(D9372/D9373)

(All 4 D’s)D9372/D9373:

D9364/D9365:

(All 4 D’s)

(D9382/D9383)

(D9360.2)

(T29_A_LSX_R2P)

Mobiles use S4 WAKE#Desktops use PCIe WAKE#

(IPD)

(C9383.2)

(C9383.2)(Both L’s)

to prevent spikes when U9310 AUXDDC_OFF

IC supports input

T29 Path

(C9373.2)

0x26/0x27 (Wr/Rd)I2C Addr:

(T29_A_LSX_P2R)

Must be 3.3V DP A port power

PI3vEDP212 (353S3055) are

86 96

86 96

85 96

85 96 2

1R9312

MF-LF1/16W

1K5%

402

2

1R93194.02K1/16W1%

402MF-LF

78

2

1R9311NO STUFF

MF-LF

5%

402

1/16W

1K

2

1R9310

1/16W5%

402MF-LF

1K

2

1 C93110.1UF10V20%

CERM402

2

1 C93120.1UF20%10V

402CERM

2

1C931920%

6.3VCERM

2.2UF

PLACE_NEAR=U9310.11:2 mm

402-LF

86 96

86 96

86 96

86 96

86 96

86 96

21C93064020.1uF 16V

X5R10%

21C93070.1uF 16V

402X5R10%

78 93

78 93

21C93040.1uF 10%

402X5R16V

78 93

21C930510%

40216V

X5R0.1uF78 93

21C9302X5R0.1uF 10%

40216V

78 93

21C9303X5R 402

16V10%0.1uF78 93

21C930016V4020.1uF 10%

X5R

78 93

21C930110% 16V0.1uF 402X5R

78 93

49

49

21C93080.1uF 16V

X5R 40210%

21C93090.1uF 16V10%

X5R 402

78 93

78 93

2

1R9399100K

MF-LF1/16W5%

402

2

1R9398

MF-LF402

1/16W5%100K

78

78

40

21

41

37

38

12

34

31

23

22

25

24

28

27

30

29

18

17

13

14

3

9

10

7

8

4

5

1

2

16

15

26

35

36

336

11

32

39

20

19

U9310

CRITICAL

QFNPS8301TQFN40GTR-A2

2

1C93102.2UF

6.3V

402-LFCERM

20%

85 96

85 96

21C936310% 16VX5R-CERM

02010.1UF

21C936216V

X5R-CERM0.1UF 10%

0201

21C93670.1UF 16V10%

X5R-CERM020121C9366

0.1UF 10% 16VX5R-CERM

0201

84

85 96

85 96

84

21C936916V10%402X5R0.1uF

21C936816V10%

X5R 4020.1uF

20 91

78

86

4

213

225

25

19

14

1

18

17

16

15

6

24

23

20

13

12

11

10

9

8

7

2

U9330HVQFN25

LPC1112A

CRITICALOMIT

49

82 84 85 96

86

49

86

2

1R9335T29

402MF-LF

1K5%1/16W

2

1R9336T29

MF-LF402

1/16W

10K5%

2

1 C93300.1UF

CERM10V20%

402

T29

86

85

84 85

2

1 C933120%

T29

402

0.1UF10VCERM

1

2R9397

MF-LF

T29

402

5%1K1/16W

1

2R9396T29

1K5%

MF-LF1/16W

402

2

1R93391M

402

1/16WMF-LF

5%

T29

2

1R9338

MF-LF402

T29

5%10K1/16W

84 85

2

1R93305%

MF-LF1/16W

402

OMIT

0

2

1R9393T29

515%1/16W

402MF-LF

2

1R9392T29

51

MF-LF

5%

402

1/16W

29

20

16

12

9 3

33

8

13

17

10

28

21

4

5

1

2

23

22

25

24

27

26

31

30

32

6

7

15

14

19

18

U9390

CKPLUS_WAIVE=NdifPr_badTerm

OMIT

CBTL04DP081

CRITICAL

HVQFN

SIGNAL_MODEL=T29DP_MUX

82 97

21

R9334

MF-LF

T29

1/16W5%

402

10K

15 18 25 91

1

2R9318

MF-LF1/16W

5%0

SDRV_PD

402

21R93081/16W1M 5%402MF-LF

21R93091M 402

5%MF-LF

1/16W

85 96

85 96

85 96

85 96

85 96

85 96

21D9364

SIGNAL_MODEL=EMPTY

TSLP-2-7

CRITICAL

GND_VOID=TRUEBAR90-02LRH

21D9373 T29

SIGNAL_MODEL=T29PIN

TSLP-2-7BAR90-02LRH

CRITICAL

GND_VOID=TRUE

21D9372 T29

SIGNAL_MODEL=T29PIN

GND_VOID=TRUE

BAR90-02LRH TSLP-2-7

CRITICAL

21D9365

SIGNAL_MODEL=EMPTY

TSLP-2-7BAR90-02LRHGND_VOID=TRUE

CRITICAL

21D9360BAR90-02LRH

SIGNAL_MODEL=EMPTY

GND_VOID=TRUETSLP-2-7

CRITICAL

21D9382BAR90-02LRH

CRITICAL

GND_VOID=TRUE

SIGNAL_MODEL=T29PIN

TSLP-2-7T29

21D9383 T29BAR90-02LRH

SIGNAL_MODEL=T29PIN

TSLP-2-7

CRITICAL

GND_VOID=TRUE21D9361

SIGNAL_MODEL=EMPTY

CRITICALTSLP-2-7

GND_VOID=TRUEBAR90-02LRH

21C93700.47UF 20% 4V

CERM-X5R-1201

GND_VOID=TRUET29

21R9372

SIGNAL_MODEL=EMPTY

MF1/20W5%

GND_VOID=TRUE

2011.5K

T29

21

R9373SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

2015% 1/20WMF

1.5KT29

21R9382 MF 201

1/20W5%GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

1.5K

T29

21


1/20W5%

GND_VOID=TRUE

201MF

1.5KT29

21C9373T290.47UF CERM-X5R-1

4V20%

201GND_VOID=TRUE

21C9372 T29

201CERM-X5R-120%

GND_VOID=TRUE

4V0.47UF

21C9371T294V

CERM-X5R-10.47UF

GND_VOID=TRUE

201

20%

21C9381T29

GND_VOID=TRUE

4V20%

201CERM-X5R-10.47UF

21C9380 T29

GND_VOID=TRUE

CERM-X5R-14V20%

2010.47UF

21C9382 T2920%CERM-X5R-1

4V

GND_VOID=TRUE

0.47UF201

21C9383T29CERM-X5R-1

201GND_VOID=TRUE0.47UF 20% 4V

21C93646.3V0.22UF 20%

X5R 020121C936520% 6.3V0.22UF X5R 0201

21C9361X5R20%0.22UF 6.3V

0201

21C93606.3V0.22UF 20%

X5R 0201

21R93851/20W201

5%MF

GND_VOID=TRUE1.5K

SIGNAL_MODEL=EMPTY


1/20W201

5%MF

1.5KGND_VOID=TRUE

85 96

85 96

21R9375GND_VOID=TRUESIGNAL_MODEL=EMPTY

1/20W201MF

5%1.5K


2011/20W

MF

GND_VOID=TRUE

5%1.5K

21L93830201-1

OVERSIZE_PAD=0.875 mm^2

1.0NH+/-0.1NHT29

21L9382 T29

1.0NH+/-0.1NH


0201-1

21L9372 T29

1.0NH+/-0.1NH 0201-1


21L9373T29

0201-1


1.0NH+/-0.1NH

21R93555%MF 201

1/20W22

21R9354MF

1/20W201

5%22

21R93505%MF 201

1/20W22

21R93515%

2011/20W

MF

22

2

1 C93900.1UF

CERM402

10V20%

2

1 C9391

402CERM

0.1UF10V20%

21R9360 1.5K1/20W5%

MF 201

21R93615%MF 201

1/20W1.5K

21R93645% 1/20WMF 201

1.5K

21R9365201MF

1/20W5%1.5K

4

5

3

2

U935974LVC1G04DBDCK

CRITICAL

SC70

2

1C9359

402X5R16V10%

0.1UF

2

1R93525%

1/20W

201MF

390

2

1R9353

201MF1/20W5%390

21

C9358

0201

0.1UF

X5R-CERM

10%16V

85

85

21R93621/20W5% 201

51MF

21R9363201MF5% 1/20W

51

21R9366201MF5%

511/20W

21R9367MF 2011/20W5%51

85

85

2

1R9370

1/20W5%

201MF

390

2

1R9371

201MF

5%1/20W

390

21

R9380

5% MF 2010

1/20W

NO_T29

21

R9381

MF5%0

2011/20W

NO_T29

21

R9378

5%0

1/20W 201MF

NO_T29

21

R93790

201MF5% 1/20W

NO_T29


DisplayPort/T29 A MUXing

PP3V3_SW_DPAPWR

T29_A_LSX_P2R

DP_A_EXT_AUXCH_N

T29DPA_ML_N<1>

T29DPA_HPD

T29DPA_ML_P<3>

PP3V3_SW_DPAPWR

T29_A_LSX_R2P

T29_A_BIAS

DP_A_CA_DET

DP_SDRVA_HPD

T29_A_BIAS

DP_A_PWRDWN

DP_SDRVA_ML_P<0>DP_SDRVA_ML_N<0>

DP_SDRVA_ML_P<2>

VOLTAGE=3.3VT29_A_BIAS_R2D_N0

T29DPA_ML_C_P<2>

DP_SDRVA_ML_P<3>

=I2C_T29AMCU_SDA

DP_SDRVA_ML_C_P<0>

DP_SDRVA_ML_C_P<2>

T29_R2D_C_P<1> T29_R2D_N<1>T29_R2D_P<1>


T29_R2D_C_P<0>T29_R2D_C_N<0>

DP_SDRVA_AUXCH_C_N

DP_A_PWRDWN

DP_SDRVA_ML_C_N<1>

DP_EXTA_ML_C_P<0>

DP_SDRVA_ML_R_N<0>

DP_A_BIAS

T29_D2R_C_P<1>

DP_SDRVA_ML_N<2>

T29_R2D_N<0> T29DPA_ML_C_N<0>

VOLTAGE=3.3VDP_A_BIAS_N_2

T29DPA_ML_C_N<2>

DP_A_BIAS_P_0VOLTAGE=3.3V

DP_A_BIAS_N_0VOLTAGE=3.3V

DP_EXTA_ML_P<1>

DPSDRVA_I2C_CTL_EN

=I2C_DPSDRVA_SCL

DPSDRVA_I2C_ADDR1DPSDRVA_I2C_ADDR0

DP_EXTA_DDC_CLK

DP_SDRVA_ML_C_P<3>

DPSDRVA_REXT

=PP3V3_S0_DPSDRVA

DP_A_PWRDWN_R

DP_SDRVA_ML_N<3>

DP_AUXCH_ISOL

DP_EXTA_AUXCH_N

DP_EXTA_HPD

DPSDRVA_CEXT

T29DPA_ML_C_P<0>

T29_LSEO<0>

T29_LSOE<1>

DP_EXTA_ML_N<1>

DP_EXTA_ML_N<0>

DP_EXTA_ML_P<1>

DP_EXTA_ML_P<2>

DP_EXTA_ML_N<3>

DP_A_CA_DET

DP_EXTA_ML_P<3>

DP_EXTA_ML_N<2>

DP_EXTA_ML_P<0>

T29DPA_ML_N<3>

T29DPA_ML_P<1>

DP_A_EXT_AUXCH_P

T29DPA_CONFIG1_RC

T29_A_UC_ADDR

DP_EXTA_ML_N<0>DP_EXTA_ML_C_N<0>

DP_EXTA_ML_N<1>

DP_EXTA_ML_N<2>

DP_EXTA_ML_P<2>

DP_EXTA_ML_N<3>

DP_EXTA_ML_C_P<1>

DP_EXTA_ML_C_N<1>

DP_EXTA_ML_C_P<2>

DP_EXTA_ML_C_N<2>

DP_EXTA_AUXCH_C_P

=PP3V3_S0_DPSDRVA

DP_EXTA_DDC_DATA

DP_EXTA_AUXCH_P

=I2C_DPSDRVA_SDA

DP_A_PWRDWN

T29_R2D_C_N<1>

DP_EXTA_ML_P<3>

=PP3V3_S0_DPSDRVA


=I2C_T29AMCU_SCL

T29_R2D_P<0>

T29_D2R_C_N<0>

DP_EXTA_ML_P<0>VOLTAGE=3.3VT29_A_BIAS_R2D_P0

DP_SDRVA_ML_R_P<2>

DP_EXTA_AUXCH_C_N

DP_EXTA_ML_C_N<3>

DP_EXTA_ML_C_P<3>

DP_SDRVA_ML_C_N<2>

DP_EXTA_AUXCH_P

DP_EXTA_AUXCH_N

VOLTAGE=3.3VT29_A_BIAS_R2D_P1

T29_D2R_C_P<0>

DP_SDRVA_ML_C_N<3>

T29_R2D_C_F_P<0>

DP_SDRVA_ML_C_N<0>

DP_SDRVA_ML_R_N<2>

T29_R2D_C_F_N<0>

T29_R2D_C_F_N<1>T29_R2D_C_F_P<1>

T29_D2R_N<1>

=T29_WAKE_L

T29_LSEO<1>T29_LSOE<0>

T29DPA_HPD

DP_A_PWRDWN

DP_SDRVA_AUXCH_C_P

T29_D2R1_BIASPT29_D2R1_BIASN

DP_SDRVA_ML_P<1>

T29_D2R_P<0>T29_D2R_N<0>

T29_D2R_C_N<1>T29_D2R_P<1>

DP_SDRVA_ML_R_P<0>

DP_SDRVA_ML_C_P<1>

T29_MCU_INT_L

T29_A_BIAS

T29DPA_CONFIG1_RC

T29_A_RSVD_NT29_A_RSVD_P

DP_A_EXT_HPD

DP_A_EXT_HPD

DP_SDRVA_AUXCH_NDP_SDRVA_AUXCH_P

DP_SDRVA_ML_N<1>

DP_A_CA_DET

T29_A_HV_EN_RT29_A_UC_ADDRDP_A_EXT_HPD

T29DPA_CONFIG2_RCT29_A_HV_EN

93 OF 110

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051-8115

84 OF 98

1178 84 95

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82 84 85 96

84

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96

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96

96

96

96

96

85

85

85

84 93

96

6 84

96 84 93

84 93

84 93

84 93

84 93

84 93

84 93

84 93

84 93

84

84 93

84 93

84 93

84 93

84 93 6 84

84 93

84 97

84 93

6 84

85

96

84 93

96

96

84 93

84 93

96

96

96

96

96

96

96

84 97

96

96

96

96

82 84 85 96

84 85

96

96

84

96

96

96

84

84

84

www.vinafix.vn

OUT

OUT

IN

IN

BI

IN

OUT

OUT

BI

BI

BI

OUT

OUT

OUT

BI

IN

IN

IN

ML_LANE2P

ML_LANE2N

RETURN

GND

ML_LANE1N

ML_LANE0N

GND

ML_LANE1P

ML_LANE0P

GND

AUX_CHP

AUX_CHN

DP_PWR

GND

ML_LANE3N

ML_LANE3PGND

HPD

CONFIG1

CONFIG2

SHIELD PINS



TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

to 100K (DPv1.1a).greater than or equaldown HPD input withDP Source must pull

DP BIAS CAPS

(Both L’s)

T29: Unused

High: 2.0 - 5.0V

Circuit threshold range: 2.877-2.941V (2.903V nominal)

470k R’s for ESD protectionon AC-coupled signals.

(Both C’s)

T29 DirDP Dir

(Both C’s)

T29: TX_1

DP Dir

T29 BIAS RC

T29: LSX_R2P/P2R (P/N)

(3, 5, 17 & 19):For J9400 T29 SMT pads

DisplayPort/T29 A Connector

T29 Dir

to C in star topology.All 3 R’s must connect

Sink HPD range:

T29: TX_0

Low: 0 - 0.8V

2

1C9400

50V10%

0.01UF

X7R402

84 96

84 96

84 96

84 96

84 96

84 96

21

R940712GND_VOID=TRUE

5%

MF201

1/20W

21

R9403 GND_VOID=TRUE

201MF

5%

12

1/20W

21

R9404 GND_VOID=TRUE

5%

12

MF1/20W

201

21

R9408

5%

12

MF1/20W

2012

1C9402

X5R

10%

201

10V

0.01UF

21

L9408FERR-120-OHM-3A

0603

21

R9402

201

1/20WMF

12

5%

21

R9401

201MF

12

5%1/20W

2

1 C940110%50VX7R402

0.01UF

2

1R9494OMIT_TABLE

201

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

1/20WMF

1K5%

2

1R9495 OMIT_TABLE

SIGNAL_MODEL=EMPTY

1K5%

GND_VOID=TRUE

MF1/20W

201

2

1C94985%50V

CERM402

30PF

T29

2

1 C94995%30PF

402

50VCERM

T29

2

1R9441

402

1/16W5%100K

MF-LF

2 1

L9498 OMIT_TABLE

CRITICAL

0603

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

650NH-5%-0.430MA-0.052OHM

2 1

L9499

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY0603

CRITICALOMIT_TABLE

650NH-5%-0.430MA-0.052OHM

84 96

84 96

84 96

84 96

84 96

2

1R94521M5%

1/16WMF-LF

402 2

1R9451

402

1/16W

1M

MF-LF

5%

2

1C9494

201

10%330PF

16VX7R

OMIT_TABLE

2

1 C9495

201X7R16V10%330PF

OMIT_TABLE

2

1R94985%

201MF

2.2K

SIGNAL_MODEL=EMPTY

1/20W

GND_VOID=TRUE

T29

2


2.2K

MF

GND_VOID=TRUE

T29

201

1/20W5%

21

L9400FERR-120-OHM-3A

0603

84

84

84

84 96

21D9499BAR90-02LRH TSLP-2-7

SIGNAL_MODEL=T29PINGND_VOID=TRUECRITICAL

T29

21D9498

CRITICAL

BAR90-02LRH TSLP-2-7

GND_VOID=TRUESIGNAL_MODEL=T29PIN

T29

2

1R9470GND_VOID=TRUE

5%470K

MF1/20W

201 2

1R9471

1/20W

GND_VOID=TRUE

5%470K

MF201

21C9471CERM-X5R-1

201

20% 4V

GND_VOID=TRUE

0.47UF

21C94700.47UF

GND_VOID=TRUE

4V20%

201CERM-X5R-1

84 96

84 96

21C94720.47UF CERM-X5R-1

201

20% 4V

GND_VOID=TRUE

21C9473CERM-X5R-1

201

20% 4V

GND_VOID=TRUE

0.47UF

2

1R9473

201

1/20WMF

GND_VOID=TRUE

5%470K

2

1R9472GND_VOID=TRUE

201

1/20WMF

5%470K

2


201

515%

1/20WMF

T29

2

1R9492515%1/20WMF201

SIGNAL_MODEL=EMPTY

T29

21

C9490

6.3V

0.1UF

201X5R

10%

T29

82 84 85 96

19

10

12

15

17

9

11

3

5

22

21

2

14 13

8 7

1

20

6

4

16

18

J9400CRITICAL

MDP-K60K62F-ANG-TH

GND_VOID=TRUE

21

C94930.01UF

10%

X5R201

10V

T29

SIGNAL_MODEL=EMPTY

21

C9492

10V

SIGNAL_MODEL=EMPTY

T29

10%

X5R201

0.01UF

2

1C9410

201X5R

0.01UF10%10V

T29

SIGNAL_MODEL=EMPTY

2

1C9417

SIGNAL_MODEL=EMPTY

X5R10V

201

10%0.01UF

2

1C9416

SIGNAL_MODEL=EMPTY

X5R10V

201

10%0.01UF

2

1C9415

SIGNAL_MODEL=EMPTY

X5R10V

201

10%0.01UF

2

1C9414

SIGNAL_MODEL=EMPTY

0.01UF10%

201

10VX5R

21

R9410

1/20W5%

51

SIGNAL_MODEL=EMPTY

MF201

T29

2

1C9411

SIGNAL_MODEL=EMPTY

X5R10V

201

10%0.01UF

T29

21


201

51

1/20WMF

5%

T29

2

1C9412

SIGNAL_MODEL=EMPTY

X5R10V

201

10%0.01UF

T29

21


51

201

1/20WMF

5%

T29

2

1C9413

SIGNAL_MODEL=EMPTY

X5R10V

201

10%0.01UF

T29

21


201

51

1/20WMF

5%

T29

21C94052010.1UF X5R

10% 6.3V

21C9406201

10%0.1UF X5R6.3V

DisplayPort/T29 A ConnectorSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

2113S0022 NO_T29L9498,L9499RES,0R,5%,0603

IND,650NH,5%,0.052OHM,0603152S1300 L9498,L94992 T29

RES,1K,5%,0201 R9494,R94952 T29117S0006

132S0165 C9494,C94952 T29CAP,330PF,10%,16V,0201

RES,0R,5%,02012 R9494,R9495 NO_T29117S0002


VOLTAGE=0V

GND_DPACONN_13

T29DPA_ML_P<1>

T29DPA_ML_P<0>T29DPA_ML_N<0>

GND_DPACONN_1


PP3V3R12V_SW_DPAPWR_RMIN_NECK_WIDTH=0.20 MMVOLTAGE=12V


T29DPA_ML_P<3>

T29DPA_CONFIG1_RC

T29DPA_CONFIG2_RC

T29_D2R_C_P<0>T29_D2R_C_N<0>

MIN_NECK_WIDTH=0.20 MMVOLTAGE=12V

MIN_LINE_WIDTH=0.38 MMDPACONN_20_RC

T29_A_BIAS_N1

T29_D2R_C_P<1>


T29_A_BIAS_P1

VOLTAGE=3.3V

GND_DPACONN_7


T29DPA_ML_N<1>

T29DPA_ML_P<2> T29DPA_ML_C_N<2>

T29_A_BIAS

T29_A_BIAS

T29_A_BIAS

PP3V3R12V_SW_DPAPWRMIN_LINE_WIDTH=0.38 MM

VOLTAGE=12VMIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MMGND_DPACONN_8MIN_NECK_WIDTH=0.20 MMVOLTAGE=0V

T29DPA_ML_C_P<2>

T29DPA_ML_C_N<0>T29DPA_ML_C_P<0>

T29DPA_ML_N<2>






VOLTAGE=3.3VDP_A_BIAS_P_2


T29DPA_D2R1_AUXCH_P

DP_A_EXT_AUXCH_PDP_A_EXT_AUXCH_N

T29_D2R_C_N<1>

T29DPA_HPD_R

MIN_NECK_WIDTH=0.20 MMVOLTAGE=0V

MIN_LINE_WIDTH=0.38 MMGND_DPACONN_19

T29DPA_ML_N<3>

MIN_LINE_WIDTH=0.38 MMGND_DPACONN_14

VOLTAGE=0VMIN_NECK_WIDTH=0.20 MM

T29DPA_D2R1_AUXCH_N

T29DPA_HPD

94 OF 110

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051-8115

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OUT

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

OUT

OUT

OUT

IN

IN

IN

OUT

IN

IN

OUT

OUT

BI

DPSNK0_ML_LANE_3P

DPSNK0_ML_LANE_3N

DPSNK0_ML_LANE_2P

DPSRC0_HOT_PLUG_DET

TEST_POINT_2

TEST_POINT_3

DPSNK0_HOT_PLUG_DET

DPSNK0_AUX_CHN

DPSNK0_AUX_CHP

DPSNK0_ML_LANE_0N

DPSNK0_ML_LANE_0P

DPSNK0_ML_LANE_1N

DPSNK0_ML_LANE_1P

DPSNK0_ML_LANE_2N

TEST_POINT_0

TEST_EN

THERM_DP

EE_CLK

EE_CS*

EE_DO

EE_DI

PCIE_CLKREQ_3*

PCIE_CLKREQ_2*

PCIE_CLKREQ_1*

PCIE_CLKREQ_0*

DPSNK1_ML_LANE_1P

DPSNK1_ML_LANE_2N

DPSNK1_ML_LANE_2P

DPSNK1_ML_LANE_3N

DPSNK1_ML_LANE_3P

DP_RES_1

DP_RES_0

DP_ATEST

DPSRC0_AUX_CHN

DPSRC0_AUX_CHP

DPSRC0_ML_LANE_0N

DPSRC0_ML_LANE_0P

DPSRC0_ML_LANE_1N

DPSRC0_ML_LANE_1P

DPSRC0_ML_LANE_2N

DPSRC0_ML_LANE_2P

DPSRC0_ML_LANE_3N

DPSRC0_ML_LANE_3P

TMU_CLK_OUT

TMU_CLK_IN

XTAL_25_IN

XTAL_25_OUT

REFCLK_100_IN_P

REFCLK_100_IN_N

TDO

TCK

TMS

TDI

PCIE_RST_3*

PCIE_RST_1*

PCIE_RST_2*

PCIE_RST_0*

RBIAS

RSENSE

PERST*

WAKE*

PER_1_P

PER_2_P

PER_3_P

MONDC0

MONOBSN

MONOBSP

MONDC1

PER_3_N

PER_2_N

PER_0_N

PER_0_P

PET_3_P

PET_3_N

PET_2_N

PET_2_P

PET_1_P

PET_1_N

PET_0_N

PET_0_P

TEST_POINT_1

DPSNK1_ML_LANE_0N

PER_1_N

DPSNK1_ML_LANE_0P

DPSNK1_ML_LANE_1N

DPSNK1_AUX_CHP

DPSNK1_HOT_PLUG_DET

DPSNK1_AUX_CHN

PRT0_T29T_N

PRT0_T29R_P

PRT0_T29R_N

T29_0_LSEO

T29_0_LSOE

PRT1_T29T_P

PRT1_T29T_N

PRT1_T29R_P

PRT1_T29R_N

T29_1_LSEO

T29_1_LSOE

T29_SDA

T29_SCL

PRT2_T29T_P

PRT2_T29T_N

PRT2_T29R_P

PRT2_T29R_N

T29_2_LSEO

T29_2_LSOE

PRT3_T29T_P

PRT3_T29T_N

PRT3_T29R_P

PRT3_T29R_N

T29_3_LSEO

T29_3_LSOE

PRT0_T29T_P

PORT2

PCIE GEN2

RECEIVE

TRANSMIT

PORTS

(SYM 1 OF 2)

JTAG

POWER ON RESET

MISC

CLOCKS

SOURCE PORT 0

DISPLAY

PORT3

PORT0

PORT1

CLK REQUEST

EEPROM

TEST PORT

SINK PORT 0

SINK PORT 1

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

IN

OUT

IN

OUT

IN

IN

C

VCC

THMVSS PAD

D Q

S_L

W_L

HOLD_L

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

SNK0 AC Coupling

SNK1 AC Coupling

(T29_SPI_MOSI) (T29_SPI_MISO)

NOTE: All unused LSOE/EO pairs should be aliased

(T29_SPI_CLK)

(T29_SPI_CS_L)

together. Other signals okay to float (TP/NC).

DEBUG: For monitoring current/voltage

100pF SRF > 40MHz

Not used in host mode.

DEBUG: For monitoring clock

Use B1 GND ball for THERM_DN

2

1R9790T29

3.3K

MF-LF402

5%1/16W

2

1R9785T29

14.0K

MF-LF

1%1/16W

402

2

1C9785T29

CERM50V5%

BYPASS=U3600.Y19::2mm

100PF

402

2

1 C9786T29

10%16VCERM402

BYPASS=U3600.Y19::5.08mm

0.01UF

78

78

2

1R9725T29

05%1/16WMF-LF402

2

1R9732T29

MF-LF

5%1/16W

100K

402

84

84 96

84 96

84

84 96

84 96

84 96

84 96

84 96

84 96

78

78 96

78 96

78

78 96

78 96

78 96

78 96

78 96

78 96

2

1R9730T29

5%

402MF-LF1/16W

100K

2

1R9731T29

1/16W5%

MF-LF

100K

402

2

1R979910K

1/16WMF-LF

402

5%

NOSTUFF

49 96

49 96

R16

P17

F1

U2

E2

R4

A2

L6

M5

N6

P5

E4

T1

T3

R2

F3

F5

H1

G2

H3

G4

H5

G6

K5

J6

E14

H17

G16

E16

A18

A16

C16

C14

A14

A12

C12

C10

A10

A8

C8

C6

A6

A4

C4

C2

F21

D21

K21

H21

P21

M21

V21

T21

E6

F19

D19

K19

H19

P19

M19

V19

T19

J4

K3

J2

K1

L4

M3

N4

P3

K17

M17

A20

B21

M1

P1

N2

L2

AA18

Y17

AA16

Y15

AA14

Y13

AA12

Y11

V3

W16

U16

V9

U8

V11

U10

V13

U12

V15

U14

U4

V7

U6

AA4

Y3

AA6

Y5

AA8

Y7

AA10

Y9

V5

V1

W2

AA20

Y21

Y19

U9700

CRITICAL

FCBGAT29

OMIT

2

1R9729T29

1/16W

402

05%

MF-LF

2

1R9793T29

3.3K

1/16WMF-LF

5%

402

2

1R9798T29

5%1/16W

10K

402MF-LF

2

1R9723T29

10K

MF-LF1/16W

5%

4022

1R9722T29

5%

402

1/16W

10K

MF-LF

2

1R9721T29

402MF-LF

10K5%1/16W

21C9729 T29

X5R16V

0.1uF10%

402

78 96

78 96

78 96

78 96

78 96

78 96

78 96

78 96

78 96

78 96

21C9728 T290.1uF X5R

10% 16V402

21C9727 T29

X5R0.1uF16V402

10%

21C9726 T29

4020.1uF X5R10% 16V

21C9725 T29

40216V

X5R0.1uF10%

21C9724 T290.1uF

10%402X5R16V

21C9723 T29

402X5R16V10%

0.1uF

21C9722 T29

X5R0.1uF10% 16V

402

2

1R9755T29

603MF-LF1/16W0.5%

1.0K

21C9721 T290.1uF

16V402X5R

10%

21C9720 T2916V4020.1uF

10%X5R

21C9730 T2916V402X5R

10%0.1uF

21C9731 T2916V402X5R

10%0.1uF

21C9732 T29

40216V10%

X5R0.1uF21C9733 T29

0.1uF16V402

10%X5R

21C9734 T2916V402

10%X5R0.1uF21C9735 T29

16V402X5R

10%0.1uF

21C9736 T2916V402

10%X5R0.1uF21C9737 T29

16V402X5R

10%0.1uF

21C9738 T2916V402X5R

10%0.1uF

21C9739 T2916V10%

0.1uF X5R 402

78 96

78 96

78 96

78 96

78 96

78 96

78 96

78 96

2

1C9790T29

402

6.3V

1UF10%

CERM

78 96

78 96

12R9751 T294025% 1/16W MF-LF10K

2

1R9796T29

1%150

402

1/16WMF-LF

21

R9795T29

1%

64.9

MF-LF1/16W

402

79 96

84

84

78

78

6

5

4

3

2

1

8

7

J9700T29

M-RT-SM78171-6006

18 96

2

1 R9743NOSTUFF

100K5%1/16WMF-LF402

2

1R9744

402

NOSTUFF

100K

MF-LF

5%1/16W

2

1 R9741NOSTUFF

100K5%1/16WMF-LF402

2

1R9742

MF-LF402

NOSTUFF

100K5%

1/16W

3

4

8

9

1

2

7

5

6

U9790M95320-RMB6TG

MLP

OMIT_TABLE

CRITICAL

80

18 96

21C9701 T290.1uF

10% 16V X5R 402

21C9700 T29X5R

0.1uF10% 16V 402

21C9702 T290.1uF

402X5R16V10%

21C9703 T290.1uF

402X5R16V10%

21C971516V10%

0.1uF402X5R

NOSTUFF

21C97160.1uF

X5R 40210% 16V

NOSTUFF

2

1R9792T29

MF-LF1/16W

402

5%3.3K

21R97110 402MF-LF5% 1/16W

NOSTUFF21R9710

0 MF-LF 4021/16W5%

NOSTUFF

21C9704 T290.1uF

10% 16V X5R 402

21C9705 T2910% 16V X5R 402

0.1uF

21C9706 T29X5R 40210% 16V

0.1uF21C9707 T29

0.1uF16V10% 402X5R

21C9740 T290.1uF

10% X5R 40216V

21C9741 T2916V

0.1uF10% 402X5R

21C9742 T29X5R

0.1uF10% 40216V

2

1R9791T29

1/16W5%

MF-LF402

3.3K

21C9743 T290.1uF

40210% 16V X5R

21C9745 T290.1uF

16V X5R 40210%

21C9744 T290.1uF

40216V X5R10%

21C9746 T290.1uF

16V10% 402X5R

21C9747 T29402X5R

0.1uF10% 16V

80 97

18 96

18 96

18 96

18 96

18 96

18 96

18 96

18 96

18 96

18 96

18 96

18 96

18 96

18 96

18 96

18 96

T29 Host (1 of 2)


TP_T29_PCIE_RESET3_L

JTAG_T29_TCK

T29_TMU_CLK_IN

DP_T29SRC_AUXCH_C_P

DP_T29SRC_AUXCH_C_N

T29_DP_ATEST

T29_R2D_C_P<2>

T29_D2R_P<3>

DP_T29SRC_ML_P<3>

DP_T29SNK1_ML_C_N<2>

DP_T29SNK1_AUXCH_PDP_T29SNK1_AUXCH_N

=PP3V3_T29_RTR

DP_T29SNK0_AUXCH_N

=PP3V3_T29_RTR

JTAG_T29_TDI

PCIE_T29_R2D_P<1>

PCIE_T29_D2R_C_N<0>

T29_LSEO<0>

DP_T29SNK0_ML_P<3>

T29_MONOBSPTP_T29_MONOBSP


JTAG_T29_TMS

JTAG_T29_TDO

=PP3V3_T29_RTR

=PP3V3_T29_RTR

SYSCLK_CLK25M_T29SYSCLK_CLK25M_T29_R

TP_T29_MONDC0

PCIE_T29_R2D_C_P<3>

PCIE_T29_R2D_N<3>



PCIE_CLK100M_T29_P

DP_T29SNK1_ML_P<3>

DP_T29SNK1_AUXCH_N

T29_LSOE<2>

T29_D2R_N<2>

DP_T29SRC_ML_P<1>

DP_T29SRC_ML_N<2>

DP_T29SRC_ML_P<2>

DP_T29SRC_HPD

DP_T29SNK0_HPD

DP_T29SRC_ML_P<0>

PCIE_CLK100M_T29_N

TP_T29_XTAL25OUT

T29_LSEO<3>

T29_LSOE<3>

T29_LSEO<2>

PCIE_T29_R2D_C_N<2>

I2C_T29_SCL

I2C_T29_SDA

PCIE_T29_D2R_P<1>

PCIE_T29_D2R_P<2>

PCIE_T29_D2R_N<3>

PCIE_T29_D2R_N<0>

TP_T29_MONDC1

PCIE_T29_R2D_C_N<1>

PCIE_T29_R2D_C_P<1>

PCIE_T29_R2D_C_P<0>

PCIE_T29_R2D_C_P<2>

PCIE_T29_D2R_N<1>

PCIE_T29_D2R_P<0>

PCIE_T29_D2R_P<3>

PCIE_T29_R2D_C_N<0>

DP_T29SNK0_ML_C_P<0>












DP_T29SNK1_AUXCH_C_P

DP_T29SNK1_AUXCH_C_N

DP_T29SNK0_ML_P<1>

DP_T29SNK0_ML_N<0>

DP_T29SNK0_ML_N<1>

DP_T29SNK1_ML_N<0>

DP_T29SNK0_AUXCH_P

DP_T29SNK0_ML_N<2>

DP_T29SNK1_ML_N<2>

DP_T29SNK1_ML_N<3>

DP_T29SNK1_AUXCH_P

DP_T29SNK1_AUXCH_N

DP_T29SNK1_ML_P<1>

DP_T29SNK1_ML_N<1>

DP_T29SNK1_ML_P<2>

DP_T29SNK1_ML_P<3>

T29_R2D_C_P<0>

T29_D2R_N<3>

T29_R2D_C_N<3>

T29_R2D_C_P<3>

T29_D2R_P<2>

T29_R2D_C_N<2>

T29_D2R_N<1>

T29_D2R_P<1>

T29_R2D_C_N<1>

T29_R2D_C_P<1>

T29_LSOE<0>

T29_D2R_N<0>

T29_D2R_P<0>

T29_R2D_C_N<0>

DP_T29SNK1_AUXCH_P

DP_T29SNK1_ML_P<0>

PCIE_T29_R2D_N<1>

DP_T29SNK1_ML_N<0>

TP_T29_TEST_POINT_1

PCIE_T29_D2R_C_P<0>

PCIE_T29_D2R_C_N<1>

PCIE_T29_D2R_C_P<1>

PCIE_T29_D2R_C_P<2>

PCIE_T29_D2R_C_N<2>

PCIE_T29_D2R_C_N<3>

PCIE_T29_D2R_C_P<3>

PCIE_T29_R2D_P<0>

PCIE_T29_R2D_N<0>

PCIE_T29_R2D_N<2>

T29_MONDC1

T29_MONDC0

PCIE_T29_R2D_P<3>

PCIE_T29_R2D_P<2>

T29_RESET_RTR_L

T29_RSENSE

T29_TMU_CLK_OUT

DP_T29SRC_ML_N<1>

DP_T29SRC_ML_N<0>

DP_T29SNK1_ML_N<3>

DP_T29SNK1_ML_P<2>

DP_T29SNK1_ML_N<2>

DP_T29SNK1_ML_P<1>

=T29_CLKREQ_L

T29_GPIO<1>

T29_GPIO<2>

T29_RSVD

TP_T29_THERM_DP

T29_TEST_EN

TP_T29_TEST_POINT_0

DP_T29SNK0_ML_N<2>

DP_T29SNK0_ML_P<1>

DP_T29SNK0_ML_N<1>

DP_T29SNK0_ML_P<0>

DP_T29SNK0_ML_N<0>

TP_T29_TEST_POINT_2

DP_T29SNK0_ML_P<2>

DP_T29SNK0_ML_N<3>

T29_PCIE_WAKE_L

T29_MONOBSN

DP_T29SNK0_ML_C_N<3> DP_T29SNK0_ML_N<3>

T29_LSEO<1>

T29_LSOE<1>



DP_T29SNK1_ML_P<0>

DP_T29SNK0_AUXCH_N

DP_T29SNK0_ML_P<3>

DP_T29SNK0_AUXCH_N

DP_T29SNK0_AUXCH_P

DP_T29SNK0_ML_P<0>

T29_RBIAS

=PP3V3_T29_RTR

DP_T29SNK1_HPD

DP_T29SNK1_ML_N<1>

T29_DP_RES

T29_TEST_POINT_3

DP_T29SNK0_ML_P<2>

DP_T29SNK0_AUXCH_PDP_T29SRC_ML_N<3>

DP_T29SNK0_AUXCH_C_N

DP_T29SNK0_AUXCH_C_P

T29_SPI_MISOT29ROM_WP_L

T29ROM_HOLD_L

=PP3V3_T29_RTR

T29_SPI_CS_L

T29_SPI_CLK

T29_SPI_MOSI

TP_T29_MONOBSN

PCIE_T29_D2R_N<2>

PCIE_T29_R2D_C_N<3>

97 OF 110

11.1.0

051-8115

86 OF 98

15 21 25 96

83 96

83 96

83 96

86 96

86 96

6 79 80 86 87

86 96

6 79 80 86 87

15 21 96

96

96

86 96

15 18 96

15 21 96

6 79 80 86 87

6 79 80 86 87

96

96

86 96

86 96

83 96

83 96

83 96

83

83 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

96

86 96

96

96

96

96

96

96

96

96

96

96

96

96

96

83 96

83 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

86 96

96

6 79 80 86 87

86 96

86 96

86 96

83 96

96

6 79 80 86 87

96

96

96

www.vinafix.vn

VCC3P3_DP_RX1

VCC3P3_DP_RX1

VCC3P3_DP_TXRX

VCC3P3_DP_TXRX

VDD3P3DP_PLL

VCC3P3_DP_TXRXBIAS

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP

VSSDP_PLL

VSSDP

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VDD1P0_DP_TXRX

VDD1P0_DP_RX1

VDD1P0_DP_TXRX

VDD1P0_DP_PLL

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VCC1P0_PE

VCC1P0_PE

VCC3P3

VCC3P3

VCC3P3

VCC3P3_T29

VCC3P3_T29

GND

VCC

(SYM 2 OF 2)




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Current numbers from Vendor slide (<REDACTED> power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.

0-ohms are placeholders for now, replace

with proper values after characterization.

2100 mA (Single Port)

2250 mA (Dual Port)

EDP: 3000 mA

135 mA (Single-Port)

152 mA (Dual-Port)

EDP: 200 mA

21

L9830T29

0402

FERR-120-OHM-1.5A

2

1 C9812T29

6.3V

1UF

CERM402

10%

2

1 C9813T29

1UF

6.3V10%

402CERM

21

R9820T29

402

5%

MF-LF1/16W

0

2

1 C9814T29

6.3V10%

402CERM

1UF

2

1 C9830T29

CERM6.3V20%2.2UF

402-LF

2

1 C9820T29

6.3V10%

402CERM

1UF

2

1 C9821T29

6.3V10%

402CERM

1UF

2

1 C9822T29

6.3V10%

402CERM

1UF

2

1 C9808T29

1UF

CERM402

10%6.3V

2

1C9800T29

10UF

X5R603

20%6.3V

2

1C9801T29

6.3V20%

603X5R

10UF

2

1C9853T29

6.3V10%

402CERM

1UF

2

1C9852T29

6.3V10%

402CERM

1UF

2

1C9844T29

6.3V10%

402CERM

1UF

2

1C9843T29

6.3V10%

402CERM

1UF

2

1 C9809T29

1UF

402

10%6.3VCERM

2

1C9870T29

6.3VCERM

20%2.2UF

402-LF

2

1C9860T29

CERM6.3V20%

2.2UF

402-LF

21

L9870T29

FERR-120-OHM-1.5A

0402

2

1C9851T29

CERM6.3V10%

402

1UF

2

1C9850T29

CERM

1UF

402

10%6.3V

21

R9860T29

MF-LF

0

402

5%1/16W

21

R9850T29

MF-LF

0

402

5%1/16W

2

1C9845T29

1UF

CERM402

10%6.3V

2

1 C9846T29

603

6.3V20%10UF

X5R 2

1 C9847T29

6.3V20%

603X5R

10UF

2

1 C9810T29

1UF

6.3V10%

402CERM 2

1 C9811T29

1UF

CERM402

10%6.3V

B19

B17

B15

B13

B11

W20

W18

U20

U18

R20

R18

B9

N20

N18

N16

L20

L18

L16

J20

J18

J16

G20

B7

G18

F17

F15

F13

F11

F9

F7

E20

E18

D17

B5

D15

D13

D11

D9

D7

D5

D3

D1

C20

C18

B3

B1T13

W8

W6

W4

V17

T17

T15

T11

T9

AA2

Y1

W14

W12

W10

T7

T5

N8

L14

L12

L10

L8

J14

J12

J10

N14

N12

N10

J8

G8

P13

R12

R10

R8

R14

G12

G10

P15

P11

P9

R6

P7

K7

M7

H7

G14

E12

E10

E8

M15

K15

H15

M13

M11

M9

K13

K11

K9

H13

H11

H9U9700

FCBGAT29

CRITICAL

OMIT

2

1 C9805T29

1UF

6.3V10%

402CERM 2

1 C9806T29

CERM402

10%6.3V

1UF

2

1 C9807T29

CERM402

10%6.3V

1UF


T29 Host (2 of 2)

PP1V05_T29_VDD_DPMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V

=PP1V05_T29_RTR

=PP3V3_T29_RTR

PP1V05_T29_VDD_DPPLL


VOLTAGE=1.05V

PP3V3_T29_DPBIAS


PP3V3_T29_PLLMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

PP3V3_T29_DPMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

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TABLE_BOARD_INFO

VERSIONALLEGRO

(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS






















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TWO OZ POWER

HALF OZ SIGNAL

0.071 PREPREGTOP

BOARD STACK-UP

2

6

7

0.370 PREPREG

HALF OZ SIGNAL

ONE OZ SIGNAL0.076 PREPREGTWO OZ GND

BOTTOM

0.101 CORETWO OZ POWER4

PHYSICAL CONSTRAINTS

BOARD THICKNESS = 62 MIL (1.5748 mm)

SPACING RULE SET

0.071 PREPREG TWO OZ GND

0.370 PREPREGONE OZ SIGNAL 0.076 PREPREG

5

3

CONSTRAINTS FOR BGA AREA

K60/62 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

0.085 MM=STANDARD 0.1 MM*1:1_DIFFPAIR =STANDARD=STANDARDY

0.200 MM* YPOWER_WIDTH 3.0 MM =STANDARD =STANDARD0.600 MM

0.300 MMY 3.0 MM =STANDARD =STANDARDPOWER_CTL 0.200 MM*

=STANDARD=STANDARD =STANDARD* N110_OHM_DIFF =STANDARD =STANDARD

=STANDARD0.075 MM110_OHM_DIFF 0.075 MM 0.15 MMTOP,BOTTOM Y 0.320 MM

0.085 MM100_OHM_DIFF 0.091 MMYTOP,BOTTOM 0.1 MM0.25 MM=STANDARD

=STANDARD=STANDARD =STANDARD110_OHM_DIFF =STANDARDISL3,ISL6 =STANDARDY

=STANDARD100_OHM_DIFF 0.081 MM0.081 MM 0.25 MMISL3,ISL6 Y 0.1 MM

=STANDARD100_OHM_DIFF N =STANDARD=STANDARD* =STANDARD=STANDARD


K60/K62 RULE DEFINITIONS

=STANDARD=STANDARD=STANDARD=STANDARD* N68_OHM_DIFF =STANDARD

0.13 MMY68_OHM_DIFF 0.090 MM =STANDARD 0.1 MMISL3,ISL6 0.16 MM

0.1 MM0.2 MMY85_OHM_DIFF =STANDARDTOP,BOTTOM 0.085 MM0.125 MM

=STANDARD85_OHM_DIFF 0.085 MMY 0.2 MM 0.1 MM0.115 MMISL3,ISL6

55_OHM_SE 0.076 MM =STANDARD* =STANDARDY =STANDARD0.076 MM

=STANDARD55_OHM_SE YTOP,BOTTOM 0.085 MM 0.085 MM

0.085 MM 15 MMYTOP,BOTTOM 0.1 MM50_OHM_SE

=STANDARD=STANDARDY*42_OHM_SE 0.135 MM 0.090 MM =STANDARD

MM 15.5.1TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,BOTTOM NO_TYPE,BGA,BGA_P1MM

0.21 MMY =STANDARDTOP,BOTTOM34_OHM_SE 0.090 MM

=STANDARD=STANDARD*39_OHM_SE Y 0.090 MM =STANDARD0.159 MM

0.085 MM =STANDARD=STANDARD* Y 0.1 MM50_OHM_SE =STANDARD

* N90_OHM_DIFF =STANDARD =STANDARD =STANDARD=STANDARD =STANDARD

ISL3,ISL6 0.085 MM 12 MM 0.1 MMY 0.2 MM90_OHM_DIFF 0.099 MM

0.1 MM0.13 MMTOP,BOTTOM Y =STANDARD0.090 MM68_OHM_DIFF 0.165 MM

TOP,BOTTOM 0.110 MM 0.085 MMY =STANDARD 0.2 MM90_OHM_DIFF 0.1 MM

STANDARD*VR_CONTROLVR_CONTROL

=STANDARD85_OHM_DIFF N* =STANDARD=STANDARD=STANDARD=STANDARD

* STANDARDSWITCHNODEVR_CONTROL

BGA* BGA_P1MMCLK_PCIE

*MEM_CLK BGA_P1P5MMBGA

** BGA BGA_P1MM

BGA_P1MM* BGA_P1MM*

* 0.2 MM ?BGA_P2MM

* 0.8 MMSWITCHNODE 1000

* ?BGA_P1P5MM 0.15 MM

=DEFAULT ?BGA_P1MM *

=STANDARD39_OHM_SE TOP,BOTTOM Y 0.175 MM 0.090 MM

POWER_CTLPOWER BGA_P1MM

POWER_WIDTH*POWER

* *VR_CONTROL SWITCHNODE

BGA*CLK_PCI BGA_P1MM

6:1_SPACING * 0.6 MM ?

* 0.5 MM ?5:1_SPACING



STANDARD * =DEFAULT ?

2:1_SPACING ?0.2 MM*

TOP,BOTTOM =STANDARD42_OHM_SE Y 0.151 MM 0.090 MM

* ?7X_DIELECTRIC 0.532 MM

0.497 MM ?TOP,BOTTOM7X_DIELECTRIC

=STANDARD* Y =STANDARD34_OHM_SE 0.19 MM 0.090 MM =STANDARD

DEFAULTVR_CTL_PHY BGA_P1MM

?* 0.380 MM5X_DIELECTRIC


5X_DIELECTRIC TOP,BOTTOM ?0.355 MM

3.5:1_SPACING * ?0.35 MM

2.5:1_SPACING * ?0.25 MM

DEFAULT * ?0.1 MM


POWER ** STANDARD

GND ** STANDARD

* ?2X_DIELECTRIC 0.155 MM

0.145 MM ?2X_DIELECTRIC TOP,BOTTOM

0.230 MM3X_DIELECTRIC * ?

0.305 MM* ?4X_DIELECTRIC

=DEFAULT=DEFAULTY =DEFAULT=DEFAULTSTANDARD 12.7 MM*

* Y =50_OHM_SE 0 MM0 MM100 MMDEFAULT =50_OHM_SE

0.2 MM*PWR_P2MM 1000

BGA BGA_P1MM*CLK_LPC

GND_P2MM * 0.2 MM 1000

GND =STANDARD* ?

GNDVR_CONTROL * STANDARD

VR_CTL_PHY POWER_CTL*

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NET_TYPE

SPACING

SPACING

NET_TYPE

Memory Bus Constraints


Memory Net Properties

ELECTRICAL_CONSTRAINT_SET SPACING PHYSICALPHYSICAL

NET_TYPE

VOLTAGEVOLTAGE

Memory Bus Spacing Group Assignments

MEMORY MISC PROPERTIES

PHYSICAL

I162

I168

I169

I170

I171

I172

I173

I174

I175

I177

*MEM_DQ_BYTE4 MEM_DQ_DIFFBYTEMEM_DQ_BYTE0

MEM_DQ_BYTE1 * MEM_DQ_DIFFBYTEMEM_DQ_BYTE0

MEM_DQ_BYTE2 MEM_DQ_DIFFBYTE*MEM_DQ_BYTE0

MEM_DQ_BYTE0 MEM_DQ_BYTE0 * MEM_DQ_SAMEBYTE

* MEM_DQ_DIFFBYTEMEM_DQ_BYTE2 MEM_DQ_BYTE5

MEM_DQ_BYTE4MEM_DQ_BYTE2 * MEM_DQ_DIFFBYTE

MEM_DATA2MEMMEM_CMD *MEM_DQ_BYTE2

MEM_DATA2MEMMEM_CTRL *MEM_DQ_BYTE0

MEM_CMD * MEM_DATA2MEMMEM_DQ_BYTE0

MEM_DATA2MEMMEM_CMD *MEM_DQ_BYTE4


MEM_DQ_BYTE2MEM_DQ_BYTE2 * MEM_DQ_SAMEBYTE

MEM_DQ_DIFFBYTEMEM_DQ_BYTE2 MEM_DQ_BYTE6 *

MEM_DQ_DIFFBYTEMEM_DQ_BYTE4MEM_DQ_BYTE1 *


MEM_DQ_DIFFBYTEMEM_DQ_BYTE5 *MEM_DQ_BYTE1

MEM_DATA2MEM*MEM_DQ_BYTE4 MEM_CTRL

MEM_DQ_DIFFBYTE*MEM_DQ_BYTE3MEM_DQ_BYTE2

MEM_DQ_BYTE4 MEM_2OTHER**



MEM_DQ_SAMEBYTEMEM_DQ_BYTE4 *MEM_DQ_BYTE4

MEM_DQ_BYTE3 MEM_DQ_BYTE7 MEM_DQ_DIFFBYTE*

MEM_DQ_BYTE3 MEM_DQ_SAMEBYTEMEM_DQ_BYTE3 *

MEM_DATA2MEMMEM_CTRL *MEM_DQ_BYTE2

MEM_CMD * MEM_CMD2MEMMEM_CTRL

MEM_CTRL MEM_CTRL2CTRLMEM_CTRL *

MEM_CTRL ** MEM_2OTHER

*MEM_DQS MEM_DQS2MEMMEM_CTRL

MEM_CMD MEM_DQS2MEM*MEM_DQS

MEM_DQS2MEMMEM_DQS MEM_DQ_BYTE1 *

MEM_DQ_BYTE0MEM_DQS MEM_DQS2MEM*





MEM_DQ_BYTE6 MEM_DQS2MEMMEM_DQS *

**MEM_DQS MEM_2OTHER

MEM_DQS MEM_DQ_BYTE7 MEM_DQS2MEM*

MEM_DQ_BYTE5 *MEM_CTRL MEM_DATA2MEM

MEM_DQ_BYTE5 *MEM_CMD MEM_DATA2MEM


*MEM_DQ_BYTE5MEM_DQ_BYTE5 MEM_DQ_SAMEBYTE


=STANDARD=34_OHM_SE =STANDARD=34_OHM_SE=34_OHM_SE*MEM_34S =34_OHM_SE

=42_OHM_SE =STANDARD* =42_OHM_SE =42_OHM_SE =STANDARDMEM_42S =42_OHM_SE

=68_OHM_DIFF =68_OHM_DIFF=68_OHM_DIFF=68_OHM_DIFF=68_OHM_DIFF=68_OHM_DIFF*MEM_68D

=STANDARDMEM_39S * =39_OHM_SE =STANDARD=39_OHM_SE=39_OHM_SE =39_OHM_SE

* =4:1_SPACING ?MEM_CLK2MEM

=4:1_SPACING*MEM_DQS2MEM ?

?=5:1_SPACING*MEM_DQ_DIFFBYTE

MEM_2OTHERMEM_CMD **

MEM_CMD2CMDMEM_CMD *MEM_CMD

*MEM_CLK MEM_2OTHER*

MEM_CLK *MEM_CLK MEM_CLK2MEM

=50_OHM_SE* =STANDARD=50_OHM_SEMEM_50S =50_OHM_SE =STANDARD=50_OHM_SE

?*MEM_CMD2MEM =3:1_SPACING

MEM_CMD2CMD ?=2:1_SPACING*

MEM_DATA2MEM*MEM_CTRLMEM_DQ_BYTE1

MEM_CMD *MEM_DQ_BYTE1 MEM_DATA2MEM

*MEM_DQ_BYTE2MEM_DQ_BYTE1 MEM_DQ_DIFFBYTE

MEM_DQ_SAMEBYTE*MEM_DQ_BYTE1 MEM_DQ_BYTE1

=42_OHM_SE* =42_OHM_SE 0.1016 MM0.1016 MM=42_OHM_SE =42_OHM_SEMEM_42S_D

*MEM_DQ_BYTE0 MEM_DQ_BYTE3 MEM_DQ_DIFFBYTE

MEM_DQ_DIFFBYTEMEM_DQ_BYTE0 MEM_DQ_BYTE5 *

MEM_2OTHER * ?=5:1_SPACING

* ?=4:1_SPACINGMEM_DATA2MEM

?=3:1_SPACINGMEM_DQ_SAMEBYTE *

?=3:1_SPACINGMEM_CTRL2MEM *

?* =2.5:1_SPACINGMEM_CTRL2CTRL

MEM_DQ_BYTE3 * * MEM_2OTHER

MEM_DATA2MEM*MEM_CMDMEM_DQ_BYTE3

*MEM_DQ_BYTE7MEM_DQ_BYTE2 MEM_DQ_DIFFBYTE



*MEM_DQ_BYTE0 MEM_2OTHER*

MEM_POWER_WIDTHMEM_POWER_PHY *

MEM_2OTHER**MEM_DQ_BYTE5

MEM_DQ_BYTE7 MEM_2OTHER**

MEM_DQ_SAMEBYTEMEM_DQ_BYTE7 *MEM_DQ_BYTE7

*MEM_CMDMEM_DQ_BYTE7 MEM_DATA2MEM

*MEM_CTRLMEM_DQ_BYTE7 MEM_DATA2MEM

* * MEM_2OTHERMEM_DQ_BYTE6

MEM_DQ_BYTE7 MEM_DQ_DIFFBYTE*MEM_DQ_BYTE6

MEM_DQ_BYTE6 *MEM_DQ_BYTE6 MEM_DQ_SAMEBYTE

MEM_CMDMEM_DQ_BYTE6 * MEM_DATA2MEM

MEM_DATA2MEM*MEM_DQ_BYTE6 MEM_CTRL

MEM_DQ_BYTE3 MEM_DQ_BYTE6 * MEM_DQ_DIFFBYTE

MEM_DQ_BYTE5MEM_DQ_BYTE3 MEM_DQ_DIFFBYTE*

* MEM_2OTHERMEM_DQ_BYTE1 *

MEM_DQ_DIFFBYTE*MEM_DQ_BYTE1 MEM_DQ_BYTE7


MEM_DQ_BYTE4 MEM_DQ_DIFFBYTEMEM_DQ_BYTE3 *

MEM_CTRLMEM_DQ_BYTE3 * MEM_DATA2MEM


Memory ConstraintsSYNC_MASTER=K60_ROSITA

* Y =STANDARDMEM_POWER_WIDTH =STANDARD=STANDARD0.500 MM 0.250 MM

?*MEM_POWER =3:1_SPACING

MEM_2OTHER*MEM_DQ_BYTE2 *

MEM_POWERMEM_POWER_PHY CPU_DIMM_VREF_B_SWMEM_POWER_PHY MEM_POWER VREFMARGIN_DIMMB_DQ

PMMEM_50S MEM_RESET_L

MEM_DQS MEM_A_DQS_N<7>MEM_42S_D

MEM_A_DQS_N<6>MEM_42S_D MEM_DQS

MEM_DQSMEM_42S_D MEM_A_DQS_P<7>

MEM_42S_D MEM_A_DQS_P<2>MEM_DQS

MEM_DQS MEM_A_DQS_N<2>MEM_42S_D

MEM_B_DQ<55..48>MEM_42S MEM_DQ_BYTE6

MEM_A_ODT<3..0>MEM_CTRLMEM_39S

MEM_B_DQS_P<5>MEM_DQSMEM_42S_D

MEM_DQS MEM_B_DQS_N<3>MEM_42S_D

MEM_DQ_BYTE5MEM_42S MEM_B_DQ<47..40>MEM_DQ_BYTE4 MEM_B_DQ<39..32>MEM_42S

MEM_DQ_BYTE3MEM_42S MEM_B_DQ<31..24>MEM_DQ_BYTE2 MEM_B_DQ<23..16>MEM_42S

MEM_DQ_BYTE1MEM_42S MEM_B_DQ<15..8>MEM_DQ_BYTE0MEM_42S MEM_B_DQ<7..0>

MEM_42S MEM_DQ_BYTE6 MEM_A_DQ<55..48>

MEM_DQS MEM_A_DQS_P<0>MEM_42S_D

MEM_CMD MEM_B_WE_LMEM_34S

MEM_B_CAS_LMEM_CMDMEM_34S

MEM_CTRL MEM_B_ODT<3..0>MEM_39S

MEM_34S MEM_B_RAS_LMEM_CMD

MEM_34S MEM_B_A<15..0>MEM_CMD

MEM_A_BA<2..0>MEM_CMDMEM_34S

MEM_A_A<15..0>MEM_CMDMEM_34S

MEM_42S MEM_A_DQ<39..32>MEM_DQ_BYTE4


MEM_42S MEM_DQ_BYTE2 MEM_A_DQ<23..16>

MEM_A_DQ<15..8>MEM_42S MEM_DQ_BYTE1

MEM_A_DQ<7..0>MEM_42S MEM_DQ_BYTE0

MEM_A_DQS_N<0>MEM_DQSMEM_42S_D


MEM_42S_D MEM_A_DQS_N<1>MEM_DQS

MEM_DQS MEM_B_DQS_N<2>MEM_42S_D

MEM_B_DQS_P<6>MEM_DQSMEM_42S_D

MEM_DQSMEM_42S_D MEM_B_DQS_N<7>

MEM_68D MEM_A_CLK_P<3..0>MEM_CLK

MEM_CLKMEM_68D MEM_A_CLK_N<3..0>

MEM_CTRLMEM_39S MEM_A_CKE<3..0>

MEM_B_DQS_N<6>MEM_DQSMEM_42S_D

MEM_42S_D MEM_DQS MEM_A_DQS_P<1>

MEM_A_CAS_LMEM_CMDMEM_34S

MEM_DQS MEM_B_DQS_P<7>MEM_42S_D

MEM_CMD MEM_A_WE_LMEM_34S

MEM_B_CLK_N<3..0>MEM_CLKMEM_68D

MEM_B_CLK_P<3..0>MEM_CLKMEM_68D

MEM_B_CKE<3..0>MEM_39S MEM_CTRL

MEM_A_RAS_LMEM_CMDMEM_34S





MEM_B_DQS_P<3>MEM_42S_D MEM_DQS


MEM_CTRL MEM_B_CS_L<3..0>MEM_39S

MEM_34S MEM_CMD MEM_B_BA<2..0>



MEM_42S MEM_B_DQ<63..56>MEM_DQ_BYTE7



MEM_42S_D MEM_DQS MEM_A_DQS_N<4>

MEM_42S_D MEM_DQS MEM_A_DQS_N<3>


MEM_42S_D MEM_DQS MEM_A_DQS_P<4>

MEM_CTRLMEM_39S MEM_A_CS_L<3..0>


MEM_42S_D MEM_A_DQS_N<5>MEM_DQS


MEM_POWER_PHY MEM_POWER CPU_DIMM_VREF_A

MEM_POWERMEM_POWER_PHY CPU_DIMM_VREF_B

MEM_POWER_PHY MEM_POWER CPU_DDR_VREF

MEM_POWERMEM_POWER_PHY VREFMARGIN_DIMMA_DACOUT

MEM_POWERMEM_POWER_PHY VREFMARGIN_DIMMA_OPFB

MEM_POWER_PHY MEM_POWER VREFMARGIN_DIMMA_DQ

MEM_POWER_PHY MEM_POWER CPU_DIMM_VREF_A_SW

MEM_POWER_PHY MEM_POWER VREFMARGIN_DIMMB_DACOUT

MEM_POWER_PHY MEM_POWER VREFMARGIN_DIMMB_OPFB

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12 32

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12 32

12 32

12 32

12 32

12 32

12 32

12 32

12 32

12 32

12 31

12 31

12 31

12 31

12 31

12 30

12 30

12 32

12 32

12 32

12 32

12 32

12 32

12 32

12 32

12 32

12 32

12 32

12 32

12 32

12 30

12 32

12 32

12 30

12 32

12 30

12 32

12 32

12 31

12 30

12 32

12 32

12 32

12 32

12 32

12 32

12 31

12 31

12 32

12 32

12 32

12 32

12 32

12 32

12 32

12 32

12 32

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12 32

12 32

12 32

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28

28

28

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TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM










SPACING

CPU

UNUSED PCIE

UNUSED CLOCKS

CLOCKS

SATA

PCIE GRAPHICS

PCI-Express

SATA Interface Constraints

PCIE REF CLOCKS

PCIE I/O

DMI


NET_TYPE

PHYSICAL SPACING

NET_TYPE


SATA

PHYSICAL

CPU ITP

CPU_MISC

PCIE

ANY OTHER LYNNFIELD CONSTRAINTS NOT COVERED ON PAGES 101 AND 107 SHOULD GO ON THIS PAGE TOO

I299

I300

I301

I302

I303

I304

I305

I306

I315

I316

I317

I318

I319

I320

I321

I322

I323

I324

I325

I326

I327

I328

I329

I330

I331

I332

I333

I334

I335

I336

I337

I338

I339

I340

I341

I342

I343

I344

I345

I347

I348

I349

I350

=6:1_SPACING ?TOP,BOTTOMSATA

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFFSATA_90D *

* 0.2 MMCPU_ITP ?

CPU_RCOMP_PHY 0.254 MM* Y 3.0 MM =STANDARD0.200 MM =STANDARD

?0.2 MM*CPU_RCOMP

=4:1_SPACING ?TOP,BOTTOMPCIE*PCIE =4X_DIELECTRIC ?

* =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFFCLK_PCIE_90D

=85_OHM_DIFF* =85_OHM_DIFFPCIE_85D =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

=6:1_SPACINGSATA * ?

=50_OHM_SE=50_OHM_SE =50_OHM_SE =STANDARD=STANDARD*CPU_50S =50_OHM_SE

CLK_PCIE * ?0.5 MM

PCIE/DMI/FDI/SATA CONSTRAINTSSYNC_MASTER=K62 SYNC_DATE=01/06/2011

PCIE_85D PCIE PCIE_USB3_1_D2R_P

PCIE_85D PCIE PCIE_USB3_1_D2R_C_N

XDP_CPU_TRST_LCPU_50S CPU_ITP

XDP_CPU_TMSCPU_ITPCPU_50S

XDP_CPU_TCKCPU_50S CPU_ITP

XDP_CPU_TDICPU_50S CPU_ITP

XDP_CPU_TDOCPU_ITPCPU_50S

PCIE PCIE_USB3_2_R2D_C_NPCIE_85D

PCIE_85D PCIE_USB3_1_D2R_NPCIE

PCIE_USB3_1_D2R_C_PPCIE_85D PCIE

PCIE_85D PCIE PCIE_USB3_2_R2D_N

PCIE PCIE_USB3_2_R2D_C_PPCIE_85D

PCIE_USB3_2_D2R_PPCIEPCIE_85D

PCIE_85D PCIE PCIE_USB3_2_D2R_C_P

CPU_ITPCPU_50S XDP_OBSDATA_B<3..0>

PCIE_USB3_2_D2R_NPCIEPCIE_85D

CPU_CFG<17..0>CPU_ITPCPU_50S

PCIE_85D PCIE PCIE_USB3_1_R2D_N

PCIEPCIE_85D PCIE_USB3_1_R2D_C_NPCIE_85D PCIE PCIE_USB3_1_R2D_C_P

PCIE_USB3_2_D2R_C_NPCIEPCIE_85D

CPU_50S XDP_CPU_CFG<0>CPU_ITP

CPU_RCOMPCPU_RCOMP_PHY CPU_PEG_COMP

CPU_ITPCPU_50S XDP_BPM_L<7..0>

PCIE_USB3_2_R2D_PPCIE_85D PCIE

SATA_SSD_R2D_NSATASATA_90D

CLK_PCIE DMI_CLK100M_CPU_NCLK_PCIE_90D

DMI_MIDBUS_CLK100M_PCLK_PCIE_90D CLK_PCIE

PCIE_85D PCIE DMI_S2N_P<3..0>

CLK_PCIECLK_PCIE_90D DMI_MIDBUS_CLK100M_N

PCIE_85D PCIE DMI_S2N_N<3..0>

PCIE_CLK100M_MINI_PCLK_PCIE_90D CLK_PCIE

CLK_PCIE GPU_CLK100M_PCIE_NCLK_PCIE_90D

PCIE_CLK100M_FW_NCLK_PCIECLK_PCIE_90D

PEG_R2D_C_N<15..0>PCIEPCIE_85D

PCIEPCIE_85D PCIE_MINI_R2D_N

PCIE_CLK100M_ENET_PENET_MIIENET_100D

CLK_PCIE_90D PCIE_CLK100M_FW_PCLK_PCIE

PCIE PEG_D2R_N<15..0>PCIE_85D

PCIEPCIE_85D PCIE_MINI_R2D_C_N

ENET_MII PCIE_CLK100M_ENET_NENET_100D

CLK_PCIE PCIE_CLK100M_MINI_NCLK_PCIE_90D

GPU_CLK100M_PCIE_PCLK_PCIECLK_PCIE_90D

DMI_CLK100M_CPU_PCLK_PCIECLK_PCIE_90D

PCIE_85D PCIE_MINI_D2R_PPCIE

PCIE_FW_R2D_C_NPCIEPCIE_85D

PCIE_FW_D2R_PPCIEPCIE_85D

PEG_R2D_C_P<15..0>PCIEPCIE_85D

PEG_D2R_P<15..0>PCIEPCIE_85D

PCIE_MINI_R2D_PPCIE_85D PCIE

PCIEPCIE_85D PCIE_MINI_R2D_C_P

PCIE_85D PCIE_MINI_D2R_NPCIE

PCIE_85D PCIE DMI_N2S_N<3..0>PCIE_85D PCIE DMI_N2S_P<3..0>

PCIE_FW_D2R_C_NPCIE_85D PCIE

PCIE_FW_D2R_C_PPCIE_85D PCIE

PCIE_FW_D2R_NPCIEPCIE_85D

PCIE_FW_R2D_C_PPCIE_85D PCIE

PCIE_FW_R2D_NPCIE_85D PCIE

PCIE_85D PCIE_FW_R2D_PPCIE

MXM_PCIE_D2R_P<7..0>PCIE_85D PCIE

MXM_PCIE_R2D_N<7..0>PCIEPCIE_85D

MXM_PCIE_R2D_P<7..0>PCIE_85D PCIE

MXM_PCIE_D2R_N<7..0>PCIE_85D PCIE

SATA SATA_HDD_R2D_NSATA_90D

SATA_HDD_R2D_C_NSATASATA_90D

SATA SATA_HDD_R2D_PSATA_90D

SATA SATA_HDD_R2D_C_PSATA_90D

SATA_ODD_D2R_C_NSATASATA_90D

SATA SATA_ODD_D2R_NSATA_90D

SATA_ODD_D2R_C_PSATASATA_90D

SATA SATA_ODD_R2D_NSATA_90D

SATA SATA_ODD_R2D_PSATA_90D

SATA_ODD_D2R_PSATASATA_90D

SATA SATA_ODD_R2D_C_PSATA_90D

SATA SATA_ODD_R2D_C_NSATA_90D

SATASATA_90D SATA_HDD_D2R_C_P

PCH_CLK100M_DMI_PCLK_PCIECLK_PCIE_90D

PCH_CLK100M_DMI_NCLK_PCIECLK_PCIE_90D

PCH_CLK96M_DOT_PCLK_PCIECLK_PCIE_90D

PCH_CLK96M_DOT_NCLK_PCIECLK_PCIE_90D

PCH_CLK100M_SATA_PCLK_PCIECLK_PCIE_90D

PCH_CLK100M_SATA_NCLK_PCIECLK_PCIE_90D

ITPXDP_CLK100M_PCLK_PCIECLK_PCIE_90D

CLK_PCIE ITPXDP_CLK100M_NCLK_PCIE_90D

CLK_PCIE ITPCPU_CLK100M_PCLK_PCIE_90D

CLK_PCIE ITPCPU_CLK100M_NCLK_PCIE_90D

CLK_PCIE TP_CLK133M_PCH_NCLK_PCIE_90D

CLK_PCIE TP_CLK133M_PCH_PCLK_PCIE_90D

XDP_CPU_CLK100M_PCLK_PCIE_90D CLK_PCIE

XDP_CPU_CLK100M_NCLK_PCIE_90D CLK_PCIE

PCIE_85D PCIE MXM_PCIE_D2R_P<8..15>PCIEPCIE_85D MXM_PCIE_R2D_N<8..15>

PCIE_85D PCIE MXM_PCIE_R2D_P<8..15>

PCIE_85D PCIE MXM_PCIE_D2R_N<8..15>

PCIE_USB3_1_R2D_PPCIE_85D PCIE

SATASATA_90D SATA_SSD_D2R_C_NSATASATA_90D SATA_SSD_D2R_C_PSATASATA_90D SATA_SSD_D2R_NSATASATA_90D SATA_SSD_D2R_P

SATA_SSD_R2D_PSATASATA_90D

SATA_SSD_R2D_C_NSATASATA_90D

SATASATA_90D SATA_SSD_R2D_C_P

SATA SATA_HDD_D2R_PSATA_90D

SATA SATA_HDD_D2R_NSATA_90D

SATA SATA_HDD_D2R_C_NSATA_90D

102 OF 110

11.1.0

051-8115

90 OF 98

11 25

11 25

11 25

11 25

11 25

25

10 15 25

25

10

11 25

42

11 18

10 19

10 19

18 33

9

18 39

9 77

33

18 37

18 39

9 77

18 33

18 37

18 33

9

11 18

18 33

18 39

18 39

9 77

9 77

33

18 33

18 33

10 19

10 19

39

39

18 39

18 39

39

39

75 77

75 77

75 77

75 77

42

18 42

42

18 42

42

18 42

42

42

42

18 42

18 42

18 42

42

18 26

18 26

18 26

18 26

18 26

18 26

18 25

18 25

11 18

11 18

26

26

25

25

75 77

75 77

75 77

75 77

42

42

18 42

18 42

42

18 42

18 42

18 42

18 42

42

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36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NET_TYPESPACING

PCI Bus Constraints

ELECTRICAL_CONSTRAINT_SET PHYSICAL

SPI Interface Constraints

HD Audio Interface Constraints

SMBus Interface Constraints

XTAL Constraints

LPC Bus Constraints

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET SPACING

PCH CONSTRAINTS

PHYSICAL SPACING

NET_TYPE

NET_TYPE

SPACINGPHYSICAL

I322

I323

I324

I325

I326

I327

I328

I329

I330

I331

I332

I334

I335

I336

I337

I338

I339

I340

I341

I342

I343

I344

I345

I346

I347

I348

I349

I350

I351

I352

I354

I355

I356

I357

I372

I373

I374

I375

I376

I377

I378

I379

I380

I381

I382

IBEX PEAK CONSTRAINTSSYNC_DATE=01/06/2011SYNC_MASTER=K62

CLK_PCH_55S =55_OHM_SE =55_OHM_SE =STANDARD=55_OHM_SE =STANDARD* =55_OHM_SE

=STANDARDPCI * ?

* 0.15 MM ?LPC

=STANDARD=55_OHM_SECLK_LPC_55S * =55_OHM_SE =55_OHM_SE =STANDARD=55_OHM_SE

=STANDARD=55_OHM_SEPCH_55S * =55_OHM_SE =STANDARD=55_OHM_SE=55_OHM_SE

0.2 MMCLK_PCI * ?

XTAL =4X_DIELECTRIC ?*

SPI ?* 0.2 MM

=55_OHM_SE =STANDARD=55_OHM_SE =55_OHM_SESMB_55S * =STANDARD=55_OHM_SE

=2x_DIELECTRICSMB * ?

0.2 MM*CLK_LPC ?

=55_OHM_SE =STANDARD*LPC_55S =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD

* =STANDARD=STANDARDHDA_55S =55_OHM_SE =55_OHM_SE=55_OHM_SE =55_OHM_SE

=2x_DIELECTRICHDA * ?

=55_OHM_SE* =STANDARD =STANDARDSPI_55S =55_OHM_SE =55_OHM_SE=55_OHM_SE

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF* =100_OHM_DIFFCLK_XTAL =100_OHM_DIFF =100_OHM_DIFF

0.2 MM ?*ITP_PCH

0.2 MM ?COMP_PCH *

=4:1_SPACINGCLK_PCH * ?

=STANDARD=55_OHM_SEPCI_55S =STANDARD=55_OHM_SE* =55_OHM_SE=55_OHM_SE

=55_OHM_SE =STANDARDCLK_PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD

PCI_REQ0_LPCIPCI_55S

PCI_55S PCIPCI_REQ2_L

PCI_REQ3_LPCI_55S PCI

PCI_55S PCIPCI_REQ1_L

PCH_PEG_CLKREQ_LPM

LPCLPC_55SLPC_FRAME_L

LPC_AD<3..0>LPCLPC_55S

CLK_PCI_55S CLK_PCIPCH_CLK33M_PCIOUT

CLK_PCIPCH_CLK33M_PCIIN

CLK_PCI_55S

DP_AUXCH_ISOLPM

PM XDPCPU_PLTRST_L

CPU_SKTOCCPM

PM PLT_RST_BUF_L

ENET_SW_RESET_LPM

ENET_RESET_LOGIC_LPM

ALL_SYS_PWRGDPM

PM AUD_IPHS_SWITCH_EN_PCH

ENET_RESET_FET_LPM

ENET_CLKREQ_FET_LPM

PGOOD_5V_1V05_3V3PM

PGOOD_CPU_UNCOREPM

PGOOD_3V3_1V05PM

PGOOD_PCH_S0_RPM

PM_EN_USB_PWRPM

T29_DP_PORTA_PWR_ENPM

DP_GPU_T29_SELPM

PM T29_CLKREQ_LPM FW_MINI_CLKREQ_L

PM T29_MCU_INT_L

PM T29_DP_PORTB_PWR_EN

ENET_CLKREQ_LPMT29_SW_RESET_LPM

PM BLC_GPIO

CLK_LPCCLK_LPC_55SLPC_CLK33M_LPCPLUS

CLK_LPC_55S PMPM_CLK32K_SUSCLK_R

CLK_LPC_55S PMPM_CLK32K_SUSCLK

LPC_CLK33M_LPCPLUS_RCLK_LPC_55S CLK_LPC

LPC_R_AD<3..0>LPC_55S LPC

LPC_FRAME_R_LLPC_55S LPC

SPI_MOSI_1_RSPI_55S SPI

SPISPI_55S SPI_CS0_R_L

SPI_MISO_RSPI_55S SPI

SPI_MOSISPISPI_55S

SPI_55S SPI SPI_MOSI_R

SPI_CLK_RSPI_55S SPI

SPI_CLKSPISPI_55S

SPI_ALT_CS_LSPI_55S SPI

SPI_55S SPI SPIROM_USE_MLB

SPISPI_55S SPI_ALT_MOSI

SPI_MLB_CS_LSPI_55S SPI

SPI_55S SPI SPI_ALT_MISO

HDAHDA_55S HDA_SDOUT_R

HDAHDA_55S HDA_SDIN0

HDA_SYNC_RHDAHDA_55S

SPI_55S SPI SPI_ALT_CLK

LPC_CLK33M_SMC_RCLK_LPCCLK_LPC_55S

HDAHDA_55S HDA_RST_R_L

PCH_55SPCH_DMI2RBIAS

COMP_PCH

PCH_55S ITP_PCH XDP_PCH_TDI

XTALCLK_XTAL CK505_XTAL_IN

CK505_XTAL_OUT_RXTALCLK_XTAL

CLK_XTAL XTAL CK505_XTAL_OUT

CLK_LPC_55S CLK_LPCLPC_CLK33M_SMC

HDA_55S AUD_SPKR_OUTLO1R_POUTHDA

AUD_SPKR_OUTLO1R_NOUTHDAHDA_55S

PCH_55S COMP_PCHPCH_XCLK_RCOMP

PCH_55S ITP_PCHXDP_PCH_TCK

PCH_55S COMP_PCHPCH_SATA3RBIAS

SPI SPI_MISOSPI_55S

PCH_CLK32K_RTCX1CLK_XTAL XTAL

PCH_CLK32K_RTCX2CLK_XTAL XTAL

XTALCLK_XTAL PCH_CLK32K_RTCX2XTALCLK_XTAL PCH_CLK32K_RTCX1

CLK_XTAL XTAL PCH_CLK32K_RTCX2_RXTALCLK_XTAL PCH_CLK32K_RTCX1_R

HDA_55S AUD_SPKR_OUTLO2L_NOUTHDA

HDA_55S HDA HDA_SDOUT

HDAHDA_55S HDA_BIT_CLK_R

HDA_55S HDA HDA_BIT_CLK

XTALCLK_XTALPCH_CLK25M_XTALIN

AUD_SPKR_OUTLO2R_POUTHDAHDA_55S

SPI_CLK_1_RSPI_55S SPI

HDAHDA_55S HDA_RST_L

HDA HDA_SYNCHDA_55S

HDA_55S HDA AUD_SDI_R

HDA AUD_SPDIF_OUT

HDA_55S HDA AUD_SPKR_OUTLO1L_NOUT

HDA_55S AUD_SPKR_OUTLO1L_POUTHDA

PCH_55S COMP_PCHPCH_SATA3COMP

XTALCLK_XTALPCH_CLK25M_XTALOUT

CLK_XTAL XTALPCH_CLK25M_XTALIN_R

CLK_XTAL XTALPCH_CLK25M_XTALOUT_R

HDA_55S AUD_SPKR_OUTLO2R_NOUTHDA

HDA_55S HDA AUD_SPKR_OUTLO2L_POUT

XTALCLK_XTALUSB_HUB2_XTAL1


HDA AUD_SPDIF_CHIP

CLK_PCHCLK_PCH_55S PCH_CLK14P3M_REFCLK


COMP_PCHPCH_55SPCH_USB_RBIAS

PCH_55SPCH_SATAICOMP

COMP_PCH

PCH_55S XDP_PCH_TDOITP_PCH

PCH_55S ITP_PCHXDP_PCH_TMS


PCH_55S COMP_PCHPCH_DMI_COMP

COMP_PCHPCH_55SUSB_HUB1_RBIAS

PCH_55S COMP_PCHUSB_HUB2_RBIAS

PM AUD_SPDIF_IN

SPISPI_55S SPI_CS0_L

103 OF 110

11.1.0

051-8115

91 OF 98

20

20

20

20

21

18 46 48

18 46 48

20 27

18 27

15 18 25 84

25 27

63

27

15 21 36

36

64 97

21 25

36 37

64 97

64 97

64 97

64 97

43 63

20 25 82 97

18 61 83

15 21 80

15 18

20 84

20 25

15 18 36

15 21 80

6 15 21

27 48

9 19 97

9 46 97

20 27

18

18

18

18 48

55

55

18 48 55

18 48 55

55

48

21 48

48

48 55

48

18

18 56

18

48

20 27

18

19

18 25

26

26

26

27 46

98

98

18

18 25

18

18 48 55

18 27 91

18 27 91

18 27 91

18 27 91

27

27

98

15 18 56

18

18 56

18 27 79

98

18

18 56

18 56

56

56 60

98

98

18

18 27

27

27

98

98

35

35

56

18 26

34

20

18

18 25

18 25

34

19

34

35

60 83 97

48

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TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM





































36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NET_TYPE

UNUSED FW NETS PHYSICAL PROPERTIES


FireWire Net PropertiesNET_TYPE

PHYSICAL SPACING

SPACINGPHYSICALELECTRICAL_CONSTRAINT_SET

NET_TYPESPACINGELECTRICAL_CONSTRAINT_SET

SOURCE:BROADCOM 5764M-DS04-RDS. PAGE 38

CAESAR II (ETHERNET) CONSTRAINTS

FireWire Interface Constraints

PHYSICAL

USB 2.0 Interface Constraints

CAESAR II (ETHERNET) CONSTRAINTS

CAESAR IV (SD) CONSTRAINTS

I243

I244

I245

I246

I249

I250

I251

I252

I253

I254

I255

I256

I257

I258

I259

I260

I261

I262

I263

I264

I265

I266

I267

I268

I269

I270

I271

I272

I273

I274

I275

I276

I277

I278

I279

I280

I281

I282

I283

I284

I285

I286

I287

I288

I289

I290

I291

USB/ENET/SD/FW/AUD CONSTRAINTS


?* =STANDARDENET_SE

ENET_100D =100_OHM_DIFF =100_OHM_DIFF* =100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

?*50MIL_SPACING 1.27 MM

* ?0.6 MMENET_DIFF

?*ENET_2OTHER =50MIL_SPACING

?*ENET_DIFF2DIFF =3:1_SPACING

*ENET_DIFF ENET_DIFF ENET_DIFF2DIFF

** ENET_2OTHERENET_DIFF_T

=50_OHM_SE =50_OHM_SE =STANDARD=50_OHM_SESD_50S * =STANDARD=50_OHM_SE

=110_OHM_DIFFFW_110D * =110_OHM_DIFF =110_OHM_DIFF=110_OHM_DIFF=110_OHM_DIFF =110_OHM_DIFF

* =3:1_SPACINGFW_TP ?

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFFUSB_90D * =90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF

=3:1_SPACINGSD ?*

* 0.3 MM ?ENET_MII

=50_OHM_SE=50_OHM_SE =50_OHM_SE =50_OHM_SE* =STANDARDENET_50S =STANDARD

=3:1_SPACING* ?USB =4x_DIELECTRIC ?TOP,BOTTOMUSB

ENET_RDACENET_SEENET_50S

CLK_PCH_55S XTAL ENET_CLK25M_XTALI

USBUSB_90DUSB_PORT1_P

ENET_100D ENETCONN_MDI_T_N<3..0>ENET_DIFF_T

SDSD_50S ENET_SD_CMD

USB_90D USBUSB_CAMERA_N

USB_IR_L_PUSB_90D USB

USB_90D USBUSB_EXTA_P

USBUSB_90DUSB_EXTA_N


USBUSB_90DUSB_EXTB_N

USBUSB_90DUSB_EXTC_N

USB_CAMERA_L_PUSB_90D USB

USB_HUB2_UP_NUSB_90D USB

USB_HUB2_UP_PUSBUSB_90D

SDSD_50S SDCONN_CLK

USB_90D USBUSB_HUB1_UP_N

USB_90D USBUSB_SDCARD_P

USB_90D USBUSB_CAMERA_L_N

USBUSB_90DUSB_BT_P

USBUSB_90DUSB_BT_L_P

USBUSB_IR_P

USB_90D

USBUSB_IR_N

USB_90D

PMSD_50S SDCONN_DETECT_BUF_L

CLK_PCH_55S XTAL ENET_CLK25M_XTALO_RCLK_PCH_55S ENET_CLK25M_XTALOXTAL

ENET_100D ENETCONN_MDI_T_P<3..0>ENET_DIFF_T

ENET_MIIPCIE_85D PCIE_ENET_R2D_P

ENET_MIIPCIE_85D PCIE_ENET_D2R_P

ENET_MII PCIE_ENET_D2R_C_NPCIE_85D

SDCONN_CMDSD_50S SD

ENET_MEDIA_SENSE_RSDSD_50S

USB_90D USBUSB_HUB1_UP_P

PM ENET_MEDIA_SENSESD_50S

SDSD_50S ENET_SD_CLK

SDSD_50S ENET_CR_DATA<7..0>

USBUSB_PORT0_N

USB_90D

USBUSB_90DUSB_EXTB_P

USBUSB_90DUSB_EXTC_P

USBUSB_90DUSB_PORT1_N


USBUSB_90DUSB_PORT2_N

USBUSB_90DUSB_EXTD_N

USBUSB_90DUSB_EXTD_P

USBUSB_90DUSB_D_MUXED_N

USBUSB_90DUSB_D_MUXED_P

USB_PORT3_PUSBUSB_90D

USBUSB_90DUSB_CAMERA_P

USB_PORT3_NUSBUSB_90D

USB_90D USBUSB_BT_L_N

ENET_SD_DETECT_LSDSD_50S

SDCONN_DATA<7..0>SDSD_50S

ENET_MII PCIE_ENET_D2R_C_PPCIE_85D

ENET_MII PCIE_ENET_R2D_C_NPCIE_85D

ENET_MII PCIE_ENET_R2D_C_PPCIE_85D

PCIE_ENET_D2R_NENET_MIIPCIE_85D

ENET_MIIPCIE_85D PCIE_ENET_R2D_N

ENET_DIFFENET_100D ENETCONN_MDI_N<3..0>ENET_100D ENET_DIFF ENETCONN_MDI_P<3..0>

CLK_PCH_55S XTAL FW_CLK24P576M_XICLK_PCH_55S XTAL FW_CLK24P576M_XO_R

XTALCLK_PCH_55S FW_CLK24P576M_XO

FW_110D FW_TP FW_PORT0_TPA_P

FW_PORT0_TPB_PFW_110D FW_TP

FW_110D FW_TP FW_PORT0_TPA_N

FW_P2_TPA_NFW_110D FW_TP

FW_110D FW_TP FW_P1_TPA_NFW_TPFW_110D FW_P1_TPA_P

FW_TPFW_110D FW_P2_TPA_P

FW_P1_TPB_NFW_TPFW_110D

FW_P1_TPB_PFW_110D FW_TP

FW_P2_TPB_PFW_110D FW_TP

FW_P2_TPB_NFW_TPFW_110D

FW_110D FW_PORT0_TPB_NFW_TP

USB_90D USBUSB_SDCARD_N

USB_IR_L_NUSBUSB_90D

USBUSB_90DUSB_BT_N

USB_90D USBUSB_SDCARD_L_P

USBUSB_90DUSB_SDCARD_L_N

USB_90D USBUSB_HUB2UNUSED_N

USBUSB_90DUSB_HUB2UNUSED_P

104 OF 110

11.1.0

051-8115

92 OF 98

37

36 37

43

38

37

20 44

44 98

34 43

34 43

43

35 43

34 43

44 98

20 35

20 35

37 45

20 34

34 44

44 98

35 44

44 98

34 44

34 44

97

36

36 37

38

37

18 37

37

37 45

20 34

15 18 37

37

37

43

35 43

34 43

43

43

43

35 43

35 43

43

43

43

20 44

43

44 98

37

37 45

37

18 37

18 37

18 37

37

37 38

37 38

39

39

39

40 41

40 41

40 41

39 40

39 40

39 40

39 40

39 40

39 40

39 40

39 40

40 41

34 44

44 98

35 44

44

44

35

35

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36

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DRAWING NUMBER SIZE

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SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PAIRS SHOULD BE WITHIN 100 MILS OF CLOCK LENGTH.

Max length of LVDS/DisplayPort/TMDS traces: 12 inches.

GRAPHICS CONSTRAINTS

USE 5X_DIELECTRIC IN K62

SPACINGPHYSICAL

NET_TYPE

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

ASSINGED IN CONT. MGR.ELECTRICAL_CONSTRAINT_SET

UNUSED VIDEO NET PHYSICAL CONSTRAINTS

I153

I154

I169

I170

I171

I172

I173

I174

I185

I186

I187

I188

I191

I192

I193

I194

I195

I196

I197

I198

I199

I200

I201

I202

I203

I204

I205

I206

I207

I208

I209

I210

I211

I212


GRAPHICS CONSTRAINTSSYNC_MASTER=K62

=85_OHM_DIFF =85_OHM_DIFFDP_85D =85_OHM_DIFF=85_OHM_DIFF 0.08MM* =85_OHM_DIFF

DISPLAYPORT * ?=3:1_SPACING

DP_85D MXM_LVDS_B_CLK_NDISPLAYPORT

DP_85D MXM_LVDS_B_CLK_PDISPLAYPORT

DP_85D MXM_LVDS_A_CLK_NDISPLAYPORT

DP_85D MXM_DP_B_ML_P<3..0>DISPLAYPORT

DP_EXTB_AUXCH_C_NDP_85D DISPLAYPORT

DISPLAYPORTDP_85D DP_EXTA_AUXCH_C_NDISPLAYPORTDP_85D DP_EXTA_AUXCH_C_P

DP_EXTA_ML_C_P<3..0>DP_85D DISPLAYPORT

DISPLAYPORTDP_85D DP_EXTA_AUXCH_N

DISPLAYPORTDP_85D DP_EXTA_ML_P<3..0>

DISPLAYPORTDP_85D DP_EXTB_ML_P<3..0>

DP_85D DISPLAYPORT MXM_DP_D_AUX_N

DP_85D DISPLAYPORT MXM_DP_C_AUX_R_NDP_85D DISPLAYPORT MXM_DP_C_AUX_R_P

MXM_DP_C_AUX_NDISPLAYPORTDP_85DMXM_DP_C_AUX_PDISPLAYPORTDP_85D

DP_85D DISPLAYPORT MXM_DP_C_ML_N<3..0>DP_85D DISPLAYPORT MXM_DP_C_ML_P<3..0>DP_85D DISPLAYPORT MXM_DP_B_AUX_N

DP_85D DISPLAYPORT MXM_DP_D_AUX_PMXM_DP_D_ML_N<3..0>DISPLAYPORTDP_85D

DP_85D DISPLAYPORT MXM_DP_D_ML_P<3..0>

DP_85D MXM_DP_B_ML_N<3..0>DISPLAYPORT

DP_85D MXM_DP_B_AUX_PDISPLAYPORT

DP_85D DISPLAYPORT DP_EXTB_AUXCH_N

DISPLAYPORTDP_85D DP_EXTA_AUXCH_PDISPLAYPORTDP_85D DP_EXTA_ML_N<3..0>

DP_85D DP_INTCONN_AUXCH_C_NDISPLAYPORT

DISPLAYPORTDP_85D DP_INTPNL_AUX_N

DP_85D DISPLAYPORT DP_EXTA_ML_C_N<3..0>

DISPLAYPORT MXM_LVDS_B_DATA_N<3..0>DP_85D

DISPLAYPORTDP_85D MXM_LVDS_B_DATA_P<3..0>

DISPLAYPORT MXM_LVDS_A_DATA_P<3..0>DP_85D

MXM_LVDS_A_DATA_N<3..0>DP_85D DISPLAYPORT

DP_85D MXM_LVDS_A_CLK_PDISPLAYPORT

DP_EXTB_ML_C_P<3..0>DISPLAYPORTDP_85D

DISPLAYPORTDP_85D DP_EXTB_ML_C_N<3..0>

DISPLAYPORT DP_INTPNL_ML_N<3..0>DP_85D

DISPLAYPORTDP_85D DP_EXTB_AUXCH_PDP_85D DISPLAYPORT DP_EXTB_ML_N<3..0>

DP_85D DISPLAYPORT DP_INTCONN_ML_C_P<3..0>DP_85D DISPLAYPORT DP_INTCONN_ML_C_N<3..0>DP_85D DISPLAYPORT DP_INTCONN_AUXCH_C_P

DISPLAYPORTDP_85D DP_INTPNL_ML_P<3..0>

DP_85D DP_INTPNL_AUX_PDISPLAYPORT

DP_85D DISPLAYPORT DP_EXTB_AUXCH_C_P

105 OF 110

11.1.0

051-8115

93 OF 98

76 78

76 78

76 78

75 78

78 84

78 84

78 84

84

84

75 78

83

83

75 83

75 83

75 83

75 83

75 78

75 78

75 78

75 78

75 78

75 78

84

84

83

81 83

78 84

76 78

76 78

76 78

76 78

76 78

81 83

83

83

83

81 83

81 83

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PAGE


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D

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8 7 5 4 2 1



NET_TYPE

PHYSICAL SPACING

PHYSICAL SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SETSPACING

NET_TYPE

SMBus Interface Constraints

PHYSICAL

SMC VOLTAGE/CURRENT NET PROPERTIES

SMC THERMAL NET PROPERTIES

SMC SMBus Net Properties

I206

I207

I208

I209

I210

I211

I212

I213

I214

I215

I216

I217

I218

I219

I220

I221

I222

I223

I224

I225

I226

I227

I228

I229

I230

I231

I232

I233

I234

I235

I236

I237

I238

I239

I240

I241

I242

I243

I244

I245

I246

I247

I248

I251

I252

I253

I254

I255

I256

I264

I265

I266

I267

I268

I269

SMC ConstraintsSYNC_MASTER=K62 SYNC_DATE=01/06/2011

POWER PWR_P2MMTHERMAL *

THERMAL *GND GND_P2MM

THERMAL * 4:1_SPACING*

THERM_DIFF * 1:1_DIFFPAIR

SNS_DIFF 1:1_DIFFPAIR*

?=2x_DIELECTRIC*SMB

=55_OHM_SE=55_OHM_SESMB_55S * =55_OHM_SE =STANDARD=55_OHM_SE =STANDARD

THERM_DIFF THERMAL SNS_T1_7_N

SMB_55S SMB I2C_VREFMRGN_DIMMA_SDA

I2C_TCON_SCLSMBSMB_55S

I2C_TCON_SDASMBSMB_55S

SMB_55S SMB SMB_BLC_TCON_SCL

SMBSMB_55S SMB_BLC_TCON_SDA

SMB_55S SMB SMB_BLC_PCH_SDA_RSMB_55S SMB SMB_BLC_PCH_SCL_R

SMBUS_SMC_BSA_SCLSMBSMB_55S

SMBUS_SMC_BSA_SDASMBSMB_55S

SMB_55S SMB SMBUS_SMC_MGMT_SCL

SMB_55S SMBUS_SMC_0_S0_SDASMB

SMBSMB_55S SMBUS_SMC_A_S3_SCL

SMB_55S SMB SML_PCH_1_DATA

SMB_55S SMB I2C_VREFMRGN_DIMMB_SCL

SMB_55S SMB SML_PCH_1_CLK

CLK_XTAL SMC_EXTALXTAL

CLK_XTAL SMC_XTALXTAL

SMB_55S SMB I2C_VREFMRGN_DIMMA_SCL

THERMALTHERM_DIFF SNS_T1_1_P

THERMAL HDD_OOB_TEMP_FB

SMC_VCORE_VSENSETHERMAL

THERMAL SMC_VCORE_ISENSE

SMC_GPU_VSENSETHERMAL

SMC_VAXG_ISENSETHERMAL

THERMAL SMC_CPU_1V5_ISENSE_R

THERMAL SMC_CPU_1V5_VSENSE

SMC_VAXG_VSENSETHERMAL

SMC_1V05_ISENSETHERMAL

GND_SMC_AVSSTHERMAL

SMC_PCH_1V05_VSENSETHERMAL

THERMAL GND_SMC_AVSS

THERMAL SMC_CPU_1V5_ISENSE

SNS_1V05_PCH_NTHERM_DIFFTHERMAL

THERMAL SNS_1V05_PCH_PTHERM_DIFF

THERMALTHERM_DIFF SNS_VCCSA_N

THERMALTHERM_DIFF SNS_CPU_1V5_NTHERM_DIFF THERMAL SNS_CPU_1V5_P

THERMALSNS_DIFF VR_ISNS_1V05_N

SNS_DIFF VR_ISNS_VAXG_NTHERMAL

SNS_DIFF VR_ISNS_VAXG_PTHERMAL

THERMAL SMC_VCCSA_VSENSETHERMAL SMC_VCCSA_ISENSE_R

SMC_VCCSA_ISENSETHERMAL


THERMAL SMC_DIMM_VSENSE

SMC_DIMM_ISENSETHERMAL

SMC_DIMM_1V5_RTHERMAL

SMC_CPU_VSENSETHERMAL

SMC_1V05_VSENSETHERMAL

THERMALTHERM_DIFF SNS_VCCSA_P

SNS_I_MXM_NTHERM_DIFF THERMAL

SNS_DIFF VR_ISNS_1V05_PTHERMAL

SNS_DIFF THERMAL VR_ISNS_VCORE_NTHERMALSNS_DIFF VR_ISNS_VCORE_P

THERM_DIFF THERMAL SNS_DIMM_1V5_N

SNS_DIMM_1V5_PTHERM_DIFF THERMAL

THERM_DIFF THERMAL SNS_I_MXM_P


SMC_PCH_1V05_ISENSETHERMAL

SMBUS_SMC_A_S3_SDASMB_55S SMB

SMBUS_SMC_B_S0_SCLSMB_55S SMB

SMBSMB_55S SMBUS_SMC_B_S0_SDA

SMBUS_SMC_0_S0_SCLSMBSMB_55S

THERM_DIFF THERMAL SNS_T2_DP2THERMAL SNS_T1_1_NTHERM_DIFF

THERMALTHERM_DIFF SNS_T2_DN2



THERMAL SNS_T1_3_PTHERM_DIFF

THERM_DIFF THERMALSNS_T1_3_N

THERM_DIFF THERMALSNS_T1_4_P

THERMALTHERM_DIFF SNS_T1_5_PTHERM_DIFF THERMAL

SNS_T1_4_N

THERMALTHERM_DIFF SNS_T1_5_N

THERM_DIFF THERMAL SNS_T1_6_P



THERM_DIFF THERMAL SNS_CPU_THERMD_P

THERM_DIFF SNS_LCD_H_PTHERMAL

THERMALTHERM_DIFF SNS_CPU_THERMD_N

THERM_DIFF THERMAL SNS_ODD_PSNS_LCD_H_NTHERM_DIFF THERMAL

THERMALTHERM_DIFF SNS_ODD_N

SNS_CPU_H_PTHERM_DIFF THERMAL

THERM_DIFF THERMAL SNS_CPU_H_N

SNS_SKIN_RIGHT_PTHERM_DIFF THERMAL

SNS_SKIN_RIGHT_NTHERM_DIFF THERMAL

SNS_SKIN_LEFT_PTHERMALTHERM_DIFF

SNS_SKIN_LEFT_NTHERMALTHERM_DIFF

THERMALTHERM_DIFF SNS_AMB_P

THERM_DIFF THERMAL SNS_AMB_N

THERM_DIFF THERMAL SNS_MXM_P

THERM_DIFF THERMAL SNS_MXM_N

THERMAL HDD_OOB_TEMP_FILT

HDD_OOB_TEMP_RTHERMAL

SMC_HDD_OOB_TEMPTHERMAL

SMC_GPU_ISENSETHERMAL


SMB I2C_VREFMRGN_DIMMB_SDASMB_55S

SMB_55S SMB SML_PCH_0_CLK

SMB_55S SMB SML_PCH_0_DATA

SMBSMB_55S SMBUS_PCH_DATASMB_55S SMB SMBUS_PCH_CLKSMB_55S SMBUS_SMC_MGMT_SDASMB

SMB_55S SMBUS_SMC_MGMT_SCLSMB

SMBUS_SMC_MGMT_SDASMB_55S SMB

106 OF 110

11.1.0

051-8115

94 OF 98

52

28

81

81

6 49 81

6 49 81

6

6

49

49

49 94

49

49

18 49

28

18 49

46 47

46 47

28

52

42

46 50

46 50

46 50

46 50

50

46 50

46 50

46 50

46 47 50 94

46 50

46 47 50 94

46 50

50

50

50

50

50

95

50 95

50 95

46 50

50

46 50

46 47 50 94

46 50

46 50

50

46 50

50

50

95

50 95

50 95

50

50

50

46 47 50 94

46 50

49

49

49

49

52

52

52

52

52

52

52

52

52

52

52

52

52

52

10 52

52

10 52

52 98

52

52 98

52

52

52 98

52 98

44 52 98

44 52 98

52 54 98

52 54 98

52

52

42 51 98

51

46 51

46 50

46 47 50 94

28

18 49

18 49

18 49

18 49

49 94

49 94

49 94

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DRAWING NUMBER SIZE

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SHEET

PAGE TITLE

C

A

D

2 1


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PAGE


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D

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VR CTRL NET PROPERTIES

VOLTAGE

NET_TYPE

PHYSICAL

NET_TYPE

SENSING NET PROPERTIES

VOLTAGE

PHYSICAL

NET_TYPE

VR VID NET PROPERTIES

SPACING VID LENGTH SKEW < 1-INCHPULL-UP STUB < 1-INCH

VID LENGTH RANGE< 1 TO 15-INCH

NET_TYPE

PHYSICAL PHYSICALSPACING SPACING

NET_TYPE

NET_TYPE

SPACINGPHYSICAL

PHYSICAL SPACING

VR CTRL NET PROPERTIES

POWER NET PROPERTIESSPACING

POWER NET PROPERTIES

I128

I129

I130

I132

I133

I134

I136

I137

I139

I140

I141

I142

I143

I144

I148

I149

I151

I152

I153

I154

I155

I156

I158

I159

I160

I162

I163

I164

I166

I171

I172

I173

I174

I175

I177

I178

I179

I182

I184

I185

I188

I193

I194

I198

I207

I209

I212

I216

I218

I221

I223

I224

I231

I234

I235

I236

I237

I238

I239

I242

I243

I244

I245

I246

I247

I248

I249

I250

I251

I252

I253

I255

I257

I258

I259

I260

I262

I263

I266

I267

I268

I270

I278

I338

I339

I341

I343

I344

I345

I347

I348

I349

I350

I351

I352

I353

I354

I357

I359

I360

I361

I363

I365

I367

I368

I370

I371

I374

I376

I377

I387

I388

I389

I390

I393

I394

I395

I396

I398

I399

I401

I402

I403

I404

I405

I406

I408

I412

I413

I419

I437

I439

I441

I442

I443

I444

I450

I451

I452

I453

I454

I455

I457

I458

I459

I461

I462

I463

I464

I466

I491

I492

I521

I536

I544

I545

I546

I557

I56

I563

I564

I57

I575

I577

I58

I587

I59

I594

I595

I596

I604

I606

I607

I608

I613

I615

I616

I619

I620

I621

I622

I623

I624

I625

I626

I627

I628

I629

I630

I631

I632

I633

I634

I635

I636

I637

I638

I639

I641

I642

I644

I645

I646

I647

I649

I650

I651

I652

I653

I654

I655

I656

I657

I658

I659

I660

I661

I662

I663

I664

I665

I666

I667

I668

I669

I670

I671

I672

I673

I674

I675

I676

I677

I678

I679

I680

I681

I682

I683

I684

I685

I686

I687

I688

I689

I690

I691

I692

I693

I694

I695

I696

I697

I698

I699

I700

I703

I704

I707

I708

I709

I710

I711

I712

I713

I714

I715

I716

I717

I718

I719

I720

I721

I723

I726

I727

I728

I729

I730

I732

I733

I734

I736

I737

I742

I743

I744

I745

I746

I747

I748

I752

I753

I754

I755

I756

I758

I759

I760

I762

I763

I764

I765

I766

I767

I768

I769

I770

I771

I772

I773

I774

I775

I776I777

I778

I779

I780

I781

I782

I783

I784

I785

I786

I787

I788

I789

I790

I791

I792

I794

I796

I797

I798

I799

I800

I801

I802

I803

I805

I808

I810

I816

I821

I824

I825

I826

I827

I828

I830

I831

I832

I833

I834

I835

I836

I837

I838

I839

*SWITCHNODE BGA_P2MMBGA_P1MM

?*VR_CTL 0.35MM

SWITCHNODESWITCHNODE BGA_P1MM BGA_P2MM

* *SWITCHNODE SWITCHNODE

=4X_DIELECTRIC* ?VR_CTL_VIDS

GND * 6:1_SPACINGSWITCHNODE

BGA_P1MMGNDSWITCHNODE BGA_P2MM

VID_PHY 50_OHM_SE*

POWER 6:1_SPACING*SWITCHNODE

BGA_P2MMSWITCHNODE POWER BGA_P1MM


POWER CONSTRAINTS

SWITCHNODE VR_CPU_PHASE3POWER 1.5V

USB_HUB1_VDD1V81.8VPOWERPOWER

PP3V3R1V8_ENET_LR_OUT_REGPOWER 1.8VPOWER

USB_HUB1_VDDPLL3V33.3VPOWER POWER

3.3V PPVBAT_G3_SYSCLK_RPOWERPOWER

USB_HUB1_VDDA3V3POWERPOWER 3.3V

PP3V3R1V5_PCH_VCCSUSHDAPOWERPOWER 3.3V

SWITCHNODE ENET_SR_LXPOWER 1.2V

3.3VPOWER PP3V3_S0_SW_SD_PWRPOWER

PP3V3_S0POWER POWER 3.3V

POWER 12V PP12V_SLG1POWER

POWER USB_HUB2_VDD1V8PLL1.8VPOWER

1.8VPOWER PP1V8_S0POWER

1.8VPOWER USB_HUB1_VDD1V8PLLPOWER

PP3V3_S0_CK505_F3.3VPOWER POWER

PP3V3_S0_HS_FPOWER POWER 3.3V

PP12V_S0_MXMPOWER 12VPOWER

PPVDDIO_25M_APOWER 1.05V

PPVDDIO_25M_CPOWER 3.3V

POWERPOWER PP5V_S5_PCH_V5REFSUS5V

5V PP5V_USB_PORT0POWERPOWER

POWER 5V PP5V_USB_PORT0_FPOWER

POWER PP5V_USB_PORT15VPOWER

PP5V_USB_PORT1_FPOWERPOWER 5V

PP5V_USB_PORT3POWER POWER 5V5VPOWER POWER PP5V_USB_PORT3_F

PP5V_USB_PORT25VPOWER POWER

3V3R2V9_DPAPWR_ADJVR_CTL_PHY PM

VR_CTL_PHY VR_CPU_DRV2_LGATEVR_CONTROL

VR_CTL_PHY VR_CONTROL VR_CPU_DRV3_BOOTVR_CTL_PHY VR_CTL VR_CPU_DRV3_GDSEL

VR_CONTROL VR_CPU_DRV3_UGATEVR_CTL_PHY

VR_CPU_DRV4_BOOTVR_CONTROLVR_CTL_PHY

VR_CPU_DRV4_GDSELVR_CTLVR_CTL_PHY

VR_CONTROL VR_CPU_DRV4_LGATEVR_CTL_PHY

VR_CONTROLVR_CTL_PHY VR_CPU_DRV4_UGATE

VR_CONTROLVR_CTL_PHY VR_AXG_DRV1_BOOTVR_CTL VR_AXG_DRV1_UGATE_RVR_CTL_PHY

VR_CTL_PHY VR_CTL CPU_VCCSA_SENSE

VR_CTL_PHY VCCSA_CRLVR_CTL

VR_CPU_FB_RCVR_CTL_PHY VR_CTL

VR_CTL_PHY VR_CTL VR_CPU_SUTH

VR_CPU_RAMP_ADJVR_CTLVR_CTL_PHY

VR_CPU_FBVR_CTLVR_CTL_PHYVR_CPU_VSNS_R_NSNS_DIFFVR_CPU_RGNDSNS_DIFF

VR_CTL_PHY VR_CONTROL VR_AXG_DRV1_LGATE

SNS_DIFF VR_AXG_RGND

1.8VPOWER PP1V8R1V5_S0_PCH_VCCVRM_FPOWER

P5VS3_REG_PHASEPOWER 5VSWITCHNODE

VR_AXG_PHASE1SWITCHNODE 1.5VPOWER

SWITCHNODE P1V05_REG_PHASE1.05VPOWER

VR_ISNS_1V05_NTHERMALSNS_DIFF

SNS_DIFF VR_AXG_ISNS_PTHERMAL

SNS_DIFF VR_AXG_ISNS_NTHERMAL

SNS_DIFF THERMAL VR_AXG_ISNS_R_N

ENET_3V3_S3_SR_INPOWER 3.3VSWITCHNODE

1.5VPOWER DDR_REG_PHASESWITCHNODE

PP0V75_S3_MEM_VREFCA_APOWER POWER 0.75V

PP0V75_S3_MEM_VREFDQ_A0.75VPOWERPOWER

3.3V PP3V3_S3POWERPOWER

3.3VPOWERPOWER PP3V3_S3_ENET_PHY_AVDDH3.3VPOWERPOWER ENET_XTALVDDH

3.3VPOWERPOWER PP3V3_S5_REG_R

PPVOUT_S0_PCH_DCPSST3.3VPOWERPOWER

POWER PPVOUT_PCH_DCPSUSBYP3.3VPOWER

POWER 3.3VPOWER PPVOUT_G3_PCH_DCPRTC

3.3VPOWERPOWER PPVBATT_G3_RTC

POWER 3.3VPOWER PP3V3_AUDIO_SPDIF_JACK

3.3VPOWERPOWER PP3V3_FW_FWPHY_VP25POWER 3.3VPOWER PP3V3_S0_T29

3.3VPOWER POWER PP3V3_SW_DPAPWR

4.5V 4V5_REG_INPOWER POWER

4.5VPOWER POWER PP4V5_AUDIO_ANALOGPOWER 4.5VPOWER PP5V_AUDIO_HPAMP

VR_CPU_VSENSNS_DIFF

VR_CPU_VSNS_R_PSNS_DIFF

VR_CPU_VSNS_XW_NSNS_DIFF

CPU_VCCIO_SENSE_PSNS_DIFF

CPU_VCCIO_SENSE_NSNS_DIFF

P1V05S0_RTNSNS_DIFF

VR_CTL_PHY P1V05S0_UGATESWITCHNODE

VR_CTL_PHY P1V05S0_LGATESWITCHNODE

P1V05S0_BOOT_RVR_CTL_PHY VR_CTL

VR_CPU_DRV1_UVCC12VPOWERPOWER

USB_HUB2_VDDPLL3V3POWER POWER 3.3V

USB_HUB2_VDDA3V3POWER 3.3VPOWER

PP3V3_S3_SDCARD_FLTPOWER POWER 3.3V

12VPOWER PP12V_S0_CPU_FLTRDPOWER

POWER 3.3VPOWER PP3V3_G3H_RTCPOWER 3.3V PP3V3_G3H_AVREF_SMCPOWER

POWERPOWER PP3V3_SW_DPBPWR3.3V

POWERPOWER 3.4V PP3V3_G3H_SMC_AVCC

CPU_VAXG_SENSE_NSNS_DIFF

SNS_DIFF VR_AXG_VSNS_R_N

POWER SWITCHNODE 1.5V VR_CPU_PHASE1POWER PP3V3R12V_SW_DPAPWR_112VPOWER

3.42VPOWER POWER PP3V42_G3H

PP5V_RAMP_VREG5VPOWER POWER

PP5V_S05VPOWER POWER

POWER 5VPOWER PP5V_S0_PCH_V5REF

1.05VPOWER POWER PPVOUT_S5_PCH_DCPSUS 5V_S0_P1V05REG_VIN5VPOWERPOWER

5VPOWERPOWER PP5V_S0_CPU_VCORE_VCCPOWER 1.05VPOWER PP1V05_S0

POWER 1.05V PP1V05_S0_PCH_VCCAPLL_EXP_FPOWER

PP1V05_S0_PCH_VCCAPLLDMI2_FPOWER POWER 1.05V

1.1VPOWER POWER PPVCORE_S0_AXG_REGOUT

PPVCORE_S0_CPU_REG3POWER POWER 1.1V

POWER 1.5VPOWER PP1V5_S0_CPU_SNS

VR_CTL_PHY VR_CTL VCCSA_CNTRL_INPUT2_R

T29BST_FBXVR_CTLVR_CTL_PHY

VR_CPU_PWM2_RVR_CTLVR_CTL_PHY

VR_CTL VR_CPU_PWM3VR_CTL_PHY

THERMALSNS_DIFF VR_AXG_ISNS_R_P

VR_CONTROLVR_CTL_PHY VR_CPU_BOOT2_RC

VR_CTL_PHY VR_CPU_BOOT4_RCVR_CTL

VR_CPU_DRV1_BOOTVR_CTL_PHY VR_CONTROL

VR_CTL_PHY VR_CTL VR_CPU_DRV1_GDSELVR_ISNS_VAXG_PSNS_DIFF THERMAL

VR_ISNS_VAXG_NSNS_DIFF THERMAL

0.75VPOWER PP0V75_S3_MEM_VREFDQ_BPOWER

VR_CTL_PHY VR_CTL VR_AXG_IMON

VR_CPU_PH1_SNUBVR_CTL_PHY SWITCHNODE

VR_CPU_PWM4VR_CTL_PHY VR_CTL

VR_RSETVR_CTL_PHY VR_CTL

SWITCHNODE VR_CPU_PH3_SNUBVR_CTL_PHY

VR_CTL_PHY VR_CTL VR_CPU_PWM1

VR_CPU_PWM1_RVR_CTL_PHY VR_CTL


VR_EN_PWR_OVPVR_CTLVR_CTL_PHY

VR_CONTROL VR_CPU_BOOT3_RCVR_CTL_PHY

VR_AXG_BOOT1_RCVR_CTL_PHY VR_CONTROL

VR_CPU_DRV1_LGATEVR_CTL_PHY VR_CONTROL

VCCSA_CNTRL_INPUT2_RVR_CTLVR_CTL_PHY

VR_CTL P5VS3_REG_FSET2VR_CTL_PHYP5VS3_REG_OCSETVR_CTLVR_CTL_PHY

P5VS3_REG_ISENVR_CTL_PHY VR_CTL

PPVCORE_S0_CPU_REG1POWER 1.1VPOWER

PP1V2_S3_ENET_PHY_PCIEPLLPOWER POWER 1.2V

VR_CPU_PWM2VR_CTLVR_CTL_PHY



VR_CPU_HFREQ_COMPVR_CTL_PHY VR_CTL

VR_CTL VR_CPU_IMON_RVR_CTL_PHY

VR_CPU_PSICOMP2VR_CTL_PHY VR_CTL

VR_CPU_FDVIDVR_CTL_PHY VR_CTL

VR_CPU_SW_FREQVR_CTL_PHY VR_CTL

VR_CTL_PHY VR_CONTROL VR_AXG_DRV1_UGATE

VR_CTL_PHY VR_CTL VR_CPU_DRV2_GDSEL

POWERPOWER 12V FW_PORT0_VP

VR_CTLVR_CTL_PHY DDR_REG_UGATE_R

VR_CTL_PHY P1V05_IMONVR_CTL

VR_CTL_PHY VR_CTL VR_AXG_FBVR_CTL_PHY VR_CTL VR_SEN_R1

P1V05S0_ICOMPVR_CTLVR_CTL_PHY

VR_CTLVR_CTL_PHY P1V05S0_VOVR_CTL_PHY VR_CTL P1V05S0_VDIF_C

P1V05S0_COMP_CVR_CTLVR_CTL_PHY

VR_CPU_ISNS2_R_NTHERMALSNS_DIFFVR_CTL DDR_REG_VDDQSNSVR_CTL_PHY

VR_CTL DDR_REG_CSVR_CTL_PHY

VR_CTL_PHY VR_CTL DDR_REG_FBVR_CTL_PHY VR_CONTROL DDR_REG_LGATE

VR_CONTROL DDR_REG_UGATEVR_CTL_PHY

VR_CONTROL DDR_REG_BOOTVR_CTL_PHY


VR_CONTROL DDR_REG_BOOT_RVR_CTL_PHY

VR_ISNS_1V05_PTHERMALSNS_DIFF

P1V05S0_VSENSNS_DIFF

SNS_DIFF CPU_VCC_SENSE_P

VR_CTL_PHY SWITCHNODE VR_AXG_PH1_SNUB

P1V05S0_FBVR_CTL_PHY VR_CTL

VR_CTLVR_CTL_PHY P1V05S0_PHASE_LP1V05S0_VWVR_CTLVR_CTL_PHY

P1V05_S0_VDIFFVR_CTLVR_CTL_PHY

P1V05S0_OCSETVR_CTLVR_CTL_PHY

P1V05S0_COMPVR_CTLVR_CTL_PHY

P1V05S0_BOOTVR_CTLVR_CTL_PHY

P1V05S0_SNUBBERVR_CTL_PHY VR_CTL

VID_PHY CPU_VIDSCLKVR_CTL_VIDS

CPU_VIDALERT_LVR_CTL_VIDSVID_PHY

VID_PHY CPU_VIDSOUTVR_CTL_VIDS

VID_PHY VR_CTL_VIDS CPU_VIDSOUT_RVID_PHY VR_CTL_VIDS CPU_VIDALERT_L_R

VR_CTL_VIDSVID_PHY CPU_VIDSCLK_R

SNS_DIFF CPU_VAXG_SENSE_P

0.75V PP0V75_S3_MEM_VREFCA_BPOWER POWER

POWERPOWER 1.05V PP1V05_S0_CK505_F

PPVCORE_S0_CPU1.1VPOWER POWER

POWER POWER 1.5V PP1V5_S31.5VPOWER POWER PP1V5_S3_MEM

12VPOWER PP12V_S5POWER

POWER PP1V0_S0_FW_VDDPOWER 1.0V

VR_CTLVR_CTL_PHY P1V8_REG_VFB

P3V3S5_REG_BOOTVR_CONTROLVR_CTL_PHY

VR_CONTROLVR_CTL_PHY P3V3S5_REG_BOOT_R

VR_CTL_PHY P1V8_REG_SYNCVR_CTL

VR_CTL_PHY P3V3S5_REG_FBVR_CTL

P3V3S5_REG_ISENVR_CTLVR_CTL_PHY

VR_CONTROLVR_CTL_PHY P3V3S5_REG_VOUT1

VR_CTL DDR_REG_PHASE_RVR_CTL_PHY

VR_CTL_PHY VR_CTL DDR_REG_VTTSNS

VR_CTL VR_CPU_COMPVR_CTL_PHY

VR_AXG_TMVR_CTL_PHY VR_CTL

VR_CTL_PHY VR_AXG_PWM_RVR_CTL

VR_AXG_PWMVR_CTLVR_CTL_PHY

1.8VSWITCHNODEPOWER P1V8_REG_PHASE

SWITCHNODE P3V3S5_REG_PHASE3.3VPOWER

12V PP12V_S0_FAN0_LPOWERPOWER

12V VR_CPU_DRV3_VCCPOWER POWER

VR_CPU_ISNS2_NSNS_DIFF THERMAL

VR_CPU_ISNS1_NSNS_DIFF THERMAL

VR_CPU_ISNS2_PTHERMALSNS_DIFFVR_CPU_ISNS1_R_NTHERMALSNS_DIFF

VR_CPU_ISNS1_PSNS_DIFF THERMAL

SNS_DIFF THERMAL P1V05S0_ISNSNS_DIFF P1V05S0_ISPTHERMAL

SNS_DIFF THERMAL VR_CPU_ISNS3_PSNS_DIFF THERMAL VR_CPU_ISNS3_N

THERMALSNS_DIFF VR_CPU_ISNS4_NVR_CPU_ISNS4_R_NSNS_DIFF THERMAL

VR_CPU_ISNS4_PTHERMALSNS_DIFF

12VPOWER PP12V_S0POWER

12V PP12V_S0_FAN1_LPOWERPOWER

POWER 12V PP12V_S0_FAN2_LPOWER

VR_CPU_DRV4_PVCCPOWER POWER 12V

POWER 12V VR_CPU_DRV4_VCCPOWER

POWERPOWER P12V_FW_D12V

POWER 12VPOWER PPVP_FW_PHY_CPSPOWER POWER 12V FW_PORT0_VP_F

VR_CPU_DRV4_UVCCPOWER 12VPOWER

VR_CPU_DRV2_UVCC12VPOWERPOWER

P1V05S0_PHASE1.05VPOWER SWITCHNODE

POWERPOWER P12V_FW_CL12V

POWER PP12V_S0_VG_OK12VPOWER

VR_CPU_DRV1_PVCC12VPOWERPOWER

VR_CPU_DRV2_PVCCPOWER 12VPOWER

VR_CPU_DRV3_PVCCPOWERPOWER 12V

VR_CPU_DRV3_UVCCPOWERPOWER 12V

POWER VR_AXG_DRV1_PVCC12VPOWER

POWERPOWER 12V PP12v_S0_P1V05_VREG_VIN

SNS_DIFF CPU_VCC_SENSE_N

VR_CTL_PHY VR_CPU_DRV2_UGATEVR_CONTROL

SNS_DIFF VR_AXG_VSNS_R_P

PP1V2_S3_ENET_PHY_GPHYPLL1.2VPOWER POWER

PPVCORE_S0_CPU_REG4POWER 1.1VPOWER

VR_CTL_PHY VR_CTL P1V05_REG_VFBVR_CTL_PHY VR_CTL ENET_SR_VFB

VR_CTLVR_CTL_PHY P1V05S0_ISP_R

5V_S0_P1V05REG_VDDPOWERPOWER 5V

POWER POWER PP5V_S35V

POWER POWER PP5V_S3_VREFMRGN_B5V

POWERPOWER 5V PP5V_S3_CAMERA_FLTPOWER 5VPOWER PP5V_S3_REG_RPOWER POWER 5V PP5V_S3_IR_FLT

PP5V_S3_DDR_REG_V5FILTPOWERPOWER 5V

POWERPOWER 0.75V PPVTT_S0_DDR

PP1V2_S3_ENET_PHY_AVDDLPOWER POWER 1.2V

1.5VPOWERPOWER PP1V5_S0

POWERPOWER PPVCORE_S0_CPU_REG21.1V

POWER POWER 1.5V PP1V5_S0_CPU_MEM

VR_CPU_BOOT1_RCVR_CTL_PHY VR_CONTROL

VR_CTL_PHY VR_EN_PWR_OVP_RVR_CTL

VR_CTLVR_CTL_PHY VR_AXG_SW_FREQ

THERMALSNS_DIFF VR_CPU_ISNS3_R_N

SWITCHNODE 1.5VPOWER VR_CPU_PHASE2

1.5V VR_CPU_PHASE4SWITCHNODEPOWER

PP1V05_S0_PCHPOWERPOWER 1.05V

POWER PPVAXG_S0POWER 1.05V

POWERPOWER 1.0V PP1V0_FW_FWPHY_AVDD

POWER 12VPOWER VCCSA_PWR_RCPOWER 12VPOWER PP12V_S0_BL_R

POWER 12VPOWER PP12V_S5_FET12VPOWERPOWER PP12V_LCD

P12V_FW_RPOWERPOWER 12V

POWER POWER 12V VR_CPU_DRV2_VCC12VPOWERPOWER VR_CPU_DRV1_VCC

POWER 12VPOWER VR_AXG_DRV1_UVCC

VR_CPU_PSICOMP1VR_CTL_PHY VR_CTL

VR_CPU_FB2VR_CTL_PHY VR_CTL

VR_CTLVR_CTL_PHY VR_AXG_IMON_RVR_CTLVR_CTL_PHY VR_AXG_HFREQ_COMP

VR_CTL_PHY VR_CTL VR_SEN_R2

VR_CTLVR_CTL_PHY VR_AXG_TCOMPVR_CTLVR_CTL_PHY VR_AXG_COMPVR_CTLVR_CTL_PHY VR_AXG_COMP_RCVR_CTLVR_CTL_PHY VR_SEN_R3

VR_CPU_PSICOMPVR_CTLVR_CTL_PHY

VR_CPU_VSNS_XW_PSNS_DIFF

SNS_DIFF VR_AXG_VSNS_XW_PVR_AXG_VSNS_XW_NSNS_DIFF

SNS_DIFF VR_AXG_VSEN

SNS_DIFF VR_ISNS_VCORE_NTHERMAL

POWERPOWER 0.925V PPVCCSA_S0_CPU

POWER 0.75V PP0V75_S0POWER

12VPOWER POWER PP12V_S5_RSN

POWER 12VPOWER PP12V_G3H

1.05V PP1V05_S0_PCH_VCCAPLL_SATA_FPOWERPOWER

1.05VPOWER PP1V05_S0_PCH_VCCCLKDMI_FPOWER

POWERPOWER 1.8V USB_HUB2_VDD1V8

PP1V05_S0_PCH_VCCADPLLB_FPOWER 1.05VPOWERPP1V05_S0_PCH_VCCADPLLA_F1.05VPOWERPOWER

PPVCORE_S0_AXG_REG11.1VPOWER POWER

PP1V05_S0_INPUT_VCCSA1.05VPOWER POWERPOWERPOWER 1.05V PP1V05_S0_T29

VR_CTL_PHY P3V42G3H_FBVR_CTL

VR_CTL P3V42G3H_BOOSTVR_CTL_PHY

3.3VPOWERPOWER PP3V3_S3_ENET_PHY_BIASVDDHPP3V3_S3_ENET_PHY_XTALVDDH3.3VPOWERPOWER

PP3V3_S3_MINI_CONN3.3VPOWER POWER

3.3VPOWER POWER PP3V3_SMCUSBMUXVR_ISNS_VCORE_PSNS_DIFF THERMAL

VR_CTL_PHY VR_CPU_DRV1_UGATEVR_CONTROL

VR_CTL_PHY VR_CONTROL VR_CPU_DRV2_BOOT

VR_CTL VR_CPU_FB_RVR_CTL_PHY

VR_CPU_IMONVR_CTL_PHY VR_CTL

VCCSA_OUTVR_CTL_PHY VR_CTL

VCCSA_CNTRL_INPUT2VR_CTLVR_CTL_PHY

VCCSA_CNTRL_INPUT1VR_CTLVR_CTL_PHY

VR_CONTROL P5VS3_REG_VOUT2VR_CTL_PHYP5VS3_REG_UGATEVR_CONTROLVR_CTL_PHY

VR_CTL_PHY P3V3S5_REG_SNUBVR_CTL

VR_CONTROL P3V3S5_REG_UGATEVR_CTL_PHY

VR_CONTROLVR_CTL_PHY P3V3S5_REG_FSET1

VR_CTL P3V3S5_REG_OCSETVR_CTL_PHY

VR_CTL_PHY P3V3S5_REG_LGATEVR_CONTROL

P5VS3_REG_LGATEVR_CONTROLVR_CTL_PHY

VR_CTL_PHY VR_CTL P5VS3_REG_FBP5VS3_REG_BOOTVR_CTL_PHY VR_CONTROL

VR_CTL_PHY VR_CTL VCCSA_GATEVR_CPU_DRV3_LGATEVR_CONTROLVR_CTL_PHY

VR_CTL_PHY VR_CPU_TMVR_CTL

VCCSA_REFVR_CTLVR_CTL_PHY

POWER 3.3VPOWER PP3V3_S5

1V5_SNUBBERVR_CTL_PHY SWITCHNODE

PP5V_USB_PORT2_FPOWER 5VPOWER

3.3V PPVDDIO_25M_BPOWER

VR_CPU_N_PSIVR_CTLVR_CTL_PHY

VR_CPU_IAUTOVR_CTL_PHY VR_CTL

POWER PP3V3R12V_SW_DPBPWR_112VPOWER

POWER PP3V3_S0_PCH_VCCA_DAC_F3.3VPOWER

3.3VPOWER POWER PP3V3_S3_BT_FLT

PP3V3_S3_ENET_PHY_FET3.3VPOWER SWITCHNODE

3.3VPOWER POWER PPVBATT_G3_RTC_R

3.3VPOWERPOWER PP3V3_FW_FWPHY_VDDA

5VPOWERPOWER PP5V_LAMP_VREG

POWER 5V PP5V_S0_SATA_FETPOWER

POWER 5VPOWER PP5V_S3_VREFMRGN_A

PP5V_S5POWER POWER 5V

1.2VVR_CTL PP1V2_S3_ENET_INTREGVR_CTL_PHY

PP1V5_S0_CK505_FPOWER POWER 1.5V

PP1V5_S0_CK505_R1.5VPOWERPOWER

DDR_REG_CSGNDPOWERPOWER

DDR_REG_PGNDPOWERPOWER

3.4VPOWER P3V42G3H_SWSWITCHNODE

1.5V PP1V5_S0_DP_RPOWER

POWER 12V PP3V3R12V_SW_DPAPWR_D12VPOWER PP3V3R12V_SW_DPAPWR_R

107 OF 110

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051-8115

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36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

T29 BIAS CONSTRAINTS

T29 ELECTRICAL ROUTES

T29 PCI-EXPRESS (SAME RULE AS PCIE)

PHYSICAL SPACING

NET_TYPE


NET_TYPE

SPACINGPHYSICAL

T29 NET PROPERTIES

T29 XTAL CONSTRAINTS

T29 SPI INTERFACE CONSTRAINTS

T29 SMBUS INTERFACE CONSTRAINTS


T29 NET PROPERTIES

GREEN CLOCK CONSTRAINTS

I421

I422

I423

I424

I425

I426

I427

I428

I431

I432

I433

I434

I435

I436

I437

I438

I439

I440

T29 CONSTRAINTSSYNC_DATE=01/06/2011SYNC_MASTER=K62

=STANDARD=STANDARD=55_OHM_SE=55_OHM_SE =55_OHM_SE=55_OHM_SE*CLK_25M_55S

* =55_OHM_SE =55_OHM_SE=55_OHM_SE =STANDARD =STANDARD=55_OHM_SET29_55S

?*T29_COMP 0.2 MM

=2x_DIELECTRIC* ?T29_SMB

T29_SMB_55S =STANDARD=STANDARD=55_OHM_SE=55_OHM_SE =55_OHM_SE=55_OHM_SE*

T29_XTAL_100D =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF* =100_OHM_DIFF=100_OHM_DIFF

T29_XTAL ?* =4X_DIELECTRIC

T29_SPI 0.2 MM ?*

T29 =7X_DIELECTRIC ?TOP,BOTTOM

T29_SPI_55S =STANDARD=55_OHM_SE=55_OHM_SE* =STANDARD=55_OHM_SE=55_OHM_SE

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFFT29_90D *

T29 * ?=5X_DIELECTRIC

* ?CLK_25M =5X_DIELECTRIC

T29_COMP T29_B_BIASDP_A_BIAST29_COMP

T29_SMB_55S I2C_T29_SCLT29_SMB

CLK_25MCLK_25M_55S SYSCLK_CLK25M_SB

CLK_25M_55S SYSCLK_CLK25M_ENETCLK_25M

ENET_CLK25M_XTALI_OSCCLK_25MCLK_25M_55S

T29_XTAL_100D SYSCLK_CLK25M_X2T29_XTAL

T29_XTAL_100D SYSCLK_CLK25M_X2_RT29_XTAL

T29_XTAL_100D SYSCLK_CLK25M_X1T29_XTAL

T29_RSENSET29_COMPT29_55S

T29_RBIAST29_COMPT29_55S

T29_COMP T29_A_BIAS

T29_SMB_55S I2C_T29_SDAT29_SMB

SYSCLK_CLK25M_T29_RCLK_25M_55S CLK_25M

PCIE_T29_R2D_P<3..0>PCIENO_TEST=TRUE PCIE_85D

PCIE_T29_R2D_C_P<3..0>PCIE_85DNO_TEST=TRUE PCIE

DP_T29SRC_ML_C_N<3..0>DP_85DNO_TEST=TRUE DISPLAYPORT

DISPLAYPORTNO_TEST=TRUE DP_85D DP_T29SNK0_AUXCH_C_N

T29_90D T29_B_RSVD_PDISPLAYPORTNO_TEST=TRUE

T29_SPI_55S JTAG_T29_TDOT29_SPI

T29_90D T29NO_TEST=TRUE T29_R2D_C_P<3..0>

T29NO_TEST=TRUE T29_90D T29_R2D_C_N<3..0>

T29NO_TEST=TRUE T29_90D T29_D2R_C_P<3..0>

T29_SPIT29_SPI_55S T29_SPI_CLKT29_SPIT29_SPI_55S T29_SPI_CS_LT29_SPIT29_SPI_55S T29_SPI_MISOT29_SPIT29_SPI_55S T29_SPI_MOSI

JTAG_T29_TDIT29_SPI_55S T29_SPI

T29_SPI_55S JTAG_T29_TMST29_SPI

T29_SPI_55S JTAG_T29_TCKT29_SPI

CLK_25M_55S CLK_25M SYSCLK_CLK25M_T29_R

SYSCLK_CLK25M_T29CLK_25M_55S CLK_25M

CLK_25M_55S SYSCLK_CLK25M_T29_CLKCLK_25M

SYSCLK_CLK25M_T29CLK_25M_55S CLK_25M

NO_TEST=TRUE T29 T29_D2R_P<3..0>T29_90D

T29_90DNO_TEST=TRUE T29_D2R_N<3..0>T29

NO_TEST=TRUE T29_90D T29_R2D_C_F_P<3..0>T29

NO_TEST=TRUE T29_90D T29 T29_D2R_C_N<3..0>

NO_TEST=TRUE T29 DP_SDRVA_AUXCH_C_PT29_90D

DP_T29SRC_ML_N<3..0>DISPLAYPORTNO_TEST=TRUE DP_85D

DP_T29SRC_AUXCH_R_C_NDISPLAYPORTDP_85DNO_TEST=TRUE

NO_TEST=TRUE DP_SDRVA_AUXCH_PDISPLAYPORTT29_90D

T29_90DNO_TEST=TRUE DP_SDRVA_AUXCH_NDISPLAYPORT

T29_90D DISPLAYPORT DP_SDRVB_AUXCH_PNO_TEST=TRUET29_90D DISPLAYPORT DP_SDRVB_AUXCH_NNO_TEST=TRUE

DISPLAYPORT DP_SDRVA_ML_C_N<3..0>NO_TEST=TRUE T29_90D

DP_SDRVA_ML_P<3..0>DISPLAYPORTT29_90DNO_TEST=TRUE

NO_TEST=TRUE DISPLAYPORT DP_SDRVA_ML_R_P<3..0>T29_90D

DP_SDRVA_ML_N<3..0>NO_TEST=TRUE DISPLAYPORTT29_90D

DP_SDRVA_ML_R_N<3..0>DISPLAYPORTT29_90DNO_TEST=TRUE

DISPLAYPORT DP_SDRVB_ML_C_N<3..0>T29_90DNO_TEST=TRUENO_TEST=TRUE DP_SDRVB_ML_C_P<3..0>DISPLAYPORTT29_90D

DISPLAYPORTT29_90D DP_SDRVB_ML_P<3..0>NO_TEST=TRUE

NO_TEST=TRUE DISPLAYPORTT29_90D DP_SDRVB_ML_R_P<3..0>T29_90D DISPLAYPORT DP_SDRVB_ML_R_N<3..0>NO_TEST=TRUE

NO_TEST=TRUE DP_SDRVB_ML_N<3..0>DISPLAYPORTT29_90D

T29_90DNO_TEST=TRUE T29_A_RSVD_NDISPLAYPORT

T29_90D DISPLAYPORT T29_B_RSVD_NNO_TEST=TRUET29_90D DISPLAYPORT T29_A_RSVD_PNO_TEST=TRUE

DP_T29SNK1_ML_C_P<3..0>DP_85DNO_TEST=TRUE DISPLAYPORT

DP_T29SNK1_ML_C_N<3..0>DP_85DNO_TEST=TRUE DISPLAYPORT

DP_T29SNK1_ML_N<3..0>NO_TEST=TRUE DP_85D DISPLAYPORT

DP_SDRVB_AUXCH_C_PT29NO_TEST=TRUE T29_90D

NO_TEST=TRUE T29 DP_A_EXT_AUXCH_NT29_90D

T29NO_TEST=TRUE T29_90D DP_A_EXT_AUXCH_P

NO_TEST=TRUE T29T29_90D T29DPA_ML_N<3..0>

DP_SDRVA_AUXCH_C_NNO_TEST=TRUE T29T29_90D

T29DPA_D2R1_AUXCH_PT29NO_TEST=TRUE T29_90D

DP_T29SRC_AUXCH_C_NDP_85D DISPLAYPORTNO_TEST=TRUE

NO_TEST=TRUE T29_R2D_P<3..0>T29_90D T29

T29DPB_ML_C_P<0>NO_TEST=TRUE T29T29_90D

DP_SDRVB_AUXCH_C_NNO_TEST=TRUE T29T29_90D

DP_B_EXT_AUXCH_PNO_TEST=TRUE T29T29_90D

NO_TEST=TRUE T29T29_90D T29DPA_ML_P<3..0>

DP_85D DISPLAYPORTNO_TEST=TRUE DP_T29SRC_AUXCH_R_C_P

DP_T29SNK1_AUXCH_PNO_TEST=TRUE DISPLAYPORTDP_85D

PCIE_T29_R2D_N<3..0>PCIENO_TEST=TRUE PCIE_85D

NO_TEST=TRUE DISPLAYPORT DP_SDRVA_ML_C_P<3..0>T29_90D

DISPLAYPORTDP_85D DP_T29SRC_AUXCH_C_PNO_TEST=TRUE

DP_85D DP_T29SNK1_AUXCH_C_NNO_TEST=TRUE DISPLAYPORT

NO_TEST=TRUE T29T29_90D T29DPB_ML_N<3..0>

DP_T29SNK0_ML_P<3..0>NO_TEST=TRUE DP_85D DISPLAYPORT

DISPLAYPORTDP_85D DP_T29SNK0_ML_N<3..0>NO_TEST=TRUEDP_85D DISPLAYPORT DP_T29SNK0_AUXCH_PNO_TEST=TRUE

NO_TEST=TRUE PCIE PCIE_T29_D2R_P<3..0>PCIE_85D

T29DPA_ML_C_P<2>T29NO_TEST=TRUE T29_90D

T29DPA_ML_C_N<2>T29NO_TEST=TRUE T29_90DT29NO_TEST=TRUE T29DPA_ML_C_P<0>T29_90D

T29T29_90DNO_TEST=TRUE T29DPB_D2R3_AUXCH_N

PCIEPCIE_85D PCIE_T29_R2D_C_N<3..0>NO_TEST=TRUE

PCIE_T29_D2R_C_P<3..0>NO_TEST=TRUE PCIE_85D PCIE

PCIE_85D PCIENO_TEST=TRUE PCIE_T29_D2R_C_N<3..0>

DP_T29SRC_ML_C_P<3..0>DP_85DNO_TEST=TRUE DISPLAYPORT

DP_T29SRC_ML_P<3..0>DISPLAYPORTNO_TEST=TRUE DP_85D

DISPLAYPORTNO_TEST=TRUE DP_85D DP_T29SNK0_ML_C_P<3..0>DP_85DNO_TEST=TRUE DISPLAYPORT DP_T29SNK0_AUXCH_N

NO_TEST=TRUE T29 T29DPB_ML_C_P<2>T29_90D

T29DPB_ML_C_N<0>T29NO_TEST=TRUE T29_90D

T29DPB_D2R3_AUXCH_PT29T29_90DNO_TEST=TRUE

DP_B_EXT_AUXCH_NNO_TEST=TRUE T29T29_90D

T29NO_TEST=TRUE T29_90D T29_R2D_N<3..0>

T29NO_TEST=TRUE T29_90D T29_R2D_C_F_N<3..0>

NO_TEST=TRUE T29T29_90D T29DPB_ML_P<3..0>

T29DPA_D2R1_AUXCH_NT29T29_90DNO_TEST=TRUE

T29DPA_ML_C_N<0>T29NO_TEST=TRUE T29_90D

T29DPB_ML_C_N<2>NO_TEST=TRUE T29T29_90D

DP_T29SNK0_AUXCH_C_PNO_TEST=TRUE DISPLAYPORTDP_85D

DP_T29SNK1_AUXCH_C_PDP_85DNO_TEST=TRUE DISPLAYPORT

DP_T29SNK1_AUXCH_NNO_TEST=TRUE DP_85D DISPLAYPORT

DP_T29SNK1_ML_P<3..0>NO_TEST=TRUE DP_85D DISPLAYPORT

DP_T29SNK0_ML_C_N<3..0>DP_85D DISPLAYPORTNO_TEST=TRUE

NO_TEST=TRUE PCIE_CLK100M_T29_PCLK_PCIECLK_PCIE_90D

PCIE_T29_D2R_N<3..0>NO_TEST=TRUE PCIE_85D PCIE

CLK_PCIE_90D CLK_PCIENO_TEST=TRUE PCIE_CLK100M_T29_N

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36

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SHEET

PAGE TITLE

C

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2 1


Apple Inc.

PAGE


A

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C

345678

D

B

8 7 5 4 2 1

NET_TYPE

SPACINGPHYSICAL

PHYSICAL SPACING

NET_TYPE

SPACINGPHYSICAL

PM NET PROPERTIES

NET_TYPE

(PM, RESET, EN, PGOOD)

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SYNC_MASTER=K62

PM RESETS ENABLES PGOOD CONSTSYNC_DATE=01/06/2011

DEFAULTGNDPM_VTT *

* DEFAULTGNDPM

PM_VTT * * 3:1_SPACING

PM_VTT PM_VTT * 2:1_SPACING

2:1_SPACING*PM *

PM SPI_DESCRIPTOR_OVERRIDE_L

PGOOD_P1V5_S0_DLYPM

SMC_PROCHOT_3_3_LPM

PM PM_SYSRST_L

PM PM_SLP_S3_5V_LPM PM_SLP_S3_5V_R2

PM PM_SLP_S4_1_L_RPM_SLP_S4_D_LPM

PM PM_SLP_S4_L

PM_VTT PM_THRMTRIP_L

PM_SLP_S3_BUF_LPM

PM PM_SYS_PWRGD

PM_VTT PM_SYNCPM PM_SLP_S5_LPM PM_SLP_S4_LPM PM_SLP_S3_L

PM_PCH_PWRGDPM

PM PM_SLP_S3_5V

PM_MXM_PGOODPM

PM PM_MEM_PWRGD_LPM_MEM_PWRGDPM_VTT

PM HDD_OOB_1V00_REFPM USE_HDD_OOB_L

MINI_RESET_LPM

MXM_CLKREQ_LPM

PM MXM_GOOD

PM ODD_PWR_EN_L

PM RSMRST_PWRGD

SMC_PM_G2_ENPM

PM S5_DG_1

SMC_WAKE_SCI_LPM

PM SMC_ONOFF_L

PM T29_PWR_ENPM T29_RESET_L

PM LPC_PWRDWN_L

PM ISOLATE_CPU_MEM_L

PM_EN_P1V05_S3_REGPM

PM_EN_P1V5_S0_FETPM

PM PM_EN_P1V8_S0_REGPM PM_EN_P3V3_S0_FET

PM PM_EN_P5V_S3_REG

PM PM_EN_VCCSA_S0_CPU

PM PM_PCH_PWRGD_R

PM PM_PECI_PWRGD_R

PM_PGOOD_DDR1V5_S3_REGPM

PM_PGOOD_P1V05_S0_REGPM

PM_PGOOD_P1V5_S0_FETPM



PM PM_PGOOD_PVCCSA_S0_REGPM PM_PGOOD_P5V_S3_REG

PM PM_PGOOD_PVAXG

PM PM_PGOOD_PVCORE_CPU

PM SMC_PM_G2_EN_R

PM S4_ENABLES

PM 3V42G3H_SHDN_L

ALL_SYS_PWRGD_RPM

ALL_SYS_PWRGD_SMCPM

PM AUD_IPHS_SWITCH_EN

PM SDCARD_PLT_RST_L_R

PM PLT_RESET_L

PM_CLK32K_SUSCLK_RPMPM_CLK32K_SUSCLKPM

PM PM_BATLOW_L

PLT_RESET_LS1V05_LPM_VTT

ENET_PWR_ENPM

ENET_LOW_PWRPM

PM FW_RESET_LPM ENET_RESET_L

PM PM_RSMRST_LPM PM_RSMRST_PCH_L

PM PM_PWRBTN_LPM_CLKRUN_LPM

SMC_ADAPTER_ENPM

PM S5_MSFT_G1

PM SDCARD_PLT_RST_L

PM RTC_RESET_L

PM 3V3R2V9_DPAPWR_ADJ

PM AUD_SPDIF_IN

PM BDV_BKL_PWM

PM SDCARD_RESET_L

PM SDCONN_STATE_RST_LSDCONN_DETECT_BUF_LPM

PM FW_PWR_EN

FW_CLKREQ_LPM

PM MEM_RESET_L

PM_VTT PM_MEM_PWRGD

PM PM_EN_P5V_S0_FET

MINI_CLKREQ_LPM

PM VTT_REG_PGOOD_L

VIDEO_ONPM

VSYNC_DPPM

VSYNC_DP_CONNPM

PM XDPPCH_PLTRST_LUSB_HUB_SOFT_RESET_LPM

XDP_PWRGDPM_VTT

PM_VTT XDP_DBRESET_L

PM SDCONN_STATE_CHANGE

PM SMC_PM_G2_EN_L

PM AUD_IP_PERIPHERAL_DET

PM SDCARD_RESET

PM RTC_RESET_L

PM FW_PME_L

PM PM_PGOOD_MINIPM_PGOOD_P5V_S0_FETPM



PM PM_PECI_PWRGD

PM PM_MXM_EN

PM_EN_PVCORE_CPUPM

PM PM_EN_PVCCSA_S0_REG_L

PM PM_EN_P3V3_S5_REG

PM_EN_P3V3_S3_FETPM

PM PM_EN_P12V_S0_FET

PM_EN_P1V05_S0_REGPM

PM PM_EN_DDR1V5_S3_REGPM PM_EN_DDRVTT_S0_REG

PM PM_MEM_PWRGD_R

PM PM_ASW_PWRGD

PM PM_DSW_PWRGD

PCIE_WAKE_LPM

PCH_DF_TVSPM

PCH_PROCPWRGDPM

PCH_DSWVRMENPM

PM PCH_INTVRMEN_L

PM PCH_SRTCRST_L

AUD_I2C_INT_LPM

BL_PWMPM

PM AUD_SPDIF_IN_CODEC

PM AP_MINI_RESET_L

BL_ENPM

BDV_BKL_PWMPM

PM AP_PWR_EN

4V5_REG_ENPM

PM MXM_PNL_BL_PWM

PM CK505_27MHZ_ENPM CPUVTT_REG_EN

CPUVTT_REG_PGOOD_RPM_VTT

PM CPU_MEM_RESET_LPM CPU_PECI_RPM_VTT CPU_PWRGD

CPU_RESET_LPM

CPU_PECIPM

CPU_PROC_SELPM

PM DEBUG_RESET_L

DP_INT_SPDIF_AUDIOPMDDRVTT_ENPM

DPAPWRSW_CTPM

T29_A_HV_ENPM

3V3R2V9_DPBPWR_ADJPM

DP_B_PWRDWN_INVPM

DPBPWRSW_CTPM

PM DP_INTPNL_HPD

DPBPWRSW_IFLTPM

PM LCD_BL_PWMLCD_BLK_ON_DLYPMLCD_BL_FILTPM

SMC_DELAYED_PWRGDPM

PM SMC_RUNTIME_SCI_L

PM T29_DP_PORTA_PWR_EN

PM SMC_LRESET_LPM DP_A_PWRDWN_INV

SMC_RESET_LPM

PM SMC_PROCHOT

PM SMC_MANUAL_RST_L

XDP_CPUPWRGDPM_VTT

PM T29_DP_PORTA_PWR_EN_REG

DP_B_PWRDWN_FET_RPM

CPU_PROCHOT_LPM

CPU_SKTOCC_LPM

PM T29_B_HV_EN

DPBPWRSW_ILIMPM

DPBPWRSW_HVEN_L_RPM

DP_B_PWRDWNPM

DP_A_PWRDWN_FET_RPM

CPU_THRMTRIP_LPM

CPU_CATERR_LPM

T29_PWR_ENPM

T29_RESET_RTR_LPM

PM DP_A_PWRDWN

DPAPWRSW_HVEN_L_RPM

DPAPWRSW_ILIMPM

PM DPAPWRSW_IFLT

PM PGOOD_1V8_S0_G2

PM PGOOD_1V8_S0_G1

PGOOD_P12V_S0PM

PGOOD_PCH_S0PM

PGOOD_P1V8_S0PM

PM PGOOD_PCH_S0_R

PGOOD_CPU_UNCOREPM

PM POWER_BUTTON_LPGOOD_SYSPWROK_RPM

PGOOD_SYSPWROKPM

12V_COMP_REFPM

PM ALL_SYS_PWRGD

PM 9V_COMP_REF

PM PGOOD_12V_S0_G2PGOOD_12V_S0_G1PM

PM PGOOD_3V3_1V05

PM PGOOD_5V_1V05_3V3

PM PGOOD_CPU_S0

PM PEG_RESET_L

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PAGE


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8 7 5 4 2 1

FUNCTIONAL TESTPOINTS FOR MAC-1 & ICT

J5551 ODD TEMP SENSOR

17 TP’S

J4780 IR BOARD

1 PP5V_S3_REG Testpoint near J4700

1 PP3V3_S3 TESTPOINT NEAR J4700

J5600 ODD FAN

J4700 USB CAMERA

2 TP’S

2 Ground Testpoints near J4750

J5400 HDD TEMP SENSOR

1 GROUND TESTPOINTS NEAR J5400

J5560 SKIN TEMP SENSOR

1 GROUND TESTPOINT NEAR J57001 PP3V3_S3 Testpoint near J4750


1 GROUND TESTPOINT NEAR J4780

J5601 HD FAN

J4750 USB CARD READER

J6603 AUDIO LEFT SPEAKER

J6602 AUDIO RIGHT SPEAKER

2 TP’S


1 PP5V_S0 Testpoint near J4520

J4520 SATA ODD (HIGH SPEED)


J6600 AUDIO AUXILIARY CONNECTOR

J5700 CPU FAN

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K60/K62 ICT/FCTSYNC_MASTER=K62

FUNC_TEST=TRUEFAN_2_PWR_L

FUNC_TEST=TRUEAUD_HP_L_JACK

FUNC_TEST=TRUEHS_MIC_HI_JACK

FUNC_TEST=TRUEAUD_HP_TIPDET_JACK

FUNC_TEST=TRUEMIN_ALLOWED_TPS=2

PP3V3_S3

FUNC_TEST=TRUEAUD_LI_R_JACK

AUD_HP_GND_JACK FUNC_TEST=TRUE

FUNC_TEST=TRUESMC_ODD_DETECT

AUD_SPDIFIN_JACK FUNC_TEST=TRUE

FUNC_TEST=TRUEAUD_IP_PERPH_JACK

AUD_HP_TYPEDET_JACK FUNC_TEST=TRUE

AUD_HP_R_JACK FUNC_TEST=TRUE

FUNC_TEST=TRUEAUD_LI_L_JACKFUNC_TEST=TRUEAUD_LI_GND_JACK

FUNC_TEST=TRUEAUD_LI_DET_JACK

PP3V3_AUDIO_SPDIF_JACKMIN_ALLOWED_TPS=2

FUNC_TEST=TRUE

FUNC_TEST=TRUEAUD_SPKR_OUTLO1L_NOUTFUNC_TEST=TRUEAUD_SPKR_OUTLO1L_POUT

FUNC_TEST=TRUEAUD_SPKR_OUTLO2L_POUT

AUD_SPKR_OUTLO2L_NOUTFUNC_TEST=TRUE

FUNC_TEST=TRUEAUD_SPKR_OUTLO1R_POUT

AUD_SPKR_OUTLO1R_NOUTFUNC_TEST=TRUE

FUNC_TEST=TRUEAUD_SPKR_OUTLO2R_POUT

AUD_SPKR_OUTLO2R_NOUTFUNC_TEST=TRUE

FUNC_TEST=TRUESNS_SKIN_RIGHT_P

FUNC_TEST=TRUESNS_SKIN_RIGHT_N

FUNC_TEST=TRUESNS_SKIN_LEFT_NFUNC_TEST=TRUESNS_SKIN_LEFT_P

USB_CAMERA_L_N FUNC_TEST=TRUE

USB_BT_L_P FUNC_TEST=TRUE

USB_BT_L_N FUNC_TEST=TRUEFUNC_TEST=TRUEFAN_0_PWR_L

FUNC_TEST=TRUEFAN_TACH2_L

PP12V_S0_FAN2_L FUNC_TEST=TRUE

SNS_AMB_N FUNC_TEST=TRUE

PP12V_S0_FAN1_L FUNC_TEST=TRUE

FUNC_TEST=TRUEFAN_1_PWR_L

FAN_TACH1_L FUNC_TEST=TRUE

FAN_1_GND FUNC_TEST=TRUEFUNC_TEST=TRUEPP5V_S3_IR_FLT

USB_IR_L_N FUNC_TEST=TRUE

FUNC_TEST=TRUEUSB_IR_L_P

FUNC_TEST=TRUEMIN_ALLOWED_TPS=1

PP5V_S3

USB_CAMERA_L_P FUNC_TEST=TRUE

FUNC_TEST=TRUEPP12V_S0_FAN0_L

FUNC_TEST=TRUEFAN_0_GND

FAN_TACH0_L FUNC_TEST=TRUE

FUNC_TEST=TRUESDCARD_RESET

SNS_AMB_P FUNC_TEST=TRUE

HDD_OOB_TEMP_FILT FUNC_TEST=TRUE

SNS_ODD_N FUNC_TEST=TRUE

MIN_ALLOWED_TPS=1PP5V_S0 FUNC_TEST=TRUE

FUNC_TEST=TRUEFAN_2_GND

SNS_ODD_P FUNC_TEST=TRUE

GNDMIN_ALLOWED_TPS=17

FUNC_TEST=TRUE

110 OF 110

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Documents

APPLE A1311 K60 820-3126-A