97
 DRAWING DESCRIPTION REFERENCE DES BOM OPTION QTY PART NUMBER CRITICAL 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. PROPRIETARY PROPERTY OF APPLE INC. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. DESCRIPTION OF REVISION CK APPD 2 1 1 2 4 5 6 7 8 B D 6 5 4 3 C A NOTICE OF PROPRIETARY PROPERTY: PAGE THE INFORMATION CONTAINED HEREIN IS THE C A D DATE R SHEET Apple Inc. THE POSESSOR AGREES TO THE FOLLOWING: DRAWING TITLE D SIZE REVISION DRAWING NUMBER BRANCH REV ECN 7 B 3  II NOT TO REPRODUCE OR COPY IT  I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE  IV ALL RIGHTS RESERVED III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 8 SCHEM,MLB,KEPLER,2PHASE,D2 Schematic / PCB #’s FSB, 5/9/2012 1 OF 99 2012-05-09 1 OF 132 4.18.0 051-9589 53 03/05/2012 D2_SEAN Voltage & Load Side Current Sensing 45 52 01/13/2012 D2_KEPLER SMBus Connections 44 51 01/13/2012 D2_KEPLER LPC+SPI Debug Connector 43 50 01/13/2012 D2_KEPLER SMC Support 42 49 01/13/2012 D2_KEPLER SMC 41 46 01/13/2012 D2_KEPLER USB 3.0 CONNECTORS 40 45 01/13/2012 D2_KEPLER SSD CONNECTOR 39 44 01/13/2012 D2_KEPLER RIO CONNECTOR 38 38 01/13/2012 D2_KEPLER Thunderbolt Power Support 37 37 01/13/2012 D2_KEPLER Thunderbolt Host (2 of 2) 36 36 01/13/2012 D2_KEPLER Thunderbolt Host (1 of 2) 35 35 01/13/2012 D2_KEPLER X29/ALS/CAMERA CONNECTOR 34 34 01/13/2012 D2_KEPLER DDR3/FRAMEBUF VREF MARGINING 33 33 01/13/2012 D2_KEPLER DDR3 Termination 32 32 01/13/2012 D2_KEPLER DDR3 SDRAM Bank B (2 OF 2) 31 31 01/13/2012 D2_KEPLER DDR3 SDRAM Bank B (1 OF 2) 30 30 01/13/2012 D2_KEPLER DDR3 SDRAM Bank A (2 OF 2) 29 29 01/13/2012 D2_KEPLER DDR3 SDRAM Bank A (1 OF 2) 28 28 01/13/2012 D2_KEPLER CPU Memory S3 Support 27 27 01/13/2012 D2_KEPLER USB HUB & MUX 26 26 01/13/2012 D2_KEPLER Chipset Support 25 25 01/13/2012 D2_KEPLER CPU & PCH XDP 24 24 03/19/2012 D2_CLEAN PCH DECOUPLING 23 23 01/13/2012 D2_KEPLER PCH GROUNDS 22 22 03/19/2012 D2_CLEAN PCH POWER 21 21 01/13/2012 D2_KEPLER PCH GPIO/MISC/NCTF 20 20 01/13/2012 D2_KEPLER PCH PCI/USB/TP/RSVD 19 19 01/13/2012 D2_KEPLER PCH DMI/FDI/PM/Graphics 18 18 01/13/2012 D2_KEPLER PCH SATA/PCIe/CLK/LPC/SPI 17 17 03/05/2012 D2_SEAN CPU DECOUPLING-II 16 16 03/05/2012 D2_SEAN CPU DECOUPLING-I 15 14 01/13/2012 D2_KEPLER CPU POWER AND GND 14 13 01/13/2012 D2_KEPLER CPU POWER 13 12 01/13/2012 D2_KEPLER CPU DDR3 INTERFACES 12 11 01/13/2012 D2_KEPLER CPU CLOCK/MISC/JTAG 11 10 01/13/2012 D2_KEPLER CPU DMI/PEG/FDI/RSVD 10 9 01/13/2012 D2_KEPLER Signal Aliases 9 8 01/13/2012 D2_KEPLER Power Aliases 8 7 01/13/2012 D2_KEPLER Functional / ICT Test 7 6 01/13/2012 D2_KEPLER BOM Variants 6 5 01/13/2012 D2_KEPLER BOM Configuration 5 4 01/13/2012 D2_KEPLER Revision History 4 3 01/13/2012 D2_KEPLER Power Block Diagram 3 2 01/13/2012 D2_KEPLER System Block Diagram 2 Memory Constraints D2_KEPLER 01/13/2012 101 90 CPU Constraints D2_KEPLER 01/13/2012 100 89 Power Sequencing EG/PCH S0 D2_KEPLER 01/13/2012 99 88 PCH VCCIO (1.05V) POWER SUPPLY D2_KEPLER 01/13/2012 98 87 LCD Backlight Driver (LP8545) D2_KEPLER 01/13/2012 97 86 Thunderbolt Connector B D2_KEPLER 01/13/2012 96 85 Thunderbolt Connector A D2_KEPLER 01/13/2012 94 84 eDP Muxed Graphics Support D2_SEAN 03/05/2012 92 83 eDP Mux D2_SEAN 03/05/2012 91 82 eDP Display Connector D2_KEPLER 01/13/2012 90 81 GFX IMVP VCore Regulator D2_SEAN 03/05/2012 89 80 KEPLER PEX PWR/GNDS D2_SEAN 03/05/2012 88 79 KEPLER GPIOS,CLK & STRAPS D2_SEAN 03/05/2012 87 78 KEPLER EDP/DP/GPIO D2_SEAN 03/05/2012 86 77 GDDR5 Frame Buffer B D2_SEAN 03/05/2012 85 76 GDDR5 Frame Buffer A D2_SEAN 03/05/2012 84 75 1V05 GPU / 1V35 FB POWER SUPPLY D2_SEAN 03/05/2012 83 74 KEPLER FRAME BUFFER I/F D2_SEAN 03/05/2012 82 73 KEPLER CORE/FB POWER D2_SEAN 03/05/2012 81 72 KEPLER PCI-E D2_KEPLER 01/13/2012 80 71 Power Control 1/ENABLE D2_KEPLER 01/13/2012 79 70 Power FETs D2_KEPLER 01/13/2012 78 69 Misc Power Supplies D2_KEPLER 01/13/2012 77 68 CPU VCCIO (1V0R1V05 S0) POWER SUPPLY D2_KEPLER 01/13/2012 76 67 CPU IMVP7 & AXG VCore Output D2_SEAN 03/05/2012 75 66 CPU IMVP7 & AXG VCore Regulator D2_SEAN 03/05/2012 74 65 1V5R1V35V DDR3 SUPPLY D2_KEPLER 01/13/2012 73 64 5V / 3.3V Power Supply D2_KEPLER 01/13/2012 72 63 System Agent Supply D2_KEPLER 01/13/2012 71 62 PBus Supply & Battery Charger D2_KEPLER 01/13/2012 70 61 DC-In & Battery Connectors D2_KEPLER 01/13/2012 69 60 AUDIO: JACK TRANSLATORS D2_CARA 03/16/2012 68 59 AUDIO: JACK D2_CARA 03/16/2012 67 58 AUDIO: SPEAKER AMP D2_CARA 03/16/2012 66 57 AUDIO: IV SENSE FILTER D2_CARA 03/16/2012 65 56 AUDIO: IV SENSE D2_CARA 03/16/2012 64 55 AUDIO: HEADPHONE FILTER D2_CARA 03/16/2012 63 54 AUDIO: CODEC/REGULATOR D2_CARA 03/16/2012 62 53 SPI ROM D2_KEPLER 01/13/2012 61 52 DIGITAL ACCELEROMETER & GYRO D2_KEPLER 01/13/2012 59 51 KEYBOARD/TRACKPAD (2 OF 2) D2_KEPLER 01/13/2012 58 50 KEYBOARD/TRACKPAD (1 OF 2) D2_KEPLER 01/13/2012 57 49 Fan Connectors D2_KEPLER 01/13/2012 56 48 Thermal Sensors D2_SEAN 03/05/2012 55 47 D2_KEPLER 01/13/2012 99  SMC12 SENSORS EXTENDED 132 D2_SEAN 03/05/2012 98  DEBUG SENSORS AND ADC 130 D2_KEPLER 01/13/2012 97  PCB Rule Definitions 109 D2_CLEAN 03/15/2012 96  Project Specific Constraints 108 D2_KEPLER 01/13/2012 95  GPU (Kepler) CONSTRAINTS 107 D2_KEPLER 01/13/2012 94  SMC Constraints 106 D2_KEPLER 01/13/2012 93  Thunderbolt Constraints 105 D2_KEPLER 01/13/2012 92  PCH Constraints 2 103 SCHEM,MLB,KEPLER_2PHASE,D2  CRITICAL SCH 1 051-9589 High Side and CPU/AXG Current Sensing D2_SEAN 03/05/2012 54 46 Sync Page Date Contents (.csa) D2_KEPLER 01/13/2012 91  PCH Constraints 1 102 Date (.csa) Contents Sync Page 1 01/13/2012 D2_KEPLER Table of Contents 1 ABBREV=ABBREV TITLE=MLB LAST_MODIFIED=Wed May 9 13:50:52 2012 Contents (.csa) Date Sync Page PCBF,MLB,KEPLER_2PHASE,D2  CRITICAL 1 820-3332  PCB SCHEM,MLB,KEPLER,2PHASE,D2 ˘»„ß–˚˙˛‹—‰»` ¨”¨””¯£”325742634 ˘»„ß–˚˙˛‹—‰»` ¨”¨””¯£”325742634

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    DRAWING

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    DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL

    2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

    PROPRIETARY PROPERTY OF APPLE INC.

    3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

    DESCRIPTION OF REVISIONCKAPPD

    2 1

    1245678

    B

    D

    6 5 4 3

    C

    A

    NOTICE OF PROPRIETARY PROPERTY:

    PAGE

    THE INFORMATION CONTAINED HEREIN IS THE

    C

    A

    D

    DATE

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    SHEET

    Apple Inc.

    THE POSESSOR AGREES TO THE FOLLOWING:

    DRAWING TITLE

    DSIZE

    REVISION

    DRAWING NUMBER

    BRANCH

    REV ECN

    7

    B

    3

    II NOT TO REPRODUCE OR COPY IT I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

    IV ALL RIGHTS RESERVEDIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

    1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

    8

    SCHEM,MLB,KEPLER,2PHASE,D2

    Schematic / PCB #s

    FSB, 5/9/2012

    1 OF 99

    2012-05-09

    1 OF 132

    4.18.0

    051-9589

    53 03/05/2012D2_SEANVoltage & Load Side Current Sensing45

    52 01/13/2012D2_KEPLERSMBus Connections44

    51 01/13/2012D2_KEPLERLPC+SPI Debug Connector43

    50 01/13/2012D2_KEPLERSMC Support42

    49 01/13/2012D2_KEPLERSMC41

    46 01/13/2012D2_KEPLERUSB 3.0 CONNECTORS40

    45 01/13/2012D2_KEPLERSSD CONNECTOR39

    44 01/13/2012D2_KEPLERRIO CONNECTOR38

    38 01/13/2012D2_KEPLERThunderbolt Power Support37

    37 01/13/2012D2_KEPLERThunderbolt Host (2 of 2)36

    36 01/13/2012D2_KEPLERThunderbolt Host (1 of 2)35

    35 01/13/2012D2_KEPLERX29/ALS/CAMERA CONNECTOR34

    34 01/13/2012D2_KEPLERDDR3/FRAMEBUF VREF MARGINING33

    33 01/13/2012D2_KEPLERDDR3 Termination32

    32 01/13/2012D2_KEPLERDDR3 SDRAM Bank B (2 OF 2)31

    31 01/13/2012D2_KEPLERDDR3 SDRAM Bank B (1 OF 2)30

    30 01/13/2012D2_KEPLERDDR3 SDRAM Bank A (2 OF 2)29

    29 01/13/2012D2_KEPLERDDR3 SDRAM Bank A (1 OF 2)28

    28 01/13/2012D2_KEPLERCPU Memory S3 Support27

    27 01/13/2012D2_KEPLERUSB HUB & MUX26

    26 01/13/2012D2_KEPLERChipset Support25

    25 01/13/2012D2_KEPLERCPU & PCH XDP24

    24 03/19/2012D2_CLEANPCH DECOUPLING23

    23 01/13/2012D2_KEPLERPCH GROUNDS22

    22 03/19/2012D2_CLEANPCH POWER21

    21 01/13/2012D2_KEPLERPCH GPIO/MISC/NCTF20

    20 01/13/2012D2_KEPLERPCH PCI/USB/TP/RSVD19

    19 01/13/2012D2_KEPLERPCH DMI/FDI/PM/Graphics18

    18 01/13/2012D2_KEPLERPCH SATA/PCIe/CLK/LPC/SPI17

    17 03/05/2012D2_SEANCPU DECOUPLING-II16

    16 03/05/2012D2_SEANCPU DECOUPLING-I15

    14 01/13/2012D2_KEPLERCPU POWER AND GND14

    13 01/13/2012D2_KEPLERCPU POWER13

    12 01/13/2012D2_KEPLERCPU DDR3 INTERFACES12

    11 01/13/2012D2_KEPLERCPU CLOCK/MISC/JTAG11

    10 01/13/2012D2_KEPLERCPU DMI/PEG/FDI/RSVD10

    9 01/13/2012D2_KEPLERSignal Aliases9

    8 01/13/2012D2_KEPLERPower Aliases8

    7 01/13/2012D2_KEPLERFunctional / ICT Test7

    6 01/13/2012D2_KEPLERBOM Variants6

    5 01/13/2012D2_KEPLERBOM Configuration5

    4 01/13/2012D2_KEPLERRevision History4

    3 01/13/2012D2_KEPLERPower Block Diagram3

    2 01/13/2012D2_KEPLERSystem Block Diagram2

    Memory Constraints D2_KEPLER01/13/201210190

    CPU Constraints D2_KEPLER01/13/201210089

    Power Sequencing EG/PCH S0 D2_KEPLER01/13/20129988

    PCH VCCIO (1.05V) POWER SUPPLY D2_KEPLER01/13/20129887

    LCD Backlight Driver (LP8545) D2_KEPLER01/13/20129786

    Thunderbolt Connector B D2_KEPLER01/13/20129685

    Thunderbolt Connector A D2_KEPLER01/13/20129484

    eDP Muxed Graphics Support D2_SEAN03/05/20129283

    eDP Mux D2_SEAN03/05/20129182

    eDP Display Connector D2_KEPLER01/13/20129081

    GFX IMVP VCore Regulator D2_SEAN03/05/20128980

    KEPLER PEX PWR/GNDS D2_SEAN03/05/201288

    79KEPLER GPIOS,CLK & STRAPS D2_SEAN

    03/05/20128778

    KEPLER EDP/DP/GPIO D2_SEAN03/05/20128677

    GDDR5 Frame Buffer B D2_SEAN03/05/20128576

    GDDR5 Frame Buffer A D2_SEAN03/05/20128475

    1V05 GPU / 1V35 FB POWER SUPPLY D2_SEAN03/05/20128374

    KEPLER FRAME BUFFER I/F D2_SEAN03/05/20128273

    KEPLER CORE/FB POWER D2_SEAN03/05/20128172

    KEPLER PCI-E D2_KEPLER01/13/20128071

    Power Control 1/ENABLE D2_KEPLER01/13/20127970

    Power FETs D2_KEPLER01/13/20127869

    Misc Power Supplies D2_KEPLER01/13/20127768

    CPU VCCIO (1V0R1V05 S0) POWER SUPPLY D2_KEPLER01/13/20127667

    CPU IMVP7 & AXG VCore Output D2_SEAN03/05/20127566

    CPU IMVP7 & AXG VCore Regulator D2_SEAN03/05/20127465

    1V5R1V35V DDR3 SUPPLY D2_KEPLER01/13/20127364

    5V / 3.3V Power Supply D2_KEPLER01/13/20127263

    System Agent Supply D2_KEPLER01/13/20127162

    PBus Supply & Battery Charger D2_KEPLER01/13/20127061

    DC-In & Battery Connectors D2_KEPLER01/13/20126960

    AUDIO: JACK TRANSLATORS D2_CARA03/16/20126859

    AUDIO: JACK D2_CARA03/16/20126758

    AUDIO: SPEAKER AMP D2_CARA03/16/20126657

    AUDIO: IV SENSE FILTER D2_CARA03/16/20126556

    AUDIO: IV SENSE D2_CARA03/16/20126455

    AUDIO: HEADPHONE FILTER D2_CARA03/16/20126354

    AUDIO: CODEC/REGULATOR D2_CARA03/16/20126253

    SPI ROM D2_KEPLER01/13/20126152

    DIGITAL ACCELEROMETER & GYRO D2_KEPLER01/13/20125951

    KEYBOARD/TRACKPAD (2 OF 2) D2_KEPLER01/13/20125850

    KEYBOARD/TRACKPAD (1 OF 2) D2_KEPLER01/13/20125749

    Fan Connectors D2_KEPLER01/13/20125648

    Thermal Sensors D2_SEAN03/05/20125547

    D2_KEPLER01/13/201299 SMC12 SENSORS EXTENDED132

    D2_SEAN03/05/201298 DEBUG SENSORS AND ADC130

    D2_KEPLER01/13/201297 PCB Rule Definitions109

    D2_CLEAN03/15/201296 Project Specific Constraints108

    D2_KEPLER01/13/201295 GPU (Kepler) CONSTRAINTS107

    D2_KEPLER01/13/201294 SMC Constraints106

    D2_KEPLER01/13/201293 Thunderbolt Constraints105

    D2_KEPLER01/13/201292 PCH Constraints 2103

    SCHEM,MLB,KEPLER_2PHASE,D2 CRITICALSCH1051-9589

    High Side and CPU/AXG Current Sensing D2_SEAN03/05/20125446

    SyncPageDate

    Contents(.csa)

    D2_KEPLER01/13/201291 PCH Constraints 1102

    Date(.csa)

    Contents SyncPage1 01/13/2012

    D2_KEPLERTable of Contents1

    ABBREV=ABBREVTITLE=MLB

    LAST_MODIFIED=Wed May 9 13:50:52 2012

    Contents(.csa) Date

    SyncPage

    PCBF,MLB,KEPLER_2PHASE,D2 CRITICAL1820-3332 PCB

    SCHEM,MLB,KEPLER,2PHASE,D2

    325742634

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    THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.

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    R

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    6 3

    THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

    III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT

    POWER SUPPLY

    PG 63

    DC/BATT

    TEMP SENSOR

    J6950

    U4900

    PG 23

    SPI

    Boot ROM

    U6100

    XDP CONN

    J2500,J2550

    J2900

    DIMM

    PG 26,28

    J3100

    PG 16

    DDR3-1067/1333MHZ

    2 DIMMS

    RTCDMI

    PG 17

    PG 44

    PG 51

    PG 44

    POWER SENSE

    FAN CONN AND CONTROLJ5650,5660

    Fan

    CONNECTION

    SMBUS

    PG 47

    PG 63

    SPEATKER

    TRACKPAD/KEYBOARD

    U6610,6620,6630

    SPEATKER

    SerADC

    PG 44

    SMC

    BSBB,0

    J3402

    U4900

    Prt

    PG 55

    PG 46

    U3600

    CAMERA

    PG 33

    PG 33

    PG 41

    PG 31

    EXTERNAL B

    EXTERNAL C

    J4501

    J4610

    PG 34

    PG 31

    PG 53

    BLUETOOTH

    EXTERNAL A

    J5713

    J3401

    J4600

    USB

    HUB 2

    PG 33

    HUB 1

    USB

    PG 34

    U3700

    LPC + SPI CONN

    Port80,serial

    J5100

    PG 19

    Misc

    SPI

    PG 16

    LPC

    PG 16

    PWR

    10

    11

    13

    12

    98

    65

    47

    32

    10

    CTRL

    PG 17

    (UP

    TO 1

    4 DE

    VICE

    S)PG 18

    USB

    AUDIO

    PG 56

    DIMM

    PG 26,28

    U6201

    AMP

    PG 59

    PG 60

    FILTER

    PG 58

    AUDIO

    CONN

    PG 57

    J6700,J6750

    LINE TIN

    FILTER

    PG 16

    PG 16

    SMB

    HDA

    J3500

    PG 37

    CONN

    (UP TO 16 LINES)

    SDCARD READER

    U1800

    2.X GHZ

    INTEL CPU

    INTEL

    MOBILE

    PG 9

    PG 17

    FDI

    PG 19

    GPIO

    GRAPHICS

    AMD WHISTLER

    U8000

    PG 73

    U2700 CLOCK

    SATA3.0/6(GB/S)

    SATA3.0/6(GB/S)

    SATA2.0/3(GB/S)

    SATA2.0/3(GB/S)

    SATA2.0/3(GB/S)

    SATA2.0/3(GB/S)

    BUFFER

    PG 16

    45

    SATA

    23

    PG 16

    10

    DP OUT

    RGB OUT

    HDMI OUT

    LVDS OUT

    DVI OUT

    PG 18

    TMDS OUT

    PCI

    PG 18

    PG 24

    PG 41

    CK5G05

    CONN

    SATA

    J4501

    ODD

    PG 41

    SATA

    CONN

    J4500

    HDD

    PG 83

    DP MUX

    XP25-5G

    PG 84

    JTAG

    PCI-E

    PG 16

    PEG

    PG 16

    PG 16

    BCM57765

    GB

    PG 36

    E-NET

    CONN

    PG 37

    E-NET

    J4000

    U3900

    PG 38

    PG 40

    CONN

    FIREWIRE

    FW643

    PG 83

    DDC MUX

    PG 86

    GMUX

    U4100

    J4310PG 31

    AirPort

    J3401

    MINI DP PORT

    LCD PANEL

    U9600

    U9320

    U9370

    J9400

    IR

    (RESERVATION)

    CODEC

    HEADPHONE

    CLK

    PANTHER-POINT

    IVY BRIDGE

    SYNC_DATE=01/13/2012SYNC_MASTER=D2_KEPLER

    System Block Diagram051-9589

    4.18.0

    2 OF 132

    2 OF 99

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    IV ALL RIGHTS RESERVED

    R

    DSIZEDRAWING NUMBER

    REVISION

    BRANCH

    6 3

    THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

    III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT

    D2 POWER SYSTEM ARCHITECTURE

    CPUVTTS0_PGOOD

    VOUTREF3333

    (PAGE 45)

    SMC AVREF SUPPLY

    VOUT

    PGOOD

    1.05VISL95870

    VIN

    SMC_RESET_L

    (PAGE 70)

    U7600

    SMC PWRGD

    NCP303LSN

    VIN

    EN

    PP5V_S0_CPUVTTS0

    (PAGE 45)U5000

    CPUVTTS0_EN

    SMC_GPU_VSENSE

    PPVCORE_GPU

    PP3V42_G3H

    V

    GPUVCORE_PGOOD

    AU5410

    SMC_GPU_ISENSE

    (PAGE 62)

    PM6640

    ENABLE

    3.425V G3HOT

    U6990

    VOUT

    PGOOD

    U8900

    VIN

    ISL6263C

    GPU VCORE

    Q5315V

    VDD

    VR_ON

    SMC_PBUS_VSENSE

    GPUVCORE_EN

    PP5V_S3_GFXIMVP6_VDD

    PPBUS_G3H

    PM_PCH_PWRGD

    U2850

    PP4V5_AUDIO_ANALOG

    SMC_CPU_VSENSE

    PPVCORE_S0_CPU

    SMC_CPU_DDR_VSENSE

    V

    U5440

    V

    VOUT

    U7980

    PM_ALL_GPU_PGOOD

    MAX88404.5V

    PP1V5_S3

    EN

    PP3V3_S0

    ALL_SYS_PWRGDQ7880

    RSMRST_PWRGD

    SMC_ONOFF_L

    PM_SLP_S3_L

    PM_SLP_S5_L

    PM_SLP_S4_L

    PP3V3_S0_PWRCTL

    ISL88042IRTJJZ

    S0PGOOD_PWROK

    VCC

    PP3V3_S0

    PP1V8_GPUIFPX

    PP3V3_S0V2MON

    RST*

    U7971

    (PAGE 72)

    TRST = 200mS

    V3MON

    V4MON

    PP1V5_S0

    PP1V05_S0

    SMC_CPU_ISENSE

    A

    SMC_DDR_ISENSE

    R7350

    CPUIMVP7_AXG_PGOOD

    PP3V3_ENET

    Q7850

    P1V8GPUIFPXFET_GATE

    PP1V2_S0

    P1V2S0_EN

    PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN

    PP1V8_S0

    VOUT

    PGOOD

    ISL95831

    U7400

    (PAGE 67)

    CPU VCORE

    VIN

    VR_ON

    A

    P5VS0_EN

    PP5V_S0

    PPDDR_S3_REG

    PPVTT_S0_DDR_LDO

    Q7860

    VOUT2

    VLDOIN

    VOUT1

    PGOOD

    PP1V5_S3RS0

    PP5V_S3_DDRREG

    VIN

    A

    R5388/U5388

    CPUIMVP7_VR_ON

    0.75V

    1.5V

    TPS51116

    Q7801

    P1V5S0FET_GATE

    U7300

    (PAGE 66)

    SMC_CPU_HI_ISENSE

    S5

    S3

    PP3V3_S5

    PP1V5_S3

    G

    U7801

    VIN

    PP3V3_S5

    PP5V_S3

    DDRREG_EN

    DDRVTT_EN

    SLG5AP020ON

    VOUT2

    VOUT1

    VREG5

    P1V5CPU_EN

    (L/H)

    (R/H)3.3V

    5V

    VIN

    G

    U7880SLG5AP020

    VIN

    Q7922

    ON

    FW_PWR_EN

    P1V8FB_EN

    PP3V3_FW_FWPHYU4201TPS22924

    (PAGE 39)

    EN

    PP1V8_S0

    P1V8S0_PGOOD

    P1V2ENET_PGOOD

    PP1V2_ENET

    PGOOD

    VOUT

    (PAGE 70)U7720ISL8014A

    VIN

    VINISL8014A

    VOUT

    PGOOD(PAGE 70)U7760EN

    PP3V3_S0GPU

    P1V2ENET_EN

    P3V3S3_EN

    EN

    P3V3S0_EN

    PP3V3_S0_FET

    PP3V3_S3

    Q7810

    Q7870

    Q7830

    U7201

    P1V8_S0_EN

    D6990

    PPBUS_G3H

    PGOOD(PAGE 65)

    PP1V0_S0GPU_REG

    PPVOUT_S0_LCDBKLT

    P5V3V3_PGOOD

    P1V0GPU_PGOOD

    P1V5FB_PGOOD

    TPS51125

    PP1V5_GPU_REG

    SMC_GPU_1V8_ISENSE

    F7040

    8A FUSE

    AR7050

    PPVBAT_G3H

    SMC_BATT_ISENSE

    VOUT

    R6990

    ISL6259HRTZ

    U7000

    PBUS SUPPLY/BATTERY CHARGER

    PP18V5_DCIN_CONN

    R7020

    VINA

    SMC_RESET_L

    SMC_DCIN_ISENSE

    F69056A FUSE

    DCIN(16.5V)

    J6900

    IN

    (PAGE 64)

    R5413

    A

    VOUT1

    POK1

    VOUT2

    EN1

    EN2

    POK2

    1.003V(L/H)

    P3V3S5_EN

    (PAGE 85)

    1.503V(R/H)

    P5VS3_EN

    VINEN1

    ISL6236

    EN2

    Q9806

    U9500

    P1V0GPU_EN

    PPVBAT_G3H_CHGR_R

    P1V5FB_EN

    Q7055

    GPUVCORE_EN

    P3V3GPU_EN

    P1V1GPU_EN

    P3V3S5_EN

    VOUT

    VIN

    LP8550

    PFWBOOST

    U9701

    (PAGE 87)

    ENABKLT_EN

    Q4260

    LCD_BKLT_NO

    BKLT_PLT_RST_L

    SMC_ADAPTER_EN&&PM_SLP_S3_L

    &&

    P5VS0_EN

    P3V3S0_EN

    PBUSVSENS_EN

    PM_SLP_S3_L_R

    P5VS3_EN

    DDRREG_EN

    P3V3S3_EN

    PM_ALL_GPU_PGOOD

    PM_SLP_S4_L

    PM_SLP_S5_L

    PM_SLP_S3_L

    PPVBATT_G3H_CONN

    EG_RAIL1_EN

    EG_RAIL3_EN

    EG_RAIL2_EN

    J6950

    (9 T

    O 12

    .6V)

    PB16B

    PB17B

    PB17AU9600

    GMUX

    PB18AEG_RAIL4_ENXP25-5

    DELAY

    RC

    SLP_S5#(E4)

    SMC_PM_G2_EN

    PL32A

    U4900

    (PAGE 86)

    SMC

    P60

    (PAGE 44)

    MOBILE

    RC

    RC

    DELAY

    DELAY

    SLP_S4#(H7)

    SLP_S3#(P12)

    (PAGE 16~21)

    U1800

    R7978

    P1V2S0_EN

    P1V8S0_EN

    P1V5CPU_EN

    CPUVTTS0_EN

    RC

    DELAY

    RC

    DELAY

    RC

    RC

    DELAY

    DELAY

    PP1V0_FW_FWPHY

    PP3V3_S5_SMC

    U5001

    (PAGE 39)

    TPS22924U4202

    FW_PWR_EN

    EN

    PM_PWRBTN_L

    PM_MEM_PWRGD

    CPU_PWRGD

    PLT_RERST_L

    SMC_ADAPTER_EN

    PM_PWRBTN_L

    PM_SYSRST_L

    CPUIMVP_VR_ON

    PM_RSMRST_L

    SMC_RESET_L

    RSMRST_OUT(P15)

    SMC_CPU_FSB_ISENSE

    PPCPUVTT_S0

    (PAGE 16~21)

    SYS_RERST#

    PWRBTN#

    SM_DRAMPWROK

    RESET*

    (P64)

    PP3V3_S5_AVREF_SMC

    99ms DLY

    IMVP_VR_ON(P16)

    SYSRST(PA2)

    P17(BTN_OUT)

    RES*

    PLTRST#

    SMC_ONOFF_L

    SMC_TPAD_RST_L

    DRAMPWROK

    PROCPWRGD

    AR7640

    CPUVTTS0_PGOOD

    VOUTREF3333

    (PAGE 45)

    SMC AVREF SUPPLY

    VOUT

    PGOOD

    1.05VISL95870

    SMC_RESET_L

    (PAGE 70)

    U1800

    PS_PWRGD

    PM_PCH_PWRGD

    U2850

    U1000

    CPU

    SMC

    (PAGE 9~14)

    PP4V5_AUDIO_ANALOG

    ALL_SYS_PWRGD

    PWR_BUTTON(P90)

    RSMRST_IN(P13)

    PWRGD(P12)

    H8S2117

    SLP_S5_L(P95)

    U4900

    SLP_S3_L(P93)

    SLP_S4_L(P94)

    (PAGE 45)

    RSMRST_PWRGD

    SMC_ONOFF_L

    PM_SLP_S3_L

    PM_SLP_S5_L

    PM_SLP_S4_L

    U6200VIN

    CHGR_BGATE

    ADAPTER

    AC

    P5V3V3_PGOOD

    P1V8S0_PGOOD

    PP3V3_S0_PWRCTL

    (PAGE 82)

    DDRREG_PGOOD

    P3V3GPU_EN

    ACPRESENT

    RSMRST#

    VCCCPUPWRGD

    3S2P

    PANTHER-POINT

    PANTHER_POINT

    Power Block DiagramSYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012

    051-9589

    4.18.0

    3 OF 132

    3 OF 99

    www.qdzbwx.com

    325742634

    325742634

  • Apple Inc.

    THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.

    124578

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    A

    NOTICE OF PROPRIETARY PROPERTY:

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    SHEET

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    6 3

    THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

    III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT

    Revision HistorySYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012

    051-9589

    4.18.0

    4 OF 132

    4 OF 99

  • TABLE_BOMGROUP_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

    TABLE_ALT_HEAD

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_ALT_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

    BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

    BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL

    Apple Inc.

    THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.

    124578

    B

    D

    8 7 6 5 4 3

    C

    B

    A

    NOTICE OF PROPRIETARY PROPERTY:

    PAGE

    12

    D

    A

    C

    PAGE TITLE

    SHEET

    IV ALL RIGHTS RESERVED

    R

    DSIZEDRAWING NUMBER

    REVISION

    BRANCH

    6 3

    THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

    III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT

    PD Parts

    Alternate PartsBOM Variants (continued on CSA 6)

    Module Parts

    Bar Code Labels / EEEE #s (continued on CSA 6)

    DRAM SPD Straps

    Programmables

    DRAM VREF Configs

    DEVELOPMENT/BASE BOM

    SMC

    EFI ROM

    BOM Groups

    085-4776 D2_DEVEL:FSB

    085-3726 D2_DEVEL:ENG

    SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012

    BOM Configuration

    128S0264 ALL128S0257

    353S3527 Pericom eDP MUX353S3528 ALL

    TI eDP MUXALL353S3526 353S3528

    Diodes alt to Toshiba376S0613 ALL376S0855

    376S0855 376S0613 Diodes alt to ToshibaALLVREFDQ:M1_M3

    ALL376S0796376S0903 Fairchild alt to Siliconix

    ALL Diodes alt to On Semi376S1076

    376S0977 ALL376S0859 Diodes alt to Toshiba

    376S1053 ALL376S0604 Diodes alt to Fairchild

    128S0311 ALL NEC alt to Sanyo

    138S0739 138S0706 ALL Samsung alt to Murata

    197S0435 197S0343 ALL NDK Alt to TXC

    197S0434 197S0343 ALL Epson Alt to TXC

    ALL197S0431 NDK Alt to Epson

    Epson Alt to TXCALL197S0181197S0452

    NDK Alt to TXCALL197S0453 197S0181

    D2,MLB,KEPLER,FSB DEV

    D2,MLB,KEPLER,DEV

    D2,MLB,KEPLER_2PHASE,COMMON607-9546

    639-3379 PCBA,2.3G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,DY3W

    639-3378

    639-3380

    639-3384 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY43,DEVEL_BOM,RAM_4G_HYNIX_1600

    639-3381

    639-3385 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY44,DEVEL_BOM,RAM_4G_HYNIX_1600

    639-2821 BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRF1,DEVEL_BOM,RAM_2G_HYNIX_1600

    639-3386 PCBA,2.3G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,DY45 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY45,DEVEL_BOM,RAM_4G_SAMSUNG_1600

    639-3387 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY4C,DEVEL_BOM,RAM_4G_SAMSUNG_1600

    639-2825

    639-2817

    639-2815

    639-2979

    639-2981 PCBA,2.6G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,DT9F

    639-2980

    639-2982

    639-3618

    639-3561 BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:DYW4,DEVEL_BOM,RAM_2G_SAMSUNG_1600

    639-3619

    639-3620

    639-3628

    639-3562

    639-3627

    639-3629

    D2_COMMON2

    D2_COMMON1

    D2_COMMON

    D2_PVB

    D2_DEVEL:ENG

    D2_PROGPARTS

    D2_DEVEL:FSB

    IVB_PPT_XDP

    CPU_IVY:2_3GHZ1 CRITICALU1000337S4266

    1337S4268

    1 U1000337S4267

    1 U1800337S4269

    IC,GPU,NV GK107-GTX-PS-A21 U8000

    U36001338S1113

    333S0622 32 2G_HYNIX_1600U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270

    32

    32333S0623

    333S0628 32 IC,SDRAM,DDR3-1600,256MX8,78FBGA,D-DIE,ELPIDA

    333S0624 32 CRITICAL

    333S0630 4 CRITICALIC,SDRAM,GDDR5,64MX32,A-DIE,HYNIX

    333S0629 CRITICAL32

    PBUS PAIR,KEMET POSCAP,TALL MYLAR,D2

    PBUS PAIR,SANYO POSCAP,SHORT MYLAR,D2

    685-0016

    685-0017

    PBUS_CAP:KEMET

    IC,SDRAM,DDR3-1600,256MX8,78FBGA,SAMSUNG

    IC,SDRAM,DDR3-1600,256MX8,78FBGA,HYNIX,C-DIE,38NM

    IC,TBT,CR-4C,B1,PRQ,CIO,228 12X12 FC-CSP

    IVB,S R0MK,PRQ,E1,2.7,45W,4+2,1.25,8M,BGA

    IVB,S R0MM,PRQ,E1,2.6,45W,4+2,1.25,6M,BGA

    PCBA,2.7G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,F0HT

    PCBA,2.7G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DYW4

    PCBA,2.3G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DY44

    PCBA,2.6G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DT9D

    PCBA,2.3G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,DY4C

    PCBA,2.3G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,DY43

    PCBA,2.3G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,DY40

    PCBA,2.3G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DY3Y

    PCBA,2.3G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,DY3V

    CRITICAL

    CRITICAL

    CRITICAL

    U1000

    341S3564 ALL341S3565 Avnet eDP MUX alt to Renesas

    107S0232 Cyntec alt to TFTALL107S0129

    Epson alt to NDK197S0466 197S0464 ALL

    ALL Panasonic alt to TDK155S0583155S0667

    152S0461 Cyntec alt to VishayALL152S1645

    ALL376S1080 376S0820 Diodes alt to On Semi

    ALL377S0066

    DDS alt to STALL371S0713

    ALL NXP alt to infineon371S0652

    377S0126 377S0066 ALL New Semtech package

    ALL376S0975 Toshiba alt to diodes376S1081

    371S0709

    Sanyo POSCAP/Mylar alt to Kemet685-0016685-0017 ALL

    CRITICAL1725-1648 PBUS_CAP:KEMET

    CRITICAL

    725-1568 1

    725-1569 CRITICAL1

    1725-1621 CRITICAL

    806-2897 CAN,COVER,2,J52 CRITICAL

    D2 MLB DYMAX ADHESIVE SEE-CURE 29993-SC CRITICAL

    IC,SDRAM,GDDR5,64MX32,D-DIE,SAMSUNG CRITICAL4333S0631

    PBUS_CAP:SANYO

    CRITICAL

    PBUS_CAP:KEMET128S0257

    CRITICAL

    CRITICAL

    TBTRTR:PRQ

    2G_SAMSUNG_1600

    PBUS_CAP:SANYO

    FB_2G_HYNIX_A_DIE

    4G_ELPIDA_1600

    4G_SAMSUNG_1600

    4G_HYNIX_1600

    2G_ELPIDA_1600

    CRITICAL

    CRITICAL

    CRITICAL

    CRITICAL

    XDP_CONN,XDP_PCH

    ALTERNATE,IVB_PPT_XDP

    SMC_PROG:FSB,BOOTROM_PROG:FSB,DPMUXMCU:PROG,TPAD_PSOC:PROG,TBTROM:PROG

    VREF:PROD,D_BKL:PROD,SENSOR_NONPROD:N

    CPUMEM_S0,SMC_DEBUG_YES,DPMUX:HOCO,TBTRTR:PRQ,TBTBST:Y,TBTHV:P15V,HUB_2NONREM,USBHUB2512B,SPEAKERID,SMC_PACKAGE:PROD,SKIP_5V3V3:AUDIBLE,CHGR_5V:LDO,P1V5S0:LDO

    ALTERNATE,COMMON,D2_COMMON1,D2_COMMON2,D2_PROGPARTS,D2_PVB

    PCBA,2.7G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,F0HM

    PCBA,2.7G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,F0HV

    BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DT9H,DEVEL_BOM,RAM_4G_HYNIX_1600

    PBUS_CAP:SANYO

    BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY3V,DEVEL_BOM,RAM_2G_HYNIX_1600

    BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY3W,DEVEL_BOM,RAM_2G_HYNIX_1600

    BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY40,DEVEL_BOM,RAM_2G_SAMSUNG_1600

    BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HM,DEVEL_BOM,RAM_4G_HYNIX_1600

    ALTERNATE,IVB_PPT_XDP,S0PGOOD_ISL,DPMUX_DEBUG,DDRVREF_DAC,VREF:ENG_M3,SENSOR_NONPROD:Y,D_BKL:DEV

    CPU_IVY:2_6GHZ

    CPU_IVY:2_7GHZ

    FB_2G_SAMSUNG

    BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HT,DEVEL_BOM,RAM_4G_SAMSUNG_1600

    BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HY,DEVEL_BOM,RAM_4G_SAMSUNG_1600

    BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:DYW5,DEVEL_BOM,RAM_4G_HYNIX_1600

    BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DT9D,DEVEL_BOM,RAM_4G_HYNIX_1600

    BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRF4,DEVEL_BOM,RAM_2G_HYNIX_1600

    BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRDN,DEVEL_BOM,RAM_2G_SAMSUNG_1600

    BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDW,DEVEL_BOM,RAM_2G_SAMSUNG_1600

    BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DT9F,DEVEL_BOM,RAM_4G_SAMSUNG_1600

    BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DT9G,DEVEL_BOM,RAM_4G_SAMSUNG_1600

    BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HN,DEVEL_BOM,RAM_2G_HYNIX_1600

    BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HR,DEVEL_BOM,RAM_2G_HYNIX_1600

    D2_COMMON,POSCAP_MYLAR_PAIR

    [EEEE:DY3V] CRITICAL825-7563 1 EEEE:DY3VLABEL,MLB/LIO,MBA

    [EEEE:DY3W]825-7563 CRITICAL EEEE:DY3W1 LABEL,MLB/LIO,MBA

    [EEEE:DY40]LABEL,MLB/LIO,MBA CRITICAL EEEE:DY40825-7563 1

    825-7563 EEEE:DY3Y1 [EEEE:DY3Y] CRITICAL

    [EEEE:DY43] EEEE:DY431825-7563 CRITICALLABEL,MLB/LIO,MBA

    825-7563 1 CRITICAL[EEEE:DY45]LABEL,MLB/LIO,MBA

    LABEL,MLB/LIO,MBA EEEE:DY44[EEEE:DY44] CRITICAL1825-7563

    825-7563 1 [EEEE:DY4C] CRITICALLABEL,MLB/LIO,MBA

    1 [EEEE:DRF1] CRITICAL825-7563 LABEL,MLB/LIO,MBA

    [EEEE:DRF4] CRITICAL1825-7563 LABEL,MLB/LIO,MBA

    EEEE:DRDNCRITICAL1825-7563 [EEEE:DRDN]LABEL,MLB/LIO,MBA

    1 [EEEE:DRDW] CRITICAL825-7563 LABEL,MLB/LIO,MBA

    LABEL,MLB/LIO,MBA825-7563 1 EEEE:DT9D[EEEE:DT9D] CRITICAL

    LABEL,MLB/LIO,MBA825-7563 1 [EEEE:DT9F] CRITICAL

    1825-7563 [EEEE:DT9H] CRITICAL

    825-7563 LABEL,MLB/LIO,MBA1 CRITICAL[EEEE:DT9G]

    LABEL,MLB/LIO,MBA825-7563 EEEE:F0HR[EEEE:F0HR] CRITICAL1

    LABEL,MLB/LIO,MBA825-7563 EEEE:F0HN[EEEE:F0HN]1 CRITICAL

    LABEL,MLB/LIO,MBA825-7563 [EEEE:DYW4] CRITICAL1 EEEE:DYW4

    825-7563 LABEL,MLB/LIO,MBA EEEE:F0HV[EEEE:F0HV]1 CRITICAL

    LABEL,MLB/LIO,MBA825-7563 EEEE:F0HM[EEEE:F0HM] CRITICAL1

    [EEEE:DYW5] CRITICALLABEL,MLB/LIO,MBA825-7563 1 EEEE:DYW5

    LABEL,MLB/LIO,MBA825-7563 EEEE:F0HT[EEEE:F0HT] CRITICAL1

    EEEE:F0HYLABEL,MLB/LIO,MBA [EEEE:F0HY] CRITICAL1

    IC,TRKPD/KYBD CNTRLR,DVB,D21341S3584 CRITICALU5701 TPAD_PSOC:PROG

    U5701IC,TP PSOC,QFN,BLANK337S2983 TPAD_PSOC:BLANK1 CRITICAL

    1 CRITICALU3690 TBTROM:PROG

    EEPROM,256KBIT,SPI,5MHZ,1.8V,2X3QFN335S0865 U3690 TBTROM:BLANKCRITICAL1

    IC,GPU ROM,D2,BLANK335S0852 U87011 GPUROM:BLANKCRITICAL

    IC,EDP MUX-95C, (RENESAS) V3.2.8,DVB,D2341S3565 1 U9100 CRITICAL DPMUXMCU:PROG

    CRITICAL DPMUXMCU:BLANK1 U9100

    VREFDQ:M1_M3,VREFCA:LDOVREFDQ:M1_M3,VREFCA:LDO_DACVREF:ENG_M3VREFDQ:M1_DAC,VREFCA:LDO_DACVREF:ENG_LDO

    RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

    RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:HRAM_1G_SAMSUNG_1600

    RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:LRAM_4G_SAMSUNG_1600_S

    RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:HRAM_1G_HYNIX_1600

    RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:LRAM_4G_ELPIDA_1600_S

    2G_SAMSUNG_1600,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:HRAM_2G_SAMSUNG_1600

    2G_HYNIX_1600,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:HRAM_2G_HYNIX_1600

    RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:LRAM_2G_SAMSUNG_1333

    4G_SAMSUNG_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:LRAM_4G_SAMSUNG_1600

    RAM_2G_ELPIDA_1600 2G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

    RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:LRAM_2G_ELPIDA_1600_S

    4G_HYNIX_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:HRAM_4G_HYNIX_1600

    4G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:LRAM_4G_ELPIDA_1600

    RAM_2G_HYNIX_1600_S RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

    RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:HRAM_2G_SAMSUNG_1600_S

    CRITICAL1685-0016 PBUS PAIR,KEMET POSCAP,TALL MYLAR,D2 POSCAP_MYLAR POSCAP_MYLAR_PAIR

    D2 MLB KEPLER 2PHASE BASE BOM BASE CRITICAL607-9546 BASE_BOM1

    1 CRITICAL085-4776 DEVEL_FSB_BOMDEVEL_FSBD2 MLB KEPLER FSB DEVEL BOM

    D2 MLB KEPLER DEVEL BOM DEVEL DEVEL_BOMCRITICAL1085-3726

    LABEL,MLB/LIO,MBA

    128S0329

    IC,MCU,H8S/2113,9X9MM,TLP-145V

    BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HV,DEVEL_BOM,RAM_2G_SAMSUNG_1600

    PCBA,2.6G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,DRDW

    PCBA,2.6G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,DRF4

    BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY3Y,DEVEL_BOM,RAM_2G_SAMSUNG_1600

    LABEL,MLB/LIO,MBA

    Kemet alt to Sanyo

    376S0634

    EEEE:DRF4

    371S0558

    197S0432

    EEEE:DY45

    EEEE:DY4C

    EEEE:DRF1

    EEEE:DRDW

    EEEE:DT9H

    EEEE:DT9F

    EEEE:DT9G

    On Semi alt to Semtech377S0147

    PCBA,2.6G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,DRF1

    PCBA,2.6G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DRDN

    PCBA,2.6G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,DT9H

    PCBA,2.6G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,DT9G

    PCBA,2.7G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,F0HN

    PCBA,2.7G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,F0HR

    PCBA,2.7G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DYW5

    PCBA,2.7G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,F0HY

    EDP:YES,MIKEY,PPCPUVCCIO:IVB,PPDDR:1V35,LPCPLUS_CONN:YES,LPCPLUS_R:YES,KBD_BL:SANDWICH,CAPS:INT,BTPWR:S4,XDP,XDP_CPU:BPM,GPU:2P,TPAD_5V:LDO_S5

    825-7563

    337S4313

    VREF:PROD

    RAM_4G_HYNIX_1600_S

    341S3597 IC,EEPROM,CACTUS RIDGE (8.1) FSB,D2

    U4900 CRITICAL1 IC,SMC,DEVELOPMENT-FSB,A3,D2341S3308 SMC_PROG:FSB

    1 CRITICALU4900

    341S3595 1 BOOTROM_PROG:FSBCRITICALU6100IC,EFI,ROM,FSB, D2

    341S3309 IC,SMC,PVB,A3,2.2F36,D2 SMC_PROG:PVB

    IVB,S R0MP,PRQ,E1,2.3,45W,4+2,1.2,6M,BGA

    337S4256

    1

    CRITICAL

    946-3819

    CRITICAL1

    1 CRITICAL825-7697 TEXT,LABEL,MLB,D2

    LBL,PART CONFIG,BOARDS,D2

    IC,SDRAM,DDR3-1600,512MX8,78FBGA,HYNIX

    CONFIG_LABEL

    EDGE_BOND

    TEXT_LABEL

    CAN_COVER1,CAN_COVER2

    PCH_INSULATOR

    GPU_INSULATOR

    CAP,TANT,POLY,68UF,20%,16V,50MOHM,D,LF

    CAP,TANT,POLY,68UF,20%,16V,50MOHM,D2E

    U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270

    U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270

    PANTHER POINT,C1,SLJ8C,PRQ,BD82HM77

    IC,SDRAM,DDR3-1600,512MX8,78FBGA,B-DIE,ELPIDA

    725-1614

    128S0264

    IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG

    U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270

    U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270

    INSULATOR,GPU,D2

    INSULATOR,PCH,D2

    825-7841

    333S0625

    1 INSULATOR,SHORT,REAR,MLB,D2

    INSULATOR,TALL,REAR,MLB,D2

    INSULATOR,CPU,D2

    U8400,U8450,U8500,U8550

    U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270

    REAR_INSULATOR

    CRITICAL

    U8400,U8450,U8500,U8550

    REAR_INSULATOR

    CPU_INSULATOR

    30

    30

    C8921,C8922,C8920,C8926,C7554,C7560,C7561,C7513,C7514,C7523,C7524,C7533,C7534,C7570,C7571,C7572,C7040,C7240,C7242,C7280,C7282,C7330,C7331,C7575,C7620,C7621,C8307,C8356,C9820,C9821

    C8921,C8922,C8920,C8926,C7554,C7560,C7561,C7513,C7514,C7523,C7524,C7533,C7534,C7570,C7571,C7572,C7040,C7240,C7242,C7280,C7282,C7330,C7331,C7575,C7620,C7621,C8307,C8356,C9820,C9821

    051-9589

    4.18.0

    5 OF 132

    5 OF 99

  • TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    Apple Inc.

    THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.

    124578

    B

    D

    8 7 6 5 4 3

    C

    B

    A

    NOTICE OF PROPRIETARY PROPERTY:

    PAGE

    12

    D

    A

    C

    PAGE TITLE

    SHEET

    IV ALL RIGHTS RESERVED

    R

    DSIZEDRAWING NUMBER

    REVISION

    BRANCH

    6 3

    THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

    III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT

    TABLE_BOMGROUP_ITEM

    BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    TABLE_BOMGROUP_ITEM

    DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL

    Keeping for PRQElipda DQd

    BOM Variants (continued from CSA 5) Bar Code Labels / EEEE #s (continued from CSA 5)

    SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012

    BOM Variants

    639-3383 PCBA,2.3G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,DY42 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY42,DEVEL_BOM,RAM_2G_ELPIDA_1600

    639-3382 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY41,DEVEL_BOM,RAM_2G_ELPIDA_1600PCBA,2.3G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,DY41

    BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DYJ5,DEVEL_BOM,RAM_4G_ELPIDA_1600639-3445 PCBA,2.3G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,DYJ5

    BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DYJ6,DEVEL_BOM,RAM_4G_ELPIDA_1600639-3446 PCBA,2.3G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,DYJ6

    LABEL,MLB/LIO,MBA [EEEE:DY41]825-7563 1 EEEE:DY41CRITICAL

    [EEEE:DYJ6]LABEL,MLB/LIO,MBA EEEE:DYJ6CRITICAL1825-7563

    LABEL,MLB/LIO,MBA825-7563 CRITICAL[EEEE:DY42]1 EEEE:DY42

    [EEEE:DYJ5]LABEL,MLB/LIO,MBA EEEE:DYJ5CRITICAL825-7563 1

    CRITICAL EEEE:DRF01825-7563 [EEEE:DRF0]LABEL,MLB/LIO,MBA

    1 EEEE:DRDPCRITICAL825-7563 [EEEE:DRDP]LABEL,MLB/LIO,MBA

    1 EEEE:DRDTCRITICAL[EEEE:DRDT]825-7563 LABEL,MLB/LIO,MBA

    CRITICAL1 [EEEE:DRDQ] EEEE:DRDQ825-7563 LABEL,MLB/LIO,MBA

    1 CRITICAL[EEEE:F0J4] EEEE:F0J4825-7563 LABEL,MLB/LIO,MBA

    CRITICAL1 [EEEE:F0JD] EEEE:F0JD825-7563 LABEL,MLB/LIO,MBA

    1 CRITICAL[EEEE:F0J3] EEEE:F0J3825-7563 LABEL,MLB/LIO,MBA

    CRITICAL1 [EEEE:F0JC] EEEE:F0JC825-7563 LABEL,MLB/LIO,MBA

    639-2818 BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRF0,DEVEL_BOM,RAM_2G_ELPIDA_1600PCBA,2.6G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,DRF0

    639-2820 PCBA,2.6G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,DRDP BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDP,DEVEL_BOM,RAM_2G_ELPIDA_1600

    639-2823 BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRDT,DEVEL_BOM,RAM_4G_ELPIDA_1600PCBA,2.6G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,DRDT

    639-2819 BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDQ,DEVEL_BOM,RAM_4G_ELPIDA_1600PCBA,2.6G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,DRDQ

    639-3633 PCBA,2.7G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,F0J3

    639-3632 BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0JD,DEVEL_BOM,RAM_2G_ELPIDA_1600PCBA,2.7G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,F0JD

    BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0J4,DEVEL_BOM,RAM_4G_ELPIDA_1600PCBA,2.7G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,F0J4

    BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0JC,DEVEL_BOM,RAM_4G_ELPIDA_1600PCBA,2.7G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,F0JC

    639-3630

    639-3631

    BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0J3,DEVEL_BOM,RAM_2G_ELPIDA_1600

    051-9589

    4.18.0

    6 OF 132

    6 OF 99

  • TP

    TP

    TP

    TP

    TP

    Apple Inc.

    THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.

    124578

    B

    D

    8 7 6 5 4 3

    C

    B

    A

    NOTICE OF PROPRIETARY PROPERTY:

    PAGE

    12

    D

    A

    C

    PAGE TITLE

    SHEET

    IV ALL RIGHTS RESERVED

    R

    DSIZEDRAWING NUMBER

    REVISION

    BRANCH

    6 3

    THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

    III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT

    PLACEABLE BEAD-PROBES FOR TBT

    2X GND

    J5050 - hall effect

    J4410 - rio flex

    10X GND

    J3502 - ALS camera

    3X P3V3_S3

    4X GND

    FUNC_TEST

    NC NO_TESTsNO_TEST

    CPU NO_TESTsNO_TEST

    NO_TESTICT Test Points

    GPU NO_TESTsNO_TEST

    NO_TESTThunderbolt NO_TESTs

    NO_TEST

    NC NO_TESTs

    NC NO_TESTs

    NO_TEST=TRUE

    FUNC_TEST

    19X GND

    5X P5V_S4

    5X GND3X P5V_S0

    3X P5V_S0

    2X2X

    FUNC_TEST

    2X GND

    4X GND

    4X

    FUNC_TEST

    4X

    3X

    16X GND

    2X GND

    8X

    2X GND

    2X

    POWER RAILS

    8X GND

    FUNC_TEST

    J9000 - eDP

    J6701 - audio flex

    J6802 - L speaker

    J6803 - R speaker

    J6900 - DC PWR

    J3501 - airport J5100 - lpc + spi

    J4400 - rio coax

    J5713 - keyboard

    J5650 - left fan

    Functional Test Points

    J5700 - ipd flex

    2X GND

    J6801 - 3-mic

    PCH ALIASES

    J6950 - battery

    J5660 - right fan

    5X GND

    J5815 - kbd backlight

    BEAD-PROBESM SIGNAL_MODEL=EMPTY

    BEAD-PROBESM SIGNAL_MODEL=EMPTY

    I1596

    I1597

    I1599

    I1600

    I1601

    I1602

    I1603

    I1604

    I1605

    I1606

    I1607

    I1608

    I1609

    I1610

    I1611

    I1612

    I1613

    I1614

    I1615

    I1616

    I1617

    I1618

    I1619

    I1620

    I1621

    I1622

    I1623

    I1624

    I1625

    I1626

    I1627

    I1628

    I1629

    I1630

    I1631

    I1632

    I1633

    I1634

    I1635

    I1636

    I1637

    I1638

    I1639

    I1640

    I1641

    I1642

    I1643

    I1644

    I1645

    I1646

    I1647

    I1648

    I1649

    I1650

    I1651

    I1652

    I1653

    I1654

    I1655

    I1656

    I1657

    I1658

    I1659

    I1660

    I1661

    I1662

    I1663

    I1664

    I1665

    I1666

    I1667

    I1668

    I1669

    I1670

    I1671

    I1672

    I1673

    I1674

    I1675

    I1676

    I1677

    I1678

    I1679

    I1680

    I1681

    I1682

    I1683

    I1684

    I1685

    I1686

    I1687

    I1688

    I1689

    I1690

    I1691

    I1692

    I1693

    I1694

    I1695

    I1696

    I1697

    I1698

    I1699

    I1700

    I1701

    I1702

    I1703

    I1704

    I1705

    I1706

    I1707

    I1708

    I1709

    I1710

    I1711

    I1712

    I1713

    I1714

    I1715

    I1716

    I1717

    I1718

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    SIGNAL_MODEL=EMPTYSM BEAD-PROBE

    SIGNAL_MODEL=EMPTYSM BEAD-PROBE

    SIGNAL_MODEL=EMPTYBEAD-PROBESM

    SYNC_DATE=01/13/2012

    Functional / ICT TestSYNC_MASTER=D2_KEPLER

    TRUE GND

    TRUE GND

    GNDTRUE

    TRUE GND

    TRUE GND

    TRUE GND

    TRUE GND

    GNDTRUE

    TRUE GND

    TRUE GND

    TRUE GND

    TRUE GND

    TRUE GND

    TRUE GND

    TRUE GND

    TRUE GND

    TRUE GND

    TP_LVDS_EG_BKL_PWMLVDS_IG_B_CLK_N

    TP_GPU_MIOA_DETP_GPU_MIOA_D

    TRUEMAKE_BASE=TRUE

    NC_PCIE_CLK100M_PE5NTRUEUSB_EXTB_P

    TRUE SD_PWR_EN

    TRUE USB_EXTB_OC_L

    TRUE WS_KBD21

    TRUE I2C_DPMUX_A_SCL

    PM_SLP_S3_LTRUE

    TRUE WS_KBD4

    TRUE WS_KBD_ONOFF_L

    TRUE PP5V_S4

    DP_TBTSNK0_ML_C_NTRUE

    TRUE WS_KBD12TRUE WS_KBD11

    TRUE ENET_RESET_L

    TRUE USB3_EXTB_TX_C_P

    TRUE USB3_EXTB_RX_N

    TRUE WS_KBD1

    TRUE SMC_LID_R

    TRUE PP5V_S3_ALSCAMERA_F

    TRUE USB_BT_CONN_N

    TRUE PCIE_CLK100M_AP_CONN_N

    TRUE WIFI_EVENT_LTRUE USB_BT_CONN_P

    TRUE WS_KBD14TRUE WS_KBD13

    TRUE HDMI_EG_DATA_C_N

    HDMI_EG_DATA_C_PTRUEPCIE_CLK100M_ENET_NTRUE

    TRUE PCIE_ENET_R2D_C_P

    TRUE PM_SLP_S4_L

    USB_CAMERA_CONN_PTRUE

    USB_CAMERA_CONN_NTRUE

    TRUE SPI_ALT_MISO

    SMC_KBDLED_PRESENT_LTRUE

    PP1V05_S0TRUE

    TRUE PP1V8_S0

    TRUE PP3V3_S0

    TRUE PP3V3_S0GPU

    PP3V3_S5_AVREF_SMCTRUE

    PP5V_S3TRUE

    TRUE CH_HS_GND

    MAKE_BASE=TRUETRUE NC_PCI_C_BE_L

    MAKE_BASE=TRUETRUE NC_HDA_SDIN3

    LED_RETURN_1TRUE

    CON_DMIC_SDA2TRUECON_DMIC_SDA1TRUE

    PP3V3_S3RS4_BT_FTRUE

    MAKE_BASE=TRUETRUE NC_PCIE_5_R2D_CP

    MAKE_BASE=TRUETRUE NC_PCIE_5_R2D_CN

    MAKE_BASE=TRUETRUE NC_PCIE_5_D2RP

    MAKE_BASE=TRUETRUE NC_PCIE_8_R2D_CN

    TRUEMAKE_BASE=TRUE

    NC_PCIE_8_D2RN

    MAKE_BASE=TRUETRUE NC_PCIE_5_D2RN

    NC_LVDS_IG_CTRL_CLKTRUEMAKE_BASE=TRUE

    NC_CRT_IG_VSYNCMAKE_BASE=TRUETRUE

    NC_CRT_IG_DDC_DATATRUEMAKE_BASE=TRUE

    NC_CRT_IG_HSYNCMAKE_BASE=TRUETRUE

    MAKE_BASE=TRUETRUE NC_TP_CPU_RSVDTRUEMAKE_BASE=TRUE

    NC_TP_CPU_RSVD

    MAKE_BASE=TRUETRUE NC_TP_CPU_RSVD

    MAKE_BASE=TRUETRUE NC_TP_CPU_RSVD

    MAKE_BASE=TRUETRUE NC_TP_CPU_RSVD_NCTF

    TRUE NC_PCIE_PE8_R2D_CPMAKE_BASE=TRUE

    TRUE NC_PCIE_PE8_R2D_CNMAKE_BASE=TRUE

    MAKE_BASE=TRUETRUE NC_PCIE_PE8_D2RNTRUE NC_PCIE_PE8_D2RP

    MAKE_BASE=TRUE

    TRUEMAKE_BASE=TRUE

    NC_PCIE_PE7_R2D_CN

    TRUE NC_PCIE_PE7_R2D_CPMAKE_BASE=TRUE

    NC_PCIE_PE6_D2RPTRUEMAKE_BASE=TRUE

    MAKE_BASE=TRUENC_PCIE_PE7_D2RPTRUE

    MAKE_BASE=TRUENC_PCIE_PE7_D2RNTRUE

    TRUE NC_PCIE_PE6_R2D_CNMAKE_BASE=TRUE NC_PCIE_PE6_R2D_CPMAKE_BASE=TRUE

    TRUE

    NC_PCIE_PE5_D2RPTRUEMAKE_BASE=TRUE

    TRUEMAKE_BASE=TRUE

    NC_PCIE_PE5_R2D_CP

    MAKE_BASE=TRUETRUE NC_PCIE_PE5_D2RN

    TRUE PCH_VSS_NCTFPCH_VSS_NCTFTRUE

    PCH_VSS_NCTFTRUEPCH_VSS_NCTFTRUEPCH_VSS_NCTFTRUE

    PCH_VSS_NCTFTRUEPCH_VSS_NCTFTRUEPCH_VSS_NCTFTRUE

    PCH_VSS_NCTFTRUE

    TRUE PCH_VSS_NCTFPCH_VSS_NCTFTRUE

    PCH_VSS_NCTFTRUE

    PCH_VSS_NCTFTRUE

    PCH_VSS_NCTFTRUE

    TRUE NC_HDA_SDIN1MAKE_BASE=TRUE

    MAKE_BASE=TRUENC_PCH_LVDS_VBGTRUE

    NC_LVDS_IG_CTRL_DATATRUEMAKE_BASE=TRUE

    TRUEMAKE_BASE=TRUENC_LPC_DREQ0_L

    TRUEMAKE_BASE=TRUE

    NC_PCIE_CLK100M_PEBNTRUEMAKE_BASE=TRUE

    NC_PCIE_CLK100M_PEBP

    MAKE_BASE=TRUETRUE NC_PCI_AD

    TRUEMAKE_BASE=TRUE

    NC_PCI_GNT3_L

    MAKE_BASE=TRUETRUE NC_PCI_GNT1_L

    NC_PCI_CLK33M_OUT3TRUEMAKE_BASE=TRUE

    NC_PCH_NV_RCOMPMAKE_BASE=TRUETRUE

    NC_NV_DQMAKE_BASE=TRUETRUE

    NC_NV_DQSTRUEMAKE_BASE=TRUE

    NC_NV_ALEMAKE_BASE=TRUETRUE

    NC_NV_CLEMAKE_BASE=TRUETRUE

    NC_NV_WR_RE_LMAKE_BASE=TRUETRUE

    NC_NV_WE_CK_LMAKE_BASE=TRUETRUE

    TRUEMAKE_BASE=TRUE

    NC_PCIE_CLK100M_PE4P

    TRUEMAKE_BASE=TRUE

    NC_PCIE_CLK100M_PE5P

    TRUEMAKE_BASE=TRUE

    NC_PCIE_CLK100M_PE6PTRUEMAKE_BASE=TRUE

    NC_PCIE_CLK100M_PE7N

    TRUEMAKE_BASE=TRUE

    NC_PCIE_CLK100M_PE7P

    MAKE_BASE=TRUETRUE NC_PSOC_P1_3TRUEMAKE_BASE=TRUE

    NC_SATA_B_D2RN

    MAKE_BASE=TRUETRUE NC_SATA_B_D2RPTRUEMAKE_BASE=TRUE

    NC_SATA_B_R2D_CN

    TRUEMAKE_BASE=TRUE

    NC_SATA_B_R2D_CP

    MAKE_BASE=TRUETRUE NC_SATA_D_D2RN

    NC_SATA_D_D2RPMAKE_BASE=TRUETRUE

    MAKE_BASE=TRUETRUE NC_SATA_D_R2D_CNTRUEMAKE_BASE=TRUE

    NC_SATA_D_R2D_CP

    MAKE_BASE=TRUETRUE NC_SATA_E_D2RN

    MAKE_BASE=TRUETRUE NC_SATA_E_D2RP

    MAKE_BASE=TRUETRUE NC_SATA_E_R2D_CN

    MAKE_BASE=TRUETRUE NC_SATA_E_R2D_CP

    MAKE_BASE=TRUETRUE NC_SATA_F_D2RN

    MAKE_BASE=TRUETRUE NC_SATA_F_R2D_CN

    TRUEMAKE_BASE=TRUE

    NC_TBT_PCIE_RESET0_L

    TRUEMAKE_BASE=TRUE

    NC_TBT_PCIE_RESET2_LTRUEMAKE_BASE=TRUE

    NC_TBT_PCIE_RESET1_L

    MAKE_BASE=TRUETRUE NC_TBT_PCIE_RESET3_L

    TRUEMAKE_BASE=TRUE

    NC_SATA_F_D2RP

    MAKE_BASE=TRUETRUE NC_SATA_F_R2D_CP

    MAKE_BASE=TRUENC_SMC_P41TRUE

    MAKE_BASE=TRUETRUE NC_DVPDATA

    MAKE_BASE=TRUETRUE NC_DVPCNTL_MTRUEMAKE_BASE=TRUE

    NC_DVPDATA

    TRUE NC_DVPDATAMAKE_BASE=TRUE

    TRUE PCH_VSS_NCTFMAKE_BASE=TRUETRUE NC_DP_TBTSRC_ML_CP

    TRUE NC_CLINK_DATAMAKE_BASE=TRUE

    TRUE NC_DP_TBTSRC_AUXCH_CNMAKE_BASE=TRUE

    TRUEMAKE_BASE=TRUE

    NC_TBT_XTAL25OUT

    MAKE_BASE=TRUETRUE NC_PCIE_7_R2D_CN

    MAKE_BASE=TRUETRUE NC_PCIE_7_R2D_CP

    TRUE NC_PCIE_6_R2D_CPMAKE_BASE=TRUE

    MAKE_BASE=TRUETRUE NC_PCIE_CLK100M_PE6N

    MAKE_BASE=TRUETRUE NC_PCIE_CLK100M_PE4N

    TRUE NC_HDA_SDIN2MAKE_BASE=TRUE

    NC_PCI_GNT2_LTRUEMAKE_BASE=TRUE

    MAKE_BASE=TRUETRUE NC_PCI_PME_LMAKE_BASE=TRUE

    NC_PCI_RESET_LTRUE

    NC_PCI_PARMAKE_BASE=TRUETRUE

    TRUE NC_NV_RB_LMAKE_BASE=TRUE

    MAKE_BASE=TRUETRUE NC_PCI_GNT0_L

    TRUE TBT_B_D2R_PTRUE TBT_B_D2R_C_N

    TBT_B_D2R_C_PTRUETRUE TBT_A_R2D_N

    TRUE TBT_A_R2D_C_N

    TRUE TBT_A_D2R_N

    DP_TBTSNK1_ML_C_NTRUE

    DP_TBTSNK1_ML_NTRUE

    DP_TBTSNK1_ML_PTRUE

    DP_TBTSNK1_AUXCH_C_PTRUEDP_TBTSNK1_AUXCH_C_NTRUEDP_TBTSNK1_AUXCH_PTRUE

    DP_TBTSNK0_AUXCH_PTRUEDP_TBTSNK0_AUXCH_NTRUE

    DP_TBTSNK0_AUXCH_C_NTRUEDP_TBTSNK0_AUXCH_C_PTRUE

    DP_TBTSNK0_ML_PTRUEDP_TBTSNK0_ML_NTRUE

    TRUE DP_TBTSNK0_ML_C_P

    TRUE TBT_B_R2D_PTRUE TBT_B_R2D_N

    TBT_B_R2D_C_PTRUETRUE TBT_B_R2D_C_N

    DP_TBTSNK1_AUXCH_NTRUE

    TBT_B_D2R_NTRUE

    TRUEMAKE_BASE=TRUE

    NC_CRT_IG_DDC_CLKNC_CRT_IG_RED

    MAKE_BASE=TRUETRUE

    NC_CRT_IG_GREENMAKE_BASE=TRUETRUEMAKE_BASE=TRUE

    NC_CRT_IG_BLUETRUE

    TRUEMAKE_BASE=TRUE

    NC_DP_IG_C_HPD

    NC_DP_IG_C_CTRL_DATATRUEMAKE_BASE=TRUE

    MAKE_BASE=TRUENC_DP_IG_C_CTRL_CLKTRUE

    NC_DP_IG_C_MLPMAKE_BASE=TRUETRUE

    NC_DP_IG_C_MLNTRUEMAKE_BASE=TRUE

    NC_DP_IG_C_AUXPTRUEMAKE_BASE=TRUE NC_DP_IG_C_AUXNTRUEMAKE_BASE=TRUE

    NC_DP_IG_D_HPDTRUEMAKE_BASE=TRUENC_DP_IG_D_CTRL_CLKTRUEMAKE_BASE=TRUE

    NC_DP_IG_D_CTRL_DATATRUEMAKE_BASE=TRUE NC_DP_IG_D_MLPTRUEMAKE_BASE=TRUE

    MAKE_BASE=TRUETRUE NC_DP_IG_D_MLNTRUE NC_DP_IG_D_AUXPMAKE_BASE=TRUE

    TRUE NC_SDVO_TVCLKINNMAKE_BASE=TRUE

    TRUE NC_DP_IG_D_AUXNMAKE_BASE=TRUE

    NC_SDVO_STALLNTRUEMAKE_BASE=TRUE

    TRUE NC_SDVO_TVCLKINPMAKE_BASE=TRUE

    MAKE_BASE=TRUENC_SDVO_INTNTRUE

    NC_SDVO_STALLPTRUEMAKE_BASE=TRUE

    NC_SDVO_INTPTRUEMAKE_BASE=TRUE

    NC_GPU_BUFRST_LMAKE_BASE=TRUETRUE

    NC_GPU_GSTATEMAKE_BASE=TRUETRUE

    NC_GPU_GSTATEMAKE_BASE=TRUETRUE

    MAKE_BASE=TRUETRUE NC_GPU_MIOA_D

    NC_GPU_MIOA_DETRUEMAKE_BASE=TRUE

    NC_LVDS_EG_BKL_PWMTRUEMAKE_BASE=TRUE

    NC_LVDS_IG_B_CLKPTRUEMAKE_BASE=TRUE

    NC_LVDS_IG_B_CLKNMAKE_BASE=TRUETRUE

    TRUE NC_SMC_BS_ALRT_LMAKE_BASE=TRUE

    TRUE NC_LVDS_IG_BKL_PWMMAKE_BASE=TRUE

    MAKE_BASE=TRUETRUE NC_PCIE_8_D2RP

    MAKE_BASE=TRUETRUE NC_PCIE_8_R2D_CP

    TRUE NC_PCIE_PE5_R2D_CNMAKE_BASE=TRUE

    TRUE NC_PCIE_PE6_D2RNMAKE_BASE=TRUE

    TRUE TBT_A_D2R_C_N

    TRUEMAKE_BASE=TRUE

    NC_NV_CE_L

    TRUE TBT_A_R2D_C_P

    DP_TBTSNK1_ML_C_PTRUE

    MAKE_BASE=TRUETRUE NC_PCIE_6_D2RN

    MAKE_BASE=TRUETRUE NC_PCIE_6_D2RP

    MAKE_BASE=TRUETRUE NC_PCIE_6_R2D_CN

    MAKE_BASE=TRUETRUE NC_PCIE_7_D2RN

    MAKE_BASE=TRUETRUE NC_PCIE_7_D2RP

    TRUE TBT_A_R2D_P

    TRUE TBT_A_D2R_C_P

    TRUE TBT_A_D2R_P

    TRUE PCIE_AP_D2R_PI_PTRUE PCIE_AP_R2D_N

    TRUE PCIE_WAKE_LTRUE PCIE_CLK100M_AP_CONN_P

    TRUE PP3V3_WLAN

    SMBUS_SMC_2_S3_SCLTRUESMBUS_SMC_2_S3_SDATRUE

    PCIE_CLK100M_ENET_PTRUE

    TRUE USB3_EXTB_TX_C_N

    PP3V3_S4TRUE

    SDCONN_STATE_CHANGE_RIOTRUE

    TRUE FAN_LT_PWM

    TRUE PP5V_S0TRUE FAN_LT_TACH

    TRUE KBDLED_ANODE2TRUE KBDLED_ANODE1

    LPC_ADTRUETRUE LPC_AD

    TRUE LPC_ADTRUE LPC_CLK33M_LPCPLUS

    TRUE SMC_TDI

    TRUE SMC_TMSTRUE SMC_TDO

    TRUE SMC_TX_L

    TRUE SPI_ALT_CLKTRUE SPIROM_USE_MLB

    TRUE SPI_ALT_CS_L

    TRUE SPI_ALT_MOSI

    TRUE PP3V3_S4

    TRUE WS_CONTROL_KBDTRUE PP3V42_G3H

    TRUE WS_KBD10

    TRUE WS_KBD15_CAPTRUE WS_KBD16_NUM

    TRUE WS_KBD18TRUE WS_KBD17

    TRUE WS_KBD19TRUE WS_KBD2TRUE WS_KBD20

    TRUE WS_KBD22TRUE WS_KBD23TRUE WS_KBD3

    TRUE WS_KBD5

    WS_KBD7TRUETRUE WS_KBD8

    TRUE WS_LEFT_OPTION_KBD

    TRUE WS_LEFT_SHIFT_KBD

    AUD_HP_PORT_RTRUETRUE AUD_HP_PORT_L

    TRUE AUD_SPDIF_OUT_JACK

    TRUE AUD_TYPEDETAUD_TIPDET_INVTRUE

    TRUE CH_HS_MICTRUE PP3V3_S0TRUE US_HS_GND

    TRUE CON_DMIC_PWRTRUE CON_DMIC_CLK

    TRUE SPKRCONN_L_ID

    TRUE SPKRCONN_L_OUT_PTRUE SPKRCONN_L_OUT_N

    TRUE SPKRCONN_SL_OUT_PTRUE SPKRCONN_SL_OUT_N

    TRUE SPKRCONN_R_OUT_NTRUE SPKRCONN_R_ID

    TRUE SPKRCONN_R_OUT_P

    TRUE SPKRCONN_SR_OUT_NTRUE SPKRCONN_SR_OUT_P

    TRUE DP_INT_AUX_PTRUE DP_INT_AUX_N

    TRUE DP_INT_ML_N

    TRUE DP_INT_ML_NTRUE DP_INT_ML_N

    LCD_HPD_CONNTRUE

    TRUE LED_RETURN_2TRUE LED_RETURN_3

    TRUE LED_RETURN_5TRUE LED_RETURN_4

    TRUE LED_RETURN_6

    TRUE PPVOUT_S0_LCDBKLTTRUE PP5VR3V3_SW_LCD

    TRUE SYS_DETECT_L

    TRUE SMC_TCK

    TRUE PCIE_AP_R2D_P

    TRUE SMC_RX_LTRUE SMC_ROMBOOT

    TRUE LPC_SERIRQTRUE LPC_PWRDWN_L

    TRUE AP_CLKREQ_Q_L

    TRUE LPC_AD

    TRUE LPCPLUS_RESET_LTRUE LPCPLUS_GPIO

    PP0V75_S0_DDRVTTTRUEPM_SLP_S3_LTRUE

    TRUE PP3V3_S5TRUE PP3V3_S3

    PP5V_S0TRUE

    PP3V42_G3HTRUE

    PPBUS_G3HTRUE

    PP5V_S5TRUE

    TRUE PPVCORE_GPU

    PPDCIN_G3HTRUE

    PPVCORE_S0_CPUTRUEPPVTTDDR_S3TRUE

    TRUE SMBUS_SMC_5_G3_SDATRUE SMBUS_SMC_5_G3_SCLTRUE PPVBAT_G3H_CONN

    TRUE LCD_FSS

    TRUE DP_INT_ML_PTRUE DP_INT_ML_PTRUE DP_INT_ML_PTRUE DP_INT_ML_N

    TRUEMAKE_BASE=TRUE

    NC_TP_CPU_RSVD

    TRUE WS_KBD6

    TRUE TP_SMC_MD1TP_SMC_TRST_LTRUE

    TRUE US_HS_MIC

    TRUE DP_INT_ML_P

    TRUE LPC_FRAME_L

    TRUE PCIE_AP_D2R_PI_NTRUE AP_RESET_CONN_L

    TRUE PP1V5_S0_RIOPP3V3_S3TRUE

    TRUE GND

    PP3V42_G3HTRUE

    TRUE HDMI_HPD_L

    TRUE USB_EXTB_N

    TRUE ENET_CLKREQ_L

    TRUE HDMI_EG_DDC_CLKTRUE HDMI_EG_DDC_DATA

    I2C_DPMUX_A_SDATRUE

    TRUE PCIE_ENET_D2R_PTRUE PCIE_ENET_R2D_C_N

    TRUE USB3_EXTB_RX_P

    TRUE PCIE_ENET_D2R_N

    HDMI_EG_DATA_C_NTRUEHDMI_EG_DATA_C_NTRUE

    TRUE HDMI_EG_CLK_C_NHDMI_EG_CLK_C_PTRUE

    HDMI_EG_DATA_C_PTRUEHDMI_EG_DATA_C_PTRUE

    TDM_ONEWIRE_MPMTRUEPP18V5_DCIN_FUSETRUEADAPTER_SENSETRUE

    SMC_RESET_LTRUETRUE PP5V_S0TRUE PM_CLKRUN_L

    TRUE Z2_DEBUG3Z2_CS_LTRUE

    TRUE Z2_MISOTRUE Z2_MOSI

    TRUE Z2_SCLKTRUE Z2_HOST_INTNTRUE Z2_CLKINTRUE Z2_KEY_ACT_L

    TRUE PP3V3_S4TRUE PICKB_L

    TRUE Z2_RESETTRUE PSOC_F_CS_L

    TRUE PP5V_S5

    TRUE PSOC_MOSITRUE PSOC_MISO

    TRUE PSOC_SCLK

    TRUE SMBUS_SMC_2_S3_SCLTRUE SMBUS_SMC_2_S3_SDA

    TRUE WS_KBD9

    TRUE NC_CLINK_RESET_LMAKE_BASE=TRUE

    TRUE NC_CLINK_CLKMAKE_BASE=TRUE

    TRUE NC_DP_TBTSRC_ML_CNMAKE_BASE=TRUETRUE NC_DP_TBTSRC_AUXCH_CPMAKE_BASE=TRUE

    TRUE FAN_RT_PWM

    TRUE FAN_RT_TACHTRUE PP5V_S0

    TBT_A_R2D_C_P

    TBT_B_R2D_C_PTBT_B_R2D_C_P

    TP_PCI_C_BE_L

    TP_NV_DQS

    TP_PCIE_CLK100M_PEBN

    TP_CLINK_DATATP_CLINK_CLK

    TP_LPC_DREQ0_L

    TP_CRT_IG_DDC_CLK

    TP_CPU_RSVDTP_CPU_RSVDTP_CPU_RSVD

    TP_CRT_IG_GREENTP_CRT_IG_RED

    TP_PCIE_5_R2D_CP

    TP_PCIE_5_D2RP

    TP_PCI_GNT1_LTP_PCI_GNT0_L

    TP_NV_DQTP_PCH_NV_RCOMP

    TP_PCI_PME_L

    LVDS_IG_BKL_PWM

    SMC_BS_ALRT_L

    LVDS_IG_B_CLK_P

    TP_GPU_GSTATETP_GPU_GSTATE

    TP_GPU_BUFRST_L

    TP_SDVO_INTP

    TP_SDVO_STALLP

    TP_SDVO_INTN

    TP_SDVO_TVCLKINP

    TP_SDVO_STALLN

    TP_DP_IG_D_AUXN

    TP_SDVO_TVCLKINN

    TP_DP_IG_D_AUXPTP_DP_IG_D_MLNTP_DP_IG_D_MLPTP_DP_IG_D_CTRL_DATATP_DP_IG_D_CTRL_CLKTP_DP_IG_D_HPD

    TP_DP_IG_C_AUXNTP_DP_IG_C_AUXPTP_DP_IG_C_MLNTP_DP_IG_C_MLP

    TP_DP_IG_C_CTRL_CLKTP_DP_IG_C_CTRL_DATA

    TP_PCI_AD

    TP_PCIE_CLK100M_PE5P

    TP_PSOC_P1_3

    TP_PCIE_CLK100M_PE6P

    TP_PCIE_CLK100M_PE7P

    TP_SATA_B_R2D_CN

    TP_PCI_GNT2_L

    TP_NV_CE_L

    TP_PCI_PARTP_PCI_RESET_L

    TP_PCI_CLK33M_OUT3

    TP_HDA_SDIN2

    TP_SATA_B_D2RN

    TP_PCIE_6_D2RNTP_PCIE_6_D2RP

    TP_TBT_XTAL25OUTTP_TBT_PCIE_RESET0_LTP_TBT_PCIE_RESET1_L

    TP_TBT_PCIE_RESET3_L

    TP_DP_TBTSRC_ML_CN

    TP_DP_TBTSRC_AUXCH_CN

    TP_DP_TBTSRC_ML_CP

    TP_SATA_E_D2RP

    TP_TBT_PCIE_RESET2_L

    TP_CLINK_RESET_L

    TP_DVPCNTL_MTP_DVPCNTL

    TP_DVPDATA

    TP_SMC_P41TP_SATA_F_R2D_CPTP_SATA_F_R2D_CNTP_SATA_F_D2RPTP_SATA_F_D2RNTP_SATA_E_R2D_CPTP_SATA_E_R2D_CN

    TP_SATA_E_D2RNTP_SATA_D_R2D_CPTP_SATA_D_R2D_CNTP_SATA_D_D2RPTP_SATA_D_D2RNTP_SATA_B_R2D_CP

    TP_SATA_B_D2RP

    TP_PCIE_CLK100M_PE7N

    TP_PCIE_CLK100M_PE6N

    TP_PCIE_CLK100M_PE5NTP_PCIE_CLK100M_PE4PTP_PCIE_CLK100M_PE4NTP_NV_WE_CK_L

    TP_PCI_GNT3_L

    TP_CRT_IG_BLUE

    TP_CRT_IG_VSYNCTP_LVDS_IG_CTRL_CLK

    TP_CRT_IG_HSYNC

    TP_LVDS_IG_CTRL_DATA

    TP_HDA_SDIN1

    TP_HDA_SDIN3

    TP_PCIE_CLK100M_PEBP

    TP_PCIE_PE5_D2RN

    TP_PCIE_PE5_R2D_CP

    TP_PCIE_PE6_D2RN

    TP_PCIE_PE5_D2RPTP_PCIE_PE5_R2D_CN

    TP_PCIE_PE6_R2D_CPTP_PCIE_PE6_R2D_CN

    TP_PCIE_PE7_D2RNTP_PCIE_PE7_D2RP

    TP_PCIE_PE6_D2RP

    TP_PCIE_PE7_R2D_CN

    TP_PCIE_PE8_D2RPTP_PCIE_PE8_D2RN

    TP_PCIE_PE8_R2D_CNTP_PCIE_PE8_R2D_CP

    TP_CPU_RSVDTP_CPU_RSVDTP_CPU_RSVD

    TP_CRT_IG_DDC_DATA

    TP_PCIE_8_R2D_CPTP_PCIE_8_R2D_CNTP_PCIE_8_D2RPTP_PCIE_8_D2RN

    TP_PCIE_7_R2D_CPTP_PCIE_7_R2D_CN

    TP_PCIE_7_D2RNTP_PCIE_7_D2RP

    TP_PCIE_6_R2D_CPTP_PCIE_6_R2D_CN

    TP_PCIE_5_R2D_CN

    TP_PCIE_5_D2RN

    TP_PCH_LVDS_VBG

    TP_CPU_RSVD_NCTF

    TP_NV_WR_RE_L

    TP_NV_CLETP_NV_ALE

    TP_DP_TBTSRC_AUXCH_CP

    TP_PCIE_PE7_R2D_CP

    TP_DVPCNTL

    TP_NV_RB_L

    TBT_A_D2R_PTBT_A_D2R_N

    TRUEMAKE_BASE=TRUE

    NC_TP_CPU_RSVD

    TP_DP_IG_C_HPD

    TP_HDMI_CEC TRUEMAKE_BASE=TRUE

    NC_HDMI_CEC

    TRUE NC_ISNS_P1V5R1V35_CPUDDRNTRUE NC_ISNS_LCDBKLTP

    TRUE NC_ISNS_LCD_PANELP

    TRUE NC_ISNS_LCD_PANELN

    TRUE NC_ISNS_AIRPORTNTRUE NC_ISNS_AIRPORTP

    TRUE NC_ISNS_P1V5R1V35_CPUDDRP

    TRUE NC_ISNS_LCDBKLTN

    TRUE NC_USB_HUB_OCS3

    TRUE NC_SMC_XOSC1TRUE NC_SMC_ODD_DETECT

    TRUE NC_SMC_HIB_LNC_SMBUS_SMC_4_ASF_SDATRUE

    NC_SMC_T25_ISENSETRUENC_SMC_T25_EN_LTRUE

    NC_SMBUS_SMC_4_ASF_SCLTRUE

    TRUE NC_USB_HUB_OCS4

    NC_SMC_FAN_2_CTLTRUE

    NC_SMC_FAN_2_TACHTRUE

    TRUE NC_USB_HUB_OCS2TRUE NC_USB_HUB_PRTPWR4

    TRUE NC_SMC_SYS_LED

    TRUE NC_USB_HUB_PRTPWR2

    TRUE NC_USB_HUB_PRTPWR3

    TRUE NC_FW2_TPANTRUE NC_FW2_TPAP

    TRUE NC_FW0_TPBP

    TRUE NC_ESTARLDO_ENTRUE NC_FW0_TPAPTRUE NC_FW0_TPBN

    TRUE NC_SMC_FAN_3_CTLTRUE NC_SMC_FAN_3_TACH

    TRUE NC_FW2_TPBNNC_FW2_TPBPTRUE

    TRUE NC_FW2_TPBIAS

    TRUE NC_ALS_GAIN

    BP07321

    BP07311

    BP07351

    BP07331

    BP07341

    051-9589

    4.18.0

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    7 18 27 38 41 70

    8 96

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    8

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    26 38 91

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  • Apple Inc.

    THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.

    124578

    B

    D

    8 7 6 5 4 3

    C

    B

    A

    NOTICE OF PROPRIETARY PROPERTY:

    PAGE

    12

    D

    A

    C

    PAGE TITLE

    SHEET

    IV ALL RIGHTS RESERVED

    R

    DSIZEDRAWING NUMBER

    REVISION

    BRANCH

    6 3

    THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

    III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT

    5V Rails

    For PCH RTC Power

    3.3V Rails

    G3H Rails1.8V/1.5V/1.2V/1.05V Rails

    Chipset "VCore" Rails

    TBT RAILS

    "GPU" Rails4A max supply

    Backlight Rails

    Defined here since TBT page does not know PBUS voltage

    I1679

    Power AliasesSYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012

    =PP3V42_G3H_TDM=PP3V42_G3H_AUDIO

    MIN_NECK_WIDTH=0.1 MM

    PP5V_S5VOLTAGE=5VMIN_LINE_WIDTH=0.5 MMMAKE_BASE=TRUE

    =PP5V_S5_TPAD=PP5V_S5_P5VSUSFET

    =PP5V_S4_AUDIO=PP5V_S4_TPAD=PP5V_S4_ISNS

    =PP5V_S4_RIOMAKE_BASE=TRUEVOLTAGE=5VMIN_LINE_WIDTH=0.5 mm

    PP5V_S4MIN_NECK_WIDTH=0.2 mm

    =PP5V_SUS_PCH

    =PPVRTC_G3_OUT

    MIN_LINE_WIDTH=0.3 MMPP3V42_G3H

    VOLTAGE=3.42VMIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

    PP5V_S3VOLTAGE=5VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 mm

    MIN_LINE_WIDTH=0.5 mm

    MIN_NECK_WIDTH=0.25 MM

    PPDCIN_G3H_ISOLVOLTAGE=18.5VMIN_LINE_WIDTH=0.6 MMMAKE_BASE=TRUE

    MAKE_BASE=TRUEMIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MM VOLTAGE=18.5VPPDCIN_G3H

    MAKE_BASE=TRUEMIN_LINE_WIDTH=0.6 mm

    PPVIN_S5_HS_OTHER_ISNSVOLTAGE=12.8V

    MIN_NECK_WIDTH=0.25 mm

    PP3V3_S4MIN_LINE_WIDTH=0.6 MM

    MAKE_BASE=TRUEVOLTAGE=3.3V

    MIN_NECK_WIDTH=0.1 MM

    VOLTAGE=12.8VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.25 mm

    PPVIN_S5_HS_GPU_ISNSMIN_LINE_WIDTH=0.6 mm

    MAKE_BASE=TRUEVOLTAGE=12.8V

    MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm

    PPVIN_S5_HS_COMPUTING_ISNS

    MAKE_BASE=TRUEVOLTAGE=12.8VMIN_LINE_WIDTH=0.6 mm

    MIN_NECK_WIDTH=0.25 mm

    PPBUS_G3H

    MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM

    MAKE_BASE=TRUEVOLTAGE=1.05V

    PP1V0_S0GPU_ISNS

    MAKE_BASE=TRUE

    PP1V5R1V35_S0GPU

    VOLTAGE=1.5VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM

    MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMPPVCORE_GPU

    MAKE_BASE=TRUEVOLTAGE=1.0V

    MIN_NECK_WIDTH=0.17 mm

    PP1V5R1V35_S3MIN_LINE_WIDTH=0.2 mm

    VOLTAGE=1.5VMAKE_BASE=TRUE

    MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

    PP15V_TBTVOLTAGE=15VMIN_LINE_WIDTH=0.4 MM

    PPVCORE_S0_AXGMIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

    MAKE_BASE=TRUEMIN_LINE_WIDTH=0.6 MM

    PPVRTC_G3HVOLTAGE=3.42VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

    MIN_LINE_WIDTH=0.3 MM

    MIN_NECK_WIDTH=0.17 mm

    MAKE_BASE=TRUEVOLTAGE=1.5V

    PP1V5R1V35_MEMMIN_LINE_WIDTH=0.2 mm

    MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

    PP1V8_S0_CPU_VCCPLL_RVOLTAGE=1.8VMIN_LINE_WIDTH=0.5 MM

    PP1V5_S3_CPU_VCCDQMIN_LINE_WIDTH=0.6 MM

    VOLTAGE=1.5VMAKE_BASE=TRUE

    MIN_NECK_WIDTH=0.2 MM

    PP1V05_S0_CPU_VCCPQEVOLTAGE=1.05VMIN_LINE_WIDTH=0.6 MMMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

    MAKE_BASE=TRUE

    PPVCCSA_S0_REGMIN_LINE_WIDTH=0.6 MM VOLTAGE=0.9VMIN_NECK_WIDTH=0.2 MM

    MIN_NECK_WIDTH=0.2 MM

    MAKE_BASE=TRUEVOLTAGE=1.5V

    MIN_LINE_WIDTH=0.6 MMPP1V5_S3RS0_CPUDDR

    MIN_NECK_WIDTH=0.25 MM

    PPVCORE_S0_CPUVOLTAGE=1.25VMAKE_BASE=TRUEMIN_LINE_WIDTH=0.6 MM

    MIN_NECK_WIDTH=0.075 mmMIN_LINE_WIDTH=0.5 MMPP3V3_S0

    VOLTAGE=3.3VMAKE_BASE=TRUE

    PP1V05_S0_P1V05TBTFETMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

    VOLTAGE=1.05V

    VOLTAGE=12.8VPPVIN_SW_TBTBST

    MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUEMIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05VPP1V05_TBTLC

    VOLTAGE=3.3VPP3V3_TBTLC

    MAKE_BASE=TRUEMIN_NECK_WIDTH=0.15 MMMIN_LINE_WIDTH=0.4 MM

    MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP1V05_TBTCIO

    VOLTAGE=1.05VMAKE_BASE=TRUE

    VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMPP3V3_S5

    MAKE_BASE=TRUE

    PP3V3_S0GPU_MISC

    MAKE_BASE=TRUEVOLTAGE=3.3VMIN_NECK_WIDTH=0.10MMMIN_LINE_WIDTH=0.3 MM

    MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMPP1V05_S0

    VOLTAGE=1.05VMAKE_BASE=TRUE

    PP1V05_PCHVCCIO_S0MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05VMAKE_BASE=TRUE

    MAKE_BASE=TRUE

    TP_GPU_PGOOD2

    PP1V5_S0MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.5VMAKE_BASE=TRUE

    MIN_NECK_WIDTH=0.17 mmMIN_LINE_WIDTH=2 mmPP0V75_S0_DDRVTT

    MAKE_BASE=TRUEVOLTAGE=0.75V

    MAKE_BASE=TRUEVOLTAGE=0.75VMIN_NECK_WIDTH=0.2 MM

    PPVTTDDR_S3MIN_LINE_WIDTH=0.3 MM

    MAKE_BASE=TRUE

    MIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05V

    MIN_LINE_WIDTH=0.4 MMPP1V05_SUS

    MIN_LINE_WIDTH=0.6 MMPP1V5_S0_RIO

    MIN_NECK_WIDTH=0.2 MMVOLTAGE=1.5VMAKE_BASE=TRUE

    MAKE_BASE=TRUEVOLTAGE=1.5V

    MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM

    PP1V8_S0

    MAKE_BASE=TRUE

    PP3V3_S3

    MIN_NECK_WIDTH=0.20MMVOLTAGE=3.3VMIN_LINE_WIDTH=0.50MM

    MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP5V_S0

    MAKE_BASE=TRUEVOLTAGE=5V

    VOLTAGE=5VMAKE_BASE=TRUE

    PP5V_SUS

    MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM

    MIN_LINE_WIDTH=0.5 MMPPBUS_SW_BKL

    MIN_NECK_WIDTH=0.25 MMMAKE_BASE=TRUEVOLTAGE=12.6V

    NC_SMC_T25_EN_LMAKE_BASE=TRUE

    VOLTAGE=3.3V

    MAKE_BASE=TRUEMIN_LINE_WIDTH=0.6 MM

    PP3V3_SUS

    MIN_NECK_WIDTH=0.2 MM

    VOLTAGE=3.3VMAKE_BASE=TRUE

    MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.10MM

    PP3V3_S0GPU=PP3V3_S0GPU_FET

    =PP3V3_S0GPU_MISC_FET

    =PP3V3_S3_DPMUX_UC

    =PP3V3_SUS_PCH_VCCSUS_GPIO

    =PP3V3_SUS_PCH_GPIO=PP3V3_SUS_PCH_VCCSUS_USB

    =PP3V3_SUS_SMC

    =PP3V3_SUS_PCH_VCCSUS

    =PP3V3_SUS_FET

    =PP3V3_S4_RIO

    =PP3V3_SUS_ROM

    SMC_T25_EN_L

    =PPBUS_SW_BKL

    =PP5V_S4_REG

    =PP5V_S4_P5VS3FET=PP5V_S0_LCD=PP5V_S3_LTUSB

    =PP5V_S3_FET

    =PP5V_S3_ISNS=PP5V_S3_ALSCAMERA

    =PP5V_S3_DEBUG_ADC_AVDD

    =PP5V_S3_DDRREG

    =PP5V_S3_DEBUG_ADC_DVDD

    =PP5V_S3_MEMRESET

    =PP5V_S0_AUDIO_XW

    =PP5V_S0_CPUIMVP=PP5V_S0_CPUVCCIOS0=PP5V_S0_FAN_LT

    =PP5V_S0GPU_P1V0P1V35_GPU=PP5V_S0_P1V5_LDO

    =PPVIN_S0_CPUAXG

    =PP3V3_S3_SMBUS_SMC_2_S3

    =PP3V3_S5_XDP

    =PP3V3_S5_PCH_GPIO

    =PP1V8_S0_P1V5_LDO=PPVDDIO_S0_SBCLK

    =PP5V_S0_FAN_RT

    =PP5V_S0_BKL

    =PP5V_S0_VCCSAS0

    =PP0V75_S0_MEM_VTT_B=PPVTT_S0_VTTCLAMP

    =PP1V5_S0_RIO

    =PPVTT_S0_DDR_LDO

    =PP0V75_S0_MEM_VTT_A

    =PP1V5_S3RS0_VMON

    =PPVIN_S3_MEM_ISNS_R=PPVIN_S0_DDRREG_LDO

    =PP1V8_S0_GPUFET=PP1V8_S0_PCH_VCCTX_LVDS

    =PP1V8_S0_PCH_VCC_DFTERM

    =PP3V3_S4_DPBPWRSW

    =PP1V8R1V5_S0_PCH_VCCVRM=PP1V8_S0_AUDIO

    =PP3V3_SUS_P1V05SUSLDO

    =PPDCIN_S5_VSENSE

    =PP18V5_DCIN_ISOL

    =P1V8GPU_ENTP_P1V8GPU_EN

    =PPDDR_S3_MEMVREF

    =PP1V5_S0_AUDIO=PP3V3R1V5_S0_PCH_VCCSUSHDA

    =PP1V8_GPU_FET

    =PP1V05_S0_RMC=PP1V05_S0_VMON=PPVCCIO_S0_SMC=PPVCCIO_S0_CPUIMVP

    =PP1V05_S0_CPU_VCCIO

    =PP3V3_GPU_MISC_P3V3GPUMISCFET

    =PP3V3_GPU_MISC

    =PP3V3_S0_GFX3V3BIAS=PP3V3_GPU_VDD33

    =PP3V3_GPU_IFPX_PLLVDD

    =PP1V8_S0_CPU_VCCPLL

    =PP3V3_GPU_P3V3GPUFET

    =PP3V3_S4_TBTBPWRSW=PP3V3_S4_TBTAPWRSW

    =PP3V3_S5_VMON

    =PP3V3_S5_SYSCLK=PP3V3_S5_SMCBATLOW=PP3V3_S5_PWRCTL

    =PP3V3_S5_PCH_VCCDSW

    =PP3V3_S5_PCHPWRGD

    =PP3V3_S5_PCH=PP3V3_S5_P3V3SUSFET

    =PP3V3_S5_P1V2P1V8=PP3V3_S5_P1V5S0

    =PP3V3_S5_CPU_VCCDDR=PP3V3_S4_P3V3S4FET

    =PP3V3_S3_P3V3S3FET=PP3V3_S4_DPAPWRSW

    =PP3V3_S0_P3V3S0FET

    =PP3V3_S3_SDBUF=PP3V3_S3_SMS=PP3V3_S3_GYRO=PP3V3_S3_WLAN=PP3V3_S3_VREFMRGN=PP3V3_S3_USB_RESET=PP3V3_S3_USB_HUB

    =PP3V3_S3_TPAD=PP3V3_S3_USBMUX

    =PP3V3_S3_SMBUS_SMC_3

    =PP3V3_S3_RIO=PP3V3_S3_PCH_GPIO=PP3V3_S3_MEMRESET=PP3V3_S3_ISNS

    =PP3V3_S3_BT

    =PP3V3_S3_FET

    =PP3V3_S5_REG

    =PPHV_SW_TBTBPWRSW

    =PP1V05_TBTLC_FET

    =PP3V3_TBTLC_RTR

    =PP3V3_TBT_PCH_GPIO

    =PP1V05_TBTLC_RTR

    =PP3V3_S0_TBTPWRCTL=PP3V3_S0_TPAD=PP3V3_S0_VMON

    =PP3V3_S0_XDP

    =PP3V3_S0_SPKRTHMSNS

    =PP1V05_S0_PCH_VCC_CORE

    =PP1V05_S0_PCH_VCCIO_PLLUSB

    =PP1V05_S0_P1V05TBTFET

    =PP1V05_TBTCIO_RTR

    =PP1V05_S0_PCH_VCCIO_PLLFDI=PP1V05_S0_PCH_VCC_DMI

    =PP3V3_S4_TPAD

    =PP3V3_S0_X29THMSNS

    =PP3V3_TBTLC_FET

    =PP3V3_S0_TBTI2C=PP3V3_S0_SYSCLK=PP3V3_S0_SSD=PP3V3_S0_SMBUS_SMC_1_S0

    =PP3V3_S0_SATAMUX=PP3V3_S0_RSTBUF=PP3V3_S0_PWRCTL=PP3V3_S0_PCH_VCCADAC

    =PP3V3_S0_PCH_VCC3_3_PCI=PP3V3_S0_PCH_VCC3_3_SATA

    =PP3V3_S0_PCH_VCC3_3_HVCMOS=PP3V3_S0_PCH_VCC3_3_GPIO=PP3V3_S0_PCH_VCC3_3_CLK=PP3V3_S0_PCH_GPIO=PP3V3_S0_PCH=PP3V3_S0_P3V3TBTFET=PP3V3_S0_P1V8GPUFET

    =PP3V3_S0_ISNS=PP3V3_S0_LCD

    =PP3V3_S0_IMVPISNS=PP3V3_S0_HS_ISNS=PP3V3_S0_GPUTHMSNS

    =PP3V3_S0_FAN_LT=PP3V3_S0_FAN_RT

    =PP3V3_S0_DPMUX_UC=PP3V3_S0_DPMUXI2C

    =PP3V3_S0_CPU_VCCIO_SEL=PP3V3_S0_DPMUX

    =PP3V3_S0_CPUTHMSNS=PP3V3_S0_BKL_VDDIO=PP3V3_S0_AUDIO_DIG=PP3V3_S0_AUDIO

    =LVDS_VCCA

    =PPVCORE_S0_CPU_REG

    =PPVCORE_GPU_REG

    =PP1V05_S0_CPU_VCCPQE

    =PP1V05_S0_PCH_VCCSSC=PP1V05_S0_PCH_V_PROC_IO

    =PP1V05_S0_PCH

    =PP1V05_S0_PCH_VCCIO_PLLPCIE

    =PPVCCIO_S0_XDP

    =PPVCCSA_S0_REG=PP1V05_S0_PCH_VCCDMI_FDI

    =PP1V5_S3_CPU_VCCDDR

    =PP1V5R1V35_S3_MEM_B=PP1V5R1V35_S3_MEM_A

    =PPVRTC_G3_PCH

    =PPVIN_S5_SMCVREF=PP3V42_G3H_TPAD

    =PP1V05_S0_PCH_VCCIO

    =PP1V05_S0_PCH_VCCIO_CLK

    =PP1V05_S0_PCH_VCCADPLL

    =PP1V05_S0_PCH_VCCIO_PCIE

    =PP3V3_S5_SMC

    =PPVBAT_G3_SYSCLK

    =PP3V3_S4_TBT_R

    =PP3V3_S4_FET

    =PP5V_S0_FET

    =PP5V_S0_PCHVCCIOS0=PP5V_S0_PCH

    =PP3V42_G3H_PWRCTL

    =PP3V3_SUS_CNTRL=PP3V3_SUS_PCH_VCC_SPI

    =PP5V_S0_RMC

    =PP5V_S0_VMON

    =PPVIN_S3_P1V5S3RS0_FET

    =PP1V05_SUS_LDO

    =PP1V8_S0_REG

    =PP1V05_GPU_IFPCD_IOVDD=PP1V05_SUS_PCH_JTAG

    =PPVCCSA_S0_CPU

    =PPBUS_G3H

    =PP5V_S5_LDO

    =PPVCORE_S0_CPU_VCCAXG

    =PP1V05_S0_PCH_VCCIO_SATA

    =PP1V05_S0_PCH_VCCIO_USB

    =PP1V05_S0_PCH_VCCASW=PP1V05_S0_PCH_VCCIO_CLK=PP1V05_S0_PCH_VCCDIFFCLK

    =PP1V05_S0_P1V05TBTFET_R

    =PP1V05_GPU_PEX_IOVDD

    =PP1V5_S3_CPU_VCCDQ

    =PPVCORE_S0_AXG_REG

    =PPVCORE_S0_CPU

    =PP1V05_TBTCIO_FET

    =PP3V3_S0_DDR3THMSNS

    =PPHV_SW_TBTAPWRSW

    =PP15V_TBT_REG

    =PP1V5_S3_MEMRESET

    =PP1V35_GPU_S0_FB

    =PP1V0_GPU_DPLL=PP1V0_GPU_DP_AB

    =PPVCORE_S0_GFX_REG

    =PPVCORE_GPU

    =PP1V05_GPU_PEX_PLLVDD

    =PP1V05_GPU_IFPEF_IOVDD

    =PP1V0_GPU_DP_CD

    =PP1V5R1V35_GPU_REG

    =PP1V05_S0GPU_REG

    =PP1V35_GPU_FBVDDQ=PP3V42_G3H_SMBUS_SMC_5=PP3V42_G3H_SMCUSBMUX

    =PP3V42_S3_HALL

    =PP3V42_G3H_REG

    =PPBUS_S0_LCDBKLT=PPVIN_S5_HS_OTHER_ISNS_R

    =PPVIN_S5_HS_GPU_ISNS_R=PPVIN_S5_HS_COMPUTING_ISNS_R

    =PPBUS_S0_VSENSE=PPVIN_SW_TBTBST

    =PPBUS_G3H_T25_R

    =PPVIN_S0_CPUIMVP=PPVIN_S3_DDRREG

    =PPVIN_S5_HS_COMPUTING_ISNS

    =PPVIN_S0_CPUVCCIOS0

    =PPVIN_S0_VCCSAS0=PPVIN_S0_PCHVCCIOS0

    =PPVIN_S0_GFXIMVP=PPVIN_S0GPU_P1V5P1V0

    =PPVIN_S5_P5VP3V3

    =PPVIN_S5_HS_OTHER_ISNS

    =PPDCIN_S5_CHGR

    =PP18V5_DCIN_CONN

    =PP3V3_S5_LPCPLUS

    =PP5V_S0_LPCPLUS=PP5V_S0_KBDLED=PP5V_S0_GFXIMVP

    =PP3V3_S4_SMC=PP3V3_S4_BT

    =PPVIN_S5_HS_GPU_ISNS

    =PP3V42_G3H_CHGR

    =PPVDDIO_TBT_CLK

    =PP3V3_S0_SMBUS_PCH=PP3V3_S0_SB_PM

    =PP3V3_S0_SMBUS_SMC_0_S0

    =PPPCHVCCIO_S0_REG

    =PPCPUVCCIO_S0_REG

    =PPVTT_S3_DDR_BUF

    =PP1V5_S0_RIO_LDO

    =PP1V5_S0_REG

    =PP1V5_S3RS0_FET_ISNS

    =PPVIN_S3_MEM_ISNS

    =PP1V8_S0_CPU_VCCPLL_R

    =PPDDR_S3_REG

    PPBUS_S0_LCDBKLT_PWR

    =PP5V_SUS_FET

    =PPDCIN_S5_CHGR_ISOL

    =PP5V_S5_P1V5S3RS0FET

    =PP5V_S4_P5VS0FET

    =PP5V_S3_DEBUG_ISNS

    =PP3V3_S0_FET

    =PP3V42_G3H_ONEWIREPROT

    GNDMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.085MMVOLTAGE=0VMAKE_BASE=TRUE

    051-9589

    4.18.0

    8 OF 132

    8 OF 99

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    49

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    7

    96

    7

    7 96

    37

    37

    7 96

    7

    7

    7

    7

    7

    7

    7

    7

    7 69 88

    69

    82

    21 23

    17 18 19 20

    21 23

    42

    21 23

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    52

    41

    99

    63

    69

    81

    40

    69

    99

    34

    98

    64

    98

    27

    9

    65 66

    67

    48

    74 68

    66

    44

    24

    20

    68

    25

    48

    86

    62

    32

    27

    38

    64

    32

    70

    45

    64

    23

    20 21 23

    21

    68

    45

    60

    88

    33

    53

    21 23 25

    88

    98

    70

    42

    65

    10 11 13 14 15

    69

    77

    80

    71 77 78 79

    77

    15

    69

    85

    84

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    25

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    68

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    69

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    51

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    26

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    36

    37

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    70

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    21 23

    21

    37 99

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    21

    21 23

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    47

    37

    25

    39

    44

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    25

    70 88

    23

    21 23

    21 23

    21 23

    21 23

    23

    17 18 19 20 25 37

    17 23

    37

    45 98 99

    81

    46

    46

    47

    48

    48

    35 78 82

    44

    13

    82 83

    47

    86

    53 58

    59

    21

    66

    45

    13 15

    21 23

    21 23

    17 23

    21

    24

    62 99 21

    11 14 16 27

    30 31

    28 29

    17 18 21

    42

    49

    21 23

    8 21 23

    23

    18

    41 42 78

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    36

    69

    69

    87

    23 25

    70

    70 21 23

    98

    70

    69

    68

    68

    77 24

    13 16

    60 61

    63

    13 14 16

    17 21 23

    21 23

    21 23

    8 21 23

    17 21 23

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    73 79

    13 16

    45 66

    13 15 45 98

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    9 37

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    73

    80

    72 79

    77 79

    77

    74

    74

    72 75 76

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    42

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    46

    46

    46

    45

    9 37

    65 66

    64

    46

    67

    62

    87

    80

    74

    63

    46

    61

    60

    43

    43

    50

    80

    25 42

    34

    46

    61 70

    25

    44

    25 70

    44

    87

    67

    33 64

    68

    68

    69

    45

    13 15

    64

    86

    69

    61

    69

    69

    98

    69

    60

  • Apple Inc.

    THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.

    124578

    B

    D

    8 7 6 5 4 3

    C

    B

    A

    NOTICE OF PROPRIETARY PROPERTY:

    PAGE

    12

    D

    A

    C

    PAGE TITLE

    SHEET

    IV ALL RIGHTS RESERVED

    R

    DSIZEDRAWING NUMBER

    REVISION

    BRANCH

    6 3

    THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

    III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT

    T29 / GMUX JTAG SignalsFrame Holes

    Digital Ground

    SMT GND TEST PONTS

    USB SIGNALS

    UNUSED USB SIGNALS

    UNUSED FDI SIGNALS

    SSD PCIE SIGNALS

    DPMUX TX & RX

    UNUSED TBT PORTS

    GPU signals

    GMUX ALIASES

    Unused PEG signals

    T29 Signals Through PEG

    CPU signals

    APN 806-2247

    THERMAL MODULE STANDOFFS

    POGO PINS

    SM

    SM

    STDOFF-4.5OD2.15H-SM

    805

    5%1/8WMF-LF

    0

    TBTBST:N

    STDOFF-4.5OD1.8H-SMSTDOFF-4.5OD2.15H-SMSTDOFF-4.5OD2.15H-SM

    STDOFF-4.5OD2.15H-SM

    STDOFF-4.5OD2.15H-SM

    STDOFF-4.5OD2.15H-SM

    STDOFF-4.5OD1.9H-SM

    2.8R2.3

    1K5%

    201MF

    1/20W

    RAMCFG0:L

    1/20W

    RAMCFG1:L

    201

    1K

    MF

    5%

    RAMCFG3:L

    1/20WMF

    5%

    201

    1K

    201MF

    1/20W

    RAMCFG2:L

    1K5%

    STDOFF-4.5OD2.15H-SM

    STDOFF-4.5OD1.8H-SM

    POGO-2.3OD-5.5H-SM-LOW-FORCESM

    I1187

    I1188

    I1189

    I1190

    I1191

    I1192

    SL-1.1X0.45-1.4x0.75

    TH-NSP

    SM

    SHLD-J5-USB

    SMPOGO-2.3OD-5.5H-SM-LOW-FORCE POGO-2.3OD-5.5H-SM-LOW-FORCE

    SM

    SMPOGO-2.3OD-5.5H-SM-LOW-FORCE POGO-2.3OD-5.5H-SM-LOW-FORCE

    SMPOGO-2.3OD-5.5H-SM-LOW-FORCE

    SM

    SL-1.1X0.45-1.4x0.75

    TH-NSP

    TH-NSP

    SL-1.1X0.45-1.4x0.75

    SL-1.1X0.45-1.4x0.75

    TH-NSP

    SL-1.1X0.45-1.4x0.75

    TH-NSP

    SL-1.1X0.45-1.4x0.75

    TH-NSP

    SL-2.3X3.9-2.9X4.5

    TH-NSP

    2.8OD1.2ID-1.35H-SM

    2.8OD1.2ID-1.35H-SM

    2.8OD1.2ID-1.35H-SM

    2.8OD1.2ID-1.35H-SM

    2.8OD1.2ID-1.35H-SM

    SMT-PAD-NSP2.1SM2.0MM-CIR 2.1SM2.0MM-CIR

    SMT-PAD-NSP SMT-PAD-NSP2.1SM2.0MM-CIR

    SMT-PAD-NSP2.1SM2.0MM-CIR

    MLB-MTG-BRKT-J5TH

    SM

    SHLD-J5-CAN-FENCE-MDP-1

    SM

    POGO-2.3OD-5.5H-SM-LOW-FORCESM

    STDOFF-4.5OD2.15H-SM-1

    STDOFF-4.9OD2.38H-SM-SL-2.6X2NP-2

    2.8OD1.2ID-1.35H-SM

    2.8OD1.2ID-1.35H-SM

    Signal AliasesSYNC_DATE=01/13/2012SYNC_MASTER=D2_KEPLER

    MAKE_BASE=TRUEGND

    NC_LVDS_IG_A_DATAPNO_TEST=TRUEMAKE_BASE=TRUE

    NC_LVDS_IG_A_DATA_PNO_TEST=TRUEMAKE_BASE=TRUE

    NC_LVDS_IG_A_DATANNO_TEST=TRUEMAKE_BASE=TRUE

    TP_PCH_GPIO65_CLKOUTFLEX1

    GND_CHASSIS_MLBCAN6

    GND_CHASSIS_MLBCAN5

    GND_CHASSIS_MLBCAN4

    GND_CHASSIS_FAN

    GND_CHASSIS_MLBCAN3

    GND_CHASSIS_MLBCAN2

    GND_CHASSIS_MLBCAN1

    LVDS_IG_BKL_ONMAKE_BASE=TRUE

    LVDS_IG_PANEL_PWRMAKE_BASE=TRUE

    MAKE_BASE=TRUETP_FW_PWR_ENMAKE_BASE=TRUESD_PWR_ENMAKE_BASE=TRUESD_PWR_EN_PCH

    MAKE_BASE=TRUEDP_TBTSNK1_HPD_IGMAKE_BASE=TRUEDP_TBTSNK0_HPD_IG

    TRUEMAKE_BASE=TRUE

    NC_PCIE_CLK100M_EXCARD_P

    TRUEMAKE_BASE=TRUE

    NC_PCIE_CLK100M_EXCARD_N

    TRUEMAKE_BASE=TRUE

    NC_PCIE_EXCARD_R2D_C_P

    TRUEMAKE_BASE=TRUE

    NC_PCIE_EXCARD_D2R_NTRUEMAKE_BASE=TRUE

    NC_PCIE_EXCARD_D2R_P

    MAKE_BASE=TRUETRUE NC_PCH_GPIO64_CLKOUTFLEX0

    MAKE_BASE=TRUETRUE NC_PCH_GPIO66_CLKOUTFLEX2

    MAKE_BASE=TRUETRUE NC_PCH_GPIO67_CLKOUTFLEX3

    TRUEMAKE_BASE=TRUE

    DPLL_REF_CLKP

    MAKE_BASE=TRUETRUE NC_PCH_GPIO65_CLKOUTFLEX1

    TRUEMAKE_BASE=TRUE

    DPLL_REF_CLKN

    TRUEMAKE_BASE=TRUE

    NC_PCIE_EXCARD_R2D_C_N

    MAKE_BASE=TRUETP_PCIE_CLK100M_FW_P

    MAKE_BASE=TRUETP_PCIE_CLK100M_FW_N

    MAKE_BASE=TRUEUSB_TPAD_N

    MAKE_BASE=TRUEUSB_TPAD_P

    MAKE_BASE=TRUEUSB_BT_N

    MAKE_BASE=TRUEUSB_BT_P

    MAKE_BASE=TRUENC_CPU_FDI_DATA_P

    NO_TEST=TRUE

    MAKE_BASE=TRUEPU_USBHUB_DN4N

    MAKE_BASE=TRUEPU_USBHUB_DN4P

    MAKE_BASE=TRUENC_PCH_FDI_DATA_P

    NO_TEST=TRUE

    MIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.2MMVOLTAGE=5V

    PP5V_S0_AUDIO_AMP_L

    MAKE_BASE=TRUEPEG_R2D_C_N

    MAKE_BASE=TRUENC_PCH_FDI_DATA_N

    NO_TEST=TRUE

    MAKE_BASE=TRUENC_CPU_FDI_DATA_N

    NO_TEST=TRUE

    MAKE_BASE=TRUEPCIE_SSD_D2R_P

    MAKE_BASE=TRUEUSB_SMC_N

    MIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.2MMVOLTAGE=5V

    PP5V_S0_AUDIO_AMP_R

    MAKE_BASE=TRUENC_CPU_FDI_LSYNC

    NO_TEST=TRUE

    MAKE_BASE=TRUENC_CPU_FDI_FSYNC

    NO_TEST=TRUE

    MAKE_BASE=TRUENC_PCH_FDI_LSYNC

    NO_TEST=TRUE

    MAKE_BASE=TRUEUSB_SMC_P

    MAKE_BASE=TRUENC_PCH_FDI_FSYNC

    NO_TEST=TRUE

    MAKE_BASE=TRUEPEG_R2D_C_P

    MAKE_BASE=TRUEPCIE_SSD_R2D_C_N

    MAKE_BASE=TRUEPEG_D2R_P

    MAKE_BASE=TRUEPEG_D2R_N

    MAKE_BASE=TRUEPCIE_SSD_R2D_C_PMAKE_BASE=TRUEPCIE_SSD_D2R_N

    MAKE_BASE=TRUENC_USB_EXTC_P

    NO_TEST=TRUE

    MAKE_BASE=TRUENC_USB_EXTC_N

    NO_TEST=TRUE

    MAKE_BASE=TRUENC_USB3_EXTD_RX_P

    NO_TEST=TRUE

    MAKE_BASE=TRUENC_USB3_EXTD_RX_N

    NO_TEST=TRUE

    MAKE_BASE=TRUE NO_TEST=TRUENC_USB_EXTD_EHCI_P

    MAKE_BASE=TRUE NO_TEST=TRUENC_USB_EXTD_EHCI_N

    MAKE_BASE=TRUENC_USB3_EXTC_TX_P

    NO_TEST=TRUE

    NC_USB3_EXTD_TX_NMAKE_BASE=TRUE NO_TEST=TRUE

    NC_USB3_EXTD_TX_PMAKE_BASE=TRUE NO_TEST=TRUE

    NC_USB3_EXTC_TX_NMAKE_BASE=TRUE NO_TEST=TRUE

    NC_USB3_EXTC_RX_PMAKE_BASE=TRUE NO_TEST=TRUE

    MAKE_BASE=TRUE NO_TEST=TRUENC_USB3_EXTC_RX_N

    DPMUX_UC_RXMAKE_BASE=TRUE

    MAKE_BASE=TRUENC_TBT_D2RN

    NO_TEST=TRUE

    MAKE_BASE=TRUENC_TBT_D2RP

    NO_TEST=TRUE

    MAKE_BASE=TRUEDPMUX_UC_TX

    MAKE_BASE=TRUENC_TBT_R2D_CN

    NO_TEST=TRUE

    MAKE_BASE=TRUENC_TBT_R2D_CP

    NO_TEST=TRUE

    MAKE_BASE=TRUENC_SATA_ODD_D2R_PMAKE_BASE=TRUENC_SATA_ODD_D2R_N

    MAKE_BASE=TRUENC_DP_IG_MLP

    NO_TEST=TRUE

    MAKE_BASE=TRUENC_DP_IG_MLN

    NO_TEST=TRUE

    MAKE_BASE=TRUENC_SATA_ODD_R2D_C_PMAKE_BASE=TRUENC_SATA_ODD_R2D_C_N

    NC_LVDS_IG_B_DATA_NMAKE_BASE=TRUE NO_TEST=TRUE

    NO_TEST=TRUEMAKE_BASE=TRUENC_LVDS_IG_A_DATA_N

    MAKE_BASE=TRUENC_PCIE_FW_R2D_CP

    NO_TEST=TRUE

    MAKE_BASE=TRUENC_PCIE_FW_R2D_CN

    NO_TEST=TRUE

    MAKE_BASE=TRUENC_PCIE_FW_D2RP

    NO_TEST=TRUE

    MAKE_BASE=TRUENC_PCIE_FW_D2RN

    NO_TEST=TRUE

    MAKE_BASE=TRUENC_LVDS_IG_DDC_DATA

    NO_TEST=TRUE

    MAKE_BASE=TRUENC_LVDS_IG_B_DATA_P

    NO_TEST=TRUE

    MAKE_BASE=TRUENC_LVDS_IG_DDC_CLK

    NO_TEST=TRUE

    PEX_CLKREQ_LMAKE_BASE=TRUE

    PEG_CLKREQ_LMAKE_BASE=TRUE

    EG_RESET_LMAKE_BASE=TRUE

    MAKE_BASE=TRUENO_TEST=TRUE

    TBT_LSEO_LSOE2NO_TEST=TRUEMAKE_BASE=TRUE

    TBT_LSEO_LSOE3

    MAKE_BASE=TRUENC_PEG_R2D_C_P

    NO_TEST=TRUE

    MAKE_BASE=TRUENC_PEG_R2D_C_N

    NO_TEST=TRUE

    MAKE_BASE=TRUEPCIE_TBT_D2R_P

    MAKE_BASE=TRUEPCIE_TBT_R2D_C_P

    MAKE_BASE=TRUEPCIE_TBT_R2D_C_N

    MAKE_BASE=TRUEPCIE_TBT_D2R_N

    MAKE_BASE=TRUENC_PEG_D2R_P

    NO_TEST=TRUE

    MAKE_BASE=TRUECPU_VID

    MAKE_BASE=TRUEMEMVTT_EN

    MAKE_BASE=TRUENC_PEG_D2R_N

    NO_TEST=TRUE

    NO_TEST=TRUENC_LVDS_IG_A_CLK_PMAKE_BASE=TRUE

    NO_TEST=TRUENC_LVDS_IG_A_CLK_NMAKE_BASE=TRUE

    NO_TEST=TRUENC_LVDS_IG_B_DATAN

    MAKE_BASE=TRUE

    NO_TEST=TRUENC_LVDS_IG_B_DATAP

    MAKE_BASE=TRUE

    MAKE_BASE=TRUETP_CPU_VTT_SELECT

    =PP15V_TBT_REG

    PCIE_FW_D2R_P

    USB3_EXTC_RX_P

    LVDS_IG_A_DATA_P

    LVDS_IG_A_DATA_N

    LVDS_IG_B_DATA_N

    PCIE_FW_D2R_N

    PCIE_FW_R2D_C_P

    USB3_EXTC_TX_N

    SATA_ODD_R2D_C_P

    SATA_ODD_R2D_C_N

    SATA_ODD_D2R_P

    LVDS_IG_DDC_DATA

    USB3_EXTD_TX_N

    USB_EXTC_P

    USB_EXTC_N

    USB_EXTD_EHCI_P

    USB_EXTD_EHCI_N

    USB3_EXTC_RX_N

    PCIE_FW_R2D_C_N

    SATA_ODD_D2R_N

    TP_DP_IG_B_MLN

    LVDS_IG_DDC_CLK

    TP_DP_IG_B_MLP

    LVDS_IG_B_DATA_P

    LVDS_IG_A_CLK_P

    LVDS_IG_A_CLK_N

    LVDS_IG_A_DATA_N

    LVDS_IG_B_DATA_P

    LVDS_IG_B_DATA_N