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Electromagnetic Compatibility of Integrated Circuits (EMC of ICs). Alexandre Boyer INSA de Toulouse. April 18 2008. OUTLINE. AGENDA 9h - 12h: EMC of ICs – part I (Course) 14h - 17h: EMC of ICs – part II (Course) OBJECTIVES - PowerPoint PPT Presentation
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1
April 18 2008
Alexandre Boyer
INSA de Toulouse
Electromagnetic Compatibility of Electromagnetic Compatibility of Integrated Circuits (EMC of ICs)Integrated Circuits (EMC of ICs)
2
OUTLINE
AGENDA
9h - 12h: EMC of ICs – part I (Course)
14h - 17h: EMC of ICs – part II (Course)
OBJECTIVES
At the end of the course, the auditor will be able to understand the origins of
electromagnetic compatibility (EMC) issues at integrated circuits level, the
basic knowledge to face with EMC issues, and become familiar with the most
common circuit-level EMC design guidelines.
PRE REQUISITES
Basic knowledge in electrical circuits, CMOS technology, electromagnetism.
3
OUTLINE
CONTENT
Introduction
EMC Basics concepts
Emission/Susceptibility Origin
Measurement methods
EMC Models
EMC Guidelines
Conclusion / Future of EMC
4
1. Introduction
5
What is EMC ?
« Disturbances of flight instruments causing trajectory deviations appear when one or several passengers switch on electronic devices. » (Air et Cosmos, April 1993)
29th July 1967 : accident of the American aircraft carrier USSForrestal. The accidental launching of a rocket blew gas tank and weapon stocks, killing 135 persons and causing damages which needed 7 month reparations. Investigations showed that a radar induced on plane wiring a sufficient parasitic voltage to trigger the launching of the rocket.
Two examples
6
What is EMC ?
« The ability of a device, equipment or system to function satisfactorily in its electromagnetic environment without introducing intolerable electromagnetic disturbance to anything in that environment. »
Guarantee the simultaneous operation of all nearby electric or electronic devices and the safety of users in a given electromagnetic environment
Reduce parasitic electromagnetic emission and their sensitivity or susceptibility to electromagnetic interferences
Maximum levels and methods to characterize emission and susceptibility of an equipment are defined by standards
7
What is EMC ?Examples of EMC standards
The existence of EMC specifications is linked to the safety and robustness level that an equipment must reach. EMC standards for automotive, aerospace, military, transport, medical, telecommunication applications, but also for
commercial products
• European EMC directive 89/336/EEC about electronic products EMC requirements
• IEC-TC77 and CISPR : IEC technical committee related to EMC standards
• For automotive applications : ISO 7637, ISO 11452, CISPR 25, SAE J1113
• For military applications : MIL-STD-461D, MIL-STD-462D
• For aerospace applications : DO-160
• For integrated circuits : IEC 61963, IEC 62132
CE mark
8
Context - Technology Scale Down
0.1
Lithography (µm)
Year
80286 16MHz
80386 33MHz 486
66MHz Pentium 120MHz
1.0
0.2
0.3
2.0
0.05
Research
Deep
submicron
Industry
Pentium III 0.7GHz
Submicron Micron Ultra deep submicron
Pentium IV 3GHz
Nano scale
65nm
45nm
83 86 89 92 95 98 01 04 07 10 13
0.01
0.02
0.03 32nm
22nm
Working 7nm device
Deep Nano
0.25µm
Pentium DualCore2.2GHz
Channel length divided by 2 each 18 month in the 90’s
Research has 5 year advance on industry
This trend has major consequences on electronic systems safety, reliability, … and EMC
9
EMC of ICs
• Until mid 90’s, IC designers had no consideration about EMC problems in their design. EMc was only handled at system and PCB levels
• Many EMC problems originate from ICs (3rd origin of IC redesign !), as it is the source of noise emission and sensitivity
• With technology trends (increased clock speed, chip complexity and reduced voltage), ICs are more emissive and sensitive to noise
• Semiconductor manufacturers are faced with increasing customer expectations for designing low emission and highly immune ICs
EMC must be handled at IC level
Why EMC of ICs
10
Customer’s specifications
Frequency
Emission level
measurementSimulation
Target
Improve or develop EMC measurement methods to respond to new customer’s requests
Develop simulation tools to predict EMC of IC behavior
Develop design guidelines aiming at reducing emission and susceptibility levels
IC emission spectrum
IC emission spectrum
EMC of IC topics
EMC of ICs
11
EMC of ICs
Design issuesEMC problems handled at the end of design cycle
DESIGN
Architectural Design
Design EntryDesign Architect
FABRICATION
Version n°
EMC Measurements
GONO GO
+ 6 months
+ $$$$$$$$
Compliance ?
Version n°
12
DESIGN
Architectural Design
Design EntryDesign Architect
FABRICATION
EMC compliant
EMC SimulationsCompliance ?
GO
NO GO
EMC validated before fabricationDesign Guidelines
Tools
Training
EMC problems handled at the end of design cycle
EMC of ICs
Design issues
13
2. EMC Basic Concepts
14
Electrical domain Electromagnetic domainVoltage V (Volt) Electric Field E (V/m)
Current I (Amp) Magnetic field H (A/m)
Impedance Z (Ohm) Characteristic impedance Z0 (Ohm)
Z=V/I Z=E/H
P=I2 x R (watts) P=H2 x 377 (watts/m2) far field conditions
The “EMC” way of thinking
EMC environment
15
Wide dynamic range of signals in EMC → use of dB (decibel)
0.1
10
1
100
0.01
Volt dBV
0.001
0.001
0.1
0.01
1
0.0001
MilliVolt
dBµV
0.00001
Voltage units
For example dBV, dBA :
AdBA
VdBV
log20
log20
Extensive use of dBµV
120log201
log20
V
µV
VVdBµV
0
20
40
-20
-40
-60
0
20
40
-20
-40
60
Specific Units
16
Specific Units
Power units
The most common power unit is the “dBm” (dB milli-Watt)
1 mV = ___ dBµV
0.1 W = ___ dBm
Exercise: Specific units
30log101
log10
W
WdBmW P
mW
PP
1 W
1 MW
1 KW
Power(Watt)
1 mW
Power(dBm)
1 µW
1 nW
30
90
60
0
-30
-60
17
Emission and susceptibility level units
30K 300K 3M 30M40
50
60
70
80
dBµV
Conducted emission level (CISPR25)
Class 4
Class 5
1M 100M 1G10
20
30
40
50
dBµV/m
Radiated emission level (CISPR25)
Class 5
10M
CISPR 25 : “Radio disturbance characteristics for the protection of receivers used on board vehicles, boats, and on devices – Limits and methods of measurement”
Specific Units
18
Fourier Transform
Time domain measurement
Volt
Time
Frequency measurementFourier transform
Freq (Log)
dB
Invert Fourier transform
Fourier transform: principle
Spectrum analyserOscilloscope
19
Fourier TransformWhy Frequency domain is so important ?
FFT
User’s specification
Time domain Frequency domain
Low level harmonics contribution
Only high level harmonics contribution appears
Contribution of each harmonic appears
20
Fourier transform - Example
50 % duty cycle trapezoidal signal
Period T = 100 ns, Tr = Tf = 2 ns
rr Tou
T
35.01
T
1
rT
1
-20 dB/dec
-40 dB/decFFT
Fourier Transform
Evaluation of signal bandwidth
21
Emission spectrum
Specification for an IC emission
Parasitic emission (dBµV)
-10
0
10
20
30
40
50
60
70
80
1 10 100 1000Frequency (MHz)
Measured emission
EMC compatible
Aggressor IC
Radiated emission
Sufficient margin
22
dBµV
0
20
40
60
80
100
10 100 1000
FM GSMRFLow parasitic emission is a key argument
Supplier A
Supplier B
EMC compliant
Not EMC compliant
Frequency(MHz)
Customer's specified limit
Emission spectrum
23
Susceptibility threshold
Immunity level (dBmA)
-40
-30
-20
-10
0
10
20
30
40
50
1 10 100 1000
Specification for board immunityCurrent injection limit
Measured immunity
A very low energy produces a fault
Frequency (MHz)
Victim IC
Immunity level has to be higher than customer specification
24
Notion of margin
Domain Lifetime Margin
Aeronautics 30 years 40 dB
Automotive 10 years 20 dB
Consumer 1 year 0 dB
Parasitic emission (dBµV)
Component/PCB/System Ageing
Nominal Level
Design Objective
Process dispersion
Measurement error/dispersion
Environment
Safety margin
To ensure the electromagnetic
compatibility, emission or
susceptibility levels have to be lower
than a nominal target … …But it is not sufficient to a zero
error probability ! Margin are required to compensate
unpredictable variations and reduce
the error probability.
Margin depends on the
safety level required in
an application domain:
25
Parasitic coupling mechanisms
Radiated mode – Antenna coupling
Example : The VSS supply track propagates noise
The EM wave propagates through the air
Coupling mechanisms
Conducted mode – Common impedance coupling
• Loop : Magnetic field coupling
• Wire : Electric field coupling
26
Parasitic coupling mechanisms
Crosstalk
Parasitic coupling between nearby conductors.
Near field coupling ≠ radiated coupling
Capacitive crosstalk Inductive crosstalk
dielectricground
C C
C12
h
t
wd
dielectricground
L12
h
t
wddt
dVCI
dt
dILV
27
Impedance
R,L,C vs. frequency
Impedance profile of:
•50 ohms resistor
•100pF capacitor
•10nH inductor
•a real 100 pF SMD capacitor
Z = constant
Z÷10 at each decade
Z×10 at each decade
28
Ceramic capacitor
Carbon resistor
Inductor
Impedance
Passive components – Real model
Understand EMC issues requires the knowledge of
electronic device parasitics
29
Interconnections
2a
l
Current
acdc RRR
2a
lRdc
a
lRac 2
1
2ln
2 a
llL o
Quasi static approximation : If l <
λ/20, interconnections are considered as electrically small
PCB
Package
Bonding wires
Parasitic resistance
Parasitic inductance
Interconnect parasitics
30
Interconnections
Coaxial line Microstrip line
• From the electromagnetic point of view:
H
EZ 0 Link to conductor geometry and material properties
jCG
jLRZ
0C
LZ 0
losslessconductor
• From the electric point of view :
Equivalent electrical schematic
Characteristic impedance
31
Interconnections
Impedance matching
Adapted: the line is transparentNot adapted: the line suffers ringing, insertion losses
time
Voltage
time
Voltage
Essential for signal integrity and power transfer
32
Interconnections
Characteristic impedance Small conductor Large conductor
What is the optimum characteristic impedance for a coaxial cable ?
• Maximum power : Z0 = 32
• Minimum loss: Z0 = 77
Small conductor
Large conductor
Power handling X
Bending X
weight X
Low loss x x
Small capacitance
x
Small inductance
x
Low Impedance x
Or ?
Ideal values:
• EMC cable (compromise between power and loss) : Z0 = 50
• TV cable (minimize Loss): Z0 = 75
Cable examples:
33
50 Ω adapted equipments
Gtem
Tem cell
Spectrum analyzer
Waveform generator
Amplifier
EMC equipments
34
3. Origin of Emission and Susceptibility of ICs
35
Two main conceptsEmission of EM wavesSusceptibility to EM waves
Personal entrainments
Safety systems
interferences
Hardware faultSoftware failureFunction Loss
Components
Printed circuit boards
Equipments
System
Noise
36
Susceptibility
Chip
Chip
EmissionPCB
PCB System
Components
Components
System
Integrated circuits are the origin of parasitic emission and susceptibility to RF disturbances in electronic systems
Noisy IC
Sensitive IC
Interferences
Radiation
Coupling
EMC at system level
37
Source of Electromagnetic Interferences Natural disturbances
(cosmic rays, thunder)Radio communications,
wireless, radars,…
Electrical Overstress
Inductive loads, motors
IC activity
IC
38
Technology trends
2000 2005 2010 2015
10nm
100nm
1m
Technology (log scale)
Year
0.13m90nm
45nm32nm
Technology trend high performance microprocessors
22nm
2020
1nm
7nm
18nm9nm
0.18m 0.13µm
65nm
Technology trend cost-performance
microcontrollers0.25m
0.35m
90nm
45nm32nm
5-years gap22nm
Year
39
Technology trends
1999
IC tech.
Complexity
Packaging
0.25 µm
50M
µC16 bit
µC16 bit
2001
0.18 µm
100M
µC32 bit
µC32 bit
2003
130 nm
250M
µC+DSPFlash
µC+DSPFlash
2005
90 nm
500M
2µC+4DSPMb Flash
2µC+4DSPMb Flash
2007
65 nm
1G
Multicore, DSP
FPGA, eRamRF multiband
Multicore, DSP
FPGA, eRamRF multiband
40
VDD
VSS
Output capa
Vin
Basic mechanisms for CMOS circuit current: CMOS inverter exemple
IDD (0.1mA)
ISS (0.1mA)
IDD (0.1mA)
ISS (0.1mA)
VOUT
Switching current
Voltage Time
Time
Origin of parasitic emission
Main noise sources comes from AC current sources:- Clock-driven blocks, synchronized logic
- Memory read/write/refresh
- I/O switching
41
Origin of parasitic emission Parasitic emission is linked to voltage drops. The current peak are not the only responsible of emission. Inductance are responsible of the conversion of current peak to voltage drops. Current peaks and voltage drops generate the conducted emission and also responsible of the radiated emission.
Vss
Vdd
50ps
i(t)
Time
Switching gatesInternal
switching noise
Vdd
Vss
i(t)
Voltage dropst
iLV
t
iLV
i(t)Radiated Emission
42
Stronger di/dt Stronger di/dt
Increase parasitic noise
Increase parasitic noise
Time
New process
VoltOld process
Why technology scale down makes things worse ?
• Current level keeps almost constant but:
• Faster current switching
• Current level keeps almost constant but:
• Faster current switching
Time
Current
di/dt
New processOld process
Origin of parasitic emission
43
Example: evaluation of switching current in an IC
• 0.1 mA / Gate in 100ps• 1 Billion gates (32 Bit Micro) => 100A• 10% switching activity => 10A• Spreading of current peak (non synchronous switching) => 1A in 1ns
0.1 mA
Ampere
0.1 nstime
Vdd
Vss
i(t)Current / gate
Ampere
1 nstime
Current / Ic
1 A
Origin of parasitic emission
44
Example: evaluation of supply voltage bounce
L=0.6nH/mm
L=1nH/mm
Lead = 10 mm
1 A en 1 ns Evaluate noise amplitude :
VDD
VSS
Lead = 10 mm
Chip
Origin of parasitic emission
45
Origin of parasitic emission
Overview of influent parameters on parasitic emission
IC
i(t)IC Internal
interconnexions
IC activity
PCB tracks and external passive
components
Vdd
VssLoad
i(t)
Internal activity of the IC
Output load of the circuit
Filtering effect of IC interconnections
Filtering effects of PCB tracks and external passive components
46
Susceptibility issues
5.0
3.3
2.51.8
0.5µ 0.35µ 0.18µ 90nm 65nmTechnology
0.7
Less voltage, more IOs
Supply (V)
1.2
45nm
Core supply
I/O supply
100 200 500 1000
Noise margin reduction
47
Susceptibility issues
Hobby
Hobby
TV UHF
Radars
Satellites
MWave
Badge
DECT
Stat. de base
1W
Frequency
1MW
1KW
1GW Radar Météo
3 MHz 30 MHz 300 MHz 3 GHz 30 GHz 300 GHz
Power
1mW
HF VHF UHF SHF xHF THF
Radar UMTS
TV VHF
GSM
Components issues
Components issues
Multiple parasitic electromagnetic sources
48
Susceptibility issues
Electromagnetic wave
System failureHardware fault
Software failure
Function loss
µp
mixed
More complex Ics, more levels in susceptibility
49
Susceptibility issues
Desynchronisation issues Jitter is becoming increasingly important in digital design due to rising operating frequencies.
The increase of operating frequencies of digital circuits reduces their dynamic margin
EMI induced jitter
EMI induced jitter
Bit error
Dynamic failure
EMI on supply
50
IC failures
Origin of IC susceptibility
Overview of influent parameters on IC susceptibility
IC
IC Internal interconnexions
IC active devices
PCB tracks and external passive
components
Vdd
Vss
RF interferences
Filtering effects of PCB tracks and external passive components
Filtering effect of IC interconnections
Impedance of IC nodes (high Z node = high susceptibility)
Non linear effects of active devices (conversion RF signals to DC offsets !)
Block own susceptibility (noise margin, delay margin, …) Internal perceived noise
51
Block type Emission SusceptibilityFast digital I/O ++ -
Power switch output ++ --
Oscillator / PLL / Clock circuitry
++ ++
Charge pump ++ --
Digital block supply + -
Analog input/supply -- ++
DC/DC converter + ++
Emission / Susceptibility issues