AR8032 Integrated 10/100 Fast Ethernet Transceiver · 2014-07-04 · to a Fast Ethernet-capable MAC. The AR8032 transceiver combines feed-forward equalizer, feedback equalizer, and

COMPANY CONFIDENTIAL

Data Sheet

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September 2009

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AR8032 Integrated 10/100 Fast Ethernet TransceiverGeneral DescriptionThe Atheros AR8032 Fast Ethernet transceiver is a highly integrated physical layer device that transmits and receives high-speed data over standard category 5 (CAT 5) unshielded twisted pair cable.The AR8032 is compliant with 100 BASE-TX and 10 BASE-T IEEE 802.3 standards. The AR8032 device uses advanced mixed-signal processing technology and integrates functions such as adaptive equalization, and timing recovery to deliver substantial power savings and operation in noisy environments. The AR8032 device supports the Media Independent Interface (MII) and Reduced Media Independent Interface (RMII) for direct connection to a Fast Ethernet-capable MAC.The AR8032 supports the Atheros Cable Diagnostic Test (CDT) feature, which uses Time Domain Reflectometry (TDR) technology to quickly and remotely identify potential cable malfunctions without deploying field support personnel or bringing down the network. The AR8032 solution detects and reports issues such as PHY malfunctions, bad/marginal cable or patch cord segments or connectors, thus significantly reducing installation time, cable debug efforts, and overall network support cost.

Manufactured in a standard CMOS process, the AR8032 is packaged in a 32-pin QFN, featuring a small body size of 5 x 5mm.

Features■ 10/100 BASE-T IEEE 802.3 compliant■ Supports MII/RMII interface■ Low power modes with internal automatic

DSP power saving scheme■ Fully integrated digital adaptive equalizers

All digital baseline wander correction■ Supports external 25 MHz clock source in

MII mode■ Supports external 50 MHz clock source in

RMII mode■ Automatic speed downshift mode■ Automatic MDI/MDIX crossover■ Automatic polarity correction■ Loopback modes for diagnostics■ IEEE 802.3u compliant Auto-Negotiation■ Software programmable LED modes■ Cable Diagnostic Test (CDT)■ Requires only one 3.3V power supply■ 32-pin QFN 5mm x 5 mm package

AR8032 Functional Block Diagram

DAC

PGA

AGC

Symbol Encoder

ADCFeed

Forward Equalizer

Decision Feedback Equalizer

Symbol Decoder/Alignment

Timing & Phase Recovery

Auto-Negotiation

MII Management Registers DLL

PMA

MII Rx

MII Tx

MDIP/N[0:1]

• 1

riving the Wireless Future®, ROCm®, Super A/G®, Super G®, ered by Atheros Communications, Inc. Atheros SST™, Signal-ions, Inc. The Atheros logo is a registered trademark of Atheros lders. Subject to change without notice.

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2 • AR8032 Integrated 10/100 Mbps Ethernet Transceiver Atheros Communications, Inc. 2 • September 2009 COMPANY CONFIDENTIAL

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Table of Contents

General Description......................................... 1Features ............................................................. 1AR8032 Functional Block Diagram ............... 11 Pin Descriptions ......................................... 52 Functional Description .............................. 9

2.1 Transmit Functions ............................. 92.2 Receive Functions................................ 9

2.2.1 Decoder Modes ......................... 92.2.2 Analog to Digital Converter . 102.2.3 Baseline Wander Canceller ... 102.2.4 Digital Adaptive Equalizer ... 102.2.5 Auto-Negotiation.................... 102.2.6 Smartspeed Function ............. 102.2.7 Polarity Correction ................. 10

2.3 Loopback Modes ............................... 112.3.1 Digital Loopback .................... 112.3.2 External Cable Loopback....... 112.3.3 Cable Diagnostic Test............. 112.3.4 LED Interface........................... 112.3.5 Power Supplies ....................... 112.3.6 Low Power Modes.................. 112.3.7 Hibernation Mode .................. 11

3 Electrical Characteristics ......................... 133.1 Absolute Maximum Ratings............ 133.2 Recommended Operating Conditions

133.3 XTAL/OSC Timing........................... 143.4 MII DC Characteristics ..................... 153.5 MDIO Characteristics ....................... 16

3.5.8 MDIO Timing.......................... 163.6 Power-On Strapping......................... 183.7 Typical Power Consumption Parame-

ters ....................................................... 184 Register Descriptions ............................... 21

4.1 PHY Register Summary ................... 214.1.1 Control Register ...................... 224.1.2 Status Register......................... 244.1.3 PHY Identifier ......................... 264.1.4 PHY Identifier 2 ...................... 264.1.5 Auto-Negotiation Advertise-

ment Register .......................... 274.1.6 Auto-Negotiation Expansion

Register..................................... 294.1.7 Link partner ability register(base

page)......................................... 304.1.8 Function Control Register ..... 314.1.9 PHY Specific Status Register 334.1.10 Interrupt Enable Register ...... 344.1.11 Interrupt Status Register ....... 364.1.12 Smart Speed Register ............. 384.1.13 Receive Error Count Register 404.1.14 Virtual Cable Tester Control

Register .................................... 404.1.15 LED Control Register............. 414.1.16 Manual LED Override Register

424.1.17 Virtual Cable Tester Status Reg-

ister ........................................... 434.1.18 Debug Port (Address Offset Set)

Register .................................... 434.1.19 Debug Port 2 (R/W Port) Regis-

ter .............................................. 444.2 Power Saving and Debug Register

Summary ............................................ 454.2.20 10Base-T Test Configuration

Register .................................... 454.2.21 100Base-TX Test Configuration

Register .................................... 464.2.22 Hibernate Control Register ... 484.2.23 Power Saving Control............ 49

5 Package Dimensions................................ 516 Ordering Information.............................. 53

Atheros Communications, Inc. AR8032 Integrated 10/100 Mbps Ethernet Transceiver • 3 COMPANY CONFIDENTIAL September 2009 • 3

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1. Pin DescriptionsThis section contains a package pinout for the AR8032 QFN 32pin and a listing of the signal descriptions (see Figure 1-1).

The following nomenclature is used for signal names:

The following nomenclature is used for signal types described in Table 1-1:

NC No connection to the internal die is made from this pin

_L At the end of the signal name, indicates active low signals

P Power

D Open drain

IA Analog input

I Digital input

IH Digital input with histeresis

I/O Digital input/output

OA Analog output

O Digital output

PD Internal pull-down for digital input

PU Internal pull-up for digital input


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Figure 1-1 shows the pinout diagram for the AR8032.

NOTE: There is an exposed ground pad on the back side of the package.

Figure 1-1. Pinout Diagram

AR8032

32 31 30 29 28 27 26 25

REX

T

LED1

LED0

CRS

COL

TXD3

TXD2

TXD1

17

18

19

20

21

22

23

24

VDD25

RX_DV

RXC

RXER

INTP

TXC

TXEN

TXD01

2

3

4

5

6

7

8

VDD12_REG

VDD3

RX‐

RX+

TX‐

TX+

XO

VDD25_REG

9 10 11 12

XI

RST

#

MDIO

MDC

13 14 15 16

RXD<3>

RXD<2>

RXD<1>

RXD<0>


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Table 1-1. Signal to Pin Relationships and Descriptions

Symbol Pin Type Description

VDD12_REG 1 AO 1.2V regulator output. A 1 uF plus a 0.1 uF cap needed to stabilize the output

VDD3 2 P 3.3V power supply.

VDD25_REG 3 AO 2.5V regulator output. A 1 uF ceramic cap needed to stabalize the output. It is for analog, digital I/O and the transformer center taps.

RX- 4 AI, AO Media Dependent Interface 0, terminate with a 49.9Ω resister and connect to XFMR

RX+ 5 AI, AO Media Dependent Interface 0, terminate with a 49.9Ω resister and connect to XFMR

TX- 6 AI, AO Media Dependent Interface 1, terminate with a 49.9Ω resister and connect to XFMR

TX+ 7 AI, AO Media Dependent Interface 1, terminate with a 49.9Ω resister and connect to XFMR

XO 8 AO Crystal oscillator output. 27 pF to GND.

XI 9 AI Crystal oscillator input. 27 pF to GND. An external 25/50 MHx clock source with swing from 0 to 1.2V can inject from this pin when a crystal is not used and the two 27pF caps removed. The 25 Mhz clock input is for MII mode, while the 50 Mhz clock input is for RMII mode.

RST# 10 IH, PU System reset input.

MDIO 11 I/O, D, PU Management data.

MDC 12 I, PU Management clock reference.

RXD<3> 13 I/O, PU, POS

MII Receive data output [3].

RXD<2> 14 I/O, PD, POS

MII Receive data output [2].

RXD<1> 15 I/O, PD, POS

MII/RMII Receive data output [1].

RXD<0> 16 I/O, PU, POS

MII/RMII Receive data output [0].

VDD25 17 P 2.5V I/O power, connect with pin 3, 0.1uF to GND.

RX_DV 18 I/O, PD, POS

Receive data valid output

RXC 19 I/O, PD, Receive clock output

RXER 20 I/O, PD Receive error output

INTP 21 I/O, PU, POS

Interrupt Output

TXC 22 I/O, PU Transmit clock output

TXEN 23 I, PU Transmit data enable

TXD0 24 I, PD MII/RMII Transmit data input [0]

TXD1 25 I, PD MII/RMII Transmit data input [1]


DO NOT COPYNOTE: All of the digital input only pads are 3.3V

input tolerant. The O and I/O pads are powered with 2.5V power. The input level of any I/O pads 9except open-drain type) is limited to 2.5V.

TXD2 26 I, PD MII Transmit data input [2]

TXD3 27 I, PD MII Transmit data input [3]

COL 28 I/O, PD, POS

Collision Detect output

CRS 29 I/O, PD POS

Carrier Sense output

LED0 30 I/O, PU POS

Programable LED 0, the default indicates Link and Activity

LED1 31 I/O, PU POS

Programmable LED 1The default indicates Speed

REXT 32 AO Connect 2.37 K to GND

PADDLE GND Gnd Ground

Table 1-1. Signal to Pin Relationships and Descriptions (continued)

Symbol Pin Type Description


2. Functional DescriptionThe Atheros AR8032 is a highly integrated analog front end (AFE) and digital signal transceiver (see Figure 2-1), providing high performance with substantial cost reduction. AFE consists of automatic gain control (AGC), ADC, DAC, drivers, and clock generation. The AR8032 provides physical layer functions to

transmit and receive high-speed data over standard category 5 (CAT5) unshielded twisted pair cable.

See also the “AR8032 Functional Block Diagram” on page 1.

The AR8032 10/100 PHY is fully 802.3, 802.3u compliant, and supports the media-independent interface (MII) and Reduced Media Independent Interface (RMII) to connect to a Fast Ethernet-capable MAC.

The AR8032 transceiver combines feed-forward equalizer, feedback equalizer, and timing recovery, to enhance signal performance in noisy environments.

2.1 Transmit FunctionsThe AR8032 transmit channel includes 4B/5B mapper and scrambler. Table 2-1 describes the transmit function encoder modes.

2.2 Receive FunctionsThe AR8032 receive channel includes digital gain control, feed forward adaptive equalizer, decision feedback equalizer, slicer, 5B/4B de-mapper and de-scrambler, PCS receive functional block, and timing recovery logic.

2.2.1 Decoder ModesTable 2-2 describes the receive function decoder modes.

Figure 2-1. Analog Front End

Baseline Wander Watchdog

Hybrid Circuits

Line Driver

Coarse

Fine

ADC

PLL

TXDAC

25 MHz CrystalLine Side

Programmable Gain Amplifier Transceiver

Side

AFE

Table 2-1. Transmit Function Encoder Modes

Encoder Mode Description100BASE-TX In 100BASE-TX mode, 4-bit data

from the MII is 4B/5B serialized, scrambled, and encoded to a three-level MLT3 sequence transmitted by the PMA.

10BASE-T In 10BASE-T mode, the AR8032 transmits and receives Manchester-encoded data.

Table 2-2. Receive Function Decoder Modes

Decoder Mode Description100BASE-TX In 100BASE-TX mode, the receive

data stream is recovered and descrambled to align to the symbol boundaries. The aligned data is then parallelized and 5B/4B decoded to 4-bit data. This output runs to the MII/RMII receive data pins after data stream delimiters have been translated.

10BASE-T In 10BASE-T mode, the recovered 10BASE-T signal is decoded from Manchester then aligned.


2.2.2 Analog to Digital ConverterThe AR8032 device employs an advanced high speed ADC on each receive channel with high resolution, which results in better SNR and lower error rates.

2.2.3 Baseline Wander CancellerBaseline wander results from Ethernet links that AC-couple to the transceivers and from AC coupling that cannot maintain voltage levels for longer than a short time. As a result, transmitted pulses are distorted, resulting in erroneous sampled values for affected pulses. The AR8032 device uses an advanced baseline wander cancellation circuit that continuously monitors and compensates for this effect, minimizing the impact of DC baseline shift on the overall error rate.

2.2.4 Digital Adaptive EqualizerThe digital adaptive equalizer removes inter-symbol interference at the receiver. The digital adaptive equalizer takes unequalized signals from ADC output and uses a combination of feedforward equalizer (FFE) and decision feedback equalizer (DFE) for the best-optimized signal-to-noise (SNR) ratio.

2.2.5 Auto-NegotiationThe AR8032 device supports 10/100 BASE-T Copper auto-negotiation in accordance with IEEE 802.3 clauses 28 and 40. Auto-negotiation provides a mechanism for transferring information between a pair of link partners to choose the best possible mode of operation in terms of speed, duplex modes, and master/slave preference. Auto-negotiation is initiated upon any of the following scenarios:

■ Power-up reset

■ Hardware reset

■ Software reset

■ Auto-negotiation restart

■ Transition from power-down to power-up

■ The link goes down

If auto-negotiation is disabled, a 10BASE-T or 100BASE-TX can be manually selected using the IEEE MII registers.

2.2.6 Smartspeed FunctionThe Atheros Smartspeed function is an enhanced feature of auto-negotiation that allows the AR8032 device to fall back in speed based on cabling conditions as well as operate over CAT3 cabling (in 10BASE-T mode) or two-pair CAT5 cabling (in 100BASE-TX mode).

By default, the Smartspeed feature is enabled. Refer to the register “Smart Speed Register” on page 38, which describes how to set the parameters. Set these register bits to control the Smartspeed feature:

■ Bit [5]: 1 = Enables Smartspeed (default)

■ Bits [4:2]: Sets the number of link attempts before adjusting

■ Bit [1]: Timer to determine the stable link condition

2.2.7 Polarity CorrectionIf cabling has been incorrectly wired, the AR8032 automatically corrects polarity errors on the receive pairs.


2.3 Loopback Modes

2.3.1 Digital LoopbackDigital loopback provides the ability to loop transmitted data back to the receiver using digital circuitry in the AR8032 device. The registers“100Base-TX Test Configuration Register” on page 46 and “10Base-T Test Configuration Register” on page 45 are used to determine at which point the signal loops back (for different modes, respectively).

Figure 2-2 shows a block diagram of digital loopback.

2.3.2 External Cable LoopbackExternal cable loopback loops MII Tx to MII Rx through a complete digital and analog path and an external cable, thus testing all the digital data paths and all the analog circuits. Figure 2-3 shows a block diagram of external cable loopback.

2.3.3 Cable Diagnostic TestThe Cable Diagnostic Test (CDT) feature in the AR8032 device uses Time Domain Reflectometry (TDR) to identify remote and local PHY malfunctions, bad/marginal cable or patch cord segments, or connectors. Some of the possible problems that can be diagnosed include opens, shorts, cable impedance mismatch, bad connectors, termination mismatch, and bad magnetics. The CDT can be performed when there is no link partner or when the link partner is auto-negotiating.

2.3.4 LED InterfaceThe LED interface can either be controlled by the PHY or controlled manually, independent of the state of the PHY. Four status LEDs are available. These can be used to indicate operation speed, duplex mode, and link status. The LEDs can be programmed to different status functions from their default value. They can also be controlled directly from the MII register interface.

2.3.5 Power SuppliesThe AR8032 device requires only one power supply: 3.3V.

2.3.6 Low Power ModesThe AR8032 device supports the software power-down low power mode. The standard IEEE power-down mode is entered by setting the POWER_DOWN bit (bit [11]) of the register “Control Register” on page 22 equal to one.

In this mode, the AR8032 device ignores all MAC interface signals except the MDC/MDIO. It does not respond to any activity on the CAT 5 cable. The device cannot wake up on its own. It can only wake up by setting the POWER_DOWN bit (bit [11]) of the register “Control Register” on page 22” to 0.

2.3.7 Hibernation ModeThe AR8032 device supports hibernation mode. When the cable is unplugged, the AR8032 will enter hibernation mode after about 10 seconds. The power consumption in this mode is very low compared to the normal mode of operation. When the cable is re-connected, the AR8032 wakes up and normal functioning is restored.

Figure 2-2. Digital Loopback

Figure 2-3. External Cable Loopback

MAC/Switch MII PHY

Digital

PHY

AFE

MAC/Switc

hMII PHY

Digital

PHY

AFE

RJ-

45



3. Electrical Characteristics

3.1 Absolute Maximum RatingsTable 3-1 summarizes the absolute maximum ratings and Table 3-2 lists the recommended operating conditions for the AR8032. Absolute maximum ratings are those values beyond which damage to the device can occur. Functional operation under these conditions, or at any other condition beyond those indicated in the operational sections of this document, is not recommended.

3.2 Recommended Operating Conditions

NOTE: The following condition must be satisfied:

ΤJmax > TCmax + ΨJT x PTypical

Where:

ΤJmax = Maximum allowable temperature of the Junction

TCmax = Maximum allowable Case temperature

ΨJT = Thermal Dissipation Coefficient

PTypical = Typical power dissipation

Table 3-1. Absolute Maximum Ratings

Symbol Parameter Max Rating Unit

VDD33 3.3V supply voltage 3.8 V

Tstore Storage temperature –65 to 150 °C

ESD Electrostatic discharge tolerance 2000 V

Table 3-2. Recommended Operating Conditions

Symbol Parameter Min Typ Max Unit

VDD33 3.3V supply voltage 3.0 3.3 3.6 V

TA Ambient Temperature 0 — 70 °C

ΤJ Junction Temperature 0 — 125 °C

ΨJT Thermal Dissipation Coefficient — 4 — °C/W


3.3 XTAL/OSC TimingFigure 3-1 shows the XTAL timing diagram.

Table 3-3. XTAL/OSC Timing — MII mode

Table 3-4. XTAL/OSC Timing — RMII mode

Figure 3-1. XTAL/OSC Timing Diagram

tXI_RISE tXI_FALL

tXI_HI tXI_LO

tXI_PER

VIL-XI

VIH-XI


T_XI_PER XI/OSCI Clock Period 40.0 - 50ppm

40.0 40.0 + 50ppm

ns

T_XI_HI XI/OSCI Clock High 14 20.0 ns

T_XI_LO XI/OSCI Clock Low 14 20.0 ns

T_XI_RISE XI/OSCI Clock Rise Time, VIL (max) to VIH (min)

4 ns

T_XI_FALL XI/OSCI Clock Fall time, VIL (max) to VIH (min)

4 ns

V_IH_XI The XTLI input high level 0.8 1.4 V

V_IL_XI The xtli input low lever voltage -0.3 0.15 V


T_XI_PER XI/OSCI Clock Period 20.0 - 50ppm

20.0 20.0 + 50ppm

ns

T_XI_HI XI/OSCI Clock High 8 10.0 ns

T_XI_LO XI/OSCI Clock Low 8 10.0 ns

T_XI_RISE XI/OSCI Clock Rise Time, VIL (max) to VIH (min)

2 ns


3.4 MII DC CharacteristicsTable 3-5 shows the MII DC characteristics.

Figure 3-2 shows the MII input AC timing diagram.

T_XI_FALL XI/OSCI Clock Fall time, VIL (max) to VIH (min)

2 ns

V_IH_XI The XTLI input high level 0.8 1.4 V

V_IL_XI The xtli input low lever voltage -0.3 0.15 V

Table 3-5. MII DC Characteristics

Symbol Parameter Min Max UnitVOH Output high voltage 2.0 3.0 V

VOL Output low voltage GND 0.4 V

VIH Input high voltage 1.7 — V

VIL Input low voltage — 0.7 V

IIH Input high current — 15 μA

IIL Input low current –15 — μA

Figure 3-2. MII Input AC Timing Diagram

TXC

TXD[3:0]/TXEN

VIH

VIL

VIH

VIL

0 ns MinMin setup 5 ns


Figure 3-3 shows the MII output AC timing diagram.

3.5 MDIO CharacteristicsTable 3-6 shows the MDIO DC characteristics.RMII Timing

3.5.8 MDIO TimingFigure 3-4 shows the MDIO timing diagram.

Figure 3-3. MII Output AC Timing Diagram

Table 3-6. MDIO DC Characteristics

Symbol Parameter Min Max UnitVOH Output high voltage 2.4 — V

VOL Output low voltage — 0.4 V

IIH Input high current — –0.4 mA

IIL Input low current 0.4 — mA

RXC

RXD[3:0]/RX_DV/RXER

VIH

VIL

VIH

VIL

100Base-TX: 15 to 25ns10Base-T: 15 to 205ns

Figure 3-4. MDIO Timing Diagram

MDC

MDIO

tmdsu

tmdc

tmdhold

tmdch tmdcl


Table 3-7. MDIO Timing

Table 3-8 shows the RMII AC timing characteristics.

Figure 3-5 shows the AC RMII timing diagram.


tmdc MDC Period 100 nS

tmdcl MDC Low Period 40 nS

tmdch MDC High Period 40 nS

tmdsu MDIO to MDC rising setup time 10 nS

tmdhold MDIO to MDC rising hold time 10 nS

Table 3-8. RMII AC Timing

Symbol Parameter Min Max UnitTck XI Period — 20 nS

Tsu TXEN, TXD to XI rising setup time 4 — nS

Thold TXEN, TXD to XI rising hold time 2 — nS

Tdly XI to RX_DV, RXD output delay 3 14 nS

Figure 3-5. RMII AC Timing Diagram

XI

TXENTXD[1:0]

tholdtsu

RX_DVRXD[1:0]

tdly

tck


3.6 Power-On StrappingTable 3-9 shows the pin-to-PHY core configuration signal power-on strapping.

3.7 Typical Power Consumption ParametersThe following conditions apply to the typical characteristics unless otherwise specified:

VDD33 = 3.3V, Tamb = 25 °C

Table 3-10 shows the typical power drain as a function of the AR8032’s operating mode.

Table 3-9. Power-On Strapping[1]

PHY Pin Name Pin PHY Core

Configuration Signal DescriptionRXD<3> 13 PHYADDRESS[0] PHY address

RXD<2> 14 PHYADDRESS[1]

RXD<1> 15 PHYADDRESS[2]

RXD<0> 16 DUPLEX 1 = Full Duplex

RXDV 18 CONFIG2 CONFIG[2:0] 000 = MII001 = RMIIAll other binary combinations are Reserved.

CRS 29 CONFIG1

COL 28 CONFIG0

TXC 22 EN_AB Enable class AB mode

RXC 19 POWER_DOWN Enable Power Down mode

RXER 20 ISOLATE 1 = enable0 = disable

INTP 21 TESTMODE 1 = normal operation0 = test mode

LED0 30 AUTO-NEGOTIATION

1 = enable0 = disable

LED1 31 SPEED 1 = 100Mbps0 = 10 Mbps

[1]Default values: 0 = Pull-down, 1 = Pull-up with 10 K resistor.

Table 3-10. Total System Power

Mode Current (mA) Power (mW) Description

LDPS 3 9.9 Link down, power-saving mode

Isolate 18 59.4 Isolate mode

100F 92 303.6 100Base-T Full Duplex

10F 89 293.9 10Base-T Full Duplex

10TX 83 273.9 10Base-T Transmit


10RX 25 82.5 10Base-T Receive

10IDLE 21 69.3 10Base-T Idle

Table 3-10. Total System Power

Mode Current (mA) Power (mW) Description



4. Register DescriptionsTable 4-1 shows the reset types used in this document.

4.1 PHY Register SummaryTable 4-2 summarizes the registers for the AR8032.

Table 4-1. Reset Types

Type Description

LH Register field with latching high function. If status is high, then the register is set to one and remains set until a read operation is performed through the management interface or a reset occurs.

LL Register field with latching low function. If status is low, then the register is cleared to a zero and remains cleared until a read operation is performed through the management interface or a reset occurs.

Retain Value written to a register field takes effect without a software reset.

SC Self-Clear. Writing a one to this register causes the desired function to execute immediately, and the register field clears to zero when the function is complete.

Update The value written to the register field does not take effect until a software reset is executed. The value can still be read after it is written.

RES Reserved for future use. All reserved bits are read as a zero unless otherworse noted.

RO Read Only

ROC Read Only Clear. After read, register field is cleard to zero.

R/W Read/Write

RWC Read/Write Clear. After read, register field is cleared to zero.

RWR Read/Write Reset. All bits are readable and writable. After reset or read, the register field is cleard to zero.

RWS Read/Write Set. All bits are readable and writable. After reset or read, the register field is set to a non-zero value specified in the text.

SC Self-Clear. Writing a one to this register causes the desired function to be immediately executed, then the register field is cleared to zero when the function is complete.

WO Write Only. Reads to this type of register return undefined data.

Table 4-1. Reset Types (continued)

Type Description

Table 4-2. Register Summary

Offset Register Page0x00 Control Register page 22

0x01 Status page 24

0x02 PHY Identifier page 26

0x03 PHY Identifier 2 page 26

0x04 Auto-Negotiation Advertisement page 29

0x05 Link Partner Ability page 30

0x06 Auto-Negotiation Expansion page 29

0x07 Reserved

0x08 Reserved

0x09 Reserved

0x0A Reserved

0x0B Reserved


4.1.1 Control Register

Offset: 0x00 Mode: Read/Write Hardware Reset: 0 Software Reset: See field descriptions

0x0C Reserved

0x0D Reserved

0x0E Reserved

0x0F Reserved

0x10 Function Control Register page 22

0x11 PHY Specific Status Register page 33

0x12 Interrupt Enable Register page 34

0x13 Interrupt Status Register page 36

0x14 Smart Speed Register page 38

0x15 Recieve Error Counter Register page 40

0x16 Virtual Cable Tester Control Register page 40

0x18 Reserved

0x19 LED Control Register page 41

0x1A Manual LED Override Register page 42

0x1B Reserved

0x1C Virtual Cable Tester Status Register page 40

0x1D Debug Port 1 (Address offset) page 43

0x1E Reserved

0x1F Reserved

Table 4-2. Register Summary (continued)

Offset Register Page

Bit Name Type Description

15 Reset Mode R/W PHY Software Reset. Writing a "1" to this bit causes the PHY the reset operation is done , this bit is cleared to "0" automatically. The reset occurs immediately.1= PHY reset0 =Normal operation

HW Rst

0

SW Rst

SC

14 Loopback Mode R/W When loopback is activated, the transmitter data presented on TXD is looped back to RXD internally. Link is broken when loopback is enabled. 1 = Enable Loopback0 = Disable Loopback

HW Rst

0

SW Rst

0


13 Speed Selection (LSB)

Mode R/W Upon hardware reset , this bit and 0.6 bit depend upon anen(bit0.12) and SPEED:anen {0.6 , 0.13} 0 {0, SPEED}1 2'b01(00:10Mbps, 01:100Mbps, 10:Reserved, 11:Reserved)

HW Rst

See Desc.

SW Rst

Retain

12 Auto-negotiation Mode R/W Upon hardware reset, this bit depends on ANEN_PAD.1 = Enable Auto-Negotiation Process0 = Disable Auto-Negotiation Process

HW Rst

See Desc.

SW Rst

Retain

11 Power Down Mode R/W When the port is switched from power down to normal operation, software reset and restart Auto-Negotiation are performed even when bits Reset (0.15) and Restart Auto-Negotiation (0.9) are not set by the user.1 = Power down0 = Normal operation

HW Rst

0

SW Rst

0

10 Isolate Mode R/W The MII output pins are tristated when this bit is set to 1.The MII inputs are ignored.1 = Isolate0 = Normal operation

HW Rst

0

SW Rst

0

9 Restart Auto-negotiation

Mode R/W, SC

Auto-Negotiation automatically restarts after hardware or software reset regardless of whether or not the restart bit (0.9) is set.1 = Restart Auto-Negotiation Process0 = Normal operation

HW Rst

0

SW Rst

SC

8 Duplex mode Mode R/W, SC

Upon hardware reset, this bit bit depends on DUPLEX_MODE_PAD and anen bit(0.12):

0.12 0.80 01 DUPLEX_MODE_PAD

1:Full Duplex 0:Half Duplex

HW Rst

See Desc.

SW Rst

7 Collision Test Mode R/W Setting this bit to 1 will cause the COL pin to assert whenever the TX_EN pin is asserted.1 = Enable COL signal test0 = Disable COL signal test

HW Rst

0

SW Rst

0

6 Speed Selection (MSB)

Mode R/W See bit 0.13.

HW Rst

See Desc.

SW Rst



4.1.2 Status Register

Offset: 0x01 Mode: Read/Write Hardware Reset: 0 Software Reset: See field descriptions

5:0 RES Mode RO Reserved for future use.

HW Rst

00000

SW Rst

00000



15 100Base-T4 Mode RO 100BASE-T4.This protocol is not available.0 = PHY not able to perform 100BASE-T4

HW Rst

0

SW Rst

0

14 100Base-Tx Full- Duplex

Mode RO Capable of 100Base-Tx Full-Duplex operation

HW Rst

1

SW Rst

1

13 100Base-Tx Half-Duplex

Mode RO Capable of 100Base-Tx Half-Duplex operation

HW Rst

1

SW Rst

1

12 10 Mbps Full-Duplex

Mode RO Capable of 10Base-T Full-Duplex operation

HW Rst

1

SW Rst

1

11 10 Mbps Half-Duplex

Mode R/W Capable of 10 Mbps Half-Duplex operation

HW Rst

1

SW Rst

1

10 100Base-T2 Full-Duplex

Mode RO Not able to perform 100Base-T2 Full-Duplex operation

HW Rst

0

SW Rst

0


9 100Base-T2 Half-Duplex

Mode R/W Not able to perform 100Base-T2 Half-Duplex operation

HW Rst

0

SW Rst

0

8 Extended Status Mode RO Extended status information in register 15

HW Rst

1

SW Rst

1

7 RES Mode RO Reserved

HW Rst

0

SW Rst

0

6 MF Preamble Suppression

Mode RO PHY accepts management frames with preamble suppressed

HW Rst

1

SW Rst

1

5 Auto-negotiation Complete

Mode RO 1: Auto negotiation process complete0:Auto negotiation process not completeHW

Rst0

SW Rst

0

4 Remote Fault Mode RO, LH

1: Remote fault condition detected0:Remote fault condition not detected

HW Rst

0

SW Rst

0

3 Auto-Negotiation Ability

Mode R/W 1: PHY able to perform auto-negotiation

HW Rst

1

SW Rst

1

2 Link Status Mode RO, LL

This register bit indicates whether the link was lost since the last read. For the current link status, readregister bit 17.10 Link Real Time.1 = Link is up0 = Link is down

HW Rst

0

SW Rst

0



4.1.3 PHY Identifier

Offset: 0x02

4.1.4 PHY Identifier 2

Offset: 0x03

1 Jabber Detect Mode RO, LH

1: Jabber condition detected0: Jabber condition not detected

HW Rst

0

SW Rst

0

0 Extended Capability

Mode RO 1: Extended register capabilitites

HW Rst

1

SW Rst

1



15:0 Orgainizationally Unique Identifer

Bits 3:18

Mode RO Orgainizationally Unique Identifer Bits 3:18

HW Rst

Always 16’h 004d

SW Rst

Always 16’h 004d


15:0 OUI bit 19:24 Model Number

Revision Number

Mode RO Orgainizationally Unique Identifer Bits 3:18

HW Rst

Always 16’h d023

SW Rst

Always 16’h d023


4.1.5 Auto-Negotiation Advertisement Register

Offset: 0x04


15 Next Page Mode R/W The value of this bit will be updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs:o Software reset is asserted (register 0.15)o Restart Auto-Negotiation is asserted (register 0.9)o Power down (register 0.11) transitions from power down to normal operationo Link goes downIf 1000BASE-T is advertised then the required next pages are automatically transmitted. Register 4.15 should be set to 0 if no additional next pages are needed.1 = Advertise0 = Not advertised

HW Rst

0

SW Rst

Update

14 Ack Mode RO Must be 0

HW Rst

Always 0

SW Rst

Always 0

13 Remote Fault Mode R/W 1 = Set Remote Fault bit0 = Do not set Remote Fault bitHW

RstSee

Desc.

SW Rst

Update

12 Reserved Mode RO Always 0.

HW Rst

Always 0

SW Rst

Always 0

11 Asymmetric Pause Mode R/W Upon hardware reset , this bit depends on ASYM_PAUSE_PAD.The value of this bit will be updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs:o Software reset is asserted (register 0.15)o Restart Auto-Negotiation is asserted (register 0.9)o Power down (register 0.11) transitions from power down to normal operationo Link goes down1 = Asymmetric Pause0 = No asymmetric Pause

HW Rst

See Desc.

SW Rst

Update


10 PAUSE Mode R/W Upon hardware reset , this bit depends on PAUSE_PAD.The value of this bit will be updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs:o Software reset is asserted (register 0.15)o Restart Auto-Negotiation is asserted (register 0.9)o Power down (register 0.11) transitions from power down to normal operationo Link goes down1 = MAC PAUSE implemented0 = MAC PAUSE not implemented

HW Rst

See Desc.

SW Rst

Update

9 100BASE-T4 Mode RO Not able to perform 100BASE-T4

HW Rst

Always 0

SW Rst

Always 0

8 100BASE-TXFull Duplex

Mode R/W The value of this bit will be updated immediately after writing this register. But the value written to this bit does not takes effect until any one of the following occurs:o Software reset is asserted (register 0.15)o Restart Auto-Negotiation is asserted (register 0.9)o Power down (register 0.11) transitions from power down to normal operationo Link goes down1 = Advertise0 = Not advertised

HW Rst

1

SW Rst

Update

7 100BASE-TXHalf Duplex


HW Rst

1

SW Rst

Update



HW Rst

1

SW Rst

Update



4.1.6 Auto-Negotiation Expansion Register

Offset: 0x06

510BASE-TXHalf Duplex


HW Rst

1

SW Rst

Update

4:0 Selector field Mode RO Selector Field mode00001 = 802.3HW

RstAlways 00001

SW Rst

Always 00001



15:5 RES Mode RO Reserved. Must be 0.

HW Rst

Always 0

SW Rst

Always 0

4 Parallel Detection Fault

Mode RO, LH 1: a fault has been detect 0: no fault has been detected HW

Rst0

SW Rst

0

3 Link Partner Next Paga Able

Mode RO 1: Link partner is Next page able0: Link partner is not next page ableHW

Rst0

SW Rst

0

2 Local Next Page Able

Mode RO 1 = Local Device is Next Page able

HW Rst

1

SW Rst

1


4.1.7 Link partner ability register(base page)

Offset: 0x05

1 Page Received Mode RO, LH 1: A new page has been received0: No new page has been receivedHW

Rst0

SW Rst

0

0 Link Partner Auto- Negotiation Able

Mode RO 1: Link partner is auto negotiation able0: Link partner is not auto negotiation ableHW

Rst0

SW Rst

0



15 Next page Mode RO Received Code Word Bit 151 = Link partner capable of next page0 = Link partner not capable of next page

HW Rst

0

SW Rst

0

14 Ack Mode RO AcknowledgeReceived Code Word Bit 141 = Link partner received link code word0 = Link partner does not have Next Page ability

HW Rst

0

SW Rst

0

13 Remote Fault Mode RO Remote FaultReceived Code Word Bit 131 = Link partner detected remote fault0 = Link partner has not detected remote fault

HW Rst

0

SW Rst

0

12 Reserved Mode RO Technology Ability FieldReceived Code Word Bit 12HW

Rst0

SW Rst

0

11 Asymmetric Pause Mode RO Technology Ability FieldReceived Code Word Bit 111 = Link partner requests asymmetric pause0 = Link partner does not request asymmetric pause

HW Rst

0

SW Rst

0


4.1.8 Function Control Register

10 PAUSE Mode RO Technology Ability FieldReceived Code Word Bit 101 = Link partner is capable of pause operation0 = Link partner is not capable of pause operation

HW Rst

0

SW Rst

0

9 100BASE-T4 Mode RO Technology Ability FieldReceived Code Word Bit 91 = Link partner is 100BASE-T4 capable0 = Link partner is not 100BASE-T4 capable

HW Rst

0

SW Rst

0


Mode RO Technology Ability FieldReceived Code Word Bit 81 = Link partner is 100BASE-TX full-duplex capable0 = Link partner is not 100BASE-TX full-duplex capable

HW Rst

0

SW Rst

0


Mode RO Technology Ability FieldReceived Code Word Bit 71 = Link partner is 100BASE-TX half-duplex capable0 = Link partner is not 100BASE-TX half-duplex capable

HW Rst

0

SW Rst

0


Mode RO Technology Ability FieldReceived Code Word Bit 61 = Link partner is 10BASE-T full-duplex capable0 = Link partner is not 10BASE-T full-duplex capable

HW Rst

0

SW Rst

0


Mode RO Technology Ability FieldReceived Code Word Bit 51 = Link partner is 10BASE-T half-duplex capable0 = Link partner is not 10BASE-T half-duplex capable

HW Rst

0

SW Rst

0

4:0 Selector field Mode RO, LH Selector FieldReceived Code Word Bit 4:0HW

Rst0

SW Rst

0



Offset: 0x10


15:12 RES Mode R/W Reserved

HW Rst

0

SW Rst

Retain

11 Assert CRS on Transmit

Mode R/W 1 = when transmitting, crs_o is asserted to 1;0 = crs_o is asserted to 1 only when receiving.When in RMII mode, this bit is fixed to 0.

HW Rst

1

SW Rst

Retain

10 RES Mode R/W Reserved

HW Rst

0

SW Rst

Retain


HW Rst

0

SW Rst

Retain

6:5 MDI Crossover Mode

Mode R/W Changes to these bits are disruptive to the normal operation; therefore any changes to these registers must be followed by a software reset to take effect.00 = Manual MDI configuration01 = Manual MDIX configuration10 = Reserved11 = Enable automatic crossover for all modes

HW Rst

11

SW Rst

Update


HW Rst

0

SW Rst

Retain

2 SQE Test Mode R/W SQE Test is automatically disabled in full-duplex mode 1 = SQE test enabled0 = SQE test disabled

HW Rst

0

SW Rst

Retain


HW Rst

0

SW Rst

Retain


4.1.9 PHY Specific Status Register

Offset: 0x11

0 Disable Jabber Mode R/W Jabber has effect only in 10BASE-T half-duplex mode.1 = Disable jabber function0 = Enable jabber function

HW Rst

0

SW Rst

Retain



15:14 Speed Mode RO These status bits are valid only after resolved bit 17.11 = 1. The resolved bit is set when Auto-Negotiation is completed or Auto-Negotiation is disabled.11 = Reserved10 = Reserved01 = 100 Mbps00 = 10 Mbps

HW Rst

00

SW Rst

Retain

13 Duplex Mode RO This status bit is valid only after resolved bit 17.11 = 1. The resolved bit is set when Auto-Negotiation is completed or Auto-Negotiation is disabled.1 = Full-duplex0 = Half-duplex

HW Rst

SW Rst

12 Page Received (real-time)

Mode RO 1 = Page received0 = Page not receivedHW

Rst0

SW Rst

Retain

11 Speed and DuplexResolved

Mode RO When Auto-Negotiation is not enabled, 17.11 = 1 for force speed mode.1 = Resolved0 = Not resolved

HW Rst

0

SW Rst

0

10 Link (real-time) Mode RO 1 = Link up0 = Link downHW

Rst0

SW Rst

0

9:7 RES Mode RO Reserved

HW Rst

Always 0

SW Rst

Always 0


4.1.10 Interrupt Enable Register

6 MDI CrossoverStatus

Mode RO This status bit is valid only after resolved bit 17.11 = 1. The resolved bit is set when Auto-Negotiation is completed or Auto-Negotiation is disabled. This bit is 0 or 1 depending on what is written to 16.6:5 in manual configuration mode. Register 16.6:5 are updated with software reset.1 = MDIX0 = MDI

HW Rst

0

SW Rst

Retain

5 Wirespeed Downgrade

Mode RO 1 = Downgrade0 = No DowngradeHW

Rst0

SW Rst

0


HW Rst

0

SW Rst

0

3 Transmit Pause Enabled

Mode RO This is a reflection of the MAC pause resolution. This bit is for information purposes and is not used by the device.This status bit is valid only after resolved bit 17.11 = 1. The resolved bit is set when Auto-Negotiation is completed; While in force mode, this bit is set to be 0.1 = Transmit pause enabled0 = Transmit pause disabled

HW Rst

SW Rst

2 Receive Pause Enabled

Mode RO This is a reflection of the MAC pause resolution. This bit is for information purposes and is not used by the device.This status bit is valid only after resolved bit 17.11 = 1. The resolved bit is set when Auto-Negotiation is completed; While in force mode, this bit is set to be 0.1 = Receive pause enabled0 = Receive pause disabled

HW Rst

SW Rst

1 Polarity (real-time) Mode RO 1 = Reversed0 = NormalHW

Rst0

SW Rst

Retain

0 Jabber (real-time) Mode RO 1 = Jabber0 = No jabberHW

Rst0

SW Rst

Retain



Offset: 0x12


15 Auto-NegotiationError Interrupt

Enable

Mode R/W 1 = Interrupt enable0 = Interrupt disableHW

Rst0

SW Rst

Retain

14 Speed Changed Interrupt Enable


Rst0

SW Rst

Retain

13 Duplex ChangedInterrupt Enable


Rst0

SW Rst

Retain

12 Page Received Interrrupt Enable


Rst0

SW Rst

Retain

11 Link Fail Interrupt Enable


Rst0

SW Rst

Retain

10 Link Success Interrupt Enable


Rst0

SW Rst

Retain


HW Rst

0

SW Rst

Retain


HW Rst

0

SW Rst

0


4.1.11 Interrupt Status Register

Offset: 0x13


HW Rst

0

SW Rst

Retain

6 MDI Crossover Changed Interrupt

Enable


Rst0

SW Rst

Retain

5 Wirespeed-downgrade

Interrupt Enable


Rst0

SW Rst

Retain


HW Rst

000

SW Rst

Retain

1 Polarity Changed Interrupt Enable


Rst0

SW Rst

Retain

0 Jabber Interrupt Enable


Rst

SW Rst



15 Auto-Negotiation Error

Mode RO, LH An error is said to occur if MASTER/SLAVE does not resolve, parallel detect fault, no common HCD, or link does not come up after negotiation is completed.1 = Auto-Negotiation Error0 = No Auto-Negotiation Error

HW Rst

0

SW Rst

Retain


14 Speed Changed Mode RO, LH 1 = Speed changed0 = Speed not changedHW

Rst0

SW Rst

Retain

13 Duplex Changed Mode RO, LH 1 = Duplex changed0 = Duplex not changedHW

Rst0

SW Rst

Retain

12 Page Received Mode RO, LH 1 = Page received0 = Page not receivedHW

Rst0

SW Rst

Retain

11 Link Fail Interrupt Mode RO, LH 1 = Link down happened.0 = Link down not happened.HW

Rst0

SW Rst

Retain

10 Link Success Interrupt

Mode RO, LH 1 = Link down happened.0 = Link down not happened.HW

Rst0

SW Rst

Retain

9 RES Mode RO, LH Reserved

HW Rst

0

SW Rst

Retain


HW Rst

0

SW Rst

0


HW Rst

0

SW Rst

0

6 MDI Crossover Changed

Mode RO, LH 1 = Crossover changed0 = Crossover not changedHW

Rst0

SW Rst

Retain



4.1.12 Smart Speed Register

Offset: 0x14

5 Wirespeed-downgrade

Interrupt

Mode RO, LH 1 = Wirespeed-downgrade detected.0 = No Wirespeed-downgrade.HW

Rst0

SW Rst

Retain


HW Rst

000

SW Rst

000

1 Polarity Changed Mode RO, LH 1 = Polarity Changed0 = Polarity not changedHW

Rst0

SW Rst

Retain

0 Jabber Mode RO, LH 1 = Jabber0 = No jabberHW

Rst0

SW Rst

Retain



15:11 RES Mode RO Reserved. Must be 00000000.

HW Rst

0

SW Rst

0

10:9 Reserved Mode R/W Reserved

HW Rst

1’b0

SW Rst

Retain


HW Rst

1’b0

SW Rst

Update



HW Rst

0

SW Rst

Update

5 Smartspeed_en Mode R/W The default value is one; if this bit is set to one and cable inhibits completion of the training phase, thenAfter a few failed attempts, the Atheros card automatically downgrades the highest ability to the next lower speed: from 100 to 10.

HW Rst

0

SW Rst

Update

4:2 Smartspeed_retry_ limit

Mode R/W The default value is three; if these bits are set to three, then the Atheros card will attempt five times before downgrading; The number of attempts can be changed through setting these bits.HW

Rst0

SW Rst

Update

1 Bypass_smartspeed_timer

Mode R/W The default value is zero; if this bit is set to one, the Smartspeed FSM will bypass the timer used for stability.

HW Rst

0

SW Rst

Update

0 RES Mode R/W Reserved.

HW Rst

0

SW Rst

0



4.1.13 Receive Error Count Register

Offset: 0x15

4.1.14 Virtual Cable Tester Control Register

Offset: 0x16


15:0 Receive Error Count

Mode RO Counter will peg at 0xFFFF and will not roll over.(when rx_dv is valid, count rx_er numbers)(in this version, only for 100Base-T)

HW Rst

0

SW Rst

0


15:11 Vct_dbg_psw Mode RO For VCT debug

HW Rst

0

SW Rst

0

10 vct_wp_Max_vcode[3]

Mode RO For VCT debug

HW Rst

1’b1

SW Rst

Retain

9:8 MDI Pair Select Mode R/W Virtual Cable Tester™ Control registers. Use the Virtual Cable Tester Control Registers to select which MDI pair is shown in the Virtual Cable Tester Status register.00 = MDI[0] pair01 = MDI[1] pair10 = Reserved11 = Reserved

HW Rst

00

SW Rst

00

7:5 vct_wp_Max_vcode[2:0]

Mode RO For VCT debug

HW Rst

3’b111

SW Rst

Retain

4:1 vct_np_Max_vcode[3:0]

Mode R/W For VCT debug

HW Rst

3’b111

SW Rst

Retain


4.1.15 LED Control Register

Offset: 0x18

0 Enable Test Mode R/W When set, hardware automatically disable this bit when VCT is done.1 = Enable VCT Test0 = Disable VCT Test

HW Rst

0

SW Rst

Retain



15 Disable LED Mode R/W Control the output LED pins.0 = Enable1 = Disable

HW Rst

0

SW Rst

Retain

14:12 LED On Time Mode R/W 000 = 5 ms001 = 10ms010 = 21 ms011 = 42ms100 = 84 ms101 = 168ms110 to 111 = 42ms

HW Rst

0

SW Rst

Retain

11 Force Interrupt Mode RO Always 0

HW Rst

0

SW Rst

0

10:8 LED Off Time Mode R/W 000 = 21 ms001 = 42 ms010 = 84 ms011 =168 ms100 =330 ms101 = 670 ms110 to 111 = 168ms

HW Rst

0

SW Rst

0


HW Rst

000

SW Rst

000

4:3 LED_LINK Control Mode R/W 00 = Direct LED mode11 = Master/Slave LED mode01, 10 = Combined LED modes

HW Rst

0

SW Rst

Retain


4.1.16 Manual LED Override Register

Offset: 0x19

2 LED_DUPLEX Control

Mode R/W 0 = Duplex1 = Duplex/CollisionHW

Rst0

SW Rst

Retain

1 LED_RX Control Mode R/W 1 = Receive activity/Link0 = Receive activityHW

Rst0

SW Rst

Retain

0 LED_TX Control Mode R/W 1 = Activity/Link0 = Transmit activityHW

Rst0

SW Rst

Retain




HW Rst

0

SW Rst

0

11:10 LED_DUPLEX Mode R/W LED "Off" means LED pin output equals high.LED "On" means LED pin output equals low.00 = Normal01 = Blink10 = LED Off11 = LED On

HW Rst

00

SW Rst

Retain

9:8 LED_LINK10 Mode RO LED "Off" means LED pin output equals high.LED "On" means LED pin output equals low.00 = Normal01 = Blink10 = LED Off11 = LED On

HW Rst

00

SW Rst

Retain

7:6 LED_LINK100 Mode R/W LED "Off" means LED pin output equals high.LED "On" means LED pin output equals low.00 = Normal01 = Blink10 = LED Off11 = LED On

HW Rst

00

SW Rst

Retain


4.1.17 Virtual Cable Tester Status Register

Offset: 0x1C

4.1.18 Debug Port (Address Offset Set) Register


HW Rst

0

SW Rst

Retain

3:2 LED_RX Mode R/W LED "Off" means LED pin output equals high.LED "On" means LED pin output equals low.00 = Normal01 = Blink10 = LED Off11 = LED On

HW Rst

00

SW Rst

Retain

1:0 LED_TX Mode R/W LED "Off" means LED pin output equals high.LED "On" means LED pin output equals low.00 = Normal01 = Blink10 = LED Off11 = LED On

HW Rst

00

SW Rst

Retain




HW Rst

0

SW Rst

0

9:8 Status Mode RO The content of the Virtual Cable Tester Status Registers applies to the cablepair selected in the Virtual Cable Tester™ Control Registers.11 = Link-up state, no short or open in cable00 = Valid test, normal cable (no short or open in cable)10 = Valid test, open in cable (Impedance > 333 ohms)01 = Valid test, short in cable (Impedance < 33 ohms)

HW Rst

00

SW Rst

00

7:0 Delta_Time Mode R/W Delta time indicates distance along the cable

HW Rst

0

SW Rst

0


Offset: 0x1D

4.1.19 Debug Port 2 (R/W Port) Register

Offset: 0x1E



HW Rst

0

SW Rst

0

5:0 Addres Offset Mode R/W The address index of the register will be written or read.

HW Rst

0

SW Rst

0


15:0 Debug Data Port Mode R/W The data port for the debug register.Before accessing this register, you must set the address offset first.

HW Rst

0

SW Rst

0


4.2 Power Saving and Debug Register SummaryTable 4-2 summarizes the registers for the AR8032.

4.2.20 10Base-T Test Configuration Register

Offset: 0x12

Table 4-3. Register Summary

Offset Register Page0x12 Test Configuration for 10Base-T page 45

0x10 Test Configuration for 100Base-Tx page 46

0x1B Hibernate Control page 48

0x29 Power Saving Control page 49


15:14 Interval_sel_timer Mode R/W Controls the interval that PHY detects whether the data frames on the cable are MLT-3 coded. This logic is used to divide Manchester code from MLT-3 code.HW

Rst0

SW Rst

Retain

13:12 Triger_sel_timer Mode R/W Controls the threshold that PHY detects at the end of the interval whether the data frames on the cable are MLT-3 coded. This logic is used to divide Manchester code from MLT-3 code.HW

Rst00

SW Rst

Retain

11 En_mask_bt Mode R/W 1: enable the function of dividing Manchester code from MLT-3 code.0: disable the function.

HW Rst

1

SW Rst

0

10 En_10bt_idle Mode R/W 1: In 10BT mode , if there's no data or NLP to transmit, shut off dac; otherwise turn on the dac;0: In 10BT, dac will not be turn off.

HW Rst

0

SW Rst

0


HW Rst

0

SW Rst

0

5 Test_mode[2] Mode R/W bit 2 of test_mode

HW Rst

0

SW Rst

0


4.2.21 100Base-TX Test Configuration Register

Offset: 0x10

4 En_longcable Mode R/W Enable long cable test

HW Rst

0

SW Rst

Retain


HW Rst

0

SW Rst

Retain

2 Loopback mode select

Mode RO 1: lpbk2-deep in Loopback mode0: lpbk1-shallow in Loopback mode(connect to dig10.test_mode_i[0])

HW Rst

0

SW Rst

0

1:0 Test_mode[1:0] Mode R/W [001]: packet with all ones, 10MHz sine wave, For harmonic test.[010]: pseudo random, for TP_IDLE/Jitter/Differential Voltage test. [011]: normal link pulse only,[100]: 5MHz sin wave.Others: normal mode.

HW Rst

0

SW Rst

0



15 TM100_ENA Mode R/W Enable dig100 loopback test mode.

HW Rst

0

SW Rst

Retain


HW Rst

0

SW Rst

Retain

7 Jitter_test Mode R/W 100Base-Tx Jitter test

HW Rst

0

SW Rst

Retain


6 Os_test Mode R/W 100Base-Tx Overshoot test

HW Rst

0

SW Rst

Retain

5 Dcd_test Mode R/W 100Base-Tx DCD test

HW Rst

0

SW Rst

Retain

4 PMD_LPBK_2 Mode R/W PMD loopback, test MLT-3 Encoder and Decoder

HW Rst

0

SW Rst

0

3 PMD_LPBK_1 Mode R/W PMD loopback, test Scrambler and Descrambler

HW Rst

0

SW Rst

0

2 PMA_LPBK_1 Mode R/W PMD loopback, test Carrier Detect and Link Monitor

HW Rst

0

SW Rst

0

1 PMA_LPBK_2 Mode R/W PMA loopback, test FEF Generator and FEF Detector

HW Rst

0

SW Rst

0

0 PCS_LPBK Mode R/W PCS loopback, test pcs_tx and pcs_rx

HW Rst

0

SW Rst

0



4.2.22 Hibernate Control Register

Offset: 0x1B


15 Ps_hib_en Mode RO Power hibernate conrol bit;

‘1’ : hibernate enable‘0’ : hibernate disable

HW Rst

0

SW Rst

0


HW Rst

0

SW Rst

0


HW Rst

0

SW Rst

0


HW Rst

0

SW Rst

0


HW Rst

0

SW Rst

0


HW Rst

0

SW Rst

0


HW Rst

0

SW Rst

0


4.2.23 Power Saving Control

Offset: 0x29


15 TOP_PS_EN Mode RO ‘1’ : Top level Power Saving Enable‘0’ : Top level Power Saving DisableHW

Rst1

SW Rst

Retain


HW Rst

3’h3

SW Rst

Retain

11:9 Dac_amp_100 Mode R/W Control amplitude of transmit signal in 100BT mode.

000: -2%

……

111: +12%

HW Rst

3’h3

SW Rst

Retain

8:6 Dac_amp_10 Mode R/W Control amplitude of transmit signal in 10BT mode.

000: -2%

……

111: +12%

HW Rst

3’h3

SW Rst

Retain


HW Rst

0

SW Rst

0


HW Rst

1

SW Rst

Retain



5. Package DimensionsThe AR8032 is packaged in a QFN 32. The body size is 5 mm by 5 mm. The package drawings

and dimensions are provided in Figure 5-1 and Table 5-1.

Figure 5-1. Package Views


Table 5-1. Package Dimensions

Dimension Label Min Nom Max Unit

A 0.80 0.85 0.90 mm

A1 0.00 0.01 0.05 mm

A2 0.60 0.65 0.70 mm

b 0.18 0.23 0.30 mm

D 5.00 Basic mm

D1 4.75 Basic mm

E 5.00 Basic mm

E1 4.75 Basic mm

P 0.24 0.42 0.60 mm

R 0.13 0.17 0.23 mm

Q 0.30 0.40 0.65 mm

D2 2.60 2.70 2.80 mm

E2 2.60 2.70 2.80 mm

θ 0 — 12 °

Notes:1. To be determined at seating plane C.2. Dimensioning and tolerences conform to ASME Y14.5M — 1994.3. Dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal tip.4. The Pin #1 identifier must be on the top surface of the package us-ing indentation mark or other feature of the package body.5. All Dimensions are in millimeters.6. The shape shown on four corners are not actual I/O.7. Q and R applies only for straght tiebar shapes.


PRELIMINARY

6. Ordering Information

The order number AR8032-AL1E specifies a current version of the AR8032.

Atheros Communications, Inc. AR8032 Integrated 10/100 Mbps Ethernet Transceiver • 53

Atheros Communications, Incorporated5480 Great America Parkway

Santa Clara, CA 95054t: 408/773-5200f: 408/773-9940www.atheros.com

The information in this document has been carefully reviewed and is believed to be accurate. Nonetheless, this document is subject to change without notice. Atheros assumes no responsibility for any inaccuracies that may be contained in this document, and makes no commitment to update or to keep current the contained information, or to notify a person or organization of any updates. Atheros reserves the right to make changes, at any time, to improve reliability, function or design and to attempt to supply the best product possible.

Document Number: 981-00072-001 MKG-0607 Rev. 1

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