ARCAM - audio-circuit.dk

untitledARCAM
This PCB provides the power for the unit through CON203: +5V_STBY – 5V standby supply L118 RS232, L126 display (on in standby) +3V3 PW338 – L122 PW338 supply (on in standby) 1V8D – L122 PW338 supply (on in standby) +5V_1 – general 5V supply +6V_1 – L156 DSP, L126 Display & L119 NET supply +40V_VFD – L126 Display +15V – linear +15V supply -15V – linear -15V supply
LK100 or the thermal switch from the power amp transformer is required to pass the live mains. SW101 switches between 230V & 115V.
R101 & R102 are NTC parts to prevent inrush currents when the power amp is turned on.
CON202 takes the Clk PSU sync signal from L121, Relay SW from L122 (to turn on the main supplies) and /AC present back to L122. /AC present is generated from the standby transformer secondaries with D200.D210 & TR200. This will prevent the unit from starting if it is not low.
The standby transformer is rectified with DBR200 (GBU4K) to give UNREG_PW338 which is used for the 1V8D (REG206 – LM2670), 3V3_PW338 (REG201 – LM2670). The 12V for the relays to switch the secondaries are also generated from REG207 (LM7812) which is then regulated down to give +5V_STBY REG200 (LM7805).
When the signal Relay SW is taken high by the PW338, the secondaries of the system & power amp transformer are switched in (RLY101 & RLY102).
This enables +15V, -15V (REG204 & REG205) & +5V_1 & +6V_1 (REG202 & REG203).
L123AY– Connection board and PSU
This PCB selects between one of five component video inputs & also provides the output connector for Zone 3 audio.
IC100, IC101 & IC104 (LT1675CGN video buffers) require +5V & -5V. The +5V comes direct from L123 & -5V is generated locally from the -15V supply (from L123).
Selection of the five inputs is via IC102 (74HCT595D serial to parallel converter, controlled via SPI Clk, Data & Vcomp latch) and IC100, IC101, IC104. IC102 generates a /ENx signal which tri-states the output when high and enables the output when low. When low the input is selected with the SELx signal, high for input1, low for input2.
Truth table: EN0 SEL0 EN1 SEL1 EN2 SEL2 0 0 1 X 1 x SAT 0 1 1 X 1 x AV 1 x 0 0 1 x VCR 1 x 0 1 1 x DVD 1 x 1 x 0 1 PVR 1 x 1 x 1 x BLANK* *When component input is not used, BLANK should be selected.
SKT101 provides zone 3 audio output.
L113AY Component Input – Output board
This PCB selects between one of five s-video & composite video inputs for the main input & zone 2 video. It also controls the volume control for Zone 2 & 3.
The main input video is selected using IC200 (LA73031V video mux) under the control of IC205 & IC208 (74HC595 serial to parallel converters, controlled by SPI Clk, Data & Vid IO Mux Latch). Inputs are selected using INSEL1, INSEL2, INSEL3 (Z2 INSEL1, Z2INSEL2, Z2INSEL3 for Zone 2 via IC203 – LA73031V video mux).
As there is only one sync separator within each LA73031V, it is necessary to select if this is used for S-video or composite (this means that once composite video is selected as the source, it is not possible to autodetect S-video) - SYNC CTL selects, low = Svideo, high = composite.
There are two buffered (IC201 & IC202 – BA7623F video buffers) tape outputs, VCR & PVR which can be muted with VCR Mute & PVR Mute respectively through a transistor network. Each output is muted when that input is selected to prevent feedback, otherwise the output is a copy of the composite or S-video signal going to the main zone.
Zone 2 video is buffered through IC204 (BA7623F video buffer) and can also be mute, if required using the signal Z2Vid Mute & a transistor network.
When S-video or composite inputs are not used, V MUX STBY should be asserted high. Note: this will disable both the main Zone & Zone 2 S-video & composite muxes.
Video Input Truth table: (Z2)INSEL1 (Z2)INSEL2 (Z2)INSEL3 (Z2)SYNCCTL 0 0 0 1 AV comp 0 0 1 1 SAT comp 0 1 0 1 DVD comp 0 1 1 1 PVR comp 1 0 0 1 VCR comp 0 0 0 0 AV S-vid 0 0 1 0 SAT S-vid 0 1 0 0 DVD S-vid 0 1 1 0 PVR S-vid 1 0 0 0 VCR S-vid
Volume control for Zone 2 & 3 uses IC300 & IC301 (BD3812F volume controls) via a two-wire interface (Zone SPI Clk & Zone SPI Data). IC300 has address D2, D1=1, IC301 has address D2, D1=0. The volume controls can be muted from IC208 (Serial to parallel converter) using Z2 vol mute or Z3 vol mute. The outputs are also relay controlled for powerup/down with Z2 Mute & Z3 Mute directly from the PW338 using RLY300 & RLY301 as shunt relays.
The +7VA & -7VA required for the BD3812F volume controls is derived using REG300 (LM1117) & REG301 (LM337LZ) from the +15V & -15V from L123.
L114AY – Video input – output
This PCB selects on of 8 external digital inputs or one of two internal digital inputs & generates BClk, WClk & MClk for the DSP (see L156) & DAC (see L117). It also generates the clocks for the ADC (see L116) when the unit is in ADC mode.
The CD, AV & DVD inputs use coaxial connector SKT100 and feed into IC200 & IC201 (DS9637ACM buffers). The Tape, SAT, VCR & PVR inputs use optical connectors RX100, RX101, RX102, RX103. The outputs are padded down to give 3v3 outputs. There is also the Aux input which can be selected (see L117), the Net input (see L119) and the HDMI SPDIF (see L122).
One of these inputs is then selected using IC202 & IC203 (74HC151 8-1 mux) under the control of IC204 (74HC595D serial to parallel converter) controlled by AN SPI Clk, AN SPI Data & Dig Mux Latch.
The selected input is fed to IC100 (WM8805 SPDIF Rx/Tx) which is controlled from the PW338 via AN SCL, AN SDA & SPDIF /RESET. IC100 generates 8805MClk, 8805BClk & 8805WClk. Also, SPDIF Out which is a de-jittered SPDIF stream which is then buffered by IC103 part A, B, C & D (parts E & F are unused) to give both the optical output (TXC100) & 75ohmcoaxial output (SKT101).
The selected input is also fed to IC205 part A (74HC123D monostable, part B unused) which gives a high output from pin 13 (SPDIF_PRESENT to the PW338) if an SPDIF signal is present.
BClk=64* WClk MClk=128*WClk (192kHz/176.4kHz), 256*WClk (96kHz/88.2kHz), 512*WClk (48kHz/44.1kHz) – this clock is used by the PSU to synchronise the switchers.
IC105 (XC95C36 Xilinx) generates a pre-delayed SPDIF stream from the HDMI clocks (only MClk & WClk used) as the HDMI SPDIF is turned off during HD audio transfer & the WM8805 does not have a zero delay PLL. IC104 (74HCT157 Quad 2-1 mux) can also be used to re-direct the clocks from the HDMI into the system.
IC100 (WM8805) can also operate in master mode to generate clocks for the ADC when processing an analogue input.
3V3D is generated locally on the PCB from 5V_1 using REG200 (LM1117).
L115AY Digital Input – Output board
This PCB selects the analogue input for the main zone & Zone 2/3 and also digitises the analogue input for processing by the DSP / transmission over SPDIF.
One of seven phono inputs (Tape, CD, AV, DVD, SAT, VCR, PVR), Aux (external) input (see L127), AM/FM & DAB(internal)/Sirius(external) inputs (see L118), Net (internal) input (see L119) and Phono (see L117).
The input for the main zone is selected using IC200, IC208, IC205, IC209 (74HC4051D 8-1 mux) under the control of IC101 & IC102 (74HC595 serial to parallel converter), controlled by AN SPI Data, AN SPI Clk & A In Mux Latch. The muxes operate on the virtual earth of IC203 part A (left channel) & IC206 part A (right channel), both NJM2114 op amps, inverting the signal. Part B of these two op amps re-invert the signal (correct phase) and this output is used by the ADC & the direct path – Main L & Main R.
IC202 (NJM2114 op amp) inverts the original output of the mux (correct phase) to provide the three tape outputs, Tape Out, PVR Out & VCR Out. Each of these has individual mutes – IC201, IC204, IC207 (DG413DY analogue mux) which mutes the output if that input is selected to prevent feedback. Otherwise, the output is the selected input. The signals for these mutes, /Tape Mute, /PVR Mute, /VCR Mute come from IC102 (74HC595 serial – parallel converter).
Selection of the Zone 2 input is very similar, using IC300, IC303, IC302, IC304 (74HC4051 8-1 muxes) and IC301 (NJM2114 op amp).
The Main L & Main R are connected to input AIN1A/AIN1B of IC100 (CS5345 ADC). Aux L & Aux R are also connected to AIN4A/AIN4B as this is configurable as the MIC input and can provide power from pin25 of IC100. the ADC is controlled from the PW338 via AN SCL & AN SDA. ADC/RESET also comes from IC102, so the ADC can be held in reset when not being used.
The ADC always operates in slave mode and will sample at the rate dictated by the incoming clocks from L115 (buffered on L122). ADC Data is sent to L115 so that it can be transmitted by the SPDIF transmitter and selected for input to the DSP.
+12VA (REG301 LM7812) & -12VA (REG304 LM7912) for the local op amps are derived from +15V & -15V from L123. +5VA (used by the ADC) is derived from the +12VA with REG302 (LM1117). +3V3D (used by the ADC) is derived from the +12VA with REG300 (LM1117). +3V3A (REG303 LM1117) & -3V3A (REG305 LM337LZ) for the muxes are derived from +5VA & -12VA.
L116AY Analogue input board
Truth table MUTE Main Asel Z2 Asel ADC
/RST VCR PVR TAPE 5 4 3 2 1 0 5 4 3 2 1 0 x x x x x x x x x x 1 1 1 0 0 0 Z2 CD x x x x x x x x x x 1 1 1 0 0 1 Z2 AV x x x x x x x x x x 1 1 1 0 1 0 Z2 SAT x x x x x x x x x x 1 1 1 0 1 1 Z2 DVD x x x x x x x x x x 1 1 1 1 0 0 Z2 VCR x x x x x x x x x x 1 1 1 1 0 1 Z2 PVR x x x x x x x x x x 1 1 1 1 1 0 Z2 TAPE x x x x x x x x x x 0 0 0 1 1 1 Z2 Phono x x x x x x x x x x 0 0 1 1 1 1 Z2 Aux x x x x x x x x x x 0 1 0 1 1 1 Z2 GND x x x x x x x x x x 0 1 1 1 1 1 Z2 AM/FM x x x x x x x x x x 1 0 0 1 1 1 Z2 DAB/Sirius x x x x x x x x x x 1 0 1 1 1 1 Z2 Net x x x x x x x x x x 1 1 0 1 1 1 Z2 Spare x x x x x x x x x x 1 1 1 1 1 1 Z2 GND x x x x 1 1 1 0 0 0 x x x x x x Main CD x x x x 1 1 1 0 0 1 x x x x x x Main AV x x x x 1 1 1 0 1 0 x x x x x x Main SAT x x x x 1 1 1 0 1 1 x x x x x x Main DVD x x x x 1 1 1 1 0 0 x x x x x x Main VCR x x x x 1 1 1 1 0 1 x x x x x x Main PVR x x x x 1 1 1 1 1 0 x x x x x x Main Tape x x x x 0 0 0 1 1 1 x x x x x x Main Phono x x x x 0 0 1 1 1 1 x x x x x x Main Aux x x x x 0 1 0 1 1 1 x x x x x x Main GND x x x x 0 1 1 1 1 1 x x x x x x Main AM/FM x x x x 1 0 0 1 1 1 x x x x x x Main DAB/Sirius x x x x 1 0 1 1 1 1 x x x x x x Main Net x x x x 1 1 0 1 1 1 x x x x x x Main Spare x x x x 1 1 1 1 1 1 x x x x x x Main GND x 1 1 0 x x x x x x x x x x x x Tape out mute x 1 0 1 x x x x x x x x x x x x PVR out mute x 0 1 1 x x x x x x x x x x x x VCR out mute x 1 1 1 x x x x x x x x x x x x No loop mute 0 x x x x x x x x x x x x x x x ADC reset 1 x x x x x x x x x x x x x x x ADC running
This PCB converts the digital audio from the DSP (see L156) to analogue audio. It also configures the use of channels 6 & 7, has the headphone amp, has the RIAA equaliser for the Phono input and handles the multi-channel analogue input.
The phono amplifier is a standard RIAA response and is intended for use with MM cartridges, 5mV (check this!) output. C128 & C129 are important to prevent the DC offset of IC100 (NJM2114 op amp) from causing problems.
IC101 forms the basis of the headphone amplifier. The output of this section goes to L127.
IC300 (CS4385 8-channel DAC) takes multichannel data (Data LR, Data CSw, Data SlSr, Data SblSbr) from the DSP (L156) in addition to clocks (DAC MClk, DAC BClk, DAC WClk) from L115 (buffered on L122). Control of the DAC is via AN SDA, AN SCL (from the PW338) and DAC /RESET (from IC212).
The balanced outputs from the DAC are filtered by IC400, IC401, IC402, IC403 (NJM2114 op amps). All channels are identical except for the subwoofer, which has 10dB (check this!) gain.
Left & right inputs to IC204 (CS3318 volume control) are multiplexed between the filtered DAC output, the Main L & Main R direct analogue inputs (from L116) and the left & right multichannel inputs (SKT200) with IC200 (74HC4052 dual 4-1 mux). This mux operates on the virtual earth of IC201 (NJM2114 op amp) and also provides the signals Mux L & Mux R.
The centre input to IC204 (CS3318 volume control) is multiplexed between the filtered DAC output and the centre multichannel inputs (SKT200) with IC203 (74HC4053 triple 2-1 mux). This mux operates on the virtual earth of IC205 part A (NJM2114 op amp).
Subwoofer, surround left & surround right inputs to IC204 (CS3318 volume control) are multiplexed between the filtered DAC output and the subwoofer, surround left & surround right multichannel inputs (SKT200) with IC214 (74HC4053 triple 2-1 mux). This mux operates on the virtual earth of IC201 (NJM2114 op amp) part A (subwoofer) & IC207 (NJM2114 op amp - Surround left & surround right).
IC213 selects between the filtered DAC output of surround back left / right, surround back right / left multichannel inputs, Z2 L / Z2R and Mux L / Mux R. This allows the use of channels 6 & 7 as either surround back left/right in the main zone, or powered Zone 2 outputs, or bi-amped left/right in the main zone. This mux operates on the virtual earth of IC209 (NJM2114 op amp).
IC204 (CS3318 volume control) is controlled by AN SCL, AN SDA (from the PW338) and VOL /RESET & VOL /MUTE from IC212.
L117AY Analogue output
Truth table Sel0 Sel1 Sel2 Sel3 Sel4 Vol /RST Vol /Mute DAC /RST 0 0 0 0 0 1 1 1 DAC output 1 0 x x x 1 1 1 L/R analogue direct 0 1 1 1 0 1 1 1 MCH output x x x 0 1 1 1 1 Sb=Zone 2 x x x 1 1 1 1 1 Sb=L/R x x x x x 0 x x Volume control reset x x x x x 1 0 x Volume control mute x x x x x x x 0 DAC reset
The output of the volume control is buffered through IC202, IC206, IC208, IC210 to remove any DC offset before going to CON100 (connection to the power amp) and SKT100 & SKT100 phono outputs sockets. Shunt relay muting is provided for power on/off, controlled from the PW338 (Main mute & Sblr/Sbr mute).
This PCB handles the following functions: RS232 communication with the PW338 iPod RS232 control (compatible with rLead & rDock) Sirius satellite radio (US) Z1, Z2, Z3 12V triggers DAB AM/FM Z1, Z2, Z3 IR inputs.
CON102 & IC102 (MAX3232 RS232 converter, part1) provide the RS232 communication with the PW338 – used for RS232 control or updating. Note, the signals RS232 Tx & RS232 Rx are labelled relative to the PW338, so RS232 Tx is the Tx FROM the PW338.
CON105 & IC102 (MAX3232 RS232 converter, part2) provide the iPod RS232 communication. Pin 9 of CON105 (/iPod Present to PW338) is taken low when an rLead is connected. Note, the signals iPod Tx & iPod Rx are labelled relative to the UART (IC403, L122), so iPod Tx is the Tx FROM the UART.
SKT101 provides the Sirius RS232 communication. Note, the signals Sirius Tx 232 & Sirius Rx 232 are labelled relative to the UART (IC403, L122), so Sirius Tx 232 is the Tx FROM the UART. SKT101 also provides the +5V for the Sirius Home Connect module, so the module does not require external power. This power comes from the +5V_1 (L123) and is connected to pins 1 & 2 of SKT101 as power & host presence. Analogue audio also passes through this socket, so this is the only connection to the Sirius module.
There are three triggers, Zone1 , Zone 2, Zone 3. These give a 12V 100mA output when activated from IC101 (74HC595 serial to parallel converter). The signals Z1 Trig, Z2 Trig & Z3 Trig are active high.
DAB uses the Gyrosignal 1122 module. As this module is normally controlled via RS232, a CPLD, IC100 (XC95C36 Xilinx) is used to provide I2C control from the PW338 (DAB SCL & DAB SDA). Due to an issue with the Gyrosignal implementation of I2C within their CPLD, IC103 (SN74HC1GU04 single inverter) is required to invert the DAB SCL signal. The DAB module gives an analogue output which is buffered through a ground balancing circuit (IC301 NJM2114 op amp) – this section is also used for the Sirius analogue output. DAB /RESET comes from IC101 (74HC595).
AM/FM uses the ALPS module. Different modules are fitted depending on region – Europe (with RDS), US (no RDS), Japan (different FM range). Control is direct from the PW338, FM CE, SPI Data, SPI Clk. Also, /RDS On from IC101 (74HC595) is used to turn off the RDS chip in EU modules when the AM band is used (the RDS chip running on AM interferes with AM performance). RDS Int & Data come from the Alps module to the PW338 for
L118AY – IR – Trig – DAB/FM - RS232
EU FM transmissions carrying RDS data. VSM goes to an ADC on the PW338 and provides a signal strength indication. The AM/FM module gives an analogue output which is buffered through a ground balancing circuit (IC302 NJM2114 op amp).
IR from the front panel comes onto this board from L126 and goes through a re-modulator circuit (IC200 LMC555) as it has been demodulated on the front panel. This signal, Z1 remod, goes through SKT200 such that inserting a plug into SKT200 will stop this signal (to prevent conflicting signals if a Zone 1 external IR sensor is used) from going to LED200 and then being demodulated by RX200. Zone 2 (SKT102) & Zone 3 (SKT103) IR inputs drive LED201 & LED202 which are demodulated by RX201 & RX202. Zone 1, Zone 2 & Zone 3 are also multiplexed together to give IR Out through TR207 & SKT104.
The ground balancing circuit uses +5V_1 from L123 and generates -5V from IC303 (SP6661EN charge pump). The AM/FM module uses +9V_FM, generated with REG202 (LM317) from +15V (from L123). +12V_IR is generated from +15V (L123) using REG200 (LM7812) and runs the IR output & 12V triggers. +5V_STBY (L123) generates +3V3_STBY with REG201 (LM1117) – used by IC102 (MAX3232) so the RS232 comms are still available in standby. +3V3_D is generated from +5V_1 (L123) with REG203 and is used by the DAB module.
This PCB handles the network connectivity & USB support. Telnet control (Ethernet to RS232 tunnelling) is also handled by this PCB.
IC102 (DM850 audio processor) does not have any internal boot code, upon being powered, it starts the BFL (First level bootloader) from the FLASH memory IC202 (S29GL064A90TFIR30). This then executes the BSL (second level bootloader) which brings up the network support. The second level bootloader then executes the application. The BFL should never need to be updated and as such will not be included in the standard upgrading application.
The FLASH memory is also used to store settings, such as the Arcam specific Cardea keys & MAC address. Note: if the FLASH device is ever changed, it is essential that the original MAC address be programmed into the unit so that the user does not lose and internet radio stations/favourites groups. The device also uses SDRAM (not until the BSL executes) – IC200 (IC42S16800-6T(G)).
Wifi connectivity is via an Edom module and plugs into CON300. Note: this module is specific to this unit and cannot be substituted, spares must come from Arcam.
Wired Ethernet uses IC400 (DM9161A MAC), L401 (TS6121C magnetics). The Ethernet connector (CON400) does not have any link or act LEDs as these were thought to be potentially annoying in an AV environment.
In addition to the SPDIF audio output, there analogue audio is generated from NET MClk, NET BClk, NET WClk & NET Data0 using IC501 (CS4345 DAC). IC500 (LM358AM op amp) buffers & filters the output of the DAC. The output can then be muted under control of the DM850 (/MUTE) and then ground balanced with IC502 (NJM2114 op amp).
The DM850 uses two switching regulators for generating the +3V3D (REG600) and 1V8 (REG601). IC601 (SP6661 charge pump) generates the - 5V used by the ground balancing circuit – IC601 has a 4V7 zener regulator circuit supplying it.
L119AY NETWORK
This PCB provides the connections between all the daughter cards, plus the main PCB (L122).
IC300 & IC301 (74HC244 buffers) take the clock signals (WClk, BClk & MClk) from L115 & DSP WClk Out & DSPBClk Out from L156 and buffer them to the ADC, DSP & DAC.
IC303 (74HC4040 divider) divides the MClk down to provide Clk PSU to sync the switchers on L123.
L121AY – Connection board
This is the main PCB with the PW338 handling the control of the entire unit, as well as video processing. HDMI Rx & Tx functions are performed on this PCB as well as video encoding & decoding.
IC200 is main PW338 micro/video processor. On sheet 4 the microprocessor interface is shown. The PW338 has no internal boot code, so relies on code in IC401 (39VF3201 FLASH) to run. IC401 is required to be pre-programmed with at least boot code. If this part requires replacement, it *must* be programmed with at least the boot code. If the FLASH is programmed with the boot code, upon starting up, the PW338 will send out a boot loader message on the RS232 port0 (sheet 3) at 115.2k baud, 8bits, no parity. If there is a problem with the DDR memory (IC600 & IC601 sheet 6) there will be a message sent along with the boot loader message. /AC present (low) and Poweron_reset (high) from IC402 (LM809M-2.93 – resets the micro if 3V3_PW338 drops below 2.93V) are also required for the PW338 to start.
IC400 (74HC4040 divider) pre-divides the wordclock so the PW338 (EXINT0) can measure the sampling frequency of incoming digital audio sources. RDS Int (from L119) is connected to EXINT1 as the RDS data is streamed out of the ALPS AM/FM module regardless of the readiness of the PW338.
IC403 is a quad UART to provide RS232 communication with the network (L119), the Sirius satellite radio (L118) & iPod (L118). All signal labels are with respect to the PW338.
Sheet 7 shows most of the connections to the daughter PCBs as well as the I2C control busses: EDID – used for the EDID dual port EEPROM (IC909, sheet 9) AN – Analogue control bus, L116 Analogue input & L117 Analogue output HDMI_Config – SiI9135 & SiI9134 x 2 & ADV7310 (sheet 5) DAB – DAB module (L118) & system EEPROM (IC706 sheet 7)
3 x 74HC595 (IC701, IC703 & IC704) provide additional control output signals.
The remaining control signals are on sheet 2. This sheet also shows the interface between the SiI9135 HDMI receiver (IC201) and the PW338. The audio outpus of IC201 go through L121 (Connection PCB) to L115 (Digital IO).
Sheet 3 shows the analogue video inputs. There are separate inputs for composite, S-video & component. The Y signal also is taken to a Sync input on the PW338.
Sheet 5 is the video output port. The digital video port of the PW338 is connected to the ADV7310 (IC501), SiI9134 (IC502) & SiI9134 (IC503). The ADV7310 converts the digital video to analogue video outputs for component, S-video & composite (depending on the resolution – up to 1080i for component, 480i/576i only for composite & s-video). The two SiI9134 parts convert the video data to HDMI serial data. While it is possible to have all
L122AY Main Board
video outputs active, resolution & copy protection limits apply. Also, when displaying 408i/576i the colour space requirements of the ADV7310 & SiI9134s are incompatible, so if an HDMI display is connected the analogue outputs are muted.
The PW338 can only output one clock pulse per pixel, so for 480i & 576i resolutions, a video clock doubler is required (IC504 ICS2402MLF) to convert the 13.5MHz pixel clock (Display Clk) to 27MHz (Display Clk2) under the control of Vid_Clk_Sw.
The output of the ADV73120 is filtered by IC500 (ADA4410). Also, the S- video signals are recombined to form the composite output signal (Cvid out). The outputs of this part are series terminated with 75ohms before going to L133 (component IO) & L114 (video IO) via L121 (connection PCB).
Sheet 9 shows the 5 HDMI inputs. The serial data differential pairs are multiplexed with IC901 & IC903 (PI3HDMI413). The DDC lines are multiplexed with IC907 & IC910 (DG408LDY) for connection with the dual port EEPROM (IC909) and the HDMI receiver (IC201). The CEC line is multiplexed with IC911 (DG408DLY) The +5V line is multiplexed with IC912 (DG408DLY) Hotplug out is controlled by IC900, IC904 & IC906 (74HCT08 AND gate) which give individual hotplug control & also global control with PW338 hotplug. All these multiplexes must operate together for an HDMI input to be correctly selected.
TMDS Mux Sel3 Sel2 Sel1 Sel0 0 0 0 0 SAT 0 0 0 1 AV 0 0 1 0 DVD 0 1 1 1 PVR 1 0 1 1 VCR 1 1 1 1 Blank
DDC/CEC/+5V Mux Sel2 Sel1 Sel0 0 0 0 Blank 0 0 1 AV 0 1 0 SAT 1 1 1 DVD 0 1 1 VCR 1 1 1 PVR
Hotplug Mux SelPVR SelVCR SelDVD SelSAT SelAV 0 0 0 0 0 Blank 0 0 0 0 1 AV 0 0 0 1 0 SAT
0 0 1 0 0 DVD 0 1 0 0 0 VCR 1 0 0 0 0 PVR
Sheet 10 shows the ESD protection devices (IC1000 & IC1004 CM2020) for the two HDMI outputs. There is also provision for turning off the 5V signal to the display device through FETs M1000 & M1001.
The two 120 way connectors on sheet 11 show all the connections between the L122 PCB and L122.
This conducts the output signals from the power amplifiers on both L125 and L129 to the speaker terminal blocks LS100 – LS103 inclusive, via 4 double pole relays RLY100 – RLY103. The 24V dc supply from the relays is fed from L129 via CON101 pin 18, returning to ground via pin 17. The relay switching transistors are TR100 – TR 103 and the logic level signals to control these also enter via CON101 pins 19 and 20. Note that the SBL and SBR channels are switched independently from the other 5 channels, as these can be re- assigned in software to support zone 2 in stereo if required.
Zobel networks, comprising 1 uH air cored chokes in parallel with 4R7 2 Watt resistors, are in series with all outputs to isolate the power amplifiers from capacitive cable loads which might otherwise provoke instability.
This contains all the power amplifier electronics for the Centre (C), Left Surround (LS) and Right Surround (RS) channels. It also contains the power supplies for all 7 channels, which are fed directly from the secondaries of the power transformer L951TX as raw AC, via CON106, to the bridge rectifiers DBR201 and DBR202 and two reservoir capacitor banks, C206/7 plus C210/213 for Vcc/Vee, and C214/5 plus C220/1 for +Vlo and –Vlo.
The power amplifier design is Class G, which is why two sets of power rails are employed; Vcc and Vee are approximately +/- 59V off load and +Vlo and – Vlo are approximately +/- 30V off load.
The rectified and smoothed power rails are fed to the lower power amp PCB L129, along with an AC power feed for checking the mains is present, via CON100.
CON103 is used to bring in the C, LS and RS line level input signals from the rest of the AVR via L129. It also imports +/-12V supplies for the front stage op-amps and +5V for the top heatsink temperature sensor IC400. Outputs comprise this sensor’s signal and two DC offset protection lines (ERR_POS and ERR_NEG), which are returned to the system microprocessor via L129.
CON105 carries the C, LS and RS outputs to the Speaker PCB L124. It also carries the speaker ground returns for all 7 channels back to the star ground point on L125.
All 7 power amplifiers are identical, except for the Centre channel where only one half of its set of the various dual driver ICs is used.
Each power amplifier is topologically split into two halves – the input stage IC, LM4702 high voltage driver IC and DC servo IC comprise the driver stage (e.g. U_driver_C); the power transistors plus their drivers and protection circuitry comprise the output stage (e.g. U_PA_C), as shown in the L125 block diagram.
L124AY – Speaker board
L125AY – Power amp upper
Additionally the 3 power amplifier channels in L125 share a common pair of power MOSFET lifters (the part of the block diagram shown as U_Lifter_C) which control the amount of output voltage fed to the collectors of the power transistors in the 3 power amplifiers.
The Centre channel Driver Stage starts with the balanced to unbalanced converter IC700B (one half of an NJM2114) which rejects common mode noise on the input when grounded to AGND_FF via the handbag link CON700. Its output feeds one half of the stereo high voltage driver IC (LM4702C - IC701) via the low pass network R706 and C704. The LM4702 is used in a non-inverting configuration and provides all the voltage gain of the system, set by R713 and R704. Pins 11 and 12 of IC701 feed the inputs of the negative and positive halves of the Output Stage. The dominant pole compensation is set by C705, C713/R714 provides some second order feedback in the audio band to provide a higher open loop gain at high audio frequencies and thus reduce hf distortion. R715 and R716 (without TR700 which is a “no fit”) provide some extra voltage to IC701’s negative supply at high negative output voltages via a bootstrap arrangement in the output stage to prevent premature clipping of the negative half of the output. Note that the heatsink of IC701 is connected to its negative rail – this must NOT be accidentally shorted to ground!
Good power supplying decoupling of IC701 is essential and is provided by C701, C708, C709, C712 and C714.
Note that the amplifier is DC coupled throughout. IC702B (one half of a TL072) has a very high input impedance and forms a ground referenced inverting integrator with R712 and C711; their time constant is approximately 1.5 seconds. Its output is fed back to the positive input IC701 via the attenuator R711 and R706 to keep the DC output of the amplifier close to zero. It can also correct moderate DC offsets appearing at the input of IC700B. Should these become excessive, or should a circuit fault cause significant DC at the loudspeaker output, then the error voltage at the output of IC702B will feed through to the system microprocessor via D700 (which works in conjunction with the similar diodes in the other power amplifier channels as a wired OR gate) to generate a system shut down signal.
NB. R702 will also mute the power amplifier electronically in the absence of the +/- 12V supply.
The Centre channel Output Stage comprises complementary triples in a classic emitter follower configuration, with enhancements to ensure near class A operation at power levels of up to about 10 watts. Both the positive and negative halves are essentially identical.
The pre-driver and driver transistors are connected to the high voltage rails Vcc and Vee (approx +/-59V). However because this is a Class G design the output transistors TR406A and TR409A normally run at half these voltages (+Vlift and –Vlift, approx +/- 30V) connecting to the +Vlo and –Vlo supplies via Shottky power diodes D100 and D101 shown on the main block diagram. When the amplifier is required to deliver more than about +/- 25V peak
(equivalent to about 30Watts rms into 8 ohms) then the lifters (fed from Vcc and Vee) are progressively powered on to maintain a constant 5V or so across the collector-emitter junctions of the output transistors.
Note that on L125 the lifter outputs are shared between all three power amplifiers for reasons of economy and space – whereas the lifters on the other 4 channels on L129 are only shared between two power amplifiers each. Since the worst thermal stress on the lifters occurs at output powers somewhat above 30W rms equivalent into 8 ohms, we do not recommend testing the amplifier for extended times with continuous signals in the 30 - 50 Watts range with all three channels (C, SL and SR) running simultaneously and driving into low impedances. This is especially true of square wave signals! The thermal sensor IC400 is located close to the lifter MOSFETs in order to monitor this condition.
The power transistors TR406A and TR409A have built in thermal compensation diodes (TR406B and TR409B) which form part of the biasing network. The thermal sense biasing transistors TR401 and TR416 are thus mounted adjacent to (and ideally in intimate contact with) the driver transistors TR403 and TR414 so that as they warm up the bias remains relatively stable. (In practice it rises somewhat, but predictably so, as the drivers warm up). The pre-drivers, TR400 and TR415, are in a DC feedback loop with TR401 and TR416, so no thermal drift in bias occurs from these. Bias is set by RV400; D403 and R421 ensure that no catastrophic increase in bias will take place if RV400 fails open circuit.
Optimum bias at quiescent operating temperature is measured across the two 0.1 ohm emitter resistors forming R408 – it is typically 15mV at the pins of C400. When setting up from cold a good starting point to achieve this is to first turn RV400 to minimum (i.e. fully anticlockwise) and then slowly turn it up to 6mV.
The transistors TR405A and B and their associated networks provide comprehensive two slope safe operating area (SOA) protection for the output devices. When the prescribed combination of voltage and current across TR406A or TR409A is exceeded, the relevant protection transistor conducts and shorts out the base drive to the associated pre-driver, thus limiting the dissipation in the output device. The output of each channel of the LM4702 is current limited to about 5-10mA so no damage can occur to it under these conditions. Note that if an output device fails short circuit then the 7 Amp fuse in its collector will fail – the driver transistors TR403 and TR414 will then try to take over and so are protected by 1 ohm fusible resistors in their collectors. Note that the heatsinks of the drivers TR403 and TR414 are “live” – an accidental short to ground here with a test probe will probably blow the associated 1 ohm fusible resistor.
Diodes D402 and D405 protect the output transistors from being reverse biased in the presence of inductive load “spikes”. Diodes D401A/B form part of a wired OR gate system with the other power amplifier channels on L124 and are used to drive the lifters connected to the collectors of TR406A and TR409A. R439 and C411 are part of a bootstrap network for the negative rail of IC701 and its associated pre-driver transistor TR415. R417 and C406 are
a Zobel network (sometimes called a Boucherot cell) to help compensate for inductive loads at high frequencies.
The Class G Lifters are in two complimentary halves – TR600, TR601 and TR602 plus p-channel power MOSFET M601 for the positive half, and TR603, TR604 and TR605 plus n-channel power MOSFET M603 for the negative half. They are arranged as CFPs (complementary feedback pairs) rather than plain emitter (source) followers so that the MOSFETs can be fully turned on without needing power supplies that exceed Vcc and Vee.
The two halves operate identically – we will examine the positive (top half) lifter to see how it works. With only small signals coming from the power amplifier, node PLD_C remains biased at about +20V (via the network R614, D600, R602., R603, R605) whilst node +VLIFT_C is held at approximately +30V (i.e. +Vlo less the 0.2V or so dropped across the Shottky power diode D100). The emitter of TR602 meanwhile is at about +24.5V, so TR602 is turned hard off. Thus the base of TR600 is connected via R600 to Vcc and the emitter is at Vcc – 0.6V. Vgs of M601 is thus -0.6V which is well under the approx -2.5V required to turn on M601.
When the voltage at node PLD_C exceeds approximately +25V this is enough to turn on TR602. When about 3V is developed across R600 this is enough to turn on M601 which conducts until the voltage at the emitter of TR602 has risen enough to stabilise the system. The output voltage then can rapidly track the input (plus about 5V) as required, reverse biasing the Shottky power diode D100 and drawing the collector current for TR406A via M600 and the +Vcc supply. The complementary emitter follower TR600, TR601 ensured the gate capacitance of the MOSFET can be both charged and discharged very quickly. C605 provides fast local decoupling to minimise switching transients.
This contains the power amplifier electronics for the Left (L), Right (R), Surround Back Left (SBL) and Surround Back Right (SBR) channels. It also contains housekeeping logic for the amplifier protection system and power drive circuits for the protection relays and cooling fans.
The power amplifiers are essentially identical to those in L125, except that the lifter circuits are only shared between pairs of power amplifiers (L and SBL, R and SBR respectively) rather than all three channels in L125. They receive their raw DC power voltages from L125 via CON100. Please refer to the description of the Centre Channel (C) power amplifier (in L125) for a detailed understanding of the circuitry of the power amplifiers in L129.
CON102 carries the L, R, SBL and SBR output signals to the speaker board L124. It also delivers +24V DC power and logic level switching signals to the 4 speaker relays on L124. NB - the ground returns shown on CON102 do not carry L129’s main speaker currents back to the star point (which is located on L125) but are merely used for the L, R, SBL and SBR amplifiers’ optional extra Boucherot networks located on L124.
Note that it is L129 which communicates with the rest of the receiver, via two ribbon cables connected to CON101 and CON 103. CON 101 receives 7 line level input signals, and low voltage supplies (+12V, -12V and +5V) from L117. CON101 also inputs the speaker relay mute signals for L124. CON103 supports temperature and DC offset monitoring for L125 and L129, plus a fan drive signal, sent to and from the system microprocessor on L122, via L121. The heatsink temperature monitors on L129 are IC800 and IC900; these are located between the relevant pairs of lifter power MOSFETs.
TR102 provides nominal +24V power to the output relays on L124, via the unregulated +30V supply on L125. The 27V zener diode DZ102 prevents excessive voltage being applied to the relays in the event of high mains voltages.
REG 101 is not normally used as links CON109 and CON110 are omitted in production. It provides +5V for the on board logic and temperature sensors if no +5V line is present (e.g. during development testing).
TR1003A/B and TR1001 together make a fan driver with a DC gain of 10, so it can be triggered with a 3V3 microprocessor signal. Power comes from the unregulated +Vlo supply (approx +30V). The fans are two 12V DC units connected in series fed from CON107 and CON108.
IC1000 is a triple 3-input NAND gate. To switch on (i.e. unmute) the speaker relays, all 3 inputs on IC1000B (for LSB and RSB channels) and/or IC1000C (for the other 5 channels) must be high. The 3 inputs come from: (a) the AC present detector based around TR1002 and IC1000A, (b) the ERR_NEG and ERR_POS detector, based around TR1004A/B, which detects excessive DC offsets on any one or more of the 7 power amplifier channels and (c) the ~MUTE_SB and ~MUTE_REST lines under the control of the system microprocessor.
L129AY – Power Amp lower
This PCB handles the VFD, keyboard scan, IR reception for the front panel & power LEDs.
The micro is an Atmel AT91SAM7S32 (IC101) which must be initially programmed via the Atmel/Segger debugger via CON101. Subsequently, the micro can be reprogrammed from the PW338 using the Arcam upgrader utility over RS232. The bootloader should never need to be updated and as such will not be included in the standard upgrading application.
Communication with the PW338 is via RS232 – IC101 sends information on keypresses to the PW338 & receives information to display & brightness commands from the PW338 – FP_TX & FP_RX. Note these signals are labelled with respect to the PW338.
IC101 uses +3V3_PW338 so is powered in standby. It has an internal 1V8 regulator which generates VDD_OUT (1V8, pin 8) which is decoupled & powers the core & PLL of IC101 (pins 18, 41 & 48).
The VFD (DISP100) is driven from serial data SIN from IC101 (AT91SAM7S32 micro). The serial data is gated through IC102 (74HC08 quad NAND gate, parts C & D unused) controlled by SIN1_CTL & SIN2_CTL from IC101 to provide dimming of the display. The output data from IC102 is clocked into the display with the signal CLK from IC101 and is latched into the display during the blanking period (LAT & BLK).
The VFD filament drive is synchronous with the display update. Signals FClock1 & FClock2 are 180deg out of phase and drive IC100 (AD8532 op amp) to give a 6V oscillating drive to the two ends of the filament (from +6V_1 – L123). The HT is provided direct from L123 (+40V_VFD). +6V_1 & +40V_VFD are not present in standby.
IR decoding (RX100) is powered by +5V_STBY, allowing IR reception when in standby. The signal pass through L121 (Connection) to L118 (Trigger) before going to L122 (Main PCB).
The power LEDs are fitted to a small snap-off PCB that is connected via a 3 wire lead. Green LED when the unit is on, Red when in standby, both during power on.
L126AY – Front Panel
This PCB handles the auxiliary input & headphone output.
SKT101 carries the headphone output from L117 (Analogue output). There is also a switch to sense the headphones being inserted. The pullup resistor for this is on L122, so if L127 PCB is not fitted or the cable not fitted, the unit will sense the headphones are permanently inserted.
SKT100 is the microphone, auxillary input (to L116 Analogue input) & also has an optical input for digital sources (Aux SPDIF to L115 Digital input) using a 3.5mm optical lead.
This PCB handles the audio decoding of digital inputs & processing of digitised analogue sources.
IC100 (ADSP-21366 DSP) handles the main decoding, including the new HD formats. Data is either from I2S Data (SPDIF/ADC data from L115) or MCH Data0, MCH Data1, MCH Data2, MCH Data3 from L122 (Main PCB). In both cases, the clocks DSP WClk, DSPBClk & DSP MClk are required.
The code for IC100 is held in IC103 (S29AL016D FLASH). The DSP also requires SRAM (IC101, IC104 71V424S SRAM). The address/data bus is multiplexed through IC102 & IC106 (74LVC573 buffers) controlled by ALE. Additional memory decoding is handled by IC105 (74LVC139 2-4 decoder).
R121 & R103 (0R0) should be fitted to allow the DSP to boot in SPI mode.
R117 (4k7) sets the internal clock multiplier to 16:1 (16*20MHz = 320MHz).
IC201 (ADSP-21367 DSP) handles the post-processing & room EQ. Data is sent in multichannel format regardless of the input between IC100 & IC201 (DSP2 LR, DSP2 LsRs, DSP2 CSw, DSP2 SblSbr). The data is clocked in using DSP2 BClk & DSP2 WClk, generated by IC100 & DSP MClk from L121.
Data is then clocked out to the DACs (Data LR, Data SlSr, Data CSw, Data SblSbr) with clocks DSP BClk Out, DSPWClk Out which are buffered on L121 before going to L117 (Analogue Out).
Communication with the PW338 is via a single SPI bus: DSP Clk - clock DSP MISO – data from PW338 DSP MOSI – data to the PW338 DSP1 /CS – select DSP1 DSP2 /CS – select DSP2 DSP1 FLAG0 – signal back to PW338 DSP2 FLAG0 – signal back to the PW338 Note: DSP reset is by asserting both /CS lins low simultaneously (IC107 74LV1G32 single Or gate).
L127AY Front Input
L156AY – DSP board
Power for the DSPs comes from two regulators 3V3 (REG300), further regulated to 1V2 (REG301). Both are heatsinked.
ISSUE
L113 C1 Component IO_D0.SchDoc
A & R Cambridge Ltd. Pembroke Avenue
Cambridge CB5 9QR Waterbeach
SPI Data
16V X7R
C141 100N
/EN0 SEL0
/EN1 SEL1
/EN2 SEL2
SA T
IN A
V IN
D V
D IN
V C
R IN
PV R
IN O
U T
EN0 SEL0 EN1 SEL1 EN2 SEL2 0 0 1 x 1 x SAT 0 1 1 x 1 x AV 1 x 0 0 1 x VCR 1 x 0 1 1 x DVD 1 x 1 x 0 1 PVR 1 x 1 x 1 x BLANK
+15V
-15V
0W063
R109
Y
Pb
Pr
Y
Pb
Pr
Y
Pb
Pr
24/9/0707_E165
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20
CON100
MOLEX
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20
CON101
MOLEX
1
23
4
FIX100
1
ISSUE
L114_C1_Video IO_D0.SchDoc
A3
ARCAM
Z2 /Mute Z3 /Mute Z3 L Z3 R Z2 L Z2 R Zone SPI data Zone SPI Clk
Z2 Vol Mute Z3 Vol Mute
Zone 2 Volume & PSU L114_C3_zone_vol_PSU_D0.SchDoc
0W063
SPI Clk
Video Mux L114_C2_Video Mux_D0.SchDoc
Vid IO Mux Latch SPI Data SPI Clk
Z2 /Mute Z3 /Mute Z3 L Z3 R Z2 L Z2 R
Zone SPI Clk Zone SPI data
Z2 R
Z2 L
B.0NC Sync control added, C/S-vid mutes removed11/06/0707_E159
C.0PK PCB change only18/12/0708_E012
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20
CON100
MOLEX
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20
CON101
MOLEX
1
23
4
FIX100
1
ISSUE
L114_C2_Video Mux_D0.SchDoc
Z2 C vid out
Z3 Vol Mute
C250
100N
Pin4 low = Svid/CVBS (high=component) Pin7 (low = 0dB gain), high = 6dB gain
Pin28 (low = LPF off), high = LPF on Pin23 low = on, high = standby
0W063 R238 39R 0W063
P291
P211
P217
P221
P242
P245
P247
P280
P283
P286
P292
VDET IN 33
LPF CTL 28
VDET IN 33
LPF CTL 28
AV Cvid
SAT Cvid
DVD Cvid
PVR Cvid
VCR Cvid
AV Y
SAT Y
DVD Y
PVR Y
VCR Y
AV C
SAT C
DVD C
PVR C
VCR C
Z2 S-vid C Out
Z2 S-vid Y Out
Z2 C vid out
P288
ISSUE
L114_C3_zone_vol_PSU_D0.SchDoc
Contact Engineer: L114CT03/07/2008
+7VAD2, D1 = 1 AGND
-7VAD2, D1 = 0
Z2 /Mute Z3 /Mute
L115_C1_Digital IO_E0.schDoc
Digital IO
ADC Data SPDIF I2S Data
8805 MClk 8805 WClk 8805 BClk
SPDIF Out
SPDIF Out
AN SDA
V C
C 1
G N
D 2
O/P 3
DGND
P135
16V X7R
C122 100N
16V X7R
C123 100N
0W063 R109
07_E092
HC-49
D.0
CLK Sel low=8805, high=HDMI
CPLD & Mux added fro HBR audio31/1/08NC
0W063
R145
I/O23 I/O22 I/O21 I/O20 I/O19
TCK11
TDI9
TDO24
TMS10
08_E034
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON103
SAMTEC
E.0R148 added for CMOS input option on 8805, CON103 changed to socket08_E125 PK
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20
CON100
MOLEX
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20
CON101
MOLEX
1
23
4
FIX100
1
0W063
R148
L115_C2_Mux_E0.SchDoc
A3
ARCAM
S7 S6 S5 S4 S3 S2 S1 S0 x x 0 0 0 0 0 0 CD In x x 0 0 0 0 0 1 AV In x x 0 0 0 0 1 0 DVD In x x 0 0 0 0 1 1 Not used x x 0 0 0 1 0 0 HDMI SPDIF x x 0 0 0 1 0 1 AUX SPDIF
x x 0 0 1 1 1 1 HDMI MCH SPDIF
P204 P205
DS 14Q015
S0 S1 S2
GND 4
GND 4
Mux Out
16V X7R
C203 100N
16V X7R
C204 100N
x x 0 1 0 1 1 1 Not used x x 0 1 1 1 1 1 Tape In x x 1 0 0 1 1 1 SAT In x x 1 0 1 1 1 1 VCR In
DGND
DGND
+5V_1
+5V_1
0W063
R200
1K0
0W063
AN SPI Data
HDMI MCH SPDIF
SPDIF_Present
IC205C
74HC123D
x 1 x x x x x x ADC Data x 0 x x x x x x SPDIF Data
x x 0 0 1 1 1 0 NET SPDIF
x x 1 1 1 1 1 1 NONE x x 1 1 0 1 1 1 VCR In
02/03/0707_E092
I04
I13
CLK Sel CLK Sel
0 x x x x x x x 8805 CLK 1 x x x x x x x HDMI Clk
D.0CPLD & Mux added fro HBR audio31/1/08NC08_E034
None to this sheet08_E125 PK E.015/05/08
ISSUE
L116_C1_Analogue Input_D1.SchDoc
A3
ARCAM
Z2 A Sel0 Z2 A Sel1 Z2 A Sel2 Z2 A Sel3 Z2 A Sel4 Z2 A Sel5
/Tape Mute /PVR Mute
Main A Sel0 Main A Sel1
Main A Sel2 Main A Sel3 Main A Sel4 Main A Sel5
ADC /RESET /VCR Mute
+3V3D
+3V3D
DGND
DGND
PVR L
CD R
AM/FM L DAB/Sirius L NET L
AV R SAT R DVD R VCR R PVR R TAPE R Phono R AUX R iPod R AM/FM R DAB/Sirius R NET R
Main R Main L
/Tape Mute /PVR Mute /VCR Mute
Tape Out L Tape Out R PVR Out L PVR Out R VCR Out L VCR Out R
Main A Sel1 Main A Sel2 Main A Sel3
Main A Sel0
S pa
re L
S pa
re R
S pa
re L
S pa
TAPE L
TAPE R
VCR L
VCR R
Z2 L Z2 R
+3V3D
+3V3D
DGND
DGND
AGND
ADC Data
ADC /RESET
/Tape Mute /PVR Mute /VCR Mute
Tape Out L Tape Out R PVR Out L PVR OUT R VCR Out L VCR Out R
Z2 L Z2 R
Main A Sel0 Main A Sel1 Main A Sel2 Main A Sel3 Main A Sel4 Main A Sel5
VCR Out L VCR Out R
PVR Out L PVR Out R
Tape Out L Tape Out R
AGND
AGND
JYE TAI
Aux R
Aux L
CD L AV L SAT L DVD L VCR L PVR L TAPE L Phono L AUX L iPod L AM/FM L DAB/Sirius L NET L
CD R AV R SAT R DVD R VCR R PVR R TAPE R Phono R AUX R iPod R AM/FM R DAB/Sirius R NET R
CD L AV L SAT L DVD L VCR L PVR L TAPE L Phono L AUX L iPod L AM/FM L DAB/Sirius L NET L
CD R AV R SAT R DVD R VCR R PVR R TAPE R Phono R AUX R iPod R AM/FM R DAB/Sirius R NET R
Main R
Main L
P128 P127 P129 P130 P131 P132 P133 P134
P126
AGND
0W063
33R
P138
ECO984
TOOL100
TOOL101
TOOL102
TOOL103
FID100
FID101
B.0PK 02/03/07 PCB clearence rule update, R110 > 12k (mic bias), IP conns added
Was iPod L
Was iPod R
PH
CON104
JST
PH
CON105
JST
PH
CON103
JST
AGND
AGND
07_E160
Blank AVR002 Analogue In PCBL116PBPCB100 1FIX101
1
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20
CON100
MOLEX
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20
CON101
MOLEX
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20
CON102
MOLEX
1
23
4
FIX100
1
ISSUE
L116_C2_Main Zone Tape_D1.SchDoc
AGND AGND AGND AGND AGND
+12VA
Main A Sel2
Main A Sel1
Main A Sel3
Main A Sel0
0W125
R202
47R
0W125
R211
47R
0W125
R225
47R
0W125
R227
47R
0W125
R239
47R
0W125
R251
47R
ECO984
AV L SAT L DVD L VCR L PVR L TAPE L
Phono L AUX L iPod L IP AM/FM L DAB/Sirius L NET L Spare L
CD R AV R SAT R DVD R VCR R PVR R TAPE R
Phono R AUX R iPod R AM/FM R DAB/Sirius R NET R Spare R
Main L
Main R
C.0PK 16/01/08 Layout change only08_E014
D.0PCB change only08_E126 PK 15/05/08
D.1NC 25/07/08 R217, R228 > 3k9, +ve opamp input 4k7s > 0R, C > NF
0W063
R217
3K9
0W063
R228
3K9
NF
NF
NF
NF
0W063
L116_C3_Zone 2 & PSU_D1.SchDoc
AGND
AGND
AGND
AGND
+12VA
Z2 A Sel2
Z2 A Sel3
Z2 A Sel3 Z2 A Sel4
Z2 A Sel0 Z2 A Sel1 Z2 A Sel2
CD L
CD R
TAPE R
A.0.2INITIAL RELEASEPK 26/09/06
ADC Mute Main ASel Z2 Asel
x x x x x x x x x x 1 1 1 0 0 0 Zone2 Input CD /RST VCR PVR TAPE 5 4 3 2 1 0 5 4 3 2 1 0
x x x x x x x x x x 1 1 1 0 0 1 Zone2 Input AV x x x x x x x x x x 1 1 1 0 1 0 Zone2 Input SAT x x x x x x x x x x 1 1 1 0 1 1 Zone2 Input DVD x x x x x x x x x x 1 1 1 1 0 0 Zone2 Input VCR x x x x x x x x x x 1 1 1 1 0 1 Zone2 Input PVR x x x x x x x x x x 1 1 1 1 1 0 Zone2 Input TAPE x x x x x x x x x x 0 0 0 1 1 1 Zone2 Input Phono x x x x x x x x x x 0 0 1 1 1 1 Zone2 Input AUX x x x x x x x x x x 0 1 0 1 1 1 GND (was Zone2 Input iPod) x x x x x x x x x x 0 1 1 1 1 1 Zone2 Input AM/FM x x x x x x x x x x 1 0 0 1 1 1 Zone2 Input DAB x x x x x x x x x x 1 0 1 1 1 1 Zone2 Input NET x x x x x x x x x x 1 1 0 1 1 1 Zone2 Input SPARE x x x x x x x x x x 1 1 1 1 1 1 Zone2 Input GND x x x x 1 1 1 0 0 0 x x x x x x Main Input CD x x x x 1 1 1 0 0 1 x x x x x x Main Input AV x x x x 1 1 1 0 1 0 x x x x x x Main Input SAT x x x x 1 1 1 0 1 1 x x x x x x Main Input DVD x x x x 1 1 1 1 0 0 x x x x x x Main Input VCR x x x x 1 1 1 1 0 1 x x x x x x Main Input PVR x x x x 1 1 1 1 1 0 x x x x x x Main Input TAPE x x x x 0 0 0 1 1 1 x x x x x x Main Input Phono x x x x 0 0 1 1 1 1 x x x x x x Main Input AUX x x x x 0 1 0 1 1 1 x x x x x x GND (was Main Input iPod) x x x x 0 1 1 1 1 1 x x x x x x Main Input AM/FM x x x x 1 0 0 1 1 1 x x x x x x Main Input DAB x x x x 1 0 1 1 1 1 x x x x x x Main Input NET x x x x 1 1 0 1 1 1 x x x x x x Main Input SPARE x x x x 1 1 1 1 1 1 x x x x x x Main Input GND x 1 1 0 x x x x x x x x x x x x TAPE Out Mute x 1 0 1 x x x x x x x x x x x x PVR Out Mute x 0 1 1 x x x x x x x x x x x x VCR Out Mute
0 x x x x x x x x x x x x x x x ADC Reset 1 x x x x x x x x x x x x x x x ADC Running
x 1 1 1 x x x x x x x x x x x x No Tape/VCR/PVR Mute
Z2 R
Z2 L Phono L AUX L iPod L AM/FM L DAB/Sirius L NET L Spare L
CD R AV R SAT R DVD R VCR R PVR R TAPE R
Phono R AUX R iPod R AM/FM R DAB/Sirius R NET R Spare R
B.0PK 02/03/07 PCB clearence rule update07_E160
C.0PK 16/01/08 Layout change only08_E014
D.0PCB change only08_E126 PK 15/05/08
D.1NC 25/07/08 R316, R334 > 3k9, R308, R328 > 0R
0W063
R316
3K9
0W063
R334
3K9
0W063
L117_C1_Analogue Output_E1.SchDoc
VOL Sbl VOL Sbr
Z2 L Z2 R
AN SCL AN SDA AN SPI Clk AN SPI Data
DAC Right DAC Left
MCH Sbl MCH Sbr
A Out Mux Latch
Headphone L
DAC BClk DAC MClk
DAC Sbl DAC Sbr
AN SCL AN SDA
A Out Mux Latch
Z2 R Z2 L
Main L
Main R
Data LR Data CSw Data SlSr Data SblSbr DAC MClk DAC BClk DAC WClk
EB2-5NU
52806 CON100 MOLEX
B.0AN SPI data/clk corrected, H/phone Rf = 75k, Phono AC coupledNC
10V
Blank AVR002 Analogue Out PCBL117PBPCB100 1
08_E015
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20
CON101
MOLEX
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20
CON102
MOLEX
1
23
4
FIX100
1
E.0C115 C122 set to NFR109, 115 changed to 4R7PK 22/07/0808_E150
1W
R109
4R7
1W
R115
4R7
ISSUE
L117_C2_Mux Vol_E1.SchDoc
A Out Sel2
A Out Sel2
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
-3V3A -3V3A -3V3A
+3V3A +3V3A +3V3A
-3V3A
+3V3A
AGND
P235
P242
P240
P233
P229
P228
B.0
AGND
AGND
AGND
P200
P202
0 1 2 3 4 Vol /Rst Vol /Mute Dac /Rst 0 0 0 0 0 1 1 1 DAC Output 1 0 x x x 1 1 1 L/R Analogue Pass through 0 1 1 1 0 1 1 1 MCH Output x x x 0 1 1 1 1 Surround Back = Zone 2 x x x 1 1 1 1 1 Surround Back = L/R x x x x x 0 x 1 Volume Reset x x x x x 1 0 1 Volume Mute x x x x x x x 0 DAC Reset
16V
C231 100N
C232 100N
C233 100N
C234 100N
C237 100N
C238 100N
C239 100N
C240 100N
C219 100N
R299 470R
R213 10K
R251 10K
R283 10K
R286 10K
R289 10K
R292 10K
R295 10K
R298 10K
R256 10K
NC 19/9/0707_E161 AN SPI data/clk corrected, H/phone Rf = 75k, Phono AC coupled
C.0MCH Centre and Sub swappedPK 18/12/0708_E015
D.0PCB change onlyPK 27/05/0808_E127
E.0PCB change onlyPK 22/07/0808_E150
E.1Noise reduction changesNC 25/07/08
L117_C3_DACs_E1.SchDoc
DAC MClk DAC WClk DAC BClk
DAC /RESET AN SCL AN SDA
AGND AGND AGND
+3V3D
+3V3D
DGND
DGND
DAC Left+ DAC Left- DAC Right+ DAC Right- DAC Centre+ DAC Centre- DAC Sw+ DAC Sw- DAC Sl+ DAC Sl- DAC Sr+ DAC Sr- DAC Sbl+ DAC Sbl- DAC Sbr+ DAC Sbr-
DAC Sbr DAC Sbl DAC Sr DAC Sl
DAC Sw DAC Centre
DAC Right DAC Left
35V YK
C311 47UF
50V YK
C302 10UF
50V YK
C304 10UF
50V YK
C309 10UF
0W063 R300
470R 0W063
DGND AGND 0W063
IC300 CS4385
NC 19/9/0707_E161 AN SPI data/clk corrected, H/phone Rf = 75k, Phono AC coupled
C.0None to this sheetPK 18/12/0708_E015
ISSUE
L117_C4_Filters_E1.SchDoc
5 7
IC403B NJM2114M
NC 19/9/0707_E161 AN SPI data/clk corrected, H/phone Rf = 75k, Phono AC coupled B.0
C.0None to this sheetPK 18/12/0708_E015
ISSUE
L117_C5_PSU_E1.SchDoc
ISSUE
L118_C1_Trig IR RS232_E0.SchDoc
FM Data Out
AM/FM L In
AM/FM R InVSM
50V NPO
C112 22P
50V NPO
C148 22P
DGND
IR in
+15V+5V_1
C1+ 1
V+2
C1- 3
C2+ 4
C2- 5
DAB/Sirius L In AM/FM R In AM/FM L In
Audio output L118_C3_GND balancing_E0.SchDoc
AM/FM L In AM/FM R In Dab/Sirius L In Dab/Sirius R In
0W063
R128
B.0PK 02/03/07 Updated 9 way D type footprint,i Pod removed
Was iPod S-vid Y
Was iPod S-vid C
DGND
10 11 12 13 14 15
52045
CON104
MOLEX
DGND
+3V3D
0W063
0W063
R121
I/O23 I/O22 I/O21 I/O20 I/O19
TCK11
TDI9
TDO24
TMS10
XC9536XL-10VQ44C
DGND
TCK
TDI
TDO
TMS
+3V3D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
SQT
CON107
SAMTECH
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21
SQT
CON106
SAMTECH
3V3RF_In1
RF_GND2
D G
N D
(A 1)
MOD100 GyroSignal
1 2 3 4 5 6 7 8 9 10 11 12 13 14
SQT
24
/RDS On
/RDS On
NF
08_E016
E.0D types changed to NELTRON part, CON108 changed to socketPK 11/03/0808_E128
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON108
SAMTEC
0W063
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20
CON100
MOLEX
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20
CON101
MOLEX
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20
CON103
MOLEX
1
23
L118_C2_IR Demod Trig Drive_E0.SchDoc
0W063
+5V_STBY
+5V_STBY
+5V_STBY
A.0.2INITIAL RELEASENC
210mA (0.63W)
50V NPO
C223 22P
RED
+5V_STBY
P205
DGND
0W063
D.0None on this sheetNC 23/01/0808_E016
E.0None on this sheetPK 11/03/0808_E128
ISSUE
L118_C3_GND balancing_E0.SchDoc
Ground Balancing
25V
C324
100UF
25V
C325
100UF
25V
C326
100UF
25V
C327
100UF
63V
C321
22UF
63V
D.0None on this sheetNC 23/01/0808_E016
E.0Pilot tone filter added to AM/FM ground balancing circuitPK 11/03/0808_E128
6
L119_C1_DM850_G0.SchDoc
DGND
+3V3D
+3V3D
NET Xtal In
NET POWER DOWN
NET WClk
AV0DATA0 4
AV0DATA1 5
AV0DATA2 6
AV0DATA3 7
AV0CLK 2
AV0CTRL0 196
AV0CTRL1 197
AV1DATA0 161
AV1DATA1 162
AV1DATA2 163
AV1DATA3 164
AV2DATA0 12
AV2DATA1 13
AV2DATA2 14
AV2CTRL0 199
AV2CTRL1 200
AV2CLK 198
AV3DATA0 39
AV3DATA1 40
AV3DATA2 44
AV3DATA3,/CS3 46
AV3CLK 33
AV3CTRL0,A22 34
AV3CTRL1,A23 35
AV4DATA0 21
AV4DATA1 22
AV4DATA2 23
AV4DATA3 24
AV4CLK 195
AV4CTRL0 167
AV4CTRL1 168
G P
IO P
O R
T/ U
LP I
0W063
Memory L119_C2_Memory_G0.schdoc
NET Mclk
Power L119_C6_Power_G0.schdoc
NET /RESET
NET BClk
NET MClk
NET L NET R
NET L NET R
P154
P155
54 RP102D 47K
54 RP103D
47K
6 3RP105C
P124
R119
0R0
FIX101
1
C.0Changed power plane through lead connect style to thermal relief,+5V_2>+6V_1PK 25/9/07
P102
HC-49 SM
P135
P136
P137
P138
P111
F.0PCB change, make CON101, 102 NF, /Mute changed to Mute08_E129 PK
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20
CON100
MOLEX
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20
CON103
MOLEX
1
23
4
FIX100
1
1
23
4
FIX102
1
15/05/08
ISSUE
L119_C2_Memory_G0.SchDoc
A18,UDQM A17,LDQM
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
A16,BA1 A15,BA0
MEMCLK MEMCKE D0
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
DGND
DGND
+3V3D
+3V3D
D1
D0
MEMCKE
A21
/WAIT MEMCLK
A20 A19 A18,UDQM A17,LDQM A16,BA1 A15,BA0 A14,/CAS A13,/RAS A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
+3V3D FLASH /CS SDRAM /CS /CS WL /OE /WE /WAIT MEMCKE
A19
+3V3D
DGND
MEMCLK
ST39VF6401B 8M fit R210 & R255, do not fit R211, R214 & R215
/RESET_FLASH
/WP
/RESET_FLASH
/WP
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
A0 D1 D2 D3 D4 D5 D6 D7 D8 D9
D10 D11 D12 D13 D14 D15
D0
/CS WL
WiFi module connector L119_C3_Wifi_G0.SchDoc
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
/CS WL /OE /WE
CKE37
CLK38
UDQM39
R211
0R0
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
/WL REG /WAIT
/WL REG
WL RESET
P220 P222 P224 P225
P226 P228 P230 P232
C.0Changed power plane through lead connect style to thermal relief
AMD29LV641DH 8M fit R211 & R215, do not fit R210, R214 & R255
PK 25/9/0707_E166
D.0No changes on this sheetPK 07/12/07
S29GL064xxxTFIR3x 8M fit R210 & R255, do not fit R211, R214 & R215
A025
A124
A223
A322
A421
A520
A619
A718
A88
A97
A106
A115
A124
A133
A142
A151
A1648
F.0PCB change only08_E129 PK 15/05/08
G.0R255 changed to fitted, PCB mechanics change for GPE panel08_E143 PK 17/07/08
ISSUE
L119_C3_WiFi_G0.SchDoc
C.0Changed power plane through lead connect style to thermal reliefPK 25/9/0707_E166
D.0No changes on this sheetPK 07/12/0708_E022
E.0PK 20/02/0808_E054 None to this sheet
G.0PCB mechanics change for GPE panel08_E143 PK 17/07/08
ISSUE
L119_C4_Ethernet_G0.SchDoc
DGND
+3V3D
+3V3D
+3V3D
DGND
DGND
C.0Changed power plane through lead connect style to thermal reliefPK 25/9/0707_E166
D.0CON400 updated for Syspro
S C
R N
ISSUE
L119_C5_Audio_G0.SchDoc
AGND
DGND
C522
100UF
C524
100UF
P527
P528
P529
P530
C.0
Changed power plane through lead connect style to thermal relief, +5V_2 > +6V_1
R527 10K
P533
ISSUE
L119_C6_Power_G0.SchDoc
C641 6P8
C640 10uF
DGND DGND
DGNDPSU Sync
PSU Sync = 768kHz for Mclk = 24.576MHz PSU Sync = 705.6kHz for Mclk = 22.579MHz
R609 390K
R613 150K
15uH
C664 10P
C665 10P
C667 10P
C668 10P
22UF
C601
22UF
C600
100N
-5V
+6V_1
DGND
P606
C.0
Changed power plane through lead connect style to thermal relief, +5V_2 > +6V_1
PK 25/9/0707_E166
PK 07/12/07
08_E022
ISSUE
L121_C1_Motherboard_F0.SchDoc
Zone SPI Data DAB SCL DAB SDA
AN SCL AN SDA
NET MISO_D NET MOSI
NET SPI Clk NET/CS
DSP Clk DSP MISO DSP MOSI
DSP /CS
NET /RESET
Amp Temp1
Amp Fault
Z1 Demod Out Z2 Demod Out Z3 Demod Out WClk PW338
Headphone Sense Z2 /Mute Z3 /Mute
/Main Mute /Sbl/Sbr Mute
Cvid In S-vid Y In S-vid C In
NET Cvid NET S-vid C NET S-vid Y
NET Tx NET Rx
Sirius Tx Sirius Rx
iPod Tx iPod Rx
Cvid Out S-vid Y Out S-vid C out
Vcomp Latch
HDMI SPDIF HDMI WClk
FP_TX FP_RX
FAN PWM
AN SPI Data AN SPI Clk
Zone SPI Data DAB SCL DAB SDA AN SCL AN SDA VidIO Mux Latch AIn Mux Latch AOut Mux Latch IRTrig Mux Latch NET MISO_D NET MOSI NET SPI Clk NET/CS NET Mode Host NET Power Down NET NIREQ Host DSP Clk DSP MISO DSP MOSI DSP /CS
RDS Int RDS Data FM Data Out FM CE NET /RESET
iPod /Present SPDIF /Reset VSM
Z1 Demod Out Z2 Demod Out Z3 Demod Out WClk PW338 Headphone Sense Z2 /Mute Z3 /Mute /Main Mute /Sbl/Sbr Mute RS232 Tx RS232 Rx Y in Pb In Pr In Cvid In S-vid Y In S-vid C In
NET Cvid NET S-vid C NET S-vid Y NET Tx NET Rx Sirius Tx Sirius Rx iPod Tx iPod Rx Y ADV7312 Pb ADV7312 Pr ADV7312 Cvid Out S-vid Y Out S-vid C out
Vcomp Latch
Clk PSUHDMI Data0 HDMI Data1 HDMI Data2 HDMI Data3 HDMI SPDIF HDMI WClk
Dig Mux Latch FP Int FP_TX FP_RX SPDIF_Present
DSP2 /CS
PH CON101
Dia 3.5mm
Vcomp Latch SPI Clk SPI Data AN SPI Data AN SPI Clk Zone SPI Clk Zone SPI Data DAB SCL DAB SDA AN SCL AN SDA VidIO Mux Latch AIn Mux Latch AOut Mux Latch IRTrig Mux Latch NET MISO_D NET MOSI NET SPI Clk NET/CS NET Mode Host NET Power Down NET NIREQ Host DSP Clk DSP MISO DSP MOSI DSP /CS DSP2 FLAG0 DSP1 FLAG0 RDS Int RDS Data FM Data Out FM CE NET /RESET DSP2 /CS iPod /Present SPDIF /Reset VSM
Z1 Demod Out Z2 Demod Out Z3 Demod Out WClk PW338 Headphone Sense Z2 /Mute Z3 /Mute /Main Mute /Sbl/Sbr Mute
RS232 Rx RS232 Tx
Y in Pb In Pr In Cvid In S-Vid Y In S-Vid C In
NET Cvid NET S-vid C NET S-vid Y NET Tx NET Rx Sirius Tx Sirius Rx iPod Tx iPod Rx Y ADV7312 Pb ADV7312 Pr ADV7312 Cvid Out S-vid Y Out S-vid C Out HDMI Data0 HDMI Data1 HDMI Data2 HDMI Data3 HDMI SPDIF HDMI WClk
Dig Mux Latch FP int FP_TX FP_RX SPDIF_Present
P100
52806
CON102
MOLEX
AGND
AGND
DGND
AGND
AGND
DGND
DGND
DGND
DGND
VGND
VGND
0W063
R100
0R0
0W063
R101
0R0
0W063
R102
0R0
0W063
R103
0R0
0W063
R104
0R0
0W063
R105
NF
NF
NF
P105
P108
P111
P114
P106
P109
P112
P115
P117
P107
P110
P113
P116
Changed power plane connect style to direct, iPod removed, +5V_2 > +6V_1 B.0PK 02/03/07
DGND
DGND
07_E126
C.0PK 02/08/07 Rename DSP signals for AD DSP, correct backwards bottom silk
Blank AVR002 Connection PCBL121PBPCB100 1
08_E017
D.0NC
ISSUE
L121_C2_Main PCB_F0.SchDoc
SPDIF_Present
VGND
12 34 56 78 910 1112 1314 1516 1718 1920 2122 2324 2526 2728 2930 3132 3334 3536 3738 3940 4142 4344 4546 4748 4950 5152 5354 5556 5758 5960 6162 6364 6566 6768 6970 7172 7374 7576 7778 7980 8182 8384 8586 8788 8990 9192 9394 9596 9798 99100 101102 103104 105106 107108 109110 111112 113114 115116 117118 119120
FX8C-120P-SV
CON200
Hirose
12 34 56 78 910 1112 1314 1516 1718 1920 2122 2324 2526 2728 2930 3132 3334 3536 3738 3940 4142 4344 4546 4748 4950 5152 5354 5556 5758 5960 6162 6364 6566 6768 6970 7172 7374 7576 7778 7980 8182 8384 8586 8788 8990 9192 9394 9596 9798 99100 101102 103104 105106 107108 109110 111112 113114 115116 117118 119120
FX8C-120P-SV
CON201
Hirose
Changed power plane connect style to direct, iPod audio/video removed B.0PK 02/03/07
Was iPod CVid
07_E126
C.0PK 02/08/07 Rename DSP signals for AD DSP, correct backwards bottom silk08_E017
D.0NC
CON317 connections altered, HDMI Clks added08_E035 08/02/08
ISSUE
L121_C3_Daughter PCBs_F0.SchDoc
AN SPI Clk
A na
lo gu
e O
ut pu
I2S Data
Data LR
Data CSw
Data SlSr
Data SblSbr
Q0 9
Q1 7
Q2 6
Q3 5
Q4 3
Q5 2
Q6 4
Q7 13
/64
P303
DGND
+3V3_PW338
Changed power plane connect style to direct, iPod removed, +5V_2 > +6V_1 B.0PK 02/03/07
Was VGnd
Was VGnd
Was VGnd
07_E126
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON312 SAMTEC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON318
SAMTEC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON300 SAMTEC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON306
SAMTEC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON301 SAMTEC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON307
SAMTEC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON302 SAMTEC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON308
SAMTEC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON314 SAMTEC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON303 SAMTEC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON309
SAMTEC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON304 SAMTEC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON310
SAMTEC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON315 SAMTEC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON305 SAMTEC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON311
SAMTEC
16V
1 2 3 4 5 6 7 8 9 10
52045 CON FFC V 1.25MM 10W
CON317
MOLEX
OE1
GND 10
VCC 20
IC301C 74HC244D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON313 SAMTEC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SSQ
CON319
SAMTEC
C.0PK 02/08/07 Rename DSP signals for AD DSP, correct backwards bottom silk08_E017
D.0NC CON317 connections altered, HDMI Clks added
HDMI BClk
HDMI MClk
08_E035 08/02/08
+5V_1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
52045
CON320
MOLEX
ISSUE
L122_C1_TopLevel_F0.SchDoc
Pr In Pb In
NET Cvid
Cvid In
RS232 /CSC iPod_UART_Int
Amp_Temp_1
Zone SPI Clk
SPI Data
S -v
id C
ou t
S -v
id Y
O ut
V co
m p
La tc
PCB change onlyNC 26/3/07 B.107_E058
C.0AC Present > /AC Present, HDMI EDID -> DAB I2C, Video doublerNC07_E177 16/10/07
Blank AVR002 HDMI PCBL122PBPCB100 1
D.0EDID I2S Bus added, CEC connected to PW338NC 20/11/0707_E205
E.0Re-name DSP signals for AD DSP, HDMI Clks routed to L121PK 13/12/0708_E037
F.0None to this sheetPK 23/04/0808_E138
ISSUE
L122_C2_PW338_Digital_Input_Port_F0.SchDoc
IN_RED0 IN_RED1
IN_RED8 IN_RED9
IN_GREEN8 IN_GREEN9
IN_BLUE8 IN_BLUE9
IN_RED0 IN_RED1
IN_RED8 IN_RED9
IN_GREEN8 IN_GREEN9
IN_BLUE8 IN_BLUE9
HSync VSync
HSync VSync
DataEnable Interlaced_EvenOdd
HDMIRx IntSiI9135 /RESET
NC NC
NC NC
NC NC
HDMIRx Mute
/RESET100 INT 102
595A Latch
NET /CS NET SPI Clk
NET MOSI NET MISO_D
63 RP200C
54 RP200D
1 8
IN1 not used
X200 28.322 MHz
P213 P214 P216
P249 P252 P255 P258 P259 P260
P261 P262 P263 P264 P265 P266 P267
P268 P269 P270 P271 P272 P273 P274 P275
P276 P277 P278 P279 P280 P281 P282 P283
HDMI MClk
SiI9135 /RESET
D.020/11/07NC No changes on this sheet07_E205
E.0PK 13/12/07 Re-name DSP signals for AD DSP, HDMI Clks routed to L121
HDMI WClk HDMI BClk
ISSUE
L122_C3_PW338_Analogue_Input_Port_F0.SchDoc
NC NC
0W063
E.013/12/07PK No changes on this sheet08_E037
F.0Add Sync on green 1 componentsPK 23/04/0808_E138
0W063
R324
75R
16V
C323
100N
L122_C4_PW338_CPU_F0.SchDoc
CPU
2-24bit addressing 1-external reset control
3-external MClk input 4-byte mode - not SST FLASH
8-scan mode 7-test mode2 6-test mode1 5-test mode0
PW338 A1 PW338 A2 PW338 A3 PW338 A4 PW338 A5 PW338 A6 PW338 A7 PW338 A8 PW338 A9 PW338 A10 PW338 A11 PW338 A12 PW338 A13 PW338 A14 PW338 A15 PW338 A16 PW338 A17 PW338 A18 PW338 A19 PW338 A20 PW338 A21 PW338 A22 PW338 A23
PW338 D0 PW338 D1 PW338 D2 PW338 D3 PW338 D4 PW338 D5 PW338 D6 PW338 D7 PW338 D8
PW338 D10 PW338 D9
PW338 D11 PW338 D12 PW338 D13 PW338 D14 PW338 D15
PW338 A21
PW338 A11 PW338 A12
PW338 A10 PW338 A9
PW338 A8 PW338 A7 PW338 A6 PW338 A5 PW338 A4 PW338 A3 PW338 A2 PW338 A1
PW338 D0 PW338 D1
PW338 D3 PW338 D2
PW338 D4 PW338 D5 PW338 D6 PW338 D7
PW338 D8 PW338 D9 PW338 D10 PW338 D11 PW338 D12 PW338 D13 PW338 D14 PW338 D15
PW338 ROM /OE
PW338 ROM /WE
/ICE
DGnd
DGnd
DGnd
DGnd
DGnd
DGnd
DGnd
A025
A124
A223
A322
A421
A520
A619
A718
A88
A97
A106
A115
A124
A133
A142
A151
A1648
Flash
DGnd
Poweron_reset
Poweron_reset
CE OE WE Addr Read L L H Ain Prog L H L Ain Erase L H L XXH
V C
C401 1N0
PW338 D0
PW338 A2 PW338 A3 PW338 A4 PW338 A5 PW338 A6 PW338 A7 PW338 A8
PW338 A9 PW338 A10 PW338 A11 PW338 A12 PW338 A13 PW338 A14 PW338 A15 PW338 A16
PW338 A17
PW338 A21 PW338 A22
PW338 D4 PW338 D5 PW338 D6 PW338 D7
PW338 D8 PW338 D9 PW338 D10 PW338 D11
PW338 D12 PW338 D13 PW338 D14 PW338 D15
PW338 ROM /OE /ICE
+3v3 PW338
+3v3 PW338
+3v3 PW338
+3v3 PW338
+3v3 PW338
G N
D 61
RXA 62
/RIA 63
/CDA 64
IC403
SC16C554BIB64
DGnd
PW338 D0 PW338 D1 PW338 D2 PW338 D3 PW338 D4 PW338 D5 PW338 D6 PW338 D7
PW338 A1 PW338 A2 PW338 A3
UART A - NET Module
UART B - Sirius Module
UART C - iPod Module
NC NC NC NC NC NC
NC NC NC NC NC NC
NC NC NC NC NC NC
NC NC NC NC NC NC NC NC
RS232 /CSA RS232 /CSB
RS232 /CSB RS232 /CSA
DGnd
1 2 3 4 5 6 7 8 9 10
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TML
CON400
SAMTEC
1 2 3 4 5 6 7 8 9 10
- CON401
Harting
50V
NC NC NC
Disabled by MCR[5]- (software flow control)
0W063
P403 P405
/RESETBE2
NMIAH9
EXINT0AF10
EXINT1AG10
EXTMCLKAG13
EXTDCLKAH13
TMSC2
TDOD1
TDID3
/TRSTNE4
TCKD2
TESTMODE0D4
TESTMODE1E5
TESTMODE2D5
SCANMODEE6
EXTRSTNE3
ADR24BE1
DGnd DGnd
DGnd DGnd
DGnd DGnd
ISSUE
L122_C5_PW338_Display_Port_F0.SchDoc
OUT_RED0 OUT_RED1
OUT_BLUE7 OUT_BLUE6 OUT_BLUE5 OUT_BLUE4 OUT_BLUE3 OUT_BLUE2 OUT_BLUE1 OUT_BLUE0
OUT_RED8 OUT_RED9
OUT_GREEN8 OUT_GREEN9
OUT_BLUE8 OUT_BLUE9
OUT_RED8 OUT_RED9
OUT_BLUE8 OUT_BLUE9
0W063
OUT_RED0 OUT_RED1
OUT_BLUE7 OUT_BLUE6 OUT_BLUE5 OUT_BLUE4 OUT_BLUE3 OUT_BLUE2 OUT_BLUE1 OUT_BLUE0
OUT_RED8 OUT_RED9
OUT_BLUE8 OUT_BLUE9
CSCL 48CSDA 49CI2CA50
CSCL 48CSDA 49CI2CA50
DCLK15
DR016 DL017
DR118 DL119
DR220 DL221
DR322 DL323
D3556 D3457 D3358 D3259 D3160 D3061 D2962 D2863 D2767 D2668 D2569 D2470
D2371 D2272 D2173 D2074 D1975 D1877 D1778 D1679 D1580 D1481 D1382 D1283
D1184 D1085 D986
Si I9
13 4
V id
DCLK15
DR016 DL017
DR118 DL119
DR220 DL221
DR322 DL323
D3556 D3457 D3358 D3259 D3160 D3061 D2962 D2863 D2767 D2668 D2569 D2470
D2371 D2272 D2173 D2074 D1975 D1877 D1778 D1679 D1580 D1481 D1382 D1283
D1184 D1085 D986
Si I9
13 4
V id
Expects 75 ohm termination i.e. 150 ohm load.
2V5A_ADV7312
2V5D_ADV7312
2V5D_ADV7312
DGnd
DGnd - Digital Ground. AGnd - Analogue Ground. Gnd_IO - Digital input/output Ground.
DGnd
DGnd
DGnd DGnd
DGnd DGnd
Y_out
Pb_out
Pr_out
Ysd_out
Csd_out
CVBS_out
N.B. This DAC is controlled via the HDMI configuration bus.
HDMI sda HDMI scl
HDMI sda HDMI scl
OUT_RED0_R OUT_RED1_R
OUT_RED8_R OUT_RED9_R
OUT_GREEN8_R OUT_GREEN9_R
OUT_BLUE8_R OUT_BLUE9_R
S 0
PBLANK changed to PBLANK*, correct in software unless PCB revised
FBIN 4
G N
D 3
+3v3 PW338
+3v3 PW338
ISSUE
L122_C6_PW338_Main_Memory_Port_F0.SchDoc
A2
ARCAM
a-RMD0 a-RMD1 a-RMD2 a-RMD3 a-RMD4 a-RMD5 a-RMD6 a-RMD7 a-RMD8 a-RMD9 a-RMD10 a-RMD11 a-RMD12 a-RMD13 a-RMD14 a-RMD15
a-RMD16 a-RMD17 a-RMD18 a-RMD19 a-RMD20 a-RMD21
a-RMD23 a-RMD22
a-RMD24 a-RMD25 a-RMD26 a-RMD27 a-RMD28 a-RMD29 a-RMD30 a-RMD31
a-RMD0 a-RMD1 a-RMD2 a-RMD3 a-RMD4 a-RMD5 a-RMD6 a-RMD7 a-RMD8 a-RMD9 a-RMD10 a-RMD11 a-RMD12 a-RMD13 a-RMD14 a-RMD15 a-RMD16 a-RMD17 a-RMD18 a-RMD19 a-RMD20 a-RMD21 a-RMD22 a-RMD23 a-RMD24 a-RMD25 a-RMD26 a-RMD27 a-RMD28 a-RMD29 a-RMD30 a-RMD31
RMCKE
RMA2 RMA3
RMA1 RMA0
RMA3 RMA4
RMA3 RMA4 RMA5 RMA6 RMA7 RMA8 RMA9 RMA10 RMA11 RMA12
RMBNK0 RMBNK1
R600
1K0
DGnd
DGnd
DGnd
DGnd
DGnd
DGnd
b-MD0 b-MD1 b-MD2 b-MD3 b-MD4 b-MD5 b-MD6 b-MD7 b-MD8 b-MD9 b-MD10 b-MD11 b-MD12 b-MD13 b-MD14 b-MD15 b-MD16 b-MD17 b-MD18 b-MD19 b-MD20 b-MD21 b-MD22 b-MD23 b-MD24 b-MD25 b-MD26 b-MD27 b-MD28 b-MD29 b-MD30 b-MD31
MRAS MCAS MWE MCS
b-MDM0 b-MDM1 b-MDQS0 b-MDQS1
e-MA3 e-MA4 e-MA5 e-MA6 e-MA7 e-MA8 e-MA9 e-MA10 e-MA11 e-MA12
MBNK0 MBNK1
2 x 16M x 16 = 16M x 32 @ 200 MHz
DGndDGnd
DGnd
Spare
10V
18 RP609A
2762mW RP609B
CKE44
CK45
LDQS16
CKE44
CK45
LDQS16
Trace Lengths to be matched such that :-
All signals beginning with "a_" to match all other "a_ " to within +/- 50 mil (thou).
And so on for b,e etc.
MVREF
Page 33 PW338 DS. MVRef has 1k to ground and 1k to Vdd25
a-RMDM1 a-RMDM0
a-RMDQS0 a-RMDQS1
a-RMDM3 a-RMDM2
a-RMDQS2 a-RMDQS3
ISSUE
L122_C7_PW338_Peripherals_F0.SchDoc
Peripherals
HDMI_config_scl HDMI_config_sda
Relay Sw
HDMIRx Sync
iPod /Present
i2s mux
AN SPI Clk AN SPI Data SPI Clk SPI Data Zone SPI Clk Zone SPI Data
HDMIRx Int HDMIRx Mute PW338 Hotplug
+3v3 PW338
+3v3 PW338
+3v3 PW338
SPIClk SPIData
P769 P771 P773
P789 P791 P793
P814
P817
P813
P859
EDID_Sel
Changed address from A0/A1 (clash with EDID I2C)
+3v3 PW338
Vid_Clk_Sw P781
D.0
P812
P815
Display_CEC
20/11/0707_E205
E.0PK 13/12/07 Re-name DSP signals for AD DSP, HDMI Clks routed to L12108_E037
ISSUE
L122_C8_PW338_Power_and_Ground_F0.SchDoc
+3 v3
A H
D M
DACV
MSPLLDPLLMPLLURESDACV
Eval board connects these to Dig supply although they are low speed analogue.
DGnd
DGnd
DGndDGndDGnd
16V
ISSUE
L122_C9_HDMI_Input_MUX_F0.SchDoc
Provides means to common CEC lines
DGnd
AV
DGnd
DGnd
CEC_Common
SDA/SCL pullup - see HDMI spec
Provides means to common CEC lines
DGnd
VCR
AV CK- AV CK+ AV D0- AV D0+ AV D1-
AV D1+ AV D2- AV D2+
SAT CK- SAT CK+ SAT D0- SAT D0+ SAT D1- SAT D1+ SAT D2- SAT D2+
HDMI spec has weak pullup at sink (47k) and strong pullup at source (1k8) hence resistors below are fitted on SDA, SCL.
DGnd
DGnd
DGnd
+5V_STBY
+5V_STBY
+5V_STBY
Vl = 0v6, Vh = 2v4, Vmax = 5v
HOTPLUG to source will only go high when : 1.The source is selected AND 2. The HOTPLUG from the TV/Display is high AND 3. The 5V power from the source is high
PVR_hotplug_out
VCR_hotplug_out
VCR_5v_in
PVR_5v_in
DVD_hotplug_out
SAT_hotplug_out
SAT_5v_in
DVD_5v_in
AV_hotplug_out
DGnd
Hotplug
N.B. Hotplug output must satisfy TTL signal thresholds so require HCT family device
Select signals are derived from HC logic running @ 3v3. (HC595).
+5V_STBY
DGnd
+5V_STBY
DGnd
+5V_STBY
DGnd
DGnd
To M
U X
DGndDGnd
Signalling :- - Source indicates ready by asserting +5V. - Sink indicates ready by asserting HOTPLUG - Souce interogates EDID etc.
In circuit below hotplug may be delayed wrt 5v more than in a conventional system which could risk a timeout.
i.e. sink asserts hotplug and expects source to start comms on I2C and read the EDID immediately.
Some sinks might register a timeout fault.
Check HDMI spec on this.
DGnd
+5V_STBY
NC
DGnd
Vl = 0v6, Vh = 2v4, Vmax = 5v
MUX1 CK- MUX1 CK+ MUX1 D0- MUX1 D0+ MUX1 D1- MUX1 D1+ MUX1 D2- MUX1 D2+
DGnd
DGnd
Changing these MUXs to channel 0 will simulate a cable being unplugged.
PW338 Hotplug
LP Filter
Sel2Sel3
0 0 0 0
Sel1 Sel0 On Switch
1 2 3 4
0 0 1 1
0 1 0 1
HDMI_TMDSSel3
DVD CK- DVD CK+ DVD D0- DVD D0+ DVD D1- DVD D1+ DVD D2- DVD D2+
VCR CK- VCR CK+ VCR D0- VCR D0+ VCR D1- VCR D1+ VCR D2- VCR D2+
PVR CK- PVR CK+

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