ARCHI Introduction ARCHI Fundamentals of Digital ... - IRISA

Page 1

ARCHIFundamentals of Digital & Analog

System Testing

Michel Renovell

ARCHI’09

ARCHI

process beginwait until not

CLOCK'stableand CLOCK=1;

if(ENABLE='1') thenTOGGLE<= not

TOGGLE;end if;

end process;

Technology

Test

Design

Test (preparation)

Application

IntroductionIntroduction

ARCHI

Problem

Manufacturing

Design

Layout ?




TOGGLE;end if;

end process;


Design Error

ProblemDeviation & Spot

ARCHIprocess begin

wait until notCLOCK'stableand CLOCK=1;


TOGGLE;end if;

end process;

Manufacturing

Design

Layout ?ProblèmeDeviation & Spot


Page 2

ARCHI

Digital Circuit

n m

• Boolean Testing• Test Patterns• Go/NoGo

00101.............................11010...

10110.............................00011...

IntroductionIntroduction ARCHI

Digital Circuit

n m

• Exhaustive Testing • 264 patterns• 1019/100MHz = 1011s •

00101.............................11010...

10110.............................00011...

• Realistic Test • 10s / 100MHz • 109

• 1 / 1010


=> 5850 years

ARCHIIntroductionIntroduction

go . Pg - m . Pm >

#

m

g

b T

2n

go

e

Tno-go

0No-Test Ideal-TestReal-Test

Margin

m.T.Pt

T

€go . Pg - m. Pm

e.Pe

T

€go . Pg - m . Pm

85%

15%

Y = 75%e = 500 ppmPe = rule of 10


go . Pg - m . Pm ≥ m . T . Pt + e . Pe

Tm.T.Pte.Pe

go . Pg - m . Pm

T

#

m

g

T2n

go

e

Tb no-go

0

€Margin

Page 3


- Criteria to stop the test generation- Estimate how many faulty circuits are already detected by the generated tests

Tm.T.Pte.Pe

go.Pg - m.Pm

T

€

#

m

g

T

go

e

Tb no-go

0

ARCHI

#

m

g

TT

b 0

Tm.T.Pte.Pe

go.Pg - m.Pm

T

€


- Criteria to optimize the test generation- Estimate how many faulty circuits are detected by each vector


#

m

g

TT

b 0

Tm.T.Pte.Pe

go.Pg - m.Pm

T

€

- Criteria to make circuit Testable- Modify the circuit / DFT

ARCHI

CircuitCircuit

0 ∞DPd1

0 ∞DPd2

± Variations / Tolerance

Pout0 ∞SM

M

M

Pdi A

FundamentalsFundamentals

Page 4

ARCHIprocess begin



TOGGLE;end if;

end process;

Manufacturing

Design

Pdi

T

Pout0 ∞S

M

± Variations

D

PdiT

Pout0 ∞M


Se=Δ Pout/ΔPdi∆ ∆

ARCHI




TOGGLE;end if;

end process;

Specification ?

Δ PsΔ PdiSensitivity : Se =

Amplitude : A / ⇒D F

Tolerance : Po / ± TS

A * Se < T ?

A < T / Se ?

Robustness

A

Se

T


ARCHI

± Variations ?Deviation

Spot

#

PdiD

A

Small & Systematic

0 ∞DR

Op

A

0 ∞DR

Sh

A

Large & Scarce

0 ∞

Short

OpenMétal

FundamentalsFundamentals ARCHI




TOGGLE;end if;

end process;

Specification ?

SpotLargeScarce

DeviationsSmallSystematic

SpotLargeScarce

Low T/Se High T/Se

A < T / Se ?

Robustness


Page 5

ARCHI

1

11

0

0

1

1

0

0

Digitalprocess begin



TOGGLE;end if;

end process;

Specification ?


- Logic- Timing

11

00

Cl

ARCHI

OutIn

μ

In

Out

Vdd

Vdd

tτ

VVin

Vout

FundamentalsFundamentalsDigital




TOGGLE;end if;

end process;

Specification ? - Logic- Timing

ARCHI

OutIn

μ

In

Out

Vdd

Vdd

Vin

Vin

Δ PsΔ PdiSe =

Very High T/Se

Circuit IndptOut

OutInμ

InVdd

Vdd

Vin

Vin

T = 50%

OutVdd

Vdd

T


ARCHI

T

Deviation

Spot

0 ∞DR

Op

A

0 ∞DR

Sh

A

#

μ

D

A

T#

PoutS

Se

SPout

M0 ∞

0 ∞


Page 6

ARCHI

R

C

V0 Vs(t) RC tV0

t

Vs(t)

Slope

T ?

#

RD

A#

CD

A

T ?#

SlopeS Se ?

Variable T/Se Circuit Dpt

FundamentalsFundamentalsAnalog

ARCHI

AnalogDigital

Deviations Small & Syst.Spots Large & Sc.

Low T/SeHigh T/Se

Spots Large & Sc.

Spec Oriented TestDefect Oriented Test

#

SlopeS

0 ∞DR

Op

0 ∞DR

Sh


Timing

ARCHI

AnalogDigital


#

PoutS


GoNoGo NoGo

Test

CD1

C1

CD2

C2

CDn

Cm

Test

Go

NoGo

ARCHI

AnalogDigital


#

PoutS


GoNoGo NoGo

Test

CD1

C1

CD2

C2

CDn

Cm

Test

Go

NoGo

e

e

Page 7

ARCHI

Spot-Free Digital Circuit <=> In Specification

2n

VT

For each possible spotCompute the stimulithat reveals its presence

Test PatternList

Digital ApproachDigital Approach ARCHI

0 ∞D Op0 ∞DR

ShRSh1 Op1

0 ∞D Op0 ∞DR

ShRSh2 Op2

0 ∞D Op0 ∞DR

ShRShn Opn

Digital ApproachDigital Approach

ARCHI

1,5V1,5V

0V/1,3V

1,5V/0,2V


11 0/11/0

1X1

X S@1

Spot <=> Fault Model- S@0- S@1


Page 8

ARCHI

11

10

01S@0

1

x

x

0

Cost• 106 gates• 106 nodes• 106 S@0• 106 S@1• 2.106 vectors• 100Mhz

Physical Structure <=> Logical Structure- Each Logic node S@0- Each Logic node S@1- TPG


11

10

01S@0

1

x

x

0

Cost• 106 S@0• 106 S@1• 2.106 vectors

100%S@Escp

FaultCoverage

=

Faul

ts

100%Spots

Def

ects

NFDNFT

100%Circuits

Circ

uitsBad


ARCHI

FC 100%

T2nT0

#

T

e

Tb no-go

%ND


MetricsFC = # detected / # total

FC = #S@ 100%

T2nT0

#

m

g

T

go

e

Tb no-go

- Criteria to optimize the test generation- Estimate how many faulty circuits are detected by each vector


%ND

Page 9

ARCHI

MetricsFC = # detected / # total

FC = #S@ 100%

TT0

#

m

g

T

go e

Tb no-go

FC%

eppm

10090

emin

emin

Quality


%ND

ARCHI

Fault Simulation :

Vi => (S@1, S@2, S@3, S@4 ...)

Circuit Description

Fault Simulation

Vector List

FC=NFD

NFT

100%

Select

T1000 10000

ComputeFault List


ARCHI

• Desired e (Application)

• Desired FC%

• Structural ATPG => Vectors

• Minimal number

11

10

01S@0

1

x

x

S@1 S@2

S@3

Cost

Test GenerationTest Generation ARCHI

11

10

01S@0

1

x

x

Cost• S@1 => S1=(T11 or T12 or T13 ...)

• S@2 => S2=(T21 or V22 or T23 ...)

• S@3 => S3=(T31 or T32 or T33 ...)

• .........

S1 and S2 and S3 and S4......

FC 95%

Test GenerationTest Generation

Page 10

ARCHI

11

10

01

1

0

1

Cost• ATPG :

• Fault Simulation :

S@1 => T11 (np)

Vij => (S@1, S@2, S@3, S@4 ...) (ok)

1 000 0

1

Test GenerationTest Generation ARCHI

Circuit Description Fault List

ATPG

Fault Simulation

S1, S2,…., Sk

Circuit Description

Vector List

Vector

FC= NFDNFT

?

Test GenerationTest Generation

Random Vectors

T1000 10000

Compute

ARCHI

11

10

01

S@0

1

010

• ATPG / Backtrack

• FC < Desired FC

• Modify the Structure

11

10

01

S@0

1

01T=0

Design For Test

DFTDFT ARCHI

#

m

g

TT

b 0

Tm.T.Pte.Pe

go.Pg - m.Pm

T

€

- Criteria to make circuit Testable- Modify the circuit / DFT

DFTDFT

Page 11

ARCHIDFTDFT

Fault List

ATPG

Fault Simulation

S1, S2,…., Sk

Vector List

Vector

DFT insertion

Circuit Description

TestableCircuit Description


Random Vectors

FC= NFDNFT

?

Testability Meas.

ARCHIDFTDFTFF

FFFF

FFFF

FF

FF

FFFF

FFFF

FF

FF

FFFF

FF

FF

FF

FF

FF

FF

I1

In

O1

Om

FFk

I1In

.

.

.

.

.

.

O1

OmSO1

SOk

FF

FF

SI1SIk

.

..

Com

bLo

g

k=100

2k=1031

ARCHIDFTDFTI1In

O1

OmSO1

SOk

FF

FF

SI1SIk

.

.. k=100

2k=1031

1011

11

NT=2k/4

~ 107No sequential ATPG

Lseq = 107 x Lcomb

ARCHIDFTDFTI1In

O1

OmSO1

SOk

SI1SIk

FF

FF

.

..

k=100

2k=1031

1011

NT=2k/4

~ 107

SCANIN

SCANOUT

InSInSEnCI

QSCAN

FF

SFF

SFF

SCANEN

Combinational ATPG

Lseq = 102 x Lcomb

Page 12

ARCHIBISTBIST

I1

In

O1

Om

.

.

.

.

.

.

Gen G

en

Gen

Control

Ana

Ana

Ana

Ana

Test Pins

ARCHIBISTBIST

Gen Ana

FF FF

FFFF

FFFF

FFFF

FFFF

k FF

Max:2k vect.

ARCHI

FF

FF FF FF FFXX2X3X4

k=4

Max=16 vect.

P(x)= 1+X2+X4LFSR

0 1 0 11 0 1 00 1 0 01 0 0 00 0 0 10 0 1 00 1 0 1

6 vect.

BISTBIST ARCHI

FF FF FFXX2X3

k=3 P(x)= 1+X2+X3LFSR

BISTBIST

011

001

111

110101

010

100

000

k FFMax:(2k-1) vect.

Si P(x) primitif

Page 13

ARCHIdegré degré degré

1 0 13 4 3 1 0 25 3 02 1 0 14 12 11 1 0 26 8 7 1 03 1 0 15 1 0 27 8 7 1 04 1 0 16 5 3 2 0 28 3 05 2 0 17 3 0 29 2 06 1 0 18 7 0 30 16 15 1 07 1 0 19 6 5 1 0 31 3 08 6 5 1 0 20 3 0 32 28 27 1 09 4 0 21 2 0 33 13 010 3 0 22 1 0 34 15 14 1 011 2 0 23 5 0 35 2 012 7 4 3 0 24 4 3 1 0 36 11 0

1)( 141534 ++++= xxxxxP

1)( 22 ++= xxxP

BISTBIST ARCHIBISTBIST

FFFF

FFFF

FFFF

FFFF

100%

Select

T

1000 10000

ComputeFC

Seed/Clock Reconf PolynTest Length2

ARCHIBISTBIST

Seed Selection

Fault Simulation

S1, S2,…., Sk

Seed/Clock List

Vectors

DFT & BIST insert

Circuit Description


LFSR Vectors

FC= NFDNFT

?

Testability Meas.

Fault List

ARCHIBoundary ScanBoundary Scan

Mechanical Probing

PCA EdgeConnector

Inputsuppliedby tester

Outputmonitoredby tester

Interconnect Test

DigitalIC

DigitalIC

DigitalIC

Inputsuppliedby tester

Outputmonitoredby tester

Component Test

Page 14

ARCHI

Mechanical Probing more difficult

PCA

DigitalIC

DigitalIC

DigitalIC

Boundary ScanBoundary Scan ARCHI

D1

D2

D3

D4

D8

D7

D6

D5

DigitalIC

FunctionalCircuitry

TestCircuitry

TDI TDO

TMS TCK

Electronic Probing IEEE 1149.1 digital chip

Boundary-Scan cellBoundary-Scan register

TAPTest Access Port

Boundary ScanBoundary Scan

ARCHI

1D

C1

1D

C1

1

1

G1

1

1

G1Mode

Update DRClock DR

SI

SO

PI

POShift DR

Boundary-Scan cell


Clock DR

1D

C1

1D

C1

11

G1

11

G1Mode

Update DR

SI

SOPI

POShift DR

1D

C1

1D

C1

11

G1

11

G1Mode

Update DRClock DR

SI

SOPI

POShift DR

D1

D2

D3

D4

D8

D7

D6

D5

FunctionalCircuitry

TestCircuitry

TDI TDO

TMS TCK

Input Boundary-Scan cell

D1

D2Functional

Cir


Page 15

ARCHI

Clock DR

1D

C1

1D

C1

11

G1

11

G1Mode

Update DR

SI

SOPI

POShift DR

1D

C1

1D

C1

11

G1

11

G1Mode

Update DRClock DR

SI

SOPI

POShift DR

D1

D2

D3

D4

D8

D7

D6

D5

FunctionalCircuitry

TestCircuitry

TDI TDO

TMS TCK

Input Boundary-Scan cellExternal-Circuit

Functional

Cir

D1

D2


Clock DR

1D

C1

1D

C1

11

G1

11

G1Mode

Update DR

SI

SOPI

POShift DR

1D

C1

1D

C1

11

G1

11

G1Mode

Update DRClock DR

SI

SOPI

POShift DR

D1

D2

D3

D4

D8

D7

D6

D5

FunctionalCircuitry

TestCircuitry

TDI TDO

TMS TCK

Input Boundary-Scan cellRegister-Register

Functional

Cir

D1

D2


ARCHI

D1

D2

D3

D4

D8

D7

D6

D5

FunctionalCircuitry

TestCircuitry

TDI TDO

TMS TCK

Clock DR

Mode

Update DR

Shift DR


Electronic Probing

PCAInput-Output Boundary-Scan cell


Page 16

ARCHI

TDI

TDO

TMS

TCK

Gen G

en

Gen

Control

Ana

Ana

Ana

Ana

TAP

INST

RU

CT.

REG

OPT

ION

AL

REG

BP

In BriefIn Brief

Thank you……Thank you……

Documents

ARCHI Introduction ARCHI Fundamentals of Digital ... - IRISA