Architectural Development and Functional Verification of SuperSpeed USB 3.0 PHY Layer Controller

8/6/2019 Architectural Development and Functional Verification of SuperSpeed USB 3.0 PHY Layer Controller

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JOURNAL OF COMPUTING, VOLUME 3, ISSUE 5, MAY 2011, ISSN 2151-9617HTTPS://SITES.GOOGLE.COM/SITE/JOURNALOFCOMPUTING/WWW.JOURNALOFCOMPUTING.ORG 1

Architectural Development and Functional

Verification of SuperSpeed USB 3.0

PHY Layer ControllerHasan Baig and Jeong-A Lee*

AbstractUniversal serial bus has supported a wide variety of devices from keyboard, mouse, flash memory device, game peripheral, imaging up tohigh speed broad band devices. In addition, user applications demand a higher performance connection between the PC and other increasingly sophisticated

peripherals. USB 3.0 addresses this need by adding even faster transfer rates. It promises a data transfer rate of 4.8 Gbps as compared to its predecessor

interface USB 2.0 which has a raw data rate at 480Mbps. This implementation of synthesizable Media Access (MAC) layer of SuperSpeed USB Memory

Device, with a pipelining concept of processing the packets, is proposed to support high speed transfer rate and high throughputs. Alongside, the use of

efficient handshaking signals complies with optimum performance of the overall device. Master controller has also been implemented to have a command

over MAC Layer and the other layers that will be implemented in a future research. This implementation meets the required specifications and ensures the

data rate of atleast 4.0Gbps [1].

Index TermsUSB3.0, MAC Layer, Physical Layer Controller, FPGA.

1 INTRODUCTION

he physical layer classifies the PHY portion of a portand the physical connection between a downstreamfacing port (on a host or hub) and an upstream facing

port on a device. The SuperSpeed physical connection iscomprised of two differential data pairs, a transmit pathand a receive path (Fig. 1).

The electrical aspects of each path are characterized asa transmitter, channel, and receiver; these collectively

represent a unidirectional differential link. Each differen-tial link is AC-coupled with the capacitors located on thetransmitter side of the differential link. The channel in-cludes the electrical characteristics of the cables and con-nectors [1].

At an electrical level, each differential link is initializedby enabling its receiver termination. The transmitter isresponsible for detecting the far end receiver terminationas an indicator of a bus connection and informing the linklayer so the connect status can be factored into link opera-tion and management.

When receiver termination is present but no signalingis occurring on the differential link, it is considered to be

in the electrical idle state. When in this state, Low Fre-quency Periodic Signaling (LFPS) is used to signal initial-ization and power management information. The LFPS isrelatively simple to generate and detect and uses very

little power.

The USB PHY Layer (PHY Chip depicted in Fig. 1)handles the low level USB protocol and signaling. Thisincludes features such as; data serialization and deseriali-zation, 8b/10b encoding, analog buffers, elastic buffersand receiver detection. The primary focus of this block isto shift the clock domain of the data from the USB rate to

one that is compatible with the general logic in the ASIC[1].

Fig 1: PHY/MAC Interface.

2 MACINTERFACES

Since the PIPE (PHY Interface for the PCI Express) is im-plemented for USB mode that supports 5.0GT/s, we havechosen 32 bits data paths with PCLK running at 125MHz[2]. The MAC Layer commands the communication ofPHY Layer with the Link Layer and LTSSM (Link Train-ing and Status State Machine).

2011 Journal of Computing Press, NY, USA, ISSN 2151-9617

http://sites.google.com/site/journalofcomputing/

T

Hasan Baig is with the Chosun University, Gwangju, South Korea, 501-759. www.hasanbaig.webs.com

Jeong-A Lee *(corresponding author) is with the Chosun University,Gwangju, South Korea, 501-759.


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PHY layer controller itself is commanded by MasterController. The top level block diagram of MAC Layer (orPhysical Layer Controller)1 is shown in Fig. 2. It can beobserved that the PHY Layer Controller itself comprisesof some internal modules that will be described later inthe following sub sections.

The MAC layer of USB 3.0 device interacts with Link

layer, LTSSM and is commanded by Master controller.LTSSM and Link Layer are beyond the scope of this re-search paper, so will be described briefly in the next subsections.

1Phy Layer Controller is also called Media Access (MAC) Layer. Wewill use these terms interchangeably throughout this paper.

2.1 Link Layer

A Super Speed link is a physical and logical connection be-tween two ports, called link partners. A port has a physicalpart and a logical part. The link layer identifies the logicalportion of a port and the communications between linkpartners. The main responsibility of link layer is to ensurethe successful data transfer with the link partner and to

maintain connectivity between them.

Fig 2: Top Level Block Diagram of PHY Layer Controller.


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2.2 Link Training and Status State Machine

The Link Training and Status State Machine (LTSSM)behaves as a leading workhorse to maintain reliable link,highly optimized power consumptions and efficientlyfast and perfect data transfer rate. It also implements var-ious algorithms for links reliability preservation and isalso liable to recover a link when an error arises.

It is LTSSM who manages the power of a device profi-ciently and greatly reduces the links power consump-tion. It also voids the condition that causes the wastage ofpower. It co-ordinates and converse with PHY chip,MAC Layer, Link Layer and Master Controller to per-form its duties.

2.3 Dual Port Reference Memory

USB 3.0 specification [1] provides a complex hardware im-plication. It has been emphasized to produce such an archi-tecture that can be easily comprehended, incorporated andimplemented without an extraordinary knowledge of inter-facing other layer in USB 3.0 device.

To achieve this, each layer is kept separated from theother by inserting dual-port-memories (Fig. 2) in betweentwo successive layers. When one of the layers is donewith writing data to intermediate memory (dual-port-memory), there is a primary need of notifiying the nextconcerned layer to begin execution and process the validmemory contents in the intermediate memory area. Thisneed is accomplished by using the Master Controllerwhich schedules the execution of layers in a pre-determined sequence which is described in next section.

2.4 Buffer InterfacesThe primary reason of using buffer interfaces (Fig. 2) is toovercome the need of incorporating a memory controller intoa layers main controller. In case, for example, if MAC layer isinstructed to start processing some valid memory contents,there could be two possibilities First MAC layer fetch thememory contents by issuing address & data to enable ports ofthe memory with incrementing each time the address for thenext valid data and asserting the enable ports.

Second possiblity is that it has a separate modulewhich is notified of the number of bytes to be fetchedfrom memory and which is resposible of incrementingthe address each time it gets valid data for memory. Inorder to simplify the implementation, it is recommendedto have separate entities so that hardware can be easilycomprehended and debugged or in another words the

main controller will remain free from some extra burdenwhile dealing with the memory.

Second approach is quite better. Thus buffer interface(or memory controllers) are used in the architecture justbeside intermdiate dual-port-memories.

3MASTERCONTROLLER

Master Controller is developed to command the commu-nication flow between each module. The centralized mas-ter controller monitors and controls the decoding andencoding operation separately. It has been designed insuch a way that it can easily be integrated later with Link

Layer, Protocol Layer and LTSSM, which would be in facta future enhancement of this research. Top level blockdiagram of Master Controller is shown in Fig. 3.

3.1 Decoding Path Controller

The decoding process is to take packet from the PHY chipand pass it to link layer controller (decoder) and so forth.Master controller follows the protocols in the sequence men-

tioned below.

Fig. 3: Top Level Block Diagram of Master Controller - showing IO inter-

face with each layer and LTSSM.

1. When Phy Layer Decoder (Fig. 2) receives thecomplete packet, it generates an indication signalto master controller which in turn initializes theLink Layer (LL) decoder, provided that LL de-coder is not already in a busy state. Meanwhile,master controller also sends the packet size tothe LL decoder that it received from the PhyLayer decoder at the complete reception of pack-et.

2. When the packet is processed by the LL decoder,it generates an indication signal to master con-troller which in turn initializes the Protocol Lay-er (PL) decoder, provided that it is not already

busy. Link layer decoder de-assembles the pack-et received and sends the new packet size (pack-et size changes after passing through the packetde-assembler) to master controller. Master thensends this new packet size to protocol layer de-coder at the time of its initialization.

Fig. 4 depicts the timing diagram of decoding process.

Note: Master must deassert the initializing signal of Link Layer

and Protocol Layer decoders as soon as they acknowledged.


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Fig. 4: Timing diagram of decoding path controller.

3.2 Encoding Path Controller

The controlling protocols, mentioned below, are followedby the master controller in order to encode the packet

1. Protocol Layer (PL) Encoder is initialized whenmaster-configuration valid signal is received bythe Master controller provided that the PL en-coder must not already busy. As soon as thecomplete packet is encoded, PL encoder gener-ates an indicating signal (pl_enc_done, Fig. 3)to the master informing it the packet has beentransferred into the buffer and ready to be

fetched by Link Layer controller. Master control-ler then generates a signal to initialize the LinkLayer (LL) encoder, provided that LL encoder isnot already in a busy state. Meanwhile, masteralso sends the packet size to the Link Layer en-coder; it had received from the PL encoder at thecomplete reception of packet.

2. After processing, assembling and transferring thecomplete packet in the buffer, LL encoder gener-ates an indication signal (ll_enc_done, Fig. 3) tomaster controller which in turn initializes thePhy Layer encoder, provided that it is not al-

ready busy. Link layer encoder also sends thenew packet size (packet size changes after pass-ing through the packet assembler) to master con-troller. Master controller then sends this newpacket size to Phy layer encoder at the time of itsinitialization.

Master controller must deassert the initializing signal ofProtocol Layer, Link Layer and Phy Layer Encoders assoon as they acknowledged. Fig. 5 depicts the timing dia-gram of encoding process.

Note: Master must deassert the initializing signal of ProtocolLayer, Link Layer and Phy Layer Encoders as soon as they

acknowledged.

4INTERFACESIGNALS

4.1 MAC LTSSM Interface Signals

The MAC LTSSM I/O signals are described in the Table1. The signals described as inputs are received by MACand those described as outputs are driven by MAC.

4.2 MAC Master Controller Interface Signals

The signals used to monitor and control the PHY LayerController are described in the Table 2. The signals aredescribed from the perspective of Master Controller. Thusthe signals described as input are received by the Mas-ter and signals described as output are driven by theMaster.

4.3 MAC Layer Internal Signals

Communication flow between intermediate modules ofPHY Layer Controller is shown in Fig. 2. The Phy Encod-er Read Buffer interface signals and Phy Decoder Write Buffer interface signals are described in the Table 3.The signals described here are from the perspective ofPhy Encoder and Phy Decoder. Thus a signal described as

an output is driven by Phy Encoder/Decoder and thesignal described as an input is received by the Phy En-coder/Decoder.

4.4 MAC PHY Interface Signals

The MAC-PHY input and output signals are described inthe Table 4. The signals described here and later are de-fined from the perspective of a PHY Layer Controller(MAC Layer). Thus a signal described as an output isdriven by MAC and the signal described as an input isreceived by the MAC.


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Fig. 5: Timing diagram of encoding path controller.

TABLE1

MACLTSSMI/OINTERFACE SIGNALS

Name Direction Active Level Description

[1:0] PowerDownLTSSM Input N/AInstruction for MAC to take PHY chip into thePower State (P0, P1, P2 or P3) mentioned byLTSSM.

transmit_LFPS Input HighInstruction for MAC to transmit Low FrequencyPeriodic Signaling (LFPS) when the PHY is inP1, P2 or P3 state.

transmit Input High Instruction for MAC to begin transmission op-eration followed by the proper protocols.

receiver_DO Input High Instruction for MAC to do receiver detectionoperation.

[2:0] Rx_status_2LTSSM Output N/A Sends encoded receiver status to LTSSM.

LTSSM_phy_status Output HighInforms LTSSM the completion of several PHYfunctions including power management, statetransitions, rate change, and receiver detection.

do_rx_termination Input High Controls the presence of receiver terminationscommanded by LTSSM.

VBUS Output High Indicates the presence of VBUS to LTSSM

LFPS_detected Output High Indicates LTSSM that Low Frequency PeriodicSignaling (LFPS) is being detected.

4.5 MAC Link Layer Controller Interface Signals

The MAC-Link Layer Controller I/O signals are describedin the Table 5. The signals described as inputs are receivedby MAC and those described as outputs are driven byMAC. DPRF (for Encoder) is used by the Link Layer Con-troller to write the data in dual port memory.

That data is read and send (to PHY chip) by the Read BufferInterface and Phy Encoder respectively (See Fig. 2). Similar-ly, the data coming from the PHY chip is received by Phydecoder, andthen written into DPRF (for Decoder) through the WriteBuffer Interface, which is then used by Link Layer Control-ler (See Fig. 2).


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TABLE 2

MACMASTER CONTROLLER I/OINTERFACE SIGNALS


clk Input N/A Pclk coming from PHY chip.

done Input HighAsserts after a complete transaction of packetfrom Read Buffer interface to PHY chip.

phy_active_tx Input High

Indicates that Encoder is active and fetching

data from Read Buffer interface.rx_done Input High Informs the Master controller that one packet

has been fetched from PHY chip.

phy_active_rx Input High Indicates that decoder is in active state and read-ing data from PHY chip.

[10:0]packet_size Input N/A Size of packet (calculated by Phy Decoder) re-ceived from the PHY chip.

[8:0] pld_base_addr Input N/A Base address of next packet generated by Phydecoder.

[8:0] pld_base_addr_en Output N/A Base address from which Phy Encoder needs toread data.

[10:0] pack_size Output N/A Instruct Phy Encoder to fetch the given size ofpacket.

reset_n Output Low Master resetstart_en Output High Starts encoding operation.

TABLE 3

MACINTERNAL SIGNALS


ready_en Output High Signal used to inquire the Read Buffer Interface

whether it is ready to send data to Phy Encoder.

ack_en Input High Acknowledgment of ready_en signal from Read

Buffer interface.

[31:0]rd_data Input N/A 32-bits data bus used to fetch data from Read BufferInterface.

EOP Input High End Of Packet: indicates last packet from Read Buffer

interface.

valid Input High Indicates valid data at rd_data bus of Read Buffer

interface

buf_if_active_en Input High It signifies that Read Buffer is in active state and

fetching data from dprf.

phy_rd_valid Output High Indicates valid data, at 32-bits RxData bus, to Write

Buffer Interface.

ready_de Output High

Signal used to inquire the Write Buffer Interface

whether it is ready to receive data from Phy Decoder.

[31:0]phy_wr_data_bus Output N/A

32-bits data bus; used to write data into Write Buffer

interface.

phy_data_last Output High Indicates last packet from PHY chip

buf_if_active_de Input High It signifies that Write Buffer is in active state and writ-

ing data into dprf.

ack_de Input High Acknowledgment of ready_de signal from Write

Buffer interface.


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TABLE 4

MAC-PHYI/OINTERFACE SIGNALS


Encoder

[31:0]Txdata Output N/A

Parallel USB data output bus. 32 bits represents the 4

symbols of transmit data. Bits [7:0] are the first symbol

to be transmitted, and bits [31:24] are the fourth sym-

bol.

[3:0]TxdataK Output N/A

Data/Control bit for the symbols of transmitted data.

For 32-bit interfaces, Bit 0 corresponds to the Low-byte

of Txdata (i.e. bits [7:0]) and Bit 3 corresponds to the

Upper-byte (i.e. bits [31:24]). A value of 0 indicates a

Data byte and a value of 1 indicates a Control byte.

TxDetectRx Output High Request PHY to begin a receiver detection operation.

Tx_elec_idle Output High

Force Tx lines to remain electrical idle when asserted in

all power states.

When deasserted while in P0 (as indicated by the Pow-

erDownLTSSM signals) indicates a valid data is present

on Txdata and TxdataK lines and must be transmitted.

[1:0] PowerDown Output N/A Power up or down the transceiver power states.

phy_status Input High Used to communicate completion of several PHY func-tions including power management state transitions,

rate change, and receiver detection.

[2:0]Rx_status Input N/A

Encodes receiver status and error codes for the received

data stream when receiving data.

Receiver is detected when Rx_status = 011.

Decoder

[31:0]RxData Input N/A

Parallel USB data input bus. 32 bits represents the 4

symbols of received data. Bits [7:0] are the first symbol

to be received, and bits [31:24] are the fourth symbol.

[3:0]RxDataK Input N/A

Data/Control bit for the symbols of received data. For

32-bit interfaces, Bit 0 corresponds to the Low-byte of

RxData (i.e. bits [7:0]) and Bit 3 corresponds to the

Upper-byte (i.e. bits [31:24]). A value of 0 indicates a

Data byte and a value of 1 indicates a Control byte.reset_rx_tx Output Low Resets the transmitter and receiver

RxPolarity Output High

Instructs PHY to perform a polarity inversion on the

received data:

0: PHY doesnt invert polarity

1: PHY does polarity inversion

RX_Termination Output High

Control the presence of receiver terminations:

0: Terminations removed

1: Terminations present

RxValid Input High Indicates valid data on RxData and RxDataK

Rx_elec_idle Input High

Indicates receiver detection of an electrical idle. While

deasserted with PHY in P0, P1, P2 or P3 indicates the

detection of LFPS [1].

PowerPresent Input High Indicates the presence of VBUS.

External

Signals

PCLK Input Rising Edge

Parallel interface differential data clock. All data

movement across the parallel data interface is synchro-

nized to this clock which operated at 125MHz (in USB

case).

Phy_mode Output N/A

Selects PHY operating mode

0: PCI Express

1: USB Mode

So it should always be kept High.


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TABLE 5

MACLINK LAYER CONTROLLER I/OINTERFACE SIGNALS


[8:0]ll_wr_dprf_addr Input N/A Address from which Link Layer Controller starts writ-

ing the data in DPRF.

[31:0]ll_wr_dprf_din Input N/A 32-bits data input bus.

[31:0]ll_wr_dprf_wem Input N/A Write enable mask.ll_wr_dprf_en Input High Enable DPRF for writing data.

[8:0]ll_rd_dprf_addr Input N/A Address from which Link Layer Controller wants to

read the data from DPRF.

ll_rd_dprf_en Input High Enable DPRF for reading data.

[31:0]ll_rd_dprf_dout Output N/A 32-bits data out.

Ignore Input High Force Phy Decoder to ignore the incoming packet of

data until lrty is found.

lrty_found Output High Informs the Link Layer Controller that header packet

is resending.

5MEDIA ACCESS (MAC)LAYER OR PHYSICAL

LAYER CONTROLLERThe main object of this research is the implementation ofMAC Layer encoder and decoder that runs in paralleland hence ensures the concurrent in-out transaction ofUSB 3.0 protocols.

Before discussing the developed algorithm of MACEncoder and Decoder, it is good to have a look at thestandard USB 3.0 packet [1] first. It is also portrayed inFig. 6. Refer [1] for detailed description of packet sym-bols.

Fig. 6: Standard USB 3.0 packet with maximum of 1024 data bytes

5.1 MAC Layer Encoder (Phy Encoder)

It is recommended to refer [2] first for PHY Chip encod-ing signals, in order to understand Phy Encoding algo-rithm. Algorithmic State Machine Description (ASMD) ofPHY Encoder is shown in Fig. 7.

When an encoding process is done by Link Layer con-troller, it asserts ll_enc_done (section III-B), informing

master controller that a valid data has been placed in du-al-port-memory and must be fetched by Phy Encoder.Master controller then asserts start_en (Fig. 3) signal toinitialize Phy encoder and waits for being acknowledgedby Phy encoder.

LTSSM controls the power state of PHY chip throughPhy Encoder. Phy chip remains idle in P1 and P3 powerstates [1]. In P2 state, encoder waits for the instructionfrom LTSSM either to force Phy Chip to transmit LFPS [1]or to do receiver detection operation (Fig. 7). When a val-id data is present in the buffers, LTSSM instructs PhyEncoder to take Phy chip into P0 state. Encoder starts theprocess of fetching data, from buffer, only when a posi-

tive edge of transmit is seen asserted.When LTSSM asserts transmit signal, encoder re-

quests the data and waits for the acknowledgment fromRead Buffer Interface. When transaction begins, encoderobtains the data payload size from the packet size (givenby master controller, in terms of bytes) and puts into theregister, named data_pld_size. The purpose of calculat-ing the data payload size is to find out how many num-ber of transactions are required to send the completepacket to Phy chip. Since each transaction can have 4symbols of transmit data (32-bit bus) [refer 1 for detaileddescription], therefore a packet size is divided by 4 toobtain the correct number of transactions required. Refer-

ring [2], TxDataK bus indicates Control or Data byte in acurrent transaction.The RTL of encoder is efficient enough to locate which

byte is a control byte or data byte in a current transaction.Fig.4 depicts that there are two such transactions (1 st and6th) which have complete control symbols (bytes) in it.The last transaction should have all control bytes, but itdepends on the data payload size. If data payload size isnot a multiple of 4, then there must be an ambiguitywhich symbol is a control or a data byte, in 2nd last trans-action. Two least significant bits of data_pld_size indi-cates the position of data byte in 2nd last transaction(Fig.6).


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5.2 MAC Layer Decoder (Phy Decoder)

Decoding process is pretty complicated and a challengingtask. It is recommended to refer [2] to grasp the PHY Chipdecoding signals. ASMD of Phy Decoder is shown in Fig. 8.

PowerState of Phy Decoder is again in a control of LTSSM.Phy Decoder remains idle in P1 & P2 states. In P3, LTSSMasserts receiver_DO (See Fig. 2) signal when it requires re-ceiver detection operation to be performed.

Fig. 7: ASMD of Phy Encoder (see Fig. 2 for block level diagram)


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Phy Decoder in-turn asserts TxDetectRx signal [2], request-ing PHY chip to begin receiver detection operation. Thissignal should remain high until phy_status signal [2] fromPhy Chip is seen asserted. When the receiver detection opera-tion is completed, PHY chip asserts phy_status signal [2].Phy decoder then deasserts TxDetectRx, meanwhile in-forms LTSSM, the status of receiver throughRx_status_2LTSSM bus.

As soon as LTSSM instructs Phy decoder to take PHY Chipinto the power state P0, decoder starts looking forRx_elec_idle signal. Phy Decoder informs the LTSSM aboutLFPS on the basis of Rx_elec_idle signal. It then goes intoidle state until valid data is present at RxData bus. Whenthe valid data is present, decoder interrogates the WriteBuffer Interface (Fig. 2) whether it is ready to accept the in-coming data, and jumps to the ackldg (acknowledge) state.

.

Fig. 8:ASMD of Phy Decoder (see Fig. 2 for block level diagram)


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It then waits for the acknowledgment from WriteBuffer Interface. As soon as the buffer acknowledges,decoder starts fetching and sending data from Phy Chipto Write Buffer Interface respectively (Fig. 2). Phy De-coder keeps on transferring packet from Phy Chip toWrite Buffer Interface unless the Link Layer Controllerasserts ignore signal.

When ignore is seen asserted, Phy decoder discardsthe incoming data from the Phy Chip and starts lookingfor LRTY [1]. Phy Decoder also calculates the size ofpacket while transferring data from Phy chip to WriteBuffer interface. Fig. 4 depicts that a packet can have amaximum size of up to 1024 bytes (max data payload) +28 bytes (standard protocol of each packet).

The packet size is calculated in such a way that a coun-ter is incremented each time a transaction occurs. Decodercontinuously monitors RxDataK lines. Control byte isindicated by RxDataK bus whenever its value is non-zero.Whenever a non-zero value is present at RxDataK lines,another separated counter is incremented to monitor thenumber of control byte transactions. Referring to the Fig.

4, it can be observed that there could only be 3 or 4 suchtransactions which have control bytes in it, i.e. the firsttransaction, the sixth transaction and the last transaction.There could be fourth control byte transaction when datapayload size is not a multiple of 4 (i.e. first three of thelast four control bytes can be a part of second last transac-tion).

Since the first and the sixth transaction is a completecontrol byte transaction, therefore one doesnt need tocare about them. The problem arises after data pay loaddue to variations in the data payload sizes.

ASMD shown in Fig. 6 depicts that decoder repeatedlychecks for rxdataK_count to become equal to 2. When

rxdataK_count become equal to 2, decoder checks thevalue of RxDataK. RxDataK = 4hF point towards that allthe four bytes are control bytes and a current transactionis End of Packet. RxDataK, other than 4hF, clearly indi-cates that the data payload size is not a multiple of 4 andthe present transaction contains the data byte(s) alongwith the control byte(s). Also we would have fourth con-trol byte transaction. If RxDataK = 4h8 (4b1000), itshows, there are 3 data bytes and 1 control byte. This onecontrol byte is actually from the four of the last controlbytes (shown in Fig. 4). This means that there will be only3 (remaining) control bytes in the next transaction and thelast byte will remain empty, thus a value of 1b1 is sub-

tracted from the size of packet (shown in Fig. 6). Similarmethod is implemented for RxDataK = 4hC and 4hE.

6HARDWARE UTILIZATION

The RTL designs of both PHY Layer and Master Control-lers are fully synthesized using Virtex-5 XC5VLX110Tdevice. The resource utilization by PHY Layer Controllerand Master Controller are presented in Table 6 and Table7 respectively.

TABLE 6

RESOURCE UTILIZATION BY PHYLAYER CONTROLLER

Resources Used Available Utilization

Register 108 69120 0.15%LUT 222 69120 0.32%Slice 116 17280 0.67%

TABLE 7RESOURCE UTILIZATION BY MASTER CONTROLLER

Resources Used Available Utilization

Register 50 69120 0.072%LUT 51 69120 0.073%Slice 18 17280 0.1%

7FUNCTIONAL VERIFICATION

Although the whole of the USB Device is written insynthesizable RTL code, this entity will be representing thebehavior of the Host plus the behavior of the PHY Chip. It is

meant only for simulation purposes and can never infer ahardware at all. It can supress the concept of separate layersand can accommodate the behavioral of the host entity andPHY Chip as a single entity which is needed to derive theMAC layer, appearing in the front-line of the upstream facingport (USB Device).

Random data is generated through a testbench and in-puts to MAC Layer (assuming that it is coming from LinkLayer, See Fig. 1, and Fig. 2) and a pre-defined packet sizefor each time a simulation runs. This data is processed byPhy Encoder via dual-port-memory and read buffer inter-face (Fig. 2). Phy Encoder passes this data to PHY Chip(behavioral model) which loop backs that to Phy Decoder.

Phy decoder remains idle unless RxValid signal (frombehavioral of PHY, Fig. 2) is seen asserted. As soon as therising edge of RxValid signal is sensed, decoder requestsWrite Buffer Interface to received data coming from theHost. Once it acknowledges, the Phy decoders startsfetching the data and place it on the ports facing writebuffer interface which in turn place the data into the dual-port-memory (Fig. 2). Meanwhile it also looks for the con-trol bytes (on RxData bus) on the basis of which it couldfind out the size of packet (See Section 4.2).

8CONCLUSION AND FUTURE WORK

Since SuperSpeed protocols are intended for dual simplextransmission lines, transmitting and receiving transactions inparallel, there is an absolute need of having the architecturewhich support such protocols.

In order to meet the requirements, separate encodeand decode paths work concurrently and independently.Thus encode path is associated with packet assemblers orencoders while the decode path is associated with packetdisassembler or decoders. Encode and decode paths areexecuted by the Master Controller State Machine to fulfillthe dual simplex capability of the bus.

This synthesizable implementation of MAC Layer(Physical Layer Controller) follows the latest specification


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of USB 3.0. It is designed in such a way that other layerscan be easily interfaced with it.

Link Layer, Protocol Layer and LTSSM will bedeveloped in future as an independent entity and

integrated with this layer. The future objective could becomplete USB 3.0 memory device whose top leveldiagram is shown in Fig. 9.

Fig. 9: The overall block diagram of proposed architecture.

REFERENCES

[1]. Universal Serial Bus 3.0 Specification, Hewlett-Packard Compa-ny, Intel Corporation, Microsoft Corporation, NEC Corporation, ST-NXP Wireless, and Texas Instruments, Revision 1.0, November 12,2008.

[2]. PHY Interface for the PCI Express TM and USB Architectures,Version 2.90, Intel Corporation, 2007-08.

[3]. Universal Serial Bus Specification, Revision 2.0, April 27, 2000.[4]. On-The-Go Supplement to the USB 2.0 Specification, Revision

1.3, December 5, 2006.[5]. Inter-Chip USB Supplement to the USB 2.0 Specification,

Revision 1.0, March 13, 2006.[6]. USB System Architecture (USB 2.0), MindShare, Inc., Don

Anderson.[7]. eXtensible Host Controller Interface for Universal Serial Bus

(xHCI), Revision 1.0, 2010.[8]. Peter J. Ashenden, Digital Design: An Embedded System Ap-

proach using Verilog, Elsevier, 2008.

Hasan Baigobtained his Bachelors of Engineering Degree(Electronics) from NED University of Engineering andTechnology, Karachi, Pakistan, in January 2010. Currentlyhe is pursuing his MS Degree in Embedded Computingfrom Chosun University, Gwangju, South Korea. Also, heis serving as a Research Assistant to Prof. Jeong-A Lee in

computer system lab. He is a recepient of Korean GlobalIT Scholarship to carry out research and higher studies.He has conducted many workshops on behalf of IEEEStudents branch. His research interest includes embeddedsystem design, FPGAs, on-chip process variationsestimation, partially reconfigured embedded systems.

Jeong-A Lee is presently a Professor of Department ofComputer Engineering, since joining Chosun Universityin 1995. She received the B.S. in Computer Engineeringwith from Seoul National University in 1982, M.S. inComputer Science from Indiana University, Bloomingtonin 1985 and Ph.D. in Computer Science from University ofCalifornia, Los Angeles in 1990. From 1990 to 1995, she

was an assistant professor at the Department of Electricaland Computer Engineering, University of Houston. Herresearch interests include computer architecture, fast digi-tal and CORDIC arithmetic, application specific architec-tures design and configurable computing. She is the au-thor of more than 100 technical papers, was a guest editorof a special issue on CORDIC, Journal of VLSI Signal Pro-cessing Systems for Signal, Image, and Video Technologyin 2000, and has been working as a programming com-mittee member for several international conferences and asenior member of IEEE.

Documents

Architectural Development and Functional Verification of SuperSpeed USB 3.0 PHY Layer Controller