36

Architecture for a General PurposeConfigurable Radio

Architecture for a General PurposeConfigurable Radio

37

Phase 1 - Proposed Reconfigurable Receiver ArchitecturePhase 1 Implementation of theConfigurable Radio

Phase 1 Implementation of theConfigurable Radio

To Be Determined

Filtering/Adaptive

Equalization

ComplexFIR Filter

Despread

BinaryCorrelator

Sampling

Tracking

Acquisition

NoncoherentDemod

FSKPSK

FEC Decoder

BlockConvolutional

Turbo

De-interleave

AntennaDiversity

Combiner

DigitalDown-

converter

DigitalDown-

converter

RFFront End

RFFront End

ReceiverControl

Host/Network

API

Sigtek ST114

Direction for replacement of DSP µP functionswith reconfigurable computing

38

Reconfigurable Computing ModulesUnder Development

Reconfigurable Computing ModulesUnder Development

l Turbo Coder/Decoderl Equalizer/ Single User CDMA Receiverl Symbol/Carrier/Code Synchronizersl Next ModulesÕ Generic sample rate converterÕ Coder/Decoder libraryÕ Demodulator library

39

Analog Tuner:Õ Downconverts from an RF of 2050 MHz

to an IF of 68 MHz for bandpassdigitizationÕ RF and IF filtering used to reject image

frequencies

RF Front EndRF Front End

l ST-114 Digital Down-converter:Õ HSP 50214 processorÕ Combines quadrature mixing to complex baseband, digital filtering and decimationÕ Up to 1.2 MHz of bandwidth

l Custom RF and IF analog filtersl Later Stages - Migrate to custom digital down-converter front end

40

Evolution of the ConfigurableComputing Platform and

Configurable Radio

Evolution of the ConfigurableComputing Platform and

Configurable Radio

41

Phase 3 - Proposed Reconfigurable Receiver Architecture (PCI-based)

Graychip

DDC

Graychip

DDC

ANALOG

SUPPLY

PCI-BASEDHOST

INTERFACE

Q FIFO

I FIFO

RF InputCircuitry

Channel 2

CombinerFPGA

RF InputCircuitry

Channel 1

ADC

DSP

ADC

DIGITAL

SUPPLY

SRAM

SRAM

OUTPUTMODULE

FPGA

PROCESSINGMODULE

#1

INPUTMODULE

FPGA

SRAM

SRAM

PROCESSINGMODULE

#2

PROCESSINGMODULE

#4

PROCESSINGMODULE

#3

PROCESSINGMODULE

#6

PROCESSINGMODULE

#5SRAM

SRAM

DP

RAM

I/QMOD

RFOUTPUT

FREQSYNTH

XMITFPGA

CODECANALOGINPUT

ANALOGSUPPLY

RAM

DAC

DAC

RAM

RAM

SRAM

DPLL

FEC

Phase 3 Final ArchitecturePhase 3 Final Architecture

Features

l Wider bandwidth front end

l Stallion processor

l Run-time reconfiguration

l Library of communication

functions

42

Hardware Based SimulatorHardware Based Simulatorl Fast simulation engine by taking advantage of

reconfigurable processorl Supports radio development effort

PC

(Preprocessorfor systemconfigurationand for settingsystemparameters)

reset

mod_sel

θAc

Externalinput

PNsequencegenerator

(Data)

Enable

init_stat

reg_length

reset

σ2

seed

Modulator

Receiver

(Demodand datadecisions)

Noisegenerator

2x1MUX

××

PC

(Post-processorfor datacollectionandanalysis)

I

Q

I

Q

43

SummarySummary

l Architecture of flexible high-performanceradio test-bed outlined

l Stream-based approach increasesflexibility of pipeline architecture

l Configurable computing very promising tomodern and future communicationsystems