1

ARM’s Product Roadmaps

December 2006William Liu

ARM Connected Community Technical Symposium

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The Developing Market

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Investing in R&DMajor challenges can only be met by significant, ongoing investmentsNeed integrated solutions

ARM continues to invest over a vast spectrum From 1GHz+ processors to 8-bit MCU replacementOptimized 90, 65 and 45nm low power librariesSoftware, tools, Fabric, Audio & Graphics processors

ARM’s model allows this to be shared across the Partnership

4

H

L

H

L

From 1$ MCU to 1 GHz+ Cortex-A8

H

L

ApplicationsProcessor

Market

Real-TimeEmbedded

Market

MicrocontrollerMarket

ARM926EJ-S

Cortex-A8

ARM11 MPCore

ARM1176JZ(F)-S

ARM1136J(F)-S

600+ MIPS Uni-Proc

2000+ MIPS Uni-Proc

2000+ MIPS Multi-proc

600+ MIPS Uni-Proc

250+ MIPS Uni-Proc

ARM7TDMICortex-M3

ARM968E-S

ARM946E-S

ARM1156T2(F)-S

ARM7TDMI

600+ MIPS Uni-Proc

150+ MIPS Uni-Proc

100+ MIPS Uni-Proc

Cortex R4 600+ MIPS Uni-Proc

5Worst case conditions

Perf

orm

ance

DM

IPS

2000

500

1500

1000

ARMv5 ARMv6

2500

90G Technology NVTDual-core performance assumes 50% utilization of 2nd core

Cortex-A8

ARM1176JZF-S

Cortex

ARM926EJ-S™

Applications Processor Roadmap

Leading the industry in performance and low power

2006 2007 2008 2009

ARM11 MPCoreDual Core

3000+

Up to 4x

ARM1136JF-S

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Cortex-A8

-

0.55

16K/16 K

3.5

5

500-550

Advantage**

Advantage-HS

Synthesized

-

0.50

16K/16 K

3.2

4.5

660-700

Custom

Advantage-CE

Optimized

65 LP process

-

0.40

16K/16 K

3.2

4.5

1GHz+

Custom

Advantage-CE

Optimized

65nm G+ process

0.45Power with cache (mW/MHz)

16K/16 KCache size

Advantage-HSStandard Cells

Advantage**Memories

-Power w/o cache (mW/MHz)

3.5Area without cache ( mm2 )

5Area with cache (mm2)

800Frequency ( MHz )

SynthesizedPPA

High performance processor delivering 2,000+ DMIPSIn-order, dual-issue, superscalar core with 13 stage pipelineThumb-2 technology for greater performance, energy efficiency, and code densityNEON™ signal processing extensions to accelerate media codecs such as H.264 and MP3, 10 stage NEON pipelineJazelle RCT technology to optimize Just In Time (JIT) and Dynamic Adaptive Compilation (DAC),reduce memory footprint by up to three timesTrustZone technology for secure transactions and Digital Rights Management (DRM)Integrated L2 Cache built using standard compiled RAMs, configurable size 64K–2MB and programmable wait states

** Optimized inst ances of Adva ntag e RAMSArea inclu des L 1 RAMS, L2 cont rol. Exclud es NEON, ETM , L2 RAMS Data scale d fr om 9 0nm ref eren ce im pleme ntati ons

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Cortex-A8 NEON Technology

MPEG-4

MP3 DecoderGSM-AMR

1x 2x 4x3x

NEONARMv6ARMv5

1) MPEG-4 Simple Profi le @ 30fps 512kbps , 133MHz S DRAM 10-1- 1-1- 1-1-1- 1 mem ory, includes deblock ing and deringing filt ers

2) MP3 Dec oder @ 320k bps 48kHz ( worst case), 133M Hz SDRAM 10-1- 1-1- 1-1- 1-1 mem ory

3) GSM-AMR (worst cas e), 3 cycle per wor d memory

4) H.264 Decoder B asel ine profile

9.4MHzMP3 decode, 320kbps 48kHz, worst case3

13MHzGSM-AMR, worst case2

350MHzH.264 (estimated)4

Video, 30fps VGA decode 275MHzMPEG-4 including de-ring and de-block filters, yuv2rgb1

Accelerating standardization of media processing for next generation mobile and consumer productsThe ideal software target to run rapidly evolving downloadable media players such as Windows Media Player 10 and Real Player

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Embedded Processor Roadmap

2005 2006

Worst case conditions

Perf

orm

ance

(DM

IPS)

250

300

400

100

500

600

2007

ARM996HS

ARM1026EJ-S™

ARM946E-S™

ARM968E-S™

ARM7TDMI®

ARM1156T2F-S™

ARM966E-S™

ARM7EJ-S ™ Cortex-M3

Cortex-R4

ARMv5 ARMv6 CortexARMv4

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Cortex-R4

** The abov e nu mbe rs a re eit her quot ed f rom f ully floo rpla nne d layou ts/synt hesis tri als or scaled wi th r espect to p rocess and li bra ry pe rfo rma nce

0.160.170.250.33-Power w/o cache (mW/MHz)

0.220.2460.330.41-Power with cache (mW/MHz)

16K/16 K16K/16 K16K/16 K16K/16 K16K/16 KCache size

0.80.971.181.661.99Area without cache ( mm2 )

1.51.71.912.53.35Area with cache (mm2)

230275400500300Frequency ( MHz )

MetroAdvantageAdvantageAdvantageHSMemories

MetroSage-XSage-XAdvantage-HSSage-HSStandard Cells

Area OptSpeed OptArea Opt

90nm process0.13um process

PPA

Highly eff icient mid-range embedded processorSelective superscalar pipelineThumb-2 for high performance with excellent code densityClass-leading 1.60 DMIPS/MHz

Highly configurable for optimum fit to applicationConfigurable caches, TCMsand MPU

Flexible TCM architectureUp to three, 64-bit interfacesNo need to split instruction/dataParity and ECC support

Designed for ease of integrationSingle 64-bit AMBA-3 AXI master interfaceIntegrated AMBA-3 AXI DMA port

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Cortex-M3

0.09

0.22

135

SAGE-X

Speed Opt

0.13um process

0.06

0.16

50

Metro

Area Opt

0.030.04Power w/o cache (mW/MHz)

0.090.10Area without cache ( mm2 )

50150Frequency ( MHz )

MetroSAGE-XStandard Cells

Area OptSpeed Opt

90 nm process

CM3 Core

** The abov e nu mbe rs a re q uote d fro m fully fl oor plan ned lay outs/sy nthesis trials

0.12

0.39

135

SAGE-X

Speed Opt

0.13um process

0.09

0.30

50

Metro

Area Opt

0.050.07Power w/o cache (mW/MHz)

0.170.19Area without cache ( mm2 )

50150Frequency ( MHz )

MetroSAGE-XStandard Cells

Area OptSpeed Opt

90 nm processCortex-M3 Proces sorMin imu m c onfigurat ion

Compact processor for microcontroller and low cost applications Cortex-M3 is ideal for cost-sensitive and low-power 32-Bit devicesUp to 60% more performance & 50% smaller code vs ARM7TDMI-SLow-power solutions at 0.09mW/MHz in 0.13um ProcessThumb-2 technology for greater performance and code densityHardware divide instructions for control applicationsIntegrated NVIC for industry leading interrupt handlingExtensive debug architecture with up to 8 hardware breakpointsFlexible bus interfaces to memory systems & peripheralsAn optional Memory Protection Unit (MPU)

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Foundry Program Supports Various Applications

Scalable processor performanceFrom ARM7 to ARM9, process support from 0.25um to 90nmProvide idea upgrade path for different applications

Basic processor ARM7TDMI Embedded controller ARM946E Application processor ARM926EJ

Multiple configurations to match different requirementsFor example ARM926EJ

Performance optimizedWith 16KB/16KB cache, 5.1m㎡, 0.54mW/MHz, 230MHz

Area optimized With 8KB/8KB cache, 2.3m㎡, 0.48mW/MHz, 238MHz

Wide range of foundry and process choice

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Foundry Core Availability Table

The blank in this table means not ready yet, but could be done in a short term based on customer request.More about supported process details at http://www.arm.com/products/FoundryProgramSchedule.html

√

√

√

√(8K,2007)

√

√

√

ARM926EJ

√√√√0.13um

√0.25um

√0.18umDongbuAnam√0.13um

√√√√0.13um√√√0.18um

UMC

0.13um

√0.18umGrace0.13um

√√0.18umSMIC

√√√0.18umChartered

√0.25umTSMC

Tower

Silterra

Foundry

√0.18um

ARM1022EARM922TARM946EJARM7TDMIProcess

√0.18um

√√0.13um

90nm

√√√0.18um

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SoC Challenges: Build a SystemArchitectureExploiture

Software Development

LogicDesign

PhysicalImplementation

SystemPrototyping

Select IP & Build SystemProven Solution

Inter-connection & System DesignDesign and Verif ication Methodology

Quick Prototyping is NOT debugging PCB50% of time is spent on OS porting and systems testing

PPA is the KEYFlexibility for Manufacture

Efficient & Effective tools at design stageSoftware development as early as possible

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Mali™ Graphics processors

Efficient Memory Bandwidth UsageHigh Performance and Image QualityRich Feature Set for DifferentiationLow Production and Integration CostUpwards and downwards scalable solutions

Drivers

Key

HW

Middleware

Applications

API Drivers

Mali200 MaliGP2

GLES 1.x interface

ARM CPUBackend

MaliGP2Backend

ARM CPU

JSR- 239 / JSR -226 M3G1 / M3G2

Java VM

3D Game / Benchmarks / 3rd Party Applications

Native EE

OS (Linux, Symbian, WinCE, RTOS etc.)

Mali Hardware Abstraction Layer (HAL)

GLES 2.x interface

GLES common layer

Mali200Backend

Test APIs

Test API

Mali GPU te

chnology

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AudioDEAudioDE delivers compelling Pow er, Performance, Area benefitsUltra Low power for increased play back time (up to >40% in system)Average 8 MHz measured playing a test track*

0.65mW on 0.13um 1.08v TSMC 17.5KBytes program memoryMinimized memory accessTested with 128Kbps MP3 bitstream, 44.1KHz, stereo output

Host controller MHz is made available for value-added features

Easy to integrate data-driven “peripheral” abstractionReprogrammable for multi CODEC standards support

MP3, AAC, WMA, AMR etc

AvailabilityAvailable for delivery from March 31, 2006

* ‘w e_wi ll_ rock_y ou.mp3’

with ARM o ptimise d c odec

AudioDE Data Engineonly 50k gates

AudioDE Reference Subsystem< 1.7mW power consumption

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SoC Designer

SoC Designer

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What is Fabric IP?Fabric IP is:

Any IP component that moves or stores data but does not process it

The central Fabric IP component is the on-chip bus but it also includes:

Cache ControllersDMA ControllersMemory ControllersInterrupt ControllersMemory Management

ARMCPU

OptimoDE™

SMMU

GIC

L2 Cache

AMBA Interconnect

DM

A

System Cache

Dynamic Mem Control

Static MemControl

Peripheral

Peripheral

PeripheralPeripheral

Peripheral

SMMU

GIC

L2 Cache

AMBA Interconnect

DM

A

System Cache

Dynamic Mem Control

Static MemControl

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Fabric Product Roadmap

AMBA Designer

PL302 AXIInterconn ect

AMBA 3

PL24x AHB M emory ControllersAHB μDMA

{AMBA 4Interconn ect

PL301 AXIInterconn ectSwerve3D

Energy Manageme

nt

AXI Performance

Verification Kit

AMBA

Specification

Design

Automation

Interconnect

Controllers

Release Adv Develop ment Concept

AXIAHB

APB

AMBA 4 {ACE

AXIAHB

APB

PL201 AHBInterconn ect

PL100 APBSub-system

PL35x AXI StaticMemory ControllersPL340 AXI DDRMemory Controller

AXI DMA AXI Syst emLevel C ach eAXI DDR2 M em. Cont.

2006 2007 2008

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AMBA Designer, PL301 & SoC Designer

Engine

GUI

SystemCSimulation

AMBA Designer

SoC DesignerConfigured

Interconnect Model

Other system modelsSystemC

ModelsPrimeCells

and3rd Part y IP

Blocks

Verilog RTL Model of

Bus Structure

SystemCModel of

Bus Structure

PL301

Generates a Customer specific RTL model

Verilog Template Files

Verilog RTL Simulation

Configured Interconnect

RTL

Other system RTL

Standard VerilogSimulator

Generates a Customer specific SystemC model

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Improving Platform IntegrationLow risk solution for System Prototyping

Modularization, ReuseSupport most of ARM CoreSupport many OS&RTOS (BSP)Middlew are library and Bootloader

ARM has technologies to parallel development and prevent delays

RealView SoC Designer system model for accurate OS-portingReal Time System Model for fast application developmentFPGAs and testchips for system integrationSingle debug and compiler for all software development platforms

No need to change tool chain – removes massive risk

Embedded Software M arket Intel ligenc e Progr amVDC, 2006

Driver/OS development

and in tegration

System tes ting

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Improving Silicon ImplementationYield-aware libraries

Extensive knowledge of design rulesDFM decks and proprietary softwareHighly robust DFM-aware libraries

Power Management KitsPower gates (MT-CMOS)Retention flip-flopsBack-bias support

Smoothing the path to implementationExtensive collaborations with EDA vendorsto create best practice power aware flows

***ClassicMainstream Platform

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PPA Is NOT Only Hardware Job

Smallest Code Size

70%

80%

90%

100%

110%

120%

130%SD

T2.5

1

AD

S1.0

.1

ADS

1.1

ADS

1.2

RV-

CT3

.0

GNU

Ven

dor

1

Ven

dor

2

Ven

dor

3

Ven

dor

4

Ven

dor

5

Best Performance

50%

60%

70%

80%

90%

100%

110%

SDT2

.51

ADS1

.0.1

ADS1

.1

ADS1

.2

RV-C

T3.0

GNU

Vend

or1

Vend

or2

Vend

or6

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RealView Microcontroller Development Kit

Powerful featuresRealView Compilation Tools.Keil µVision Integrated Development Environment.

Configuration support for microcontrollersComplete simulation of target hardware

Optional hardware productsULINK USB-JTAG AdapterEvaluation Boards

RTX Real Time KernelReleased Q2,06

Complete software development environment for ARM based microcontrollers. Easy to learn and easy to use!

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ARM Embedded SoftwareEmbedded software products for mobile and consumer markets

Enabling rich user experience to consumers

Fast, consistent execution for Java applications

Execution of 3D content for an outstanding gaming

experience

Secure, open framework for

security applications

Run-time control for maximizing battery life

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Support Your Success

Fabric IP

Integrator™Versatile

SoC Designer

AMBA Designer

System Generator

Mali3D Engine

ArchitectureExploiture

Software Development

LogicDesign

PhysicalImplementation

SystemPrototyping