Arvind Sudarsanam Resume

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Arvind Sudarsanam47 Alder St Unit 11 Waltham MA - 02453 (435) 512-7769 [email protected]

OBJECTIVE

Seeking a full-time research and development position.

SUMMARY

An accomplished compiler engineer with multiple years of industry experience focusingon managing compiler designs for varied architectures.

PhD degree in Electrical and Computer Engineering focusing on design and performanceanalysis of novel systolic array architectures of Kalman filters for FPGAs and presentedand published research work at numerous forums.

PROFESSIONAL EXPERIENCE

Mediatek (Sep 2013Current)Senior Compiler Engineer

Involved in compiler development targeting varying platforms. Work includedcontributions towards re-targeting of 16-bit compiler to a 32-bit compiler, automated

testing of compiler using csmith, and helping towards multiple releases of the dsptoolkit.

Mathworks (Sep 2012Sep 2013)Senior Compiler Engineer

Involved in compiler optimization towards efficient code generation for Matlab and

Simulink

CPU Technology Inc(Oct 2009Aug 2012)

Software Design Engineer

Project #1: Multicore exploration and Compiler front-end development using LLVM

o Extensive Object-Oriented Programming using C++ to develop a compiler front-

end using LLVM base classes to generate CHiMPS Intermediate Representation(IR)

o

Exploration of cache hierarchy for multicore architectures using cycle-accuratesimulation of CHiMPS IR

o Developed in a Linux environment. Makefiles and scripts used for building and

testing programs. Subversion used for version controlo

Project #2: Development of integrated solutions for secure data transactions between

storage servers, desktop clients, mobile phones, etc.o

Development of secure server using Xilinx Virtex and Spartan FPGAs. Work

included compilation and running of linux kernel on microblaze soft processorand also developing a C-based multithreaded OpenSSL server to provide forsecure channel of communication

Project #3: Temperature cycling for Physical Unclonable Functions (PUFs) on Xilinx

FPGAso

Designed a 2-D array of PUFs on Xilinx FPGAs using VHDL and Xilinxsynthesis tools for Spartan FPGAs


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o Analysis of PUF frequency by controlled temperature variation in a thermalchamber

Intel Corporation(June 2008August 2008)

Graduate Intern in the Visual Computing Group, Hillsboro, OR

Summer project towards developing a reconfigurable motion estimation accelerator

towards Intels Larrabeeo

Developed a novel memory architecture using Verilog by analyzing results of

data dependency analysis of motion estimation algorithms.

Texas Instruments(Jan 2001Jun 2001)

Intern with the OMAP (Open Multimedia Application Platform) team

o 6 month project for optimizing algorithms for video preprocessing on TI C5510DSP

EDUCATION

Ph.D. Computer Engineering, Utah State University, Sep 2004Sep 2009

DissertationAnalysis of FPGA based Kalman Filter Architectureso

A novel polymorphic systolic array based Kalman filter architecture wasdeveloped for Xilinx Virtex FPGA. By varying algorithm and architectural

parameters, a comprehensive analysis was performed and partial reconfigurationtechniques were used to derive the optimal architecture for a given set of designconstraints

Course work in Compiler construction, Reconfigurable computing, Advanced

computer architectures, Real-time processing

M.S.Electrical Engineering, Arizona State University, Sep 2001 - Aug. 2004

GPA 3.6 / 4.0

Masters ThesisDynamic Memory Management and Scheduling for Reconfigurable

Media Processing

Course work in Verilog/VHDL design, VLSI design and architectures.

B.E.Electronics and Instrumentation, BITS, Pilani, India, Sep 1997 - Jun. 2001

GPA 3.53 / 4.0

Course work in DSP and Image Processing, microcontroller, analog and digitaldesign

ACHIEVEMENTS

Six publications in refereed peer journals, including International Journal of

Computers and Applications, IET Computers & Digital Techniques, and Journal forScalable computing: Practice and Experience

Ten publications in refereed conferences, including IEEE Proceedings of Parallel and

Distributed Processing Symposium, Proceedings of the High Performance EmbeddedComputing workshop (HPEC), and Proceedings of the SPIE conference on Electronic

Imaging. Presented work at the conferences

Best Graduate Researcher award in 2007. Conferred by the ECE department at Utah

State University

Two Patents (One pending and one accepted)


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JOURNALS (In chronological order)

A. Dasu,A. Sudarsanam,S. Panchanathan,Design of Embedded Compute Intensive

Processing Elements and their Scheduling in a Reconfigurable Environment, in theCanadian Journal of Electrical and Computer Engineering (CJECE), 2005.

T. Hauser, A. Dasu, A. Sudarsanam,and S. Young,Performance of LU decomposition

on a Multi-FPGA System Compared to a Low Power Commodity Microprocessor

System, in the journal for Scalable computing: Practice and Experience, 2007,Vol 8, No4.

J. Phillips, A. Sudarsanam, R. Kallam, J. Carver, and A. Dasu, Methodology to Derive

Polymorphic Soft-IP Cores for FPGAs, in the journal of IET Computers & DigitalTechniques, 2008.

A. Sudarsanam, T. Hauser, A. Dasu, and S. Young,A Power Efficient Linear

Equation Solver on a Multi-FPGA Accelerator, in the International Journal ofComputers and Applications, 2009.

A. Sudarsanam, R. Barnes, R. Kallam, J. Carver, and A. Dasu, DynamicallyReconfigurable Systolic Array Accelerators: A Case Study with EKF and DWT

Algorithms, in the journal of IET Computers & Digital Techniques, 2009.

A. Sudarsanam, A. Dasu, and K. Vaithianathan, Analysis and Design of a ContextAdaptable SAD/MSE Accelerator, in the International Journal of ReconfigurableComputing, 2009.

CONFERENCES (In chronological order)

1. A. Akoglu, A. Dasu, A. Sudarsanam, M. Srinivasan, S. Panchanathan,Pattern

recognition tool to detect reconfigurable patterns in MPEG4 video processing, in theIEEE Proceedings of Parallel and Distributed Processing Symposium, 2002.

2. A. Sudarsanam, S. Panchanathan, Current Trends for Silicon and Embedded

Computing Solutions for Automotive Applications, in the Proceedings of theconvergence conference of SAE, Detroit, October, 2002.

3. A. Sudarsanam, A. Dasu, S. Panchanathan, Task Scheduling of Control Data Flow

Graphs for Reconfigurable Architectures, in the Proceedings of the InternationalConference on Engineering of Reconfigurable Systems and Algorithms, 2004.4.

A. Sudarsanam, M.Srinivasan, S. Panchanathan,Resource Estimation and TaskScheduling for Multithreaded Reconfigurable Architectures, in the Proceedings of the

International Conference on Parallel and Distributed Systems (ICPADS 2004).5. A. Sudarsanam. S, Panchanathan, Novel predicated data flow analysis based memory

design for data and control intensive multimedia applications, in the Proceedings of theSPIE conference on Electronic Imaging, 2005.

6. A. Sudarsanam, A. Dasu, High Level - Application Analysis Techniques &

Architectures - to Explore Design possibilities for Reduced Reconfiguration AreaOverheads in FPGAs executing Compute Intensive Applications,in the Proceedings of

the Reconfigurable Architectures Workshop (RAW), 2005.

7.

A. Sudarsanam, A. Dasu, Implementation of Polymorphic Matrix Inversion usingViva,presented at the MAPLD conference, 2005.8. A. Sudarsanam, A. Dasu, A Fast and Efficient FPGA-Based Implementation

for Solving a System of Linear Interval Equations, in the IEEE Proceedings of the

conference on Field Programmable Technology (FPT), 2005.9. A. Sudarsanam, S. Young, T. Hauser, and A. Dasu,Multi FPGA based High

Performance LU Decomposition, in the Proceedings of the High PerformanceEmbedded Computing workshop (HPEC), 2006.


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10.S. Young, A. Sudarsanam, T. Hauser, and A. Dasu,Memory Support Design for LUDecomposition on Starbridge Hypercomputer, in the IEEE Proceedings of the

conference on Field Programmable Technology (FPT), 2006.

PATENTS

Patent approved on Methodology to Design a Reconfigurable Processor, Arizona State

UniversityPatent pending on A Near Optimal Configurable Adder Tree For Arbitrary Shaped 2d

Block Sum Of Absolute Differences (Sad) Calculation Engine, Intel Corporation

TECHNICAL EXPERTISE

HARDWARE

DESIGN TOOLS

Xilinx tools, Cadence HDL synthesis, Intels IPP, TI code composerstudio, Tanner tools

DESIGN

LANGUAGES

VHDL, Verilog, Viva (Starbridge Systems)

SOFTWARE

LANGUAGES

C++, C, Assembly (IXP1200, SSE2, AltiVec, TMS320C55x, ARM)

OS Windows, Unix, DOS

COMPILERS GNU C compiler, Lance compiler, Intel C++ compiler, LLVM, mingw

IDEs Qt, Xilinx EDK, Unix Development Environment, Matlab

DOCUMENTATION MS Word, Latex, Powerpoint, Visio

OTHERS Pthreads, Subversion

COURSE PROJECTS

VLSI design of a VLIW processor

FPGA-based hardware design for solving a system of linear interval equations

Layout design of Pseudo Random Number Generator using Tanner tools

VLSI architecture for MPEG-4 Sprite decoder

VHDL design of JPEG encoder

Matlab design of Multi-Resolution Motion Estimation

Analysis of MPEG-4 Motion Estimation Algorithm with the Two Level Top-Down

Partitioning Approach.

Speech recognition and Lip reading using Hidden Markov Models.

REFERENCES

Dr. Sethuraman Panchanathan; Dr. Aravind Dasu; Dave Bennett; Dr. Thomas Hauser;Dr. Brandon Eames

Documents

Arvind Sudarsanam Resume