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2008 International Conference on Application-specific Systems, Architectures and Processors (ASAP) Copyright © 2008 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Copyright and Reprint Permission : Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of U.S. copyright law for private use of patrons those articles in this volume that carry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid through Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923. For other copying, reprint or republication permission, write to IEEE Copyrights Manager, IEEE Operations Center, 445 Hoes Lane, P.O. Box, 1331, Piscataway, NJ 08855-1331. All rights reserved. IEEE Catalog number: CFP08063 ISBN: 978-1-4244-1898-5 Library of Congress: 2007908829 Additional copies of this publication are available from: IMEC vzw, tav Fred Loosen, Kapeldreef 75, B-3001 Leuven, Belgium. Phone: +32 16 281498. E-mail: Fred.Loosen@imec.be

 

 

 

 

 

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Session 2: System-level Interconnect and Mapping in SoCs ........................... 61

· A New High-Performance Scalable Dynamic Interconnection for FPGA-based Reconfigurable Systems .................................................................................. 61

· Extending the SIMPPL SoC Architectural Framework to Support Application-Specific Architectures on Multi-FPGA Platforms ................................................... 67

· PERMAP: A Performance-Aware Mapping for Application-Specific SoCs .................. 73

Session 3: Advances in Cryptography ........................................................ 79

· Low-cost Implementations of NTRU for Pervasive Security .................................. 79 · On the High-Throughput Implementation of RIPEMD-160 Hash Algorithm ............. 85 · Zodiac: System Architecture Implementation for a High-Performance Network

Security Processor ........................................................................................ 91

Session 4: New Computational Methods ..................................................... 97

· Efficient Systolization of Cyclic Convolution for Systolic Implementation of Sinusoidal Transforms .................................................................................... 97

· Resource Efficient Generators for the Floating-point Uniform and Exponential Distributions ............................................................................................... 102

· Low Discrepancy Sequences for Monte Carlo Simulations on Reconfigurable Platforms .................................................................................................... 108

Session 5: Novel Applications ................................................................. 114

· A Subsampling Pulsed UWB Demodulator Based on a Flexible Complex SVD ......... 114 · Dynamically Reconfigurable Regular Expression Matching Architecture ................ 120 · An MPSoC Architecture for the Multiple Target Tracking Application in Driver

Assistant System ......................................................................................... 126

Session 6: New Directions in Application-Specific Design ............................ 132

· Managing Multi-Core Soft-Error Reliability Through Utility-driven Cross Domain Optimization ............................................................................................... 132

Interactive Session 2 ............................................................................. 138

· An Efficient Implementation Of A Phase Unwrapping Kernel On Reconfigurable Hardware ................................................................................................... 138

· A Parallel Hardware Architecture for Connected Component Labeling Based on Fast Label Merging ....................................................................................... 144

· Operation Shuffling over Cycle Boundaries for Low Energy L0 Clustering ............. 150 · An Efficient Digital Circuit for Implementing Sequence Alignment Algorithm in an

Extended Processor ...................................................................................... 156 · Concurrent Systolic Architecture for High-Throughput Implementation of 3-

Dimensional DWT ........................................................................................ 162 · Hierarchical Design Space Exploration of a Cooperative MIMO Receiver for

Reconfigurable Architectures ......................................................................... 167 · A Dynamic Holographic Reconfiguration on a Four-Context ODRGA ..................... 173

vi  

· FGPA-based Hardware Accelerator of the Heat Equation with Applications on Infrared Thermography ................................................................................ 179

· FPGA Based Singular Value Decomposition for Image Processing Applications ....... 185

Session 7: Acceleration of Scientific and DSP Applications ........................... 191

· Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs .................................................................................................... 191

· A Multi-FPGA Application-Specific Architecture for Accelerating a Floating Point Fourier Integral Operator .............................................................................. 197

· Reconfigurable Acceleration of Microphone Array Algorithms for Speech Enhancement .............................................................................................. 203

Session 8: Advanced Communications Applications .................................... 209

· Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4G Wireless Standards ...................................................................... 209

· Architecture and VLSI Realization of a High-Speed Programmable Decoder for LDPC Convolutional Codes ............................................................................ 215

· Buffer allocation for Advanced Packet Segmentation in Network Processors .......... 221

Session 9: Arithmetic............................................................................. 227

· New Insights on Ling Adders ......................................................................... 227 · Integer and Floating-Point Constant Multipliers for FPGAs .................................. 233 · An Efficient Method for Evaluating Polynomial and Rational Function

Approximations ........................................................................................... 239

Session 10: Interconnect and Mapping ..................................................... 245

· Mapping of the AES Cryptographic Algorithm on a Coarse-Grain Reconfigurable Array Processor ........................................................................................... 245

· RECONNECT: A NoC for polymorphic ASICs using a Low Overhead Single Cycle Router ....................................................................................................... 251

· Loop-Oriented Metrics for Exploring and Application-Specific Architecture Design-Space .............................................................................................. 257

Session 11: Novel Processor and Memory System Techniques ..................... 263

· Rapid Estimation of Instruction Cache Hit Rates Using Loop Profiling ................... 263 · Reducing Power Consumption of Embedded Processors through Register File

Partitioning and Compiler Support .................................................................. 269 · Lightweight DMA Management Mechanisms for Multiprocessors on FPGA .............. 275 · Memory Copies in Multi-Level Memory Systems ............................................... 281

Session 12: Image and Video Processing .................................................. 287

· Architecture of a Polymorphic ASIC for interoperability across multi-mode H.264 decoders .................................................................................................... 287

· An FPGA Architecture for CABAC Decoding in Many-core Systems ....................... 293

vii  

· Novel Approach on Lifting-Based DWT and IDWT Processor with Multi-Context Configuration to Support Different Wavelet Filters ............................................ 299

· Throughput-Scalable Hybrid-Pipeline Architecture for Multilevel Lifting 2-D DWT of JPEG 2000 Coder ..................................................................................... 305

Author Index ........................................................................................ 310

 

 

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