Ashish Kumar Singh

Indian Institute Of Technology Hyderabad, India Phone: 07659931178

E-mail: ashishsingh804@gmail.com

https://in.linkedin.com/pub/ashish-kumar-singh/64/3b1/191

Objectives

Looking forward to associate myself with an organization where there is an opportunity to

share, contribute and enhance my knowledge for development of self and the organization.

Willing to work as a key player in challenging & creative environment.

Work Experience

Role Project Assistant

Institute Indian Institute of Technology Hyderabad Telangana, India

Employed Since June 2014 – May 2015.

Area of work RTL design, verification and implementation on hardware

Role Project Intern

Institute Sion Semiconductors Pvt. Ltd. Bangalore Karnataka, India

Employed Since March-2013 - June-2014

Area of work RTL design & verification

Education

Post

Graduate Diploma

VLSI & Embedded

Hardware Design

National Institute of Electronics &

Information Technology, Calicut, Kerala.

Grade: A

(77.6%) 2012-

2013

Bachelor of

Technology

Applied

Electronics &

Instrumentation

ABES Engineering College,

Ghaziabad, Uttar Pradesh.

60.64%

2007-

2011

Resume: Ashish Kumar Singh

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Skills

Programming Languages Verilog

VHDL

System Verilog

C & C++

Embedded C Basic knowledge of OVM and UVM.

CAD Tools

Xilinx ISE Design Suite 14.4

Xilinx Vivado 14.4

Xilinx PlanAhead 14.4

Xilinx ChipScope Pro 14.4 Xilinx SDK 14.4

Xilinx System Generator 14.4

Mentor ModelSim 10.3

Mentor QuestaSim 6.4

Altera Quartus II 13.1

MATLAB 2013.b

Development Platform Xilinx Kintex-7

Xilinx Virtex-7

Xilinx ZedBoard (Zynq Evaluation & Development Board)

Xilinx Spartan-3E Altera Cyclone II

Career summary

Expertise in RTL coding, debugging and verification using Verilog and System

Verilog.

Working experience on different FPGA platforms using CAD tool like ISE, Vivado,

PlanAhead, etc. .

Have knowledge of hardware debugging using ChipScope Pro.

Have knowledge and interest in RTL code optimization.

Have knowledge of AXI bus Architecture.

Resume: Ashish Kumar Singh

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Project Experience

RTL design of Mid End of portable handheld ultrasound device for ASIC.

RTL design & implementation of FIR filter (Hilbert Envelop Detection IP)

for ASIC.

RTL design & implementation of Log Compression module for ASIC.

RTL design & implementation of Decimation filter for ASIC.

RTL design & implementation of Linear Interpolation filter for ASIC.

RTL design and implementation of Basic Ethernet model on FPGA

Programming Language Verilog

Platform Xilinx Kintex-7

CAD Tool ISE Design Suite 14.4, ChipScope Pro 14.4

The aim of this project was to develop RTL code for mid end of handheld ultrasound device for

ASIC. The RTL coding for mid end involved development of various modules such as envelop

detection, log compression, decimation & linear interpolation using Verilog. The project also

aimed at verification & successful implementation of these IP’s on Xilinx FPGA board Kintex-

7. Resource utilization and power analysis was carried out after synthesis.

Implementation of AXI_BUS protocol on ZedBoard

Programming Language Verilog

Platform ZedBoard

CAD Tool Vivado 14.4 & SDK 14.4

This project was aimed to develop communication channel between programming system (PS)

and programming logic (PL) for SoC based ultrasound device. So AXI_BUS protocol was

implemented to communicate from PL to PS using Xilinx Vivado and SDK.

Resume: Ashish Kumar Singh

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RTL Verification of RISC Processor.

RTL Verification of Static Random Access Memory(SRAM).

Programming Language Verilog & System Verilog

CAD Tool QuestaSim

The aim of these projects was RTL verification of RISC processor and SRAM IP for

various test cases. The verification involves development of test environment, test cases

and verification components and integration of all the above in the environment.

Academic Project

RTL Verification of 2D-DWT-IP (Discrete Wavelet Transform –Image

Processing) for ASIC.

Programming Language Verilog, System Verilog

CAD Tool QuestaSim

The aim of this project was RTL verification of 2D-DWT IP for various test images. The

verification involves development of test environment, test cases and verification

components, coverage and assertions plan and integration of all the above in the environment. The project also aims Synthesis of DWT block for ASIC libraries. Static

Timing analysis and Gate count estimation was carried out after synthesis.

Design & Synthesis of RISC Processor.

Programming Language Verilog

CAD Tool ModelSim

This project was aimed to develop RTL code & synthesis of RISC processor in Verilog

language. This RISC processor was designed to have small set of instructions that

execute in short clock cycles, with small number of cycles per instruction. The Design also serves starting point for developing architectural variants and more robust

instruction set.

Resume: Ashish Kumar Singh

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Personal Detail

Passport No. K3430505

Date of Birth 26 June 1987

Gender Male

Father’s Name Mr. Ram Prakash Singh

Present address Indian Institute of Technology Hyderabad ODF Yeddumailram

Telangana -502205.

Permanent

address

N-2/149-1 Sunderpur P.O. Sunderpur (via- B.H.U), Varanasi Uttar

Pradesh – 221005.

Declaration I hereby declare that the information furnished by me above is true to the best of my

knowledge.

Place :

Date : Signature