ASIC Design Flow – An Overview

Ing. Pullini Antonioantonio.pullini@epfl.ch

Outline

Introduction to ASIC Design Flow Standard Cells Design Details of Design Flow Timing Validation Post Layout Validation

A Typical ASIC Design Flow

Ideally, one-shot linear flow In practice, iterations needed to fix issues

– Validation failures– Bad quality of results– No timing closure

DesignSpace

Exploration

RTLCoding

LogicSynthesis

Placement Routing

Basics of a ASIC Design Flow

LayoutPlaced and routed network of gates

LayoutPlaced and routed network of gates

Standard Cell Design

Standard-cell libraries are a fixed set of well-characterized logic blocks

Basic logic functions that are used several times on the same integrated circuit

It will have leaf cells ranging from simple gates to latches and flip-flops. These can then be used to build arithmetic blocks like adders and multipliers.

ASIC designers commonly employ the use of standard cell libraries due to their robustness and flexibility resulting in quick turnaround times

All cells have the same height (with adjacent power and ground) Cells tiled into rows

Standard Cell Designs - Libraries

Library of precharacterized cells– Delay/Power vs. Rise Time and

Output Capacitance– Physical Dimension and Pin

Position

Timing

Delay of cell depends on Rise Time and Output Load

Capacitive Loads

Load depends on Input Capacitance and Interconnect Capacitance

Standard Cell Designs – The Cells

Standard Cell Designs – The Rows

VDDVDD

VDD

GND

Basic High Level Design Flow

RTL Simulation

Behavioral simulationno delays for processing

No performance parametersonly functionality is verified

Hardware descriptionNot every construct inVHDL or Verilog can beimplemented in hardware.This simulation will not show this.

Testbenches

Synthesis - Requirements

Constraints to drive the synthesis process

– Clock Period– IN/OUT delays– Max Area/Power

Technology library– Timing view– Power consumption– Area Occupation

RTL

Gate LevelNetlist

SynthesisTechLib

Constraints

Synthesis – Analyze design

Check the syntax of the HDL files– Checks if the file is compliant with one of the

supported HDL files (Verilog/VHDL)

Check the synthesizability of the design– Reports if some of the non-synthesizable construct

have been used

Identify the connectivity of the block– All the ports and their directions are identified

Synthesize - Elaborate

Identifies all the components inferred in the RTL

Map the inferred components to a Generic Library (GTECH)

Applies the required optimizzation on the RTL (ex. Clock Gating)

Synthesis – Elaborate – an example

module simpleadder(ina,inb,out,clk); input [3:0] ina; input [3:0] inb; output [4:0] out; reg [4:0] out; input clk; reg [3:0] internal_a; reg [3:0] internal_b; reg [4:0] internal_res; always @(posedge clk) begin internal_a <= ina; internal_b <= inb; out <= internal_res; end always @(internal_a or internal_b) begin internal_res <= internal_a + internal_b; endendmodule

Synthesis – Linking And Opcond Setup

Set the Operating Condition at which the synthesis will take place (process voltage and temperature P.V.T.)

Select the target library Links the design to other pre-characterized

blocks or hard macros

Synthesis – Tech Mapping and Optimization

The GTECH components are mapped onto the technology library

Logic is minimized Implementation of basic building blocks (e.g.

adders) are chosen considering the area/power/timing budget

Synthesis – Map & Opt an example

Internal_a

Out

internal_b

Timing Design and Delay Test

Timing simulation: Critical paths are identified by static (vector-less) timing

analysis tools like Primetime (Synopsys). Timing or circuit-level simulation using designer-

generated functional vectors verifies the design.

Layout optimization: Critical path data are used in placement and routing. Delay parameter extraction, timing simulation and layout are repeated for iterative improvement.

Testing: Some form of at-speed test is necessary. Critical paths and all gate transition delays are tested.

Static Timing Analysis

Finds maximum and minimum delays between all clocked flip-flops.

Combinationalcircuit

Flip

-flo

ps

Flip

-flo

ps

Flip

-flo

ps

STA example

0

0

0

0

0

0

0

0

A1

B3 E

1

F1

G2

H3

J1

C1

D2

STA example

0

0

0

0

0

0

0

0

A1

B3 E

1

F1

G2

H3

J1

C1

D2

85

2

1

10

74

3

1

STA example

0

0

0

0

0

0

0

0

A1

B3 E

1

F1

G2

H3

J1

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D2

85

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STA example

0

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1

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H3

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D2

4,8

2,2

1,1

4,10

4,72,4

3,3

1,1

3,5

Floorplanning

Inputs: – Blocks with well-defined

shapes and area– Blocks with approximated

area and no particular shape

– Netlist specifying block connections

Outputs:– Locations for all blocks

Objectives– Minimize area– Reduce wirelength– Maximize routability– Determine shapes of flexible

blocks Constraints

– Shape of each block– Area of each block– Pin locations for each block– Aspect ratio

Placement

The process of arranging circuit components on a layout surface

Inputs: Set of fixed modules, netlist Output: Best position for each module based

on various cost functions Cost functions include wirelength, wire

routability, performance, I/O pads

Placement

Good placement– No congestion– Shorter wires– Fewer metal levels– Smaller delay– Lower power dissipation

Bad placement– Congestion– Longer wires– More metal levels– Higher delay– Higher power dissipation

Power Planning

Clock Distribution

Standard digital systems rely on the clock signal being present everywhere on the chip at the same time: skew

Clock signal has to be connected to all flip-flops: high fan out

Specialized tools insert multi level buffers (to drive the load) and balance the timing by ensuring the same wirelength for all connection

Clock Distribution

CTS example

CTS example

CTS example

CTS example

CTS example

CTS example

Routing

Connect the various standard cells using wires

Input:– Cell locations, netlist

Output:– Geometric layout of each

net connecting various standard cells

Two-step process– Global routing– Detailed routing

Objective– 100% connectivity of a

system– Minimize area– Minimize wirelength

Constraints– Number of routing layers– Design rules– Timing (delay)– Crosstalk– Process variations

Routing Global vs. Detailed

Extraction

Once the physical design is complete, everything about the interconnection network is known. It is possible to extract parasitic capacitance for the interconnection

– Wire capacitance– Wire to wire capacitance– Wire - via resistance

The extracted information can be used to extract timing information. It can be stored in special files (SDF, SPEF) and can be used by circuit simulators.

Optimization

Parasitics may influence timing severely. It is possible to make local optimizations to combat additional capacitance:– Buffers are added to long connections– Driver strength of the standard cells is adjusted– Incremental change of placement– Critical paths are resynthesized

Design Rule Check

Every physical layer has limits that are determined by the production flow. These include:– Minimum spacing– Minimum width– Minimum coverage– Minimum area

Layout Versus Schematic

The physical layout contains only geometric information

The devices (transistors) and interconnections are extracted.This is the extracted netlist

The extracted netlist is compared to the initial netlist that we started with.

Shorts between layers can be detected in this stage.

Very important step, this step tells us that the chip is good to go.