66
ASPI8-4: DSP Design Methodologi es, AAU 1/66 ASPI8-4 SP Design Methodolog

ASPI8-4 DSP Design Methodology

  • Upload
    finnea

  • View
    25

  • Download
    1

Embed Size (px)

DESCRIPTION

ASPI8-4 DSP Design Methodology. Practical issues Webpage: http://www.cs.aau.dk/~moullec/aspi8-4/ • Literature: available on the webpage and in your mailbox (or ask Dorthe) YOUR feedback about the course is most welcome: during the lecture after the lecture ([email protected]). - PowerPoint PPT Presentation

Citation preview

Page 1: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 1/66

ASPI8-4

DSP Design Methodology

Page 2: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 2/66

Practical issues• Webpage: http://www.cs.aau.dk/~moullec/aspi8-4/

• Literature: available on the webpage and in your mailbox (or ask Dorthe)

• YOUR feedback about the course is most welcome:• during the lecture• after the lecture ([email protected])

Page 3: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 3/66

Outline of the course• MM1: Design meta modelsIntroduction/Y-chart model/Rugby meta model

• MM2: Computational modelsFSMD/SDFG/CDFG/HCDFG/ASM-charts

• MM3: Design DomainsFunction/Communication/Data/Timing

Page 4: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 4/66

MM1:

Design meta models

• Introduction

• Y-chart model

• Rugby meta model

• Conclusion

Page 5: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 5/66

Introduction: the need for design methodologies• Pervasive computing with an always-on Internet infrastructure.• Voice activated controls enabled by speech synthesis.• Wireless communications that keep us in touch no matter where or when we need it. • A consumer industry dominated by a plethora of entertainment devices.

Page 6: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 6/66

Introduction: the need for design methodologies

“ Digital signal processing (DSP) has become the technology of focus with consensus expectations of exponential growth. Everybody knows that DSP is the technology driver for the semiconductor industry,” Will Strauss, analyst, Forward Concepts Co., Tempe, AZ.

Page 7: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 7/66

Introduction: the need for design methodologies

But ???

NEW PLATFORMS (DSPs, FPGAs, SoC,…) NEW METHODOLOGIES

Source: Xilinx

Page 8: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 8/66

Introduction: the need for design methodologies

{nlSsBord = nl - n lCo re2;ncSsBord = nc - nc Core2;

}for (y=n lCore2; y<n lSs Bord; y++) {for (x=nc Core 2; x<ncSsBord; x++) {{

xy Offset= (y * nc) + x;

erode=255;}for (k=0; k<nbPointIn Core; k++) {erode= (erode & & pImage[ xy Offset + offset[k] ]);

}if (erode) {pImage Erode[xyOffset]=255;

}else {pImage Erode[xyOffset]=0;

}}}for (y=0; y<n lCore2; y++) {for (x=0; x<(nc); x++) {pImage Erode[(y * nc) + x]=0;}}

{nlSsBord = nl - n lCo re2;ncSsBord = nc - nc Core2;

}for (y=n lCore2; y<n lSs Bord; y++) {for (x=nc Core 2; x<ncSsBord; x++) {{

xy Offset= (y * nc) + x;

erode=255;}for (k=0; k<nbPointIn Core; k++) {erode= (erode & & pImage[ xy Offset + offset[k] ]);

}if (erode) {pImage Erode[xyOffset]=255;

}else {pImage Erode[xyOffset]=0;

}}}for (y=0; y<n lCore2; y++) {for (x=0; x<(nc); x++) {pImage Erode[(y * nc) + x]=0;}}

{nlSsBord = nl - n lCo re2;ncSsBord = nc - nc Core2;

}for (y=n lCore2; y<n lSs Bord; y++) {for (x=nc Core 2; x<ncSsBord; x++) {{

xy Offset= (y * nc) + x;

erode=255;}for (k=0; k<nbPointIn Core; k++) {erode= (erode & & pImage[ xy Offset + offset[k] ]);

}if (erode) {pImage Erode[xyOffset]=255;

}else {pImage Erode[xyOffset]=0;

}}}for (y=0; y<n lCore2; y++) {for (x=0; x<(nc); x++) {pImage Erode[(y * nc) + x]=0;}}

{nlSsBord = nl - n lCo re2;ncSsBord = nc - nc Core2;

}for (y=n lCore2; y<n lSs Bord; y++) {for (x=nc Core 2; x<ncSsBord; x++) {{

xy Offset= (y * nc) + x;

erode=255;}for (k=0; k<nbPointIn Core; k++) {erode= (erode & & pImage[ xy Offset + offset[k] ]);

}if (erode) {pImage Erode[xyOffset]=255;

}else {pImage Erode[xyOffset]=0;

}}}for (y=0; y<n lCore2; y++) {for (x=0; x<(nc); x++) {pImage Erode[(y * nc) + x]=0;}}

{nlSsBord = nl - n lCo re2;ncSsBord = nc - nc Core2;

}for (y=n lCore2; y<n lSs Bord; y++) {for (x=nc Core 2; x<ncSsBord; x++) {{

xy Offset= (y * nc) + x;

erode=255;}for (k=0; k<nbPointIn Core; k++) {erode= (erode & & pImage[ xy Offset + offset[k] ]);

}if (erode) {pImage Erode[xyOffset]=255;

}else {pImage Erode[xyOffset]=0;

}}}for (y=0; y<n lCore2; y++) {for (x=0; x<(nc); x++) {pImage Erode[(y * nc) + x]=0;}}

{nlSsBord = nl - n lCo re2;ncSsBord = nc - nc Core2;

}for (y=n lCore2; y<n lSs Bord; y++) {for (x=nc Core 2; x<ncSsBord; x++) {{

xy Offset= (y * nc) + x;

erode=255;}for (k=0; k<nbPointIn Core; k++) {erode= (erode & & pImage[ xy Offset + offset[k] ]);

}if (erode) {pImage Erode[xyOffset]=255;

}else {pImage Erode[xyOffset]=0;

}}}for (y=0; y<n lCore2; y++) {for (x=0; x<(nc); x++) {pImage Erode[(y * nc) + x]=0;}}

{nlSsBord = nl - n lCo re2;ncSsBord = nc - nc Core2;

}for (y=n lCore2; y<n lSs Bord; y++) {for (x=nc Core 2; x<ncSsBord; x++) {{

xy Offset= (y * nc) + x;

erode=255;}for (k=0; k<nbPointIn Core; k++) {erode= (erode & & pImage[ xy Offset + offset[k] ]);

}if (erode) {pImage Erode[xyOffset]=255;

}else {pImage Erode[xyOffset]=0;

}}}for (y=0; y<n lCore2; y++) {for (x=0; x<(nc); x++) {pImage Erode[(y * nc) + x]=0;}}

Standards

{nlSsBord = nl - n lCo re2;ncSsBord = nc - nc Core2;

}for (y=n lCore2; y<n lSs Bord; y++) {for (x=nc Core 2; x<ncSsBord; x++) {{

xy Offset= (y * nc) + x;

erode=255;}for (k=0; k<nbPointIn Core; k++) {erode= (erode & & pImage[ xy Offset + offset[k] ]);

}if (erode) {pImage Erode[xyOffset]=255;

}else {pImage Erode[xyOffset]=0;

}}}for (y=0; y<n lCore2; y++) {for (x=0; x<(nc); x++) {pImage Erode[(y * nc) + x]=0;}}

{nlSsBord = nl - n lCo re2;ncSsBord = nc - nc Core2;

}for (y=n lCore2; y<n lSs Bord; y++) {for (x=nc Core 2; x<ncSsBord; x++) {{

xy Offset= (y * nc) + x;

erode=255;}for (k=0; k<nbPointIn Core; k++) {erode= (erode & & pImage[ xy Offset + offset[k] ]);

}if (erode) {pImage Erode[xyOffset]=255;

}else {pImage Erode[xyOffset]=0;

}}}for (y=0; y<n lCore2; y++) {for (x=0; x<(nc); x++) {pImage Erode[(y * nc) + x]=0;}}

{nlSsBord = nl - n lCo re2;ncSsBord = nc - nc Core2;

}for (y=n lCore2; y<n lSs Bord; y++) {for (x=nc Core 2; x<ncSsBord; x++) {{

xy Offset= (y * nc) + x;

erode=255;}for (k=0; k<nbPointIn Core; k++) {erode= (erode & & pImage[ xy Offset + offset[k] ]);

}if (erode) {pImage Erode[xyOffset]=255;

}else {pImage Erode[xyOffset]=0;

}}}for (y=0; y<n lCore2; y++) {for (x=0; x<(nc); x++) {pImage Erode[(y * nc) + x]=0;}}

{nlSsBord = nl - n lCo re2;ncSsBord = nc - nc Core2;

}for (y=n lCore2; y<n lSs Bord; y++) {for (x=nc Core 2; x<ncSsBord; x++) {{

xy Offset= (y * nc) + x;

erode=255;}for (k=0; k<nbPointIn Core; k++) {erode= (erode & & pImage[ xy Offset + offset[k] ]);

}if (erode) {pImage Erode[xyOffset]=255;

}else {pImage Erode[xyOffset]=0;

}}}for (y=0; y<n lCore2; y++) {for (x=0; x<(nc); x++) {pImage Erode[(y * nc) + x]=0;}}

{nlSsBord = nl - n lCo re2;ncSsBord = nc - nc Core2;

}for (y=n lCore2; y<n lSs Bord; y++) {for (x=nc Core 2; x<ncSsBord; x++) {{

xy Offset= (y * nc) + x;

erode=255;}for (k=0; k<nbPointIn Core; k++) {erode= (erode & & pImage[ xy Offset + offset[k] ]);

}if (erode) {pImage Erode[xyOffset]=255;

}else {pImage Erode[xyOffset]=0;

}}}for (y=0; y<n lCore2; y++) {for (x=0; x<(nc); x++) {pImage Erode[(y * nc) + x]=0;}}

{nlSsBord = nl - n lCo re2;ncSsBord = nc - nc Core2;

}for (y=n lCore2; y<n lSs Bord; y++) {for (x=nc Core 2; x<ncSsBord; x++) {{

xy Offset= (y * nc) + x;

erode=255;}for (k=0; k<nbPointIn Core; k++) {erode= (erode & & pImage[ xy Offset + offset[k] ]);

}if (erode) {pImage Erode[xyOffset]=255;

}else {pImage Erode[xyOffset]=0;

}}}for (y=0; y<n lCore2; y++) {for (x=0; x<(nc); x++) {pImage Erode[(y * nc) + x]=0;}}

{nlSsBord = nl - n lCo re2;ncSsBord = nc - nc Core2;

}for (y=n lCore2; y<n lSs Bord; y++) {for (x=nc Core 2; x<ncSsBord; x++) {{

xy Offset= (y * nc) + x;

erode=255;}for (k=0; k<nbPointIn Core; k++) {erode= (erode & & pImage[ xy Offset + offset[k] ]);

}if (erode) {pImage Erode[xyOffset]=255;

}else {pImage Erode[xyOffset]=0;

}}}for (y=0; y<n lCore2; y++) {for (x=0; x<(nc); x++) {pImage Erode[(y * nc) + x]=0;}}

StandardsStandards?But ???

INCREASED COMPLEXITY (multiple standards, Quality of Service, …) NEW METHODOLOGIES

Page 9: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 9/66

• “The way in which you find out information; a methodology describes how something will be (or was) done. The methodology includes the methods, procedures, and techniques used to collect and analyze information”

Introduction: the need for design methodologies

What is a methodology ?

• “A documented approach for performing activities in a coherent, consistent, accountable, and repeatable manner”

• “A collection of methods, procedures, and standards that defines an integrated synthesis of engineering approaches to the development of a product”

• A method is not a methodology, it’s part of a methodology.

Page 10: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 10/66

Page 11: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 11/66

Introduction: elements for a design methodology

• Domains: functional, structural, physical, …

• Abstraction levels: system, algorithmic, RTL, logic, circuit, …

• Activities: analysis, synthesis, refinement, optimization …

Page 12: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 12/66

• Functional domain: emphasis is on behavior (functionality, I/O), no reference to the implementation of this behavior

• Structural domain: interconnected functional components, possibly hierarchical

• Physical domain: a.k.a geometric, physical placement in space and physical properties, no direct relation to functionality

Specification domains for digital systems

Page 13: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 13/66

Abstraction levels for digital systems

• System level: subsystems (modules,…) interacting with each other(for example exchanging messages). Structural elements: processsors, communication channels, memories,…

• Algorithmic level: a.k.a behavioral level, algorithm(s) describing the functionality. Structural elements: controller, netlist,…

• Register Transfer Level: a.k.a RTL level, operations described as transfer of data between registers and functional units.Structural elements: registers, ALUs, multiplexers, controller,…

Page 14: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 14/66

Abstraction levels for digital systems

• Logic level: operations described as Boolean equations. Structural elements: gates and interconnections.

• Circuit level: differential equations describing the relation between voltage, current, …Structural elements: transistors, resistors, capacitors

Page 15: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 15/66

Meta models : Y-chart and Rugby

• Meta model: a model used to describe and analyze other models

• Higher level of abstraction

Page 16: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 16/66

Y-chart

• The Y-chart is a representation proposed by Gajski and Khan to capture specifications domains, abstraction levels and their inter-relation.

• Specification domains are represented as three axes (hence the Y)In each domain the specification can be at different abstraction levels.

• The Y-chart tries to capture the relation between design activities (synthesis activities) such as synthesis, partitioning, …

Page 17: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 17/66

Domains and Levels of Modeling

high level of abstraction

FunctionalStructural

Geometric “Y-chart” by Gajski & Kahn

low level of abstraction

Page 18: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 18/66

Domains and Levels of Modeling

FunctionalStructural

Geometric

Algorithm(behavioral)

Register-TransferLanguage

Boolean Equation

Differential Equation

“Y-chart” by Gajski & Kahn

Page 19: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 19/66

Domains and Levels of Modeling

FunctionalStructural

Geometric

Processor-MemorySwitch

Register-Transfer

Gate

Transistor

“Y-chart” by Gajski & Kahn

Page 20: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 20/66

Domains and Levels of Modeling

FunctionalStructural

Geometric “Y-chart” by Gajski & Kahn

Polygons

Sticks

Standard Cells

Floor Plan

Page 21: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 21/66

Inverted as compared to previous slides

Page 22: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 22/66

Page 23: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 23/66

Design activities

Page 24: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 24/66

Rugby meta model

Axel Jantsch, Shashi Kumar*, Ahmed Hemani

Royal Institute of TechnologyDepartment of electronicsElectronic systems design laboratoryElectrum 229S – 164 40 Kista, Sweden

* School of Engineering, Jönköping University, Jönköping, Sweden

Page 25: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 25/66

Rugby meta model

“A conceptual framework, in which designs, design processes and design tools can be studied.

The model has similar objectives as the well known Y chart but its scope is extended to handle designs and design processes required for complex systems requiringconcurrent processes and mixed HW/SW implementation.

The Rugby model has four domains, namely, Computation, Communication, Data and Time. “

Axel Jantsch, Shashi Kumar, Ahmed Hemani

Page 26: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 26/66

Rugby meta model

“The behavioral domain of the Y chart is replaced with more restricted computation domain.

The structural and physical domain of the Y chart are merged into a more generic domain called Communication.

The new domains Data and Time have become necessary to model data abstractions used at various levels of design, and to explicitly model timing constraints at various levels in the design process, respectively”.

Axel Jantsch, Shashi Kumar, Ahmed Hemani

Page 27: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 27/66

Rugby meta model

“The Rugby model is able to represent mixed HW/SW designs and design processes for HW/SW codesign at various levels of abstraction.

It not only can represent state-of-the-art of current electronic systems and electronic system design automation, but it also points to gaps in the availability of tools and methodologies for designing complex system”.

Axel Jantsch, Shashi Kumar, Ahmed Hemani

Page 28: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 28/66

Rugby meta model

Domain, Hierarchy, and Abstraction: “Abstraction and hierarchy are two different means to handle complexity.

Hierarchy partitions a system into smaller parts; abstraction replaces one model with another model which contains significantly less detail and information. Both reduce the amount of information and details that must be considered for a particular purpose.

A third way to tackle complexity is the analytical slicing of models into domains. Unlike hierarchy and abstraction it does not lead to physically separate models or parts of a model, but it is an analytical means to study different aspects of a model separately”.

Axel Jantsch, Shashi Kumar, Ahmed Hemani

Page 29: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 29/66

Rugby meta model

Hierarchy: “A hierarchy is a, possibly recursive, partitioning of a design model such, that the details of each part is hidden into a lower hierarchical level.

Hierarchy defines the amount of information presented and visible at a particular hierarchical level of a model.

At all hierarchy levels the same modelling concepts are used. The motivation for hierarchy is to hide information when it is not needed and to display details when they are useful”.

Axel Jantsch, Shashi Kumar, Ahmed Hemani

Page 30: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 30/66

Rugby meta model

Abstraction: “An abstraction level defines the modelling concepts and their semantics for representing a system.The type of information available at different levels is different. A higher level ignores some irrelevant information at a lower level and encodes it using different concepts.

Abstraction defines the type of information present in a model. Unlike hierarchy, abstraction is not concerned with the amount of information visible, but with the semantic principles of a model. In general, the movement from high to low abstraction levels includes a decision making process”.

Axel Jantsch, Shashi Kumar, Ahmed Hemani

Page 31: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 31/66

Rugby meta model

Domain: “A domain is an aspect of a model which can logically be analysed independently from otheraspects.A domain focuses on one design aspect. Real models always contain several aspects or domainsbut different models may emphasize one domain more than another. Models, which focus on one particulardomain use modelling notations and constructs to model the design aspect of concern explicitly.Other design aspects may be implicitly part of the models. Whereas hierarchy and abstraction simpli-fies the design, domain partitioning helps the developers of tools and methodologies to cope with thecomplexity. The domains considered in this article are computation, communication, data, and time.”

Axel Jantsch, Shashi Kumar, Ahmed Hemani

Page 32: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 32/66

Rugby meta model

“While hierarchical partitioning is mostly a manual endeavour, the definition of abstraction levels and transformations between them, is behind most of the advances in design automation. While hierarchy is a general and important concept, it is not explicit in the Rugby model. We assume, hierarchy is possible at all abstraction levels in any domain.

The Rugby model is based on these definitions and identifies four domains, computation, communication, time and data, and several abstraction levels for each domain.

Hierarchy is not further discussed but we assume, that a model at any abstraction level can have an arbitrary number of hierarchy levels.”

Axel Jantsch, Shashi Kumar, Ahmed Hemani

Page 33: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 33/66

“The model derives its name from the similarity of its visual representation (see figure 4) to the shape of a Rugby, with the domain lines forming the seams.”

Axel Jantsch, Shashi Kumar, Ahmed Hemani

Page 34: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 34/66

Axel Jantsch, Shashi Kumar, Ahmed Hemani

Page 35: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 35/66

Page 36: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 36/66

Page 37: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 37/66

Page 38: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 38/66

Page 39: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 39/66

Page 40: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 40/66

Page 41: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 41/66

Page 42: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 42/66

Page 43: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 43/66

Page 44: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 44/66

Page 45: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 45/66

Page 46: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 46/66

Page 47: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 47/66

Page 48: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 48/66

Page 49: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 49/66

Page 50: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 50/66

Page 51: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 51/66

Page 52: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 52/66

Page 53: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 53/66

Page 54: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 54/66

Page 55: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 55/66

Page 56: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 56/66

Page 57: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 57/66

Page 58: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 58/66

Page 59: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 59/66

Page 60: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 60/66

Page 61: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 61/66

Page 62: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 62/66

Page 63: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 63/66

Page 64: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 64/66

Rugby summary

• Separates the modeling issues computation, communication, time and data;

• Defines abstraction levels in these four domains independently;

• Allows to organize the design phases with respect to the abstraction levels;

Page 65: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 65/66

ConclusionsWhat have we seen in the lecture ?

• motivation for DSP design methodologies• some elements for DSP design methodologies

Domains, abstraction level and design activities• the Y-chart model• the rugby meta-model• illustration of the rugby meta-model

• Meta-models can be used to define the domains of design• they can be used to analyze and describe other methods (SPU, OO…)• they make the design domains explicit• they can be used to map a particular design method• they can be used to find room for improvement in existing methods

Page 66: ASPI8-4 DSP Design Methodology

ASPI8-4: DSP Design Methodologies, AAU 66/66

Conclusions

Exercices:

1) define the new terms encountered in the articles:

• A Model of Design Representation and Synthesis• The Rugby Meta-Model

2) For those who know the SPU method, try to put in line with the rugby model