DSP Architecture First yr. M.Tech (SP)

Assignment No 3

(Units 3,4,6 and 7)

(Due on 22-Apr-2014)

Q.1 Why the trend for multicore DSP is on rise? Discuss the Hierarchical networks approach versus Mesh network approach in the context of Interconnect type multicore DSP architectures.

Q.2 Explain the Master Slave model vis-à-vis Data Flow model of multicore programming. What is the role of Fork and Join methodlogy in creating teams of threads in Multicore programming?

Q.3 What is achieved by resorting to multithreading? Explain the commonly used #pragma directives supported in openMP programming on keystone multicore DSP TI320C6678 platform.

Q.4 The following code snippet of openMp on TI’s multicore DSP uses compiler directives and openMP library modules. Explain the functioning of the code line by line.

#include <ti/omp/omp.h>

Void main()

{ omp_set_num_threads(4);

#pragma omp parallel

{

Int tid=omp_get_thread_num();

{printf(“I am thread = %d\n”, td);} }}

Q.5 The following code snippet of openMp on TI’s multicore DSP uses compiler directives and openMP library modules. Explain the functioning of the code line by line.

#include <ti/omp/omp.h>

Void main()

{ int i, N; for(i=0; i<N; i++)

{a[i]=a[i]+b[i];}

#pragma omp parallel

{#pragma omp for

{ for(i=0; i<N; i++)

{a[i]=a[i]+b[i];}}}}

Q.6 Identify the addressing modes of the operands in each of the following instructions & their operation.

Q.7 Draw the table showing the content of the instruction pipeline when the following program is executed in TI C5X processor.

ADD *+SAMM TREG0MPY *+SQRA *+,AR2

If the first instruction was changed to ADD #2500h, what is the effect on instruction pipeline?

Q. 8 (a) How many cycles are needed for Branch instruction in TI C5X processor family? What is the significance of delayed branch instruction in TI C5X ?(b) When do you use NORM instruction in C5X processor family (c) Let the initial value of ARP, AR2 and ACC be 3, 00h and 0FFFF F002h respectively. Show the contents of ARP, AR2 and ACC after executing the NORM *+ instructionQ. 9 Consider execution of the following code snippet on C5X processor. Explain what the code segment is executing.

ZAPB PGM1250hADD *SACL*+MAC 4500H,25h

PGM1250: LACC *+If the second instruction from the top is replaced by BD PGM1250 h, what is its impact on the code execution?Q.10 The assembly code for C5X processor is given below. What is the purpose of assembler directives? Which DSP operation can make use of such an initialization?

.mmregs

.ps 0a00h

.word 1h,2h,3h,3h,1h

.ds 1000h

.word 0h,0h,0h,0h

.word 3h,4h,5h

.word 0h,0h,0h,0h

.entryQ. 11 Explain the working of the following code and show the contents of Accumulator and AR0 on C5X processor.

.mmregs

.ps 0a00h

.entryLACC #1000hLACC #0004h,4LAR AR0,#1000h

LOOP: B LOOP.end

Q. 12 Explain the different types of interrupts in TMS320C50 Processor family.Q. 13 Explain the operation of serial I/O ports and hardware timer of TMS320C50 on chip peripherals.Q.14 (a) With the help of a suitable block diagram, explain the working of ARAU of TMS320C50 processor. (b) Find out the output from the following code on TMS320C50 processor

.mmregs .text

START: LDP #100hLACC #037Ah, 0SACL 0000, 0LACC # 012Eh, 0SACL #0001, 0LT 0000MPY 0001PACSACL 0003, 0

HLT: B HLTQ.15 (a) With the help of a schematic block diagram of TMS320C25 explain its programmers model. How is the address generation mechanism implemented in direct and indirect addressing?(b) What is the significance of REPEAT instruction in TC25 processor?(c) Write a assembly code for complex multiplication on TMS320C25 processor.(d) How is the on-chip program and data memory organized in c25? What is the need for B0, B1 and B2 blocks in data memory?Q.16 (a) Draw a block diagram of C28X multiplier and ALU/Shifter. How is the memory arranged in pages?(b) Find out the operation performed by the following TMS320F2812 assembly code

START: SETC XF CLRC XF

B START, UNCWhat is the effect of interchanging the sequence of first two instructions in the above code?Q. 17 Write short notes on(a) Code security module in TMS320F2812(b) Atomic Arithmetic and Logic Unit in C28X ?