Upload
trinhdien
View
235
Download
4
Embed Size (px)
Citation preview
Asynchronous Asynchronous FSMs and FSMs and
VerilogVerilog
PLD registered outputPLD registered output
Outputs selection capability Outputs selection capability in CPLDin CPLD
State Machine with Moore outputState Machine with Moore output
State State Machine Machine with with Embedded Embedded Mealy Mealy output output definitions definitions (7.28)(7.28)
Table 7.29. FSM with pipelined output definitions
Test VectorsTest Vectors
Test Vectors continuedTest Vectors continued
Table for example state machineTable for example state machine
FFs in librariesFFs in libraries
Behavioral Verilog for Behavioral Verilog for DFFDFF
Verilog for D FFVerilog for D FF
Verilog for D FFVerilog for D FF
Clock generation within a Clock generation within a test benchtest bench
Moore FSM implied by Moore FSM implied by Verilog coding styleVerilog coding style
Table for example Table for example FSMFSM
Table 7.58. Table 7.58. Verilog Verilog
Program for Program for FSM FSM
exampleexample
Synchronous and Asynchronous Synchronous and Asynchronous reset for FSMs in Verilogreset for FSMs in Verilog
Verilog code for pipelined Verilog code for pipelined outputoutput
Verilog FSM with pipelined Verilog FSM with pipelined outputsoutputs
Table 7.61. Table 7.61. Simplified Simplified
Verilog Verilog FSM FSM
designdesign
Table 7.62. Alternative Verilog for Table 7.62. Alternative Verilog for ones-counting machineones-counting machine
Ones-Counting MachineOnes-Counting Machine
Fastest and smallest Verilog Fastest and smallest Verilog counting logic for ones-counting counting logic for ones-counting
machinemachine
Memory for lock machineMemory for lock machine
Explicit FF instantiation in Explicit FF instantiation in Verilog Verilog
One-Hot encodingOne-Hot encoding
Table 7.68. Table 7.68. Test Bench Test Bench for FSM of for FSM of Table 7.58 Table 7.58
(with (with synchronous synchronous reset added) reset added) or Table 7.60, or Table 7.60, 7.61, 7.66 or 7.61, 7.66 or
7.577.57
SR latchSR latch