Asynchronous vlsi circit design

8/13/2019 Asynchronous vlsi circit design

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Advanced VLSI Design

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Self Timed PipelinesSelf Timed Pipelines


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synchronous systems

Sync. systems

logical ordering of events by clk. It provides a

time base

EE141 2

Physical timing constraint- next edge comeswhen all blocks have reached steady state

Problem CLB has to wait even though it mayfinish earlier. Clock distribution network

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Wave pipeline systems

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Implementation of pipeline

Synchronous pipeline- --robust design,delay= N x worst case delay

Wave i eline ---low latenc no re isters in between but delays through all paths of

combination logic must be matched. HereOver all latency=sum of stage delays

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Self timed pipelines

In between two approaches Best attributes of both---

safety and tolerances of sync. Pipeline, low increased throughput of wavepipeline Data token transfer can happen exactly when

data computations complete. So logicalfunctions will be correct for any actual gatedelays thereby achieving speed independence

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Asynch. designmeeting

constraints Adv.next block can start computation as

soon as previous block has finished.

Problem when to latch the out ut ? When

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output is a correct value?

Remedy system has to meet timingconstraints


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Local signals

Logical ordering and physical timing --

START, DONE, -- physical timing

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REQUEST , ACKNOWLEDGE - Logical

ordering


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Self timed system

System generate its own timing signal Req Req Req Req

Ack Ack Ack ACK HS HS HS

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R2 Out F 2 In

t pF 2

Start Done

R1 F 1

t pF 1

Start Done

R3 F 3

t pF 3

Start Done


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Self timed system --Hand shake

protocol Hand shaking- synchronize by mutual agreement

adv .--timing signals generated locally

less prop. Delay, high speed,

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,

power saving,

robust regarding manufacturing and operatingconditions.

Sync. circuits are guided by extreme conditions andasync. Ckts guided by actual conditions

Disadv . hand shaking circuit design


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Encoding Aperiodic events For events that are not periodic, an explicit transition is

required to start every symbol.

A binary event cannot be encoded on a single binarysignal, for at any point in time for there are three

possibilities:

continue sending the current symbol,

start the next symbol with the same value,

and start the next symbol with the complement value. Either a ternary signal or two binary signals are required

to encode a binary event.

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Types of dual rail signaling Dual rail Return-to-Zero (RZ) -- With return-to-zero

signaling, the unary event lines return to zero after every event, andonly the positive transitions are significant . Return-to-zero dual-railsignaling is the timing convention employed by dual-rail domino logic

Dual rail Nonreturn-to-Zero (NRZ) Signaling Non- re urn- o-zero s gna ng requ res remem er ng e o s a e o o

lines to decode the present value

Clocked Signaling and Bundling--- With clocked signaling,one line, the clock, encodes a unary event stream that denotes the start of each new symbol while the other line carries the value of the symbol. Theclock can either be NRZ, denoting a new symbol on each transition, or RZ,where only the positive transitions are meaningful

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The primary advantage of separating the timinginformation from the symbol values is that it permitsbundling of several values with a single event stream.

If N signals are bundled together and associated with asingle clock line, then the simultaneous events

associated with the N signals can be encoded on N + 1

information were unbundled.

Ternary Signaling--- binary event stream could beencoded on a single NRZ ternary logic symbol/ or RZternary logic

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2 phase protocol

SIMPLE AND FAST

TRANSITION SIGNALLING or EVENTLOGIC

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DATA TRANSFER HAPPENS AT BOTHTHE EDGES (FALLING, RECEIVING)

NO RESET STATE


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Implementation of HS protocol-

2 phase (no return to zero)

3RECEIVERSENDER

ReqReq

Ack

Ack

Data

2

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11Data(a) Sender-receiver configuration

(b) Timing diagram

cycle 1 cycle 2

Senders actionReceivers action


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2 phase protocol (NRTZ)

Data change---request----data acceptance----acknowledge ----

Data change---request----acknowledge----dataacceptance events Proceeds in cyclic order.

Successive cycles may take different time

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2 active cycles-

Sender ---terminated by request event (no change in o/ppossible)

Receiver-------terminated by acknowledge event


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4 phase protocol (RTZ)

2 4Req

Senders action

Receivers action

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Level sensitivedata transfer at only one (positive) edge

1 1

3 5

Data

Cycle 1 Cycle 2


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4 phase protocol

Data change---request----dataacceptance----acknowledge---- Reset---

Data chan e---re uest----data

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acceptance----acknowledge-

Proceeds in cyclic order


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Bundled data / single rail protocol

Req shd be issued when data output is stable

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Bundled Data Protocol

Two control wires associated with each n-bit data channel(n+2) bits for each n-bit channel

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Producer Consumer Ack

Data

Micropipelines use 2-phase bundled data protocol

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Dual rail protocol

I bit information coded using two wires

Request/ done is merged with data wires

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Dual-Rail ProtocolTwo wires for each bit of data (a 0-wire and a 1-wire) +

An ack wire for each data channel(n*2 + 1) bits for each n-bit channel

Redundant encoding realizes QDI circuit

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SENDER RECIEVER

Ack

B0

B1

B2

B3

A 4-bit dual-rail channel


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Self timed pipelines

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mp emen a on


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Asynchronous pipeline

example The simplest asynchronous pipeline, in

which the LOGIC blocks are just wires,

acts as a first-in first- out (FIFO) buffer

Here data being clocked into the alignstages by the input request signal andclocked out by the output acknowledgesignal. 26


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Possible combinations

2-phase single rail (event transition, req. separate)

2 phase dual rail (event transition, req. merged with data)

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4 phase single rail (level transition, req. separate)

4- phase dual rail (level transition, req. merged with data)


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Circuit implementations

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Event Logic The Muller-C Element A B F n 1

0011

010

(b) Truth table(a) Schematic

1

0F nF n1

F

A

B

C

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S

F F

R

Q A

B

(a) Logic

(b) Majority Function

(c) Dynamic

A B

B

B

A

V DD

B

F A

B

V DDV DD


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2 phase

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Muller C pipeline

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2-phase single rail FIFO Transition signaling, Special capture-pass

latches alternate between capture and pass First pass data to next, then hold, then capture

next data token

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CC

ACK ACK

REQ REQ

ACK

REQ

LATCH LATCH

C P C P

C

LATCH

C P

ACK

REQc1

p1 c2 p2 c3


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Operation details

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Operation

req 1

c1 1, latch 1 get data latched but can

not ass on to latch 2

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c1 1, c2 1, p1 1, latch 2 gets thedata, latch1 in hold

c2 1, c3 1, p2 1, latch 3gets the data, latch2 in hold, latch1ready

for new


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Operation

req 0

c1 0, latch 1 get data latched but can

not pass on to latch 2,

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c1 0, c2 0, p1 0, latch 2 gets thedata, latch1 in hold

c2 0, c3 0, p2 0, latch 3 gets thedata, latch2 in hold, latch1ready for new


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Operation

Hence we get a sequence of

Eval hold eval hold-------

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Capture-Pass transition-controlled latch

Transitions on Cand P alternate

Micropipelines

Elegant, no RZ

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Butimplementation(latches and other control circuits) iscomplex


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Micropipelines with processing

2 stage

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4 stage pipeline

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Event controlled latch design

4242


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Alternative implementation--Eventcontrolled switch/ latch

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Delay element design

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Mousetrap pipelines

These are examples of 2 phase single railpipelines

No muller-C element.

Stage disables itself

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MOUSETRAP PipelinesSimple asynchronous implementation style, uses

standard logic implementation: Boolean gates , transparent latches simple control : 1 gate/pipeline stage

MOUSETRAP uses a capture protocol: Latches

are normally transparent: before new data arrives

become o a ue: a ter data arrives ca ture data

Control Signaling: transition-signaling = 2-phase

simple protocol: req/ack = only 2 events per handshake (not 4) no return-to-zero

each transition (up/down) signals a distinct operation

Our Goal: very fast cycle time

simple inter-stage communication

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Mousetrap pipelines

These are also examples of 2 phasesingle rail (bundled data) pipelines

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ack N-1 ack N Latch Controller

MOUSETRAP: A Basic FIFOStages communicate using

transition-signaling:

1 transition1 transition per data item! per data item!

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req N req N+ 1

Data Latch

done N

Data in Data out

Stage N Stage N- 1 Stage N+ 1

En

11stst data item flowing through the pipelinedata item flowing through the pipeline1st data item flowing through the pipeline22ndnd data item flowing through the pipelinedata item flowing through the pipeline


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Important points for 2-phase single

rail Asynch design

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Drawback of single rail circuits

Matched delay element needs to beintroduced in between latches to

synchronize request and data arrival

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2 PHASE DUAL RAIL FIFO

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2 phase dual rail FIFO

Done signal act as Req.

Monotonic Dual rail signals need to be

enerated

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Done/ Completion Signal

Generation--no glitches

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Using Redundant Signal Encoding


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Completion Signal in DCVSL

B0 B1

Start

V DD V DD

Done B0

B1and

start

done

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PDN PDN

In1 In1 In2 In2

Start Event logic

Done

Req


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2 phase

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2-Phase dual rail FIFO

start1 Ack1

Done / req2

start3start2

req3

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data

Req1

D1

Edge triggered reg


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2 registers are req. for event logic

Edge triggered reg

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Edge triggered reg


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Latch implementation USING C 2MOS

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Start Start


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Event Latch implementationusing TG [start is delayed Req], valid data is issued before Req

DATA IN OUT

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Req START

Req START


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Signal arrival

REQ1

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done2

star1

reduce


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Operation Req1 1

start1 1, latch1 gets the data, D1/ req21

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req3./ Ack1 1, latch1 in hold, start3 1,latch3 gets the data

Req1 can go 0


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Operation

Req1 0


0

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req3./ Ack1 0, latch1 in hold, start3 0,latch3 gets the data

Req1 can go 1


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Logic implementation

B0 B1

Start

V DD V DD

Done B0

B1and

start

done

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PDN PDN

In1 In1 In2 In2

Start Start /start


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4 phase

RZ

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4 phase- require pre-charge evaluate logic

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4-phase bundled data circuits-FIFO

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Operation

Initially all nodes 0 Req 1 en1 1, en2 1, en3 1, ---- with some delay

in between

Latch1 data latch 2 Latch2 data latch 3

Latch3 data latch 4------ when req 0 en1 0, en2 0, en3 0, ----- Latch1 ,latch 2, latch 3 all in hold mode Operation similar to synchronous pipeline 68


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4-phase bundled data circuits

CCC

ACK ACK ACK

REQ REQ REQ

ACK

REQ

LATCH LATCH LATCH

EN EN EN

C

ACK ACK

REQ REQ

LATCH

EN

FUNC.BLOCK

DELAYC

LATCH

EN

FUNC.BLOCK

DELAY

ACK

REQC

ACK

REQ

LATCH

EN

FUNC.BLOCK

DELAY

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4-Phase bundled data FIFOReq must be a pulse signal

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4-phase bundled data circuits Looks like a sync pipe, with local clocks

When full, the C-elements are 1010101,only half the latches store data

Similar to master-slave flip-flops

Speed limited by handshake (2-way

comm.) better implementations available

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Dual rail circuits

Dual muller pipeline- implementation1

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4-phase dual rail FIFO-- implementation1

CC C

C C C

ACKACK

d.t

d.f

d.t

d.f

Two muller pipeline in parallel using commom Ack sig in per stage to synchronize

Muller pipeline (again) with CompletionDetection

No REQ embedded in the data73


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4-phase dual rail FIFO many bits

C C C

ACKACK

CC C

C C C

CC C

C C C

d[0].t

d[0].f

d[1].t

d[1].f

d[0].t

d[0].f

d[1].t

d[1].f

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Drawback

No. of muller C elements increase with no.of data bits

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Data

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4 phase dual rail FIFO 2 nd implemen

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Operation

R1 should be disabled when start begins

When done1 is issued req shd go low

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,precharges


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Signal arrival

REQ1

En. 1

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start1

done1

reduce


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Adv.

No such drawback as no. of Muller Celements do not increase with no. of bits

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Implementation-34-Phase post charge with reset from successor using MullerC

Ack

Done

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data

start/ Req


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Latency of this pipeline

Lf forward latency

Delay from new valid data outputs at one stage to newvalid data outputs from the following stage

Lr reverse latency

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Delay from the acknowledgement of a stages output tothe acknowledgement of its predecessor output

Because data tokens and reset stage alternate, so we

take average of two delay


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Latency

Lf t d+ t c+ t f

Lr

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[ t c + t f + t d + tc + t f

+ t d ]


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start

Done/ Req

Ack

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data


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4 phase dual rail FIFO (ex3)post charge logic

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Post charge with reset from successor different way of generating control signals other than mullerC elemet


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HS Control signal implementation-I

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Do not delay evaluation until successor has finishedresetting


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Latency of this pipeline

Lf t d + t c+ t f

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r c c


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HS Control signal implementation-IImix of single rail and dual rail, Req a separate wire

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Do not delay evaluation until predecessor hasfinished evaluation


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Lf t f

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r c c


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Latency

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Latency

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4 phase protocol

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4 Ph b dl d d P l


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4-Phase bundled data Protocol--FIFO

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4-Phase dual rail Protocol--FIFO

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Asynchronous vlsi circit design