Atom‐by‐Atom Fabrication of Single and Few Dopant Quantum

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Atom-by-Atom Fabrication of Single and Few Dopant Quantum Devices

Jonathan Wyrick,* Xiqiao Wang, Ranjit V. Kashid, Pradeep Namboodiri, Scott W. Schmucker, Joseph A. Hagmann, Keyi Liu, Michael D. Stewart Jr., Curt A. Richter, Garnett W. Bryant, and Richard M. Silver*

Atomically precise fabrication has an important role to play in developing atom-based electronic devices for use in quantum information processing, quantum materials research, and quantum sensing. Atom-by-atom fabrication has the potential to enable precise control over tunnel coupling, exchange coupling, on-site charging energies, and other key properties of basic devices needed for solid-state quantum computing and analog quantum simula-tion. Using hydrogen-based scanning probe lithography, individual dopant atoms are deterministically placed relative to atomically aligned contacts and gates to build single electron transistors, single atom transistors, and gate-controlled quantum sensing devices. The key steps required to fabricate and demonstrate the essential building blocks needed for spin selective initializa-tion/readout and coherent quantum manipulation are described.

DOI: 10.1002/adfm.201903475

Dr. J. Wyrick, Dr. X. Wang, Dr. R. V. Kashid, Dr. P. Namboodiri, Dr. S. W. Schmucker, Dr. J. A. Hagmann, K. Liu, Dr. M. D. Stewart Jr., Dr. C. A. Richter, Dr. G. W. Bryant, Dr. R. M. SilverNanoscale Device Characterization DivisionNational Institute of Standards and TechnologyGaithersburg, MD 20899, USAE-mail: [email protected]; [email protected]. X. Wang, Dr. S. W. Schmucker, K. LiuJoint Quantum InstituteUniversity of MarylandCollege Park, MD 20742, USADr. X. WangChemical Physics ProgramUniversity of MarylandCollege Park, MD 20742, USAK. LiuDepartment of PhysicsUniversity of MarylandCollege Park, MD 20742, USA

The ORCID identification number(s) for the author(s) of this article can be found under https://doi.org/10.1002/adfm.201903475.

However such systems encounter chal-lenges in reaching the low temperature limit with regards to the phase space of physics that can be explored, and present a challenge to scalability and integration if they are to become part of functional materials and devices. The advent of atom-by-atom fabrication in a solid-state silicon environment has the potential to enable single or few-atom, spin-based qubits for quantum computing,[5] analog quantum simulation,[6] and novel synthetic quantum materials to realize topological and exotic physical states in the solid state.[7]

There has been significant recent pro-gress in developing single atom devices in the solid state as an analog to ultra-

cold atoms or ions in a vacuum using intricate ion implanta-tion methods[8] or scanning tunneling microscope (STM) based patterning.[9] Atomically precise fabrication can be uniquely achieved using STM H-depassivation lithography which ena-bles dopant atom placement with near atomic precision. A solid state, silicon environment is a compelling platform because atom-based devices can be directly integrated with traditional electronic architectures while the overall size of an atom-based device is on the scale of the atomic lattice. Atomic devices can be fabricated such that single electron transport occurs through a single atom using atomically aligned gates, source, drain, and quantum islands as sensors.[10] Charge offset drift and charge stability are excellent in these materials, which is essential for repeatable control of qubits. Additionally, single atom struc-tures are quite stable—we have manipulated and studied an individual P atom in a single atom transistor for more than six months with multiple thermal cycles while observing stable device behavior.

In addition to dopant-based spin and charge qubits for quantum information processing,[5,11] there is growing interest in using an atomically precise array of atoms, arranged in any number of different geometries, to explore a variety of many-body physics and as a tunable Hubbard system.[6,12] All of these examples rely on one key theme: atoms or atomic structures precisely placed and encapsulated in a clean, solid state crystal-line environment.

The sensitivity of atom-scale devices to atomic imperfections and defects necessitates development of robust lithographic processes and low temperature epitaxial silicon overgrowth to ensure a pristine crystalline environment free from defects,

Atomic Fabrication

1. Introduction

Atom-based devices have been pioneered in a variety of plat-forms, including optical lattices of ultracold atoms[1] and trapped ions.[2] The foundations for manipulating ultracold atoms and trapped ions have now been established and were used in the first demonstrations of quantum information pro-cessing.[3] These same systems have also been instrumental in exploring novel physics, such as Bose–Einstein condensation.[4]

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while using temperatures low enough to avoid inducing atomic movement. It is a further challenge as to how one measures and quantifies atomic movement in buried devices. Standard methods like secondary ion mass spectrometry (SIMS) and transmission electron microscopy (TEM) are destructive and are generally susceptible to averaging or mixing of atomic species. As a result, there is a clear need to explore materials metrology techniques and coherent transport measurements that are able to extract structural and electronic characteris-tics of the device layer, such as electronic thickness, scattering lengths, and phase coherence length.

In this manuscript we discuss key challenges and solu-tions in achieving robust atom-by-atom fabrication, ultimately resulting in the successful construction of a single-atom tran-sistor; while this is the second demonstration of a single atom transistor produced by any group to date, as a part of this work we demonstrate reproducibility of key results from the Simmons group who fabricated the world’s first single atom transistor in 2012.[13] That other groups have not managed to successfully reproduce a single atom transistor to date high-lights the degree of difficulty in achieving true atomic precision and the clear need for a detailed and systematic development of all aspects of atom by atom fabrication. For this reason, we describe our implementation of STM H-depassivation lithography and the associated fabrication processes to build fully functioning atom-based devices. We will briefly discuss methods to reliably relocate optically invisible devices buried under 30 nm of silicon to enable subsequent metallization and to ensure back end processes are properly aligned. Additionally, reliable contact processes that enable high yield, low resistance contact to devices are essential to robust fabrication and high device yield.[14] Contacts are in fact one of the most influential drivers in producing functional devices while at the same time being subject to significant constraints such as process temper-atures and high contact yield. The solutions to these challenges must have an emphasis on minimizing process-induced dopant movement and maintaining pristine atomically clean materials; it is imperative to maintain the precise atomic positions and key device dimensions.

After an in-depth discussion of our fabrication technology, we present measurements and analysis of atomically precise single electron transistors (SETs) that demonstrate stable Coulomb blockade oscillations. These measurements are instrumental in understanding fabrication accuracy at the single atom level and its direct effect on transport behavior in donor atom devices. The single and few atom transistors described here show excel-lent Coulomb blockade and charge stability that agree well with theoretical predictions and bulk dopant behavior.

2. Results

2.1. Fabrication Technology

The key enabling technology for this fabrication technique is STM-based H-depassivation lithography. The basic methods of H-depassivation lithography were first introduced by Lyding, Tucker, and Shen,[15] and then further developed by Simmons et al.[9]

True atomic-scale lithography is achieved by patterning the H terminated silicon surface, Si(100) 2 × 1:H, in an ultrahigh vacuum (UHV) environment. A silicon chip is loaded into UHV after a thorough cleaning procedure. The sample is flashed to 1200 °C for a period of ≈45 s (refs. [14,16] provide further exper-imental details of the sample preparation procedures). After forming the Si(100) 2 × 1 reconstruction, the surface is passi-vated with atomic hydrogen, resulting in a stable, well-ordered, and chemically inert H-terminated surface. This surface can be patterned using the STM tip in order to selectively remove H atoms and leave behind chemically active regions on the sur-face. After patterning, the sample is typically exposed to five Langmuirs of phosphine gas. By a thermally activated process, P adatoms substitute with Si atoms within the first atomic layer of the substrate. Low temperature (275 °C) epitaxial Si over-growth is then performed to encapsulate patterned Si:P devices in an epitaxial silicon matrix. The samples can then be safely removed from UHV.

The STM can be used in one of two modes to pattern the surface. In the vibrational heating regime,[15a,17] the tip is typi-cally scanned at 4.5 V or less with a tunneling current generally ranging from 1–16 nA, depending on the tip. High-resolution lithography using this mode is shown in Figure 1. The single dangling bonds (which manifest as bright dots in the STM topograph) do not contribute to Si:P patterning errors because nominally six dangling bonds along a dimer row (three dimers, where dimers have a pitch of 0.38 nm along the row) must be removed to enable the dissociative chemisorption of a single PH3 molecule and thus the incorporation of a single P dopant atom into the Si lattice.[18] The image of Figure 1b shows high resolution patterning at the atomic scale: a 2 dimer rows by 6 dimers patterned dot between a source and drain. The larger scale image shows two plunger gates as well. The larger contact pads (labeled S, D, G1, and G2 in Figure 1a) can be patterned at higher speeds using a higher voltage (generally 6 to 8 V) mode.

A key to achieving quality overgrowth and pristine STM patterning is achieving ultra (or even extreme) high vacuum (XHV) conditions. At a minimum, UHV systems must operate in the low 10−11 Torr (10−9 Pa) pressure range to realize the ultimate atomic lattices and quantum devices. SIMS analysis during the overgrowth process and patterning stages indicates that vacuum pressures in the 1 × 10−12 Torr (1.3 × 10−10 Pa) range would further improve device performance and resulting materials properties. If a pristine vacuum environment is not maintained, our data show that lithographic quality suffers and atomic precision is not achievable.

It is possible to go beyond the standard methods of pat-terning with the STM illustrated in Figure 1. Feedback con-trolled lithography (FCL) has been developed as a technique to enable the selective and localized depassivation of a single SiH bond.[19] We have further developed this technique to enable atomically precise lithography with both single- and two-atom FCL capabilities[16c] as illustrated in Figure 2. It should be noted that the results of Figure 2b were obtained using a low temperature STM, and the patterning and imaging were performed at low temperature (4.5 K). Here the tip sits over a dimer pair of atoms. The tip is then operated in the high-resolution lithography mode and, when the first H atom bond breaks and is depassivated, a change in tunnel conditions




causes a change in the feedback loop as seen in the schematic of Figure 2a (the tip moves away from the surface in order to maintain a constant current in the presence of a newly formed dangling bond). As the second atom is depassivated, a second change in the tunneling occurs (the tip moves closer to the sur-face due to a lower electronic density at the center of the dimer). In response to each depassivation event, the STM is returned to imaging mode parameters (low bias, and low current) to avoid further hydrogen removal. This is a repeatable process. Although true single atom and single dimer lithography is per-formed one atom at a time, as shown on the right, in imaging mode the individual atoms are not resolved. The detailed lobe structure observed, however, is unique to the precise pattern of single atoms that have been depassivated, and therefore can be mapped to the exact lithographic pattern even without a priori knowledge of which hydrogen atoms were removed. The STM image shows a pattern in which five patches of dangling bonds have been written using FCL, each patch consisting of three dimers in the geometry known to accommodate exactly one P atom incorporation.

As noted above, after H-depassivation lithography, the sample is exposed to phosphine gas followed by a thermal activation process.[20] The sample is then prepared for Si overgrowth.[16b,21] During overgrowth, diffusion and segrega-tion of P atoms can drive substantial distortion of patterned devices. It is necessary to optimize the growth process to ensure growth temperatures are high enough to facilitate Si epitaxy, yet low enough to mitigate dopant movement. The implementation of a locking layer (LL) approach has been shown to substantially improve confinement of the device layer during overgrowth.[16d,22] In this approach, a thin (≈11 atomic layers) Si layer is deposited at room temperature. The low growth temperature mitigates P segregation while the use of extremely thin layers facilitates epitaxy. Epitaxy is lost if room temperature growth continues,[23] but once the P atoms are locked beneath 11 monolayers of Si, further growth can proceed at temperatures as low as 275 °C while preserving the epitaxial quality of the overgrowth.


Figure 1. H-depassivation lithography for a single atom transistor. a) STM patterned contact pads are labeled S, D, G1, G2 for the source, drain, first gate, and second gate leads, respectively. The large-scale image is stitched together from multiple smaller scale images (gray areas were not imaged by the STM): this imaging strategy minimizes the risk of unintentionally despassivating regions not meant to be part of the device while inspecting the quality of previous depassivation steps. b) Atomic resolution image, stitched together from multiple STM scans, showing the depassivated source and drain leads and the central island into which a single P atom was later incorporated. White arrows highlight isolated dangling bonds while the black arrow highlights a single dangling bond at the corner of the depassivated island and the green arrow points to a lone defect (corresponding to 1 defect in the 1296 atoms imaged). STM images were acquired at −2 V sample bias with the exception of the cen-tral island of the single atom transistor (outlined with a dashed white box) which was acquired at +2 V sample bias. Imaging at +2 V sample bias carries with it the risk of creating spurious dangling bonds but allows for a clearer determination of the degree of dimer depassivation, in the pre-sent case indicating that two full dimer rows have been depassivated: at positive bias a fully depassivated dimer row will appear as two long lobes along the length of the row with a minimum along the centerline of the row, while two neighboring fully depassivated rows will appear as shown in the image, where the upper lobe of the bottom row appears to join the lower lobe of the top row to create a thick lobe sandwiched between two thinner ones. The asymmetric shape of the dangling bonds in the −2 V portion of (b) is due to tip imaging artifacts. Images are acquired after patterning and before dosing.

Figure 2. Precision achieved through controlled ramping of bias and current. a) Schematic illustrating the FCL procedure. Representative currents and voltages for each step are shown above the tip (gray triangles), with triangle height representing the separation between the tip and the underlying Si:H surface. Red ovals represent increased electronic density due to creation of a single dangling bond, while double orange ovals represent the slightly reduced charge density (in comparison to a single dangling bond) of a fully depassivated dimer. The respective tip heights for the fully passivated dimer, single dangling bond, and fully depassivated dimer are labeled z0, z1DB, and z2DB, respectively. Orange arrows indicate depassivation events in which a hydrogen atom is removed and the tip responds accordingly (corresponding black arrow). b) STM image acquired after use of FCL to write a cross-shaped pattern. Each elongated double-lobe pattern is a set of three fully depassivated dimers (with the long axis pointing along the dimer row); the set of six black circles represents the lattice positions of the underlying dimerized silicon atoms. The two smaller rounded lobes are spurious dangling bonds separated from the depassivated patterns with 1 H atom between, and therefore would not be able to accommodate any additional PH3 molecules. The image was acquired at a +2 V sample bias (at negative sample bias the double-lobes appear as single protrusions).



Figure 3 shows the basic process flow for a “blanket” develop-ment sample used to quantify the delta layer thickness, where an ideal delta layer is defined to be a single atomic layer of P encased in silicon. These blanket samples are used for SIMS, TEM, and electrical characterization to quantify the dopant movement and optimize the locking layer process. The figure shows a substantial difference in delta layer thickness as meas-ured by corrected SIMS analysis when comparing the samples with and without the locking layer. It should be noted that the locking layer results in lower electron mobility and higher sheet resistance because the ion cores are more densely packed and there is increased scattering. Achieving the best mobility and conductivity results in more spread in the P delta layers. Although the electrical conductivity is degraded, the locking layer results in the final devices having better defined tunnel junction geometry and device performance. This is critical in the design of tunnel coupling between a quantum dot and a donor with the potential for a major effect on the exchange cou-pling between single donors or few atom quantum dots.

There are several challenges in the measurement of 2D phos-phorous delta layers and atom-scale solid-state devices. It is essential to understand the effects of subtle variation in atomic fabrication processes on device characteristics such as coher-ence times or tunnel coupling. We need to quantify atomic

positioning and subsequent movement during fabrication, identify individual atomic contaminants, and characterize epitaxial quality to ensure pristine, crystalline encapsula-tion. Weak localization and coherent electron scattering can be used to characterize the electronic quality and help under-stand atomic impurity scattering processes. Transport methods capable of measuring atom scale defects are currently our best solution because conventional TEM and atom probe tomog-raphy have limited utility due to averaging.[24]

We have implemented an alternative nondestructive elec-trical measurement capability using weak localization.[24b,25] The Hikami–Larkin–Nagaoka (HLN) equation[24a,26] is used to fit the quantum correction to conductivity and extract the phase coherence length and dimensionality of the blanket 2D elec-tronic system as well as to directly characterize STM patterned devices such as van der Pauw squares. These electrical meas-urements address important challenges encountered when transitioning processes from blanket layer development chips to actual STM patterned devices. Figure 4 shows an example of an optical image of an STM patterned van der Pauw square with contacts as well as magneto transport and weak localiza-tion measurements. We observed significant reduction in the electrical performance of patterned devices when using the standard blanket layer processes. After reoptimizing our


Figure 3. Locking layers to suppress dopant movement. a) Process flow diagram indicating the timing for each thermal process and procedure involved in the UHV stage of fabrication of a delta layer device (times given are variable as they depend on calibrations as well as desired properties such as locking layer thickness). Here, RTA stands for rapid thermal anneal. b) Schematic of a typical delta layer device, consisting of a nominally single layer of phosphorus atoms (red) topped by a locking layer (labeled by LL and bounded by the dashed line) and imbedded in epitaxial silicon. c) TEM cross-section of a delta layer device showing epitaxial quality (scale is approximately the same as the schematic); the red arrow indicates the location of the delta layer which has near identical contrast to the surrounding Si. d) SIMS data (deconvoluted to yield more accurate depth dependence) illustrating the depth profiles for P in a delta layer device without (left) and with (right) an 11 monolayer (ML) locking layer (where 1 atomic layer = 0.138 nm).



processes for STM patterned van der Pauws, we found that typical coherence lengths at 3 K ranged from 30 to 45 nm in STM patterned devices as opposed to 50 to 100 nm in delta layer devices, where the large variation in electrical character-istics for the blanket delta layers is due to changes in dopant confinement that result from intentional changes in overgrowth parameters. STM patterned devices require a modified process window in the overgrowth parameter space because of the dif-ferences in the doping density at the surface (the patterned region is degenerately doped while the surrounding silicon is minimally doped) as well as the significant difference in hydrogen coverage between the passivated surface and the pat-terned surface. Electrical characterization has proven to be a necessary tool to track and monitor how processes need to be modified to achieve well-behaved devices.

Having developed the ability to reliably pattern devices, dose and incorporate phosphorus, and overgrow with minimal dopant movement, the problem of making contact to buried structures remains.[27] In our implementation, this involves relocation of buried devices in order to specify their coordi-nates to a sufficient degree of certainty, followed by fabrication of functional metallic contacts to the buried device. To facili-tate device relocation we use a prepatterned wafer as shown in Figure 5. After a four-inch wafer is patterned and etched, it is diced into chips ≈2.5 mm × 10 mm. The two-level etched pat-terns include a deep etch for e-beam alignment and a shallow 50 nm etch for STM tip alignment. One pattern can then be written in each 50 µm × 50 µm square (see bottom-right of Figure 5), although typically not more than two patterned devices per chip are written. We emphasize that this approach is a flexible strategy in that multiple devices per chip can be written and each device can be written in the cleanest area of a flat atomic terrace with minimal atomic defects. The location of the STM tip is recorded during device patterning and then the sample is removed from vacuum. Kelvin probe data are acquired simultaneously with atomic force microscopy imaging and then combined with optical bright-field and dark-field data to create a map that allows an e-beam patterning tool to align to the deep etch alignment marks and write complicated back end metallization features properly aligned to the underlying device.

Once the device coordinates are determined, a low tempera-ture palladium silicide process is used to make high quality, low contact resistance, high yield contacts to the buried devices.[14] In this process, palladium is deposited over the known location

of the buried STM-patterned contact pads, and then annealed for 20 min at 250 °C. Contact to the buried pads is achieved by interdiffusion of palladium and silicon during the anneal,


Figure 4. Electrical characterization of STM patterned van der Pauw. a) Optical micrograph of a van der Pauw device. The STM patterned structure is not optically visible as it is buried in silicon (dashed white outline shows the lateral location of the structure), while the four surface contacts are clearly visible. b) Magneto transport measurements at 3.2 K yielding a carrier density of 1.6 × 1014 cm−2 and mobility of 45 cm2 V−1 s−1. c) Weak localization, Δσ, measurements (black squares) and HLN fit (red line) resulting in a phase coherence length of 34 nm.

Figure 5. Pre-etched fiducial marks to relocate UHV STM Fabricated devices and align them relative to e-beam readable fiducial marks: shallow etch marks (blue) can be imaged by a scanning probe (STM or AFM) without damaging the tip, while deep etch marks (red) are deep enough to be aligned to by standard e-beam lithography tools. a) The set of all chip-level fiducial marks. b) Global e-beam alignment mark. c) Optical micrograph of overlay targets for determining alignment between shallow (inner square) and deep etch (outer square) marks. d) Optical micrograph of shallow etch marks used for alignment of STM fabricated patterns.



resulting in a clean interface between the newly formed palladium silicide and the device. It is important to highlight that this contacting process solves significant challenges associ-ated with fabrication of fully functional STM-patterned devices: previous contacting schemes that have been utilized by the com-munity have generally suffered from either high temperature requirements that risk unwanted dopant diffusion, low contact yield, or potential risk of contaminated interfaces (for a detailed discussion, see ref. [14]). The palladium silicide sequence of processes is reliable with near 100% yield, and therefore ena-bles writing of complex devices that require many functioning contacts which will be absolutely crucial as this field advances.

Having successfully made contact, the samples are then wire bonded and loaded into a low temperature cryostat for electrical measurement. This entire process, from chip to wire bonded contacts, typically takes 6–9 days to complete, including testing and optimization of lithography parameters.

2.2. Single Electron Transistors

The single electron transistor is a critical device in several solid state qubit realizations because it provides a reliable method to perform charge sensing and spin selective manipulation at the single electron level.[28] Additionally, we have identified SETs as a robust device framework that allows for nondestructive validation of device performance for a given set of fabrication processes and parameters while establishing a baseline for the expected electronic behavior of more complex quantum devices that build off of the same properties exhibited by SETs. A typ-ical device is shown in Figure 6 which consists of a source, drain, quantum island, and two in-plane gates. The principle of operation of an SET is that the chemical potentials for adding single electrons onto the island are discretized due to both Cou-lomb repulsion and quantum confinement (particularly for small islands). The two effects result in a spectrum of quan-tized electron addition energies that can be gated by capacitive coupling to turn on one electron tunneling channel at a time. In the devices described here, we observe a range of electron addition energies from 10 to 15 meV depending on the island size and state of charge; these addition energies are dominated by the charging energy associated with Coulomb repulsion since the islands are large enough that quantized energy level spacing is small relative to all other relevant energy spacings of the system. A source drain bias voltage is applied to open a bias window that allows current to flow from the source to the drain if the chemical potential of the quantum island is appropri-ately aligned in the bias window. The in-plane gates, commonly referred to as plunger gates, are used to sequentially turn on and off conduction through the SET. Figure 6f,g shows charge stability diagrams of two SETs (Figure 6d,e) fabricated using the techniques described in Section 2.1 in two independent UHV systems, labeled STM-1 and STM-2, respectively (see ref. [29] for a systematic study of SETs fabricated on these STMs).

From the charge stability diagrams of Figure 6, we extract addition energies, Eadd, of 13 meV for the SET from STM-1 and 12 meV for the SET from STM-2; capacitive couplings between device components have also been extracted from the charge stability diagram and are presented in Table 1. Additionally, we

have input the experimental design layout into a Poisson solver to determine the capacitive coupling for the various device ele-ments for an ideal device of the same geometry. The source, drain, and gates are treated as metallic in this analysis which is reasonable based on the nominal 1 × 1021 dopants cm−3 doping level (i.e., the device components are degenerately doped) and that the leads and island are more than 10 nm in width. The equivalent circuit diagram (Figure 6c) outlines the capacitive coupling of the elements as well as the tunnel cou-pling between the source and island and the island and drain. Table 1 shows a comparison between calculated capacitances and measured values. The agreement is quite good—continued agreement will be necessary as the device complexity increases. We can also reliably calculate expected tunneling rates based on a given design geometry following ref. [29] which is essential for controlling the tunnel rates for single shot spin read out and initialization. These types of calculations will be very impor-tant in designing complex multiqubit layouts with several gates needed to control charge-sensing SETs.

2.3. Single-Atom and Few-Atom Transistors

Using atom-by-atom fabrication, this SET geometry can be scaled to the single-atom domain, effectively creating a single-atom transistor. Figure 1 shows the STM lithography image for the single-atom transistor measurements shown in Figure 7. In these data, we observe three charge states and two electron-charging transitions. The data are, therefore, consistent with the signature associated with a single atom between the source and drain. The D+ charge state is the singly ionized state where the chemical potential for binding an electron (the additional valence electron that P has when compared to Si) to the atom lies above those of the source and drain, leaving the P atom with a net positive charge. The D0 state is where a single electron has been added and the atom is in a neutral state. The D− state is where the chemical potential has been lowered an additional 60 meV (the so-called addition energy) and a second electron has been added to the atom. The location of the ground state above the Fermi level, 69 meV, indicates that this is a single P atom (here the ground state energy is estimated by multiplying the zero-bias ground state peak position, VGS = 405 mV, by the lever arm, α = 0.17, as determined by the first diamond). When taking into account the local electrostatic environment and the significant changes in ground state energies that would result from two or more dopants as discussed in depth below, our observed D0 ground state energy is in reasonable agreement with the ground state energy measured by the Simmons group on their single-atom transistor[13] of 54 meV (based on a gate voltage of 450 mV and lever arm of 0.12 from their data).

As noted in Section 2.1, it should only be necessary to desorb hydrogen from three dimers in order to incorporate a single P; the lithographic pattern of Figure 1 consists of 12 fully depassivated dimers and two spurious dangling bonds (white and black arrows inside the dashed box of Figure 1b) and was designed to accommodate between 4 and 6 P atoms. The trans-port data presented in Figure 7 are not sufficient to fully rule out the possibility that the island consists of more than one P atom. In order to investigate this possibility, we consider what




effect a second nearby P atom would have on the ground state energy, thereby determining the relevant energy scale by which to evaluate our measured ground state energy with respect to other values reported in the literature.

The tight-binding analysis presented in Figure 7c shows that when two P atoms form a cluster the ground state shifts considerably lower in energy. If two P atoms were to incor-porate into the lithographic island of Figure 1, they would be at most 2.5 nm apart, corresponding to a lowering of the ground state energy by more than 50 meV, or a shift to the left in gate space of more than 290 mV. These values define the relevant energy scale for ground state energy comparison


Figure 6. STM patterned single electron transistors. a) STM image (composite of a larger and smaller image) showing the standard SET layout. b) 3D mesh model of SET input supplied as input to the FastCap software package.[35,36] Device components are treated as metallic conductors whose geom-etry is extracted from the STM-lithography image with a uniform thickness of z = 2 nm to account for the finite 2-D confinement in the z-direction, and are imbedded in Si with a dielectric constant of 11.7.[37] A lateral seam of s = 2.5 nm is added to account for the spatial extension of electron density in the lateral directions.[38] This fixed lateral seam has been found to produce good agreement with experimentally measured capacitances over a range of varied geometries. Simulation results can be seen in Table 1. c) Equivalent circuit diagram for the standard SET design (assuming both gates are oper-ated together). d) and e) Two SETs fabricated with the same geometric parameters in two separate UHV systems (STM-1 and STM-2, respectively) by different operators. f) Charge stability diagram acquired on the SET from (d), showing the differential conductance, G = dIDS/dVDS versus VDS and VGS, where VGS is the voltage applied to both side gates simultaneously. g) Charge stability diagram acquired on the SET from (e). For the charge stability diagram in (g), VGS was only applied to one side gate while the other was left floating. White arrows in (f) and (g) illustrate how addition energy, Eadd, is determined from the charge stability diagrams.

Table 1. Comparison between calculated and experimentally measured addition energies and capacitances for the SETs of Figure 6. The capaci-tance CΣ is defined to be the sum of all of the capacitances in the system for which one electrode is the island (which are defined in the equivalent circuit of Figure 6c).

Device Eadd [meV] CΣ [aF] CG1 [aF] CG2 [aF] CS [aF] CD [aF]

SET from STM-1 (Exp.) 13 12 1.7 1.7 4.4 4.3

SET from STM-1 (Sim.) 13.0 12.3 1.4 1.4 4.7 4.8

SET from STM-2 (Exp.) 12 14 1.1 1.3 5.8 5.7

SET from STM-2 (Sim.) 12.7 12.6 1.1 1.2 5.1 5.1



between single-atom and few-atom clustered systems and lead us to identify the transistor of Figure 1 as a single atom. In addition, we have made measurements on few atom tran-sistors intended to have between 2 and 4 atoms which have repeatedly shown the ground state to lie below the Fermi level consistent with the expected energetic shift from the tight-binding calculations. Figure 7b shows a charge stability plot from one such device.

It is beneficial to place the measured electron addition ener-gies for the single P atom measured in this study in the context of previous measurements of single P atoms. A range of values have been reported for the addition energy associated with tran-sitions from the D0 to the D− state for P in silicon: 44 meV[30] for isolated P in a bulk Si environment, Morello and Dzurak observed 28 meV[8e] in a surface-gated device where the P atoms were implanted, and the Simmons group observed 47 meV[13] for their single atom transistor and 50[10d] and 61 meV[31] for P atoms weakly coupled to SETs. While the basic properties of the P atom in Si are not changing in each of these cases (e.g., orbital structure), the electrostatic environment as influenced by the placement and type of electrodes does vary considerably and has been cited as the principle cause for lowering of the addition energy relative to bulk in the FET devices.[32] In the context of these previous measurements, all of the single P atom devices reported show ground state energies above the Fermi level, while all reported STM-fabricated planar devices additionally exhibit electron addition energies above the bulk value.

3. Discussion

One of the primary themes of this work is the importance of atomic precision during fabrication: control over the precise geometric layout in these devices is a key challenge because device performance is fundamentally based on tunnel coupling which itself is exponentially dependent on the spatial dimen-sions of the tunnel barrier as well as its energetic height. The position of individual atoms or defects directly affects device properties in qualitative ways. For example, in a few-atom quantum dot device, if an unintended atom is incorporated in proximity to the dot, the device becomes a double quantum dot which would clearly behave qualitatively differently from the intended design. Even without addition of unintended dots, if a tunnel junction in a charge sensing SET with similar design


Figure 7. Single atom and clustered transistors. a) Charge stability dia-gram showing the three charge configurations (D+, D0, and D−) for the single atom transistor of Figure 1, measured at 7 K. The red arrow points to the zero-bias peak position for the ground state of the single P atom

system. b) Charge stability diagram for a few-atom cluster transistor measured at 5 K. The red arrow points to the zero-bias peak position for the highest possible ground state based on the data (the ground state could lie below the gate space explored). c) Single-particle eigenvalues for a set of two P atoms in Si as a function of separation as determined from tight-binding calculations. The zero in energy is chosen to be the ground state energy when the P atoms are separated by 11 nm. The red curve highlights the position of the ground state at each separation. For the calculations, we used an sp3s*d5 basis set with tight-binding param-eters from Boykin et al.[39] and a central cell cutoff of 3.5 eV which have been previously demonstrated to yield good agreement with experiments for P in Si (see ref. [40] for examples). Dopants were separated along the [100] direction with distances varied in increments of 1 lattice constant in a supercell consisting of the Si lattice extending 40 lattice constants in each direction.



parameters to those given in Figure 6 (i.e., lead widths and island size) is less than about 4 nm, then the resistance drops below the quantum of resistance and Coulomb blockade effects are lost; this property changes at the scale of one dimer row (0.77 nm). Whether or not these kinds of errors occur is directly affected by the atomic precision of the junction and the local atomic defect and charge trap states in the immediate vicinity of the device. Therefore, having a single atom out of place in a key device region can fundamentally change its behavior.

These effects become even more crucial when analyzing single-atom transistors and tunnel coupling between few-atom structures to be used as exchange-coupled qubits—there is a strong atomic-scale dependence,[33] as well as cluster-size (i.e., number of atoms) dependence,[34] on the exchange coupling. Furthermore, our single-atom transistor results support previous reports that the precise layout of gates and source and drain electrodes relative to a single P atom can have a significant effect on its charging behavior.[8e,10d,13,30–31] Notably, the Simmons group found that the second electron to be added to their single atom transistor was more tightly bound than expected and that this could largely be understood through multiscale modeling of the potential landscape gen-erated by their specific device geometry when gate voltages were applied;[32] that the D− diamond for our transistor is even larger suggests that our device geometry creates stronger confinement, although in-depth modeling is necessary to con-firm this. This highlights the importance of modeling device characteristics over a range of scales and degrees of accuracy using coarse techniques such as capacitance modeling (as detailed in Figure 6 and Table 1), quantum mechanical mod-eling such as tight binding (as detailed in Figure 7), and more sophisticated schemes that bridge the gap between the two (as described in ref. [32]).

Similarly, the number of dopant atoms in a cluster will have significant effects on the charging energies and level spacing. Because any part of the fabrication process can affect final atomic positions, to achieve properly functioning devices it is necessary to implement high quality, high precision lithog-raphy, well-controlled P incorporation, defect free epitaxial low temperature overgrowth, accurate controlled thermal pro-cessing, and high-yield contacts that do not exceed the thermal budget. These are key requirements to achieve good device performance essential to future quantum devices. Although emphasizing the fact that control over each of the above men-tioned fabrication steps is absolutely necessary, it is worth-while to highlight two of the features of the present work that distinguish it from previous work in the field: 1) while this is not the first use of locking layers for delta layer confinement, accurate measurement of the growth temperatures and growth rates, and consistent use of optimized locking layers has led to a high degree of reproducibility, and 2) our contacting strategy has proven to be a higher yield, lower contact resistance process than previously utilized methods.

The arguments presented in Section 2.3 for the single atom versus cluster nature of the transistor of Figure 1 highlight two important challenges in regards to atomic precision device fab-rication: 1) as currently implemented, the hydrogen lithography technique while offering the highest available precision control over P placement in Si is still a stochastic process with respect

to the number of P atoms that incorporate into a lithographic patch, and 2) a detailed understanding of the energetics of various cluster configurations still remains to be fully explored both experimentally and theoretically. Building quantum devices using small clusters as their fundamental components allows us to accommodate the first point above, but will require significant research efforts to address the second.

Quantum devices based on single or few dopant clusters are likely to have certain advantages over devices fabricated by con-ventional means. First, the device characteristics are likely to be more reproducible than is currently achieved in convention-ally fabricated devices due to fabrication based on the natural atomic lattice. This fabrication approach enables devices to be buried in a pure, epitaxial silicon environment and therefore has the potential for an exceptionally clean operational envi-ronment resulting in reduced charge noise and higher stability because the sensitive portion of the device is removed from the SiO2 (or other) interface typical of conventional devices.

4. Conclusion

We have discussed our implementation of processes and methods that minimize dopant movement during fabrication and overgrowth, and therefore maximize reproducibility and yield. We have presented measurement techniques to charac-terize dopant distributions and dopant movement at the atomic scale using coherent transport and corrected SIMS techniques specific to understanding dopant movement as it relates to tunnel coupling in quantum devices. Single-electron, single- and few-atom transistor devices were demonstrated that exhibit well-behaved Coulomb diamonds and charge stability; these are the key building blocks to realize spin selective manipula-tion, quantum sensing and future qubits based on single or few atom structures.

Our results highlight the critical importance of under-standing single and few atom clusters. The detailed atomic configuration including number of P atoms in a cluster, atomic spacing, distance to nearby interfaces and device components will have a significant impact on performance in quantum devices. It is therefore a remaining challenge to implement techniques for determining fidelity between lithographic design and resultant P atom placements (e.g., knowing how many atoms incorporate into a pattern intended for four atoms), preferably in such a way as to determine the relative locations of all atoms in a few-atom structure. Further-more, after subsequent processing steps such as overgrowth, the fate of individual atoms that may have been placed with absolute precision is not necessarily known—they may have hopped a lattice site, or moved to a different atomic layer while following the growth front; while we have developed insights into this process by studying and optimizing blanket delta layers, the future of atomic precision will require more detailed knowledge. In order to advance this field in the imme-diate future, we need to develop devices whose functionality is minimally sensitive to the uncertainties mentioned here; at the same time there is room to explore ways to improve atom-scale device metrology with improved deterministic placement of atoms in devices.



1903475 (10 of 11) © 2019 WILEY-VCH Verlag GmbH & Co. KGaA, WeinheimAdv. Funct. Mater. 2019, 1903475

AcknowledgementsThis research was funded in part by the Department of Energy Advanced Manufacturing Office Award Number DE-EE0008311 and by a National Institute of Standards and Technology (NIST) Innovations in Measurement Science award, “Atom-Based Devices: Single Atom Transistors to Solid State Quantum Computing.” This work was performed in part at the Center for Nanoscale Science and Technology NanoFab at NIST. The authors acknowledge helpful discussions with Neil Zimmerman.

Conflict of InterestThe authors declare no conflict of interest.

Keywordscharge transport, nanodevices, quantum dots, single electron transistors

Received: April 30, 2019Revised: July 20, 2019

Published online:

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