ATtiny417 / ATtiny814 / ATtiny816 / ATtiny817

AVR 8-bit Microcontrollers

ATtiny417 ATtiny814 ATtiny816 ATtiny817

DATASHEET ADVANCE INFORMATION

Introduction

The Atmelreg ATtiny417814816817 is a series of microcontrollers using the8-bit AVRreg processor with hardware multiplier running at up to 20MHz withup to 8KB Flash 512 bytes of SRAM and 128 bytes of EEPROM in a 14-20- and 24-pin package The series uses the latest technologies from Atmelwith a flexible and low power architecture including Event System andSleepWalking accurate analog features and advanced peripheralsCapacitive touch interfaces with driven shield are supported with theintegrated QTouchreg peripheral touch controller

Features

bull CPUndash Atmelreg AVRreg 8-bit CPUndash Running at up to 20MHzndash Single cycle IO accessndash Two-level interrupt controllerndash Two-cycle hardware multiplier

bull Memoriesndash 48KB In-system self-programmable Flash memoryndash 128B EEPROMndash 256512B SRAM

bull Systemndash Power-on Reset (POR)ndash Brown-out Detection (BOD)ndash Clock options

bull Fusible 1620MHz low power internal RC oscillator withndash plusmn3 accuracy over full temp and voltage rangendash plusmn15 drift over limited temp and full voltage range

bull 32768kHz Ultra Low Power (ULP) internal RC oscillatorwith plusmn10 accuracy plusmn2 calibration step size

bull 32768kHz external crystal oscillatorbull External clock input

Atmel-42721A-ATtiny417814816817_Datasheet_Advance Information-092016

ndash Single pin Unified Program Debug Interface (UPDI)ndash Three sleep modes

bull Idle with all peripherals running and mode for immediate wake up timebull Standby

ndash Configurable operation of selected peripheralsndash SleepWalking peripherals

bull Power Down with limited wake-up functionalitybull Peripherals

ndash One 16-bit TimerCounter type A with dedicated period register 3 compare channels (TCA)ndash One 16-bit TimerCounter type B with input capture (TCB)ndash One 12-bit TimerCounter type D optimized for control applications (TCD)ndash One 16-bit Real Time Counter (RTC) running from external crystal or internal RC oscillatorndash One USART with fractional baud rate generator autobaud and start-of-frame detectionndash Masterslave Serial Peripheral Interface (SPI)ndash Masterslave I2C with dual address match

bull Standard mode (Sm 100kHz)bull Fast mode (Fm 400kHz)bull Fast mode plus (Fm+ 1MHz)

ndash Configurable Custom Logic (CCL) with two programmable Lookup Tables (LUT)ndash Analog Comparator (AC) with fast propagation delayndash 10-bit 150ksps Analog to Digital Converter (ADC)ndash 8-bit Digital to Analog Converter (DAC)ndash Five selectable internal voltage references 055V 11V 15V 25V and 43Vndash Automated CRC memory scanndash Watchdog Timer (WDT) with Window Mode with separate on-chip oscillatorndash Peripheral Touch Controller (PTC)(1)

bull Capacitive touch buttons sliders and wheelsbull Wake-up on touchbull Driven shield for improved moisture and noise handling performancebull Six self-capacitance and nine mutual-capacitance channels

ndash External interrupt on all general purpose pinsbull IO and Packages

ndash 12 to 22 programmable IO linesndash 14-pin SOIC150ndash 20-pin QFN 3x3 and SOIC300ndash 24-pin QFN 4x4

bull Temperature Ranges -40degC to 105degC within specificationndash Some device variants -40degC to 125degC with reduced spec

bull Speed Gradesndash 0-5MHz 18V ndash 55Vndash 0-10MHz 27V ndash 55Vndash 0-20MHz 45V ndash 55V

Note 1 Only available in devices with 8KB Flash

Atmel ATtiny417 ATtiny814 ATtiny816 ATtiny817 [DATASHEET]Atmel-42721A-ATtiny417814816817_Datasheet_Advance Information-092016

Table of Contents

Introduction1

Features 1

1 Configuration Summary10

2 Ordering Information 1121 ATtiny81x 1122 ATtiny41x12

3 Block Diagram 13

4 Pinout1441 24-pin QFN1442 20-pin QFN1543 20-pin SOIC1644 14-pin SOIC17

5 IO Multiplexing and Considerations1851 Multiplexed Signals18

6 Memories2061 Overview2062 Memory Map2163 In-System Reprogrammable Flash Program Memory2164 SRAM Data Memory2265 EEPROM Data Memory 2266 User Row2367 IO Memory2368 FUSES - Configuration and User Fuses23

7 Peripherals and Architecture 3871 Peripheral Module Address Map 3872 Interrupt Vector Mapping 39

8 SYSCFG - System Configuration 4181 Overview4182 Functional Description4183 Register Summary - SYSCFG4484 Register Description 44

9 AVR CPU 4791 Overview4792 Features 4793 Architecture 4794 ALU - Arithmetic Logic Unit 49

95 Functional Description5096 Register Summary5597 Register Description 55

10 NVMCTRL - Non Volatile Memory Controller 59101 Overview59102 Features 59103 Block Diagram 60104 Product Dependencies 60105 Functional Description61106 Register Summary - NVMCTRL 67107 Register Description 67

11 CLKCTRL - Clock Controller75111 Overview75112 Features 75113 Block Diagram - CLKCTRL76114 Signal Description77115 Functional Description77116 Register Summary81117 Register Description 81

12 SLPCTRL - Sleep Controller 92121 Overview92122 Features 92123 Block Diagram 92124 Product Dependencies 92125 Functional Description93126 Register Summary96127 Register Description 96

13 RSTCTRL - Reset Controller98131 Overview98132 Features 98133 Block Diagram 98134 Signal Description99135 Functional Description99136 Register Summary - RSTCTRL101137 Register Description 101

14 CPUINT - CPU Interrupt Controller 104141 Overview104142 Features 104143 Block Diagram 105144 Signal Description105145 Product Dependencies 105146 Functional Description106147 Register Summary - CPUINT111148 Register Description111

15 EVSYS - Event System116151 Overview116152 Features116153 Block Diagram 117154 Signal Description118155 Product Dependencies 118156 Functional Description 119157 Register Summary - EVSYS121158 Register Description 121

16 PORTMUX - Port Multiplexer134161 Overview134162 Signal Description134163 Register Summary135164 Register Description 135

17 PORT - IO Pin Controller140171 Overview140172 Features 140173 Block Diagram 141174 Signal Description141175 Product Dependencies 142176 Functional Description142177 Register Summary - PORT146178 Register Description - Ports146179 Register Summary - VPORT 1581710 Register Description - Virtual Ports 158

18 BOD - Brownout Detector163181 Overview163182 Features 163183 Block Diagram 163184 Product Dependencies 164185 Functional Description165186 Register Summary167187 Register Description 167

19 VREF - Voltage Reference 174191 Overview174192 Features 174193 Block Diagram 174194 Functional Description175195 Register Summary176196 Register Description 176

20 WDT - Watchdog Timer 179201 Overview179202 Features 179

203 Block Diagram 180204 Signal Description180205 Product Dependencies 180206 Functional Description181207 Register Summary185208 Register Description 185

21 TCA - 16-bit TimerCounter Type A 189211 Overview189212 Features 189213 Block Diagram 190214 Signal Description191215 Product Dependencies 191216 Functional Description192217 Register Summary - Normal Mode (CTRLDSPLITM=0) 201218 Register Description - Normal Mode 202219 Register Summary - Split Mode (CTRLDSPLITM=1) 2222110 Register Description - Split Mode222

22 TCB - 16-bit TimerCounter Type B 238221 Overview238222 Features 238223 Block Diagram 239224 Signal Description239225 Product Dependencies 239226 Functional Description240227 Register Summary250228 Register Description 250

23 TCD - 12-bit TimerCounter Type D262231 Overview262232 Features 262233 Block Diagram 263234 Signal Description263235 Product Dependencies 263236 Functional Description265237 Register Summary286238 Register Description 287

24 RTC - Real Time Counter 312241 Overview312242 Features 312243 Block Diagram 313244 Signal Description313245 Product Dependencies 313246 RTC Functional Description314247 PIT Functional Description 315248 Events316249 Interrupts 317

2410 Sleep Mode Operation 3172411 Synchronization3172412 Configuration Change Protection 3182413 Register Summary - RTC3192414 Register Description319

25 USART - Universal Synchronous and Asynchronous Receiver and Transmitter 336251 Overview336252 Features 336253 Block Diagram 338254 Signal Description338255 Product Dependencies 339256 Functional Description340257 Register Summary354258 Register Description 354

26 SPI - Serial Peripheral Interface 373261 Overview373262 Features 373263 Block Diagram 373264 Signal Description374265 Product Dependencies 374266 Functional Description375267 Register Summary379268 Register Description 379

27 TWI - Two Wire Interface388271 Overview388272 Features 388273 Block Diagram 389274 Signal Description389275 Product Dependencies 389276 Functional Description391277 Register Summary - TWI402278 Register Description 402

28 CRCSCAN - Cyclic Redundancy Check Memory Scan 420281 Overview420282 Features 420283 Block Diagram 421284 Product Dependencies 421285 Functional Description422286 Register Summary425287 Register Description 425

29 CCL ndash Configurable Custom Logic 430291 Overview430292 Features 430293 Block Diagram 431

294 Signal Description431295 Product Dependencies 431296 Functional Description432297 Register Summary - CCL 440298 Register Description 440

30 AC ndash Analog Comparator 449301 Overview449302 Features 449303 Block Diagram 450304 Signal Description450305 Product Dependencies 450306 Functional Description451307 Register Summary - AC454308 Register Description 454

31 ADC - Analog to Digital Converter460311 Overview460312 Features 460313 Block Diagram 461314 Signal Description461315 Product Dependencies 461316 Functional Description462317 Register Summary472318 Register Description 472

32 DAC - Digital to Analog Converter491321 Overview491322 Features 491323 Block Diagram 491324 Signal Description491325 Product Dependencies 491326 Functional Description493327 Register Summary495328 Register Description 495

33 PTC - Peripheral Touch Controller498331 Overview498332 Features 498333 Block Diagram 499334 Signal Description499335 Product Dependencies 500336 Functional Description501

34 UPDI - Unified Program and Debug Interface 502341 Overview502342 Features 502343 Block Diagram 503344 Product Dependencies 503

35 Instruction Set Summary 537

36 Electrical Characteristics 544361 Disclaimer544362 Absolute Maximum Ratings 544363 General Operating Ratings 545364 Voltage Protection 546

37 Typical Characteristics548371 Power Consumption 548

38 Package Drawings554381 WARNING 554382 14-pin SOIC150555383 20-pin SOIC300556384 20-pin VQFN557385 24-pin QFN558

39 Datasheet Revision History 559391 RevA - 092016559

1 Configuration SummaryTable 1-1 Configuration Summary

Pins 24 20 14

SRAM 256512B 512B 512B

Flash 48KB 8KB 8KB

EEPROM 128B 128B 128B

Max frequency 20MHz 20MHz 20MHz

16-bit TimerCounter type A (TCA) 1 1 1

16-bit TimerCounter type B (TCB) 1 1 1

12-bit TimerCounter type D (TCD) 1 1 1

Real Time Counter (RTC) 1 1 1

USART 1 1 1

SPI 1 1 1

TWI (I2C) 1 1 1

ADC 1 1 1

ADC channels 12 12 10

DAC 1 1 1

AC 1 1 1

AC inputs 2p2n 2p2n 1p1n

Peripheral Touch Controller (PTC)(1) No Yes(2) Yes(2) Yes(2)

PTC number of self-capacitance channels(1) 6 6 6

PTC number of mutual-capacitance channels(1) 9 9 9

Custom Logic 1 1 1

Window Watchdog 1 1 1

Event System channels 6 6 6

General purpose IO 22 18 12

External interrupts 22 18 12

CRCSCAN 1 1 1

Note 1 PTC is only available in devices with 8KB Flash (ATtiny817 ATtiny816 and ATtiny814)2 The PTC serves as input to the ADC

2 Ordering Information

21 ATtiny81xTable 2-1 ATtiny817 Ordering Codes

Ordering Code(1) Flash Package Type Leads Power Supply Operational Range Carrier Type

ATtiny817-MNRES(2)

8KB QFN 4x4 24 18V - 55V Industrial (-40degC+105degC)

Tape amp Reel

ATtiny817-MNR 8KB QFN 4x4 24 18V - 55V Industrial (-40degC+105degC)

Tape amp Reel

ATtiny817-MFR 8KB QFN 4x4 24 18V - 55V Industrial (-40degC+125degC)

Tape amp Reel

Table 2-2 ATtiny816 Ordering Codes

ATtiny816-MNRES(2)

Tape amp Reel

ATtiny816-SNR 8KB SOIC300 20 18V - 55V Industrial (-40degC+105degC)

Tape amp Reel

ATtiny816-SFR 8KB SOIC300 20 18V - 55V Industrial (-40degC+125degC)

Tape amp Reel

Ordering Code(1) Flash PackageType

Leads Power Supply Operational Range Carrier Type

ATtiny814-SSNRES(2)

8KB SOIC150 14 18V - 55V Industrial (-40degC+105degC)

Tape amp Reel

ATtiny814-SSNR 8KB SOIC150 14 18V - 55V Industrial (-40degC+105degC)

Tape amp Reel

ATtiny814-SSFR 8KB SOIC150 14 18V - 55V Industrial (-40degC+125degC)

Tape amp Reel

Note 1 Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances

(RoHS directive) Also Halide free and fully Green2 Engineering samples

Tape amp Reel

1 Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances(RoHS directive) Also Halide free and fully Green

3 Block Diagram

Oscillators Clock generation

BUS Matrix

PTC ADC

AINN[10]AINP[10]

ADC[150]X[150]Y[150]

PDS[10]

OC[20]

OC[10]

MISOMOSISCK_SS

SDASCL

System Management

SLEEPCTRL

RSTCTRL

CLKCTRL

SYSTEM

DATABUS

UPDICRC

NVM Controller

EEPROM

UPDIphy

System Interface

System info

OSC20M

OSC32K

XOSC32K

EXTCLK

Detectors

POR BG

WindowWDT

INTCTRL

SINGLE

DATABUS

ResetRST12V

CPUINT

Bridge Bridge

OC[20]

4 Pinout

41 24-pin QFN

7 8 9 10 11 12

192021222324

Analog

ClockXOSCRESETProg

Digital

Input SupplyGround

42 20-pin QFN

PA2 PC0

6 7 8 9 10

1617181920

Analog

ClockXOSCRESETProg

Digital

Input SupplyGround

43 20-pin SOIC

VCC GND

PA3PA4

44 14-pin SOIC

VCC GND

PA3PA4

5 IO Multiplexing and Considerations

51 Multiplexed SignalsTable 5-1 PORT Function Multiplexing

QFN24-pin

QFN20-pin

SOIC20-pin

SOIC14-pin

PinName (1)

Event(5) OtherSpecial

EXTINTn(2)

ADC0 PTC(3)

AC0 DAC USART0 SPI0 TWI0 TCA0 TCB0 TCD0 CCL

23 19 16 10 PA0 EVINA0 EVINS0 RESET

S AIN0 LUT0-IN0

24 20 17 11 PA1 EVINA0 EVINS0

S AIN1 TXD MOSI SDA LUT0-IN1

1 1 18 12 PA2 EVINA0 EVINS0 EVOUT0

A AIN2 RxD MISO SCL LUT0-IN2

CLKI S AIN3 XCK SCK W03

3 3 20 14 GND4 4 1 1 VDD5 5 2 2 PA4 EVINA0

EVINS0S AIN4 X0Y0 XDIR SS W04 TCDOUTA LUT0-

OUT6 6 3 3 PA5 EVINA0

EVINS0S AIN5 X1Y1 ACOUT W05 W0 TCDOUTB

A AIN6 X2Y2 N0 OUT

S AIN7 X3Y3 P0 LUT1-OUT

9 PB7 EVINA1 EVINS1

10 PB6 EVINA1 EVINS1

11 9 6 PB5 EVINA1 EVINS1

CLKOUT S AIN8 P1 W02

S AIN9 DS1 N1 W01 LUT0-OUT

13 11 8 6 PB3 EVINA1 EVINS1 EVOUT1

TOSC1S RxD W00

14 12 9 7 PB2 EVINA1 EVINS1

TOSC2 A DS0 TxD W02

S AIN10 X4Y4 XCK SDA W01

S AIN11 X5Y5 XDIR SCL W00

17 15 12 PC0 EVINA2 EVINS0

S SCK W0 TCDOUTC

S MISO TCDOUTD LUT1-OUT

19 17 14 PC2 EVINA2 EVINS0 EVOUT2

A MOSI

S SS W03 LUT1-IN0

21 PC4 EVINA2 EVINS0

S W04 LUT1-IN1

RESET S W05 LUT1-IN2

Note 1 Pins PAn are configured by PORT instance A pins PBn are configured by PORT B etc2 S Detection = Synchronous and limited asynchronous A Detection = Synchronous and full

asynchronous3 PTC is only available in devices with 8KB Flash (ATtiny817 ATtiny816 ATtiny814) Every PTC line

can be configured as X-line or Y-line4 Default pin assignment of signals are in regular font Signals on alternative pin locations are in

italic5 EVINA Event input for asynchronous channel EVINS Event input for synchronous channel

6 Memories

61 OverviewThe main memories are SRAM data memory EEPROM data memory and Flash program memory Inaddition the peripheral registers are located in the IO memory space

Table 6-1 Physical Properties of EEPROM

Property ATtiny817816814 ATtiny417

Size 128B 128B

Page size 32B 32B

Number of pages 4 4

Start address 0x1400 0x1400

Table 6-2 Physical Properties of SRAM

Size 512B 256B

Start address 0x3E00 0x3F00

Table 6-3 Physical Properties of Flash Memory

Size 8KB 4KB

Page size 64B 64B

Number of pages 128 64

62 Memory MapFigure 6-1 Memory Map

(Reserved)

NVM IO Registers and data

64 IO Registers

960 Ext IO Registers

0x0000 ndash 0x003F

0x0040 ndash 0x0FFF

0x1400 - 0x1480EEPROM128B

Flash code

0x1000 ndash 0x13FF

Internal SRAM256512B

0x3F000x3E00

48KB 0x8000 - 0x8FFF0x9FFF

0x3FFF

Flash code48KB

0x0000

CPU Code space PDICPU Data space

63 In-System Reprogrammable Flash Program MemoryThe ATtiny417814816817 contains 48KB On-Chip In-System Reprogrammable Flash memory forprogram storage Since all AVR instructions are 16 or 32 bits wide the Flash is organized as 4K x 16 Forwrite protection the Flash Program memory space can be divided into three sections Boot Loadersection Application code section and Application data section with restricted access rights among them

The program counter is 1211 bits wide to address the whole program memory The procedure for writingFlash memory is described in detail in the documentation of the Non-Volatile Memory Controller(NVMCTRL) peripheral

The entire Flash memory is mapped in the memory space and is accessible with normal LDSTinstructions as well as the LPM instruction For LDST instructions the Flash is mapped from address0x8000 For the LPM instruction the Flash start address is 0x0000

The ATtiny417814816817 also has a CRC module that acts a master on the bus If the CRC isconfigured to run in the background it will read the Flash memory and can modify the program timing

Related LinksConfiguration Summary on page 10NVMCTRL - Non Volatile Memory Controller on page 59Flash Write Protection on page 64

64 SRAM Data MemoryThe 512B SRAM is used for data storage and stack

Related LinksAVR CPU on page 47Stack and Stack Pointer on page 51

65 EEPROM Data MemoryThe ATtiny417814816817 contains 128 bytes of data EEPROM memory see Memory Map TheEEPROM memory supports single byte read and write The EEPROM is controlled by the Non-VolatileMemory Controller (NVMCTRL)

Preventing EEPROM CorruptionDuring periods of low VDD the EEPROM data can be corrupted because the supply voltage is too low forthe CPU and the EEPROM to operate properly These issues are the same as for board level systemsusing EEPROM and the same design solutions should be applied

An EEPROM data corruption can be caused by two situations when the voltage is too low First a regularwrite sequence to the EEPROM requires a minimum voltage to operate correctly Also the CPU itself canexecute instructions incorrectly when the supply voltage is too low

EEPROM data corruption can easily be avoided by these measures

Keep the AVR RESET active (low) during periods of insufficient power supply voltage This is done byenabling the internal Brown-Out Detector (BOD)

If the detection levels of the internal BOD does not match the required detection level an external low-VDD-reset protection circuit can be used If a Reset occurs while a write operation is ongoing the writeoperation will be completed provided that the power supply voltage is sufficient

Related LinksMemory Map on page 21NVMCTRL - Non Volatile Memory Controller on page 59BOD - Brownout Detector on page 163

66 User RowIn addition to the EEPROM the ATtiny417814816817 contains one extra page of EEPROM memorythat can be used for firmware settings the User Row (USERROW) This memory supports single byteread and write as the normal EEPROM The CPU can write this memory as normal EEPROM and theUPDI can write it as a normal EEPROM memory if the part is unlocked The User Row can also be writtenby the UPDI when the part is locked with a special key USERROW is not affected by a chip erase

Related LinksMemory Map on page 21NVMCTRL - Non Volatile Memory Controller on page 59UPDI - Unified Program and Debug Interface on page 502

67 IO MemoryAll ATtiny417814816817 IOs and peripherals are located in the IO space All IO locations can beaccessed by the LDLDSLDD and STSTSSTD instructions transferring data between the 32 generalpurpose working registers and the IO space

IO Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBIinstructions In these registers the value of single bits can be checked by using the SBIS and SBICinstructions Refer to the Instruction Set section for more details

The IO specific commands IN and OUT can access the IO addresses 0x00 - 0x3F

The IO address range from 0x00 to 0x3F can be accessed in single cycle using IN and OUT instructionsFor the Extended IO space from 0x0040 - 0x0FFF only the STSTSSTD and LDLDSLDD instructionscan be used

For compatibility with future devices reserved bits should be written to zero if accessed Reserved IOmemory addresses should never be written

Some of the Status Flags are cleared by writing a 1 to them Note that on ATtiny417814816817devices the CBI and SBI instructions will only operate on the specified bit and can therefore be used onregisters containing such Status Flags The CBI and SBI instructions work with registers 0x00 - 0x1F only

General Purpose IO RegistersThe ATtiny417814816817 devices provide four General Purpose IO Registers These registers can beused for storing any information and they are particularly useful for storing global variables and StatusFlags

Related LinksMemory Map on page 21Instruction Set Summary on page 537

68 FUSES - Configuration and User Fuses

681 Signature Row Summary - SIGROW

Offset Name Bit Pos

0x00 DEVICEID0 70 DEVICEID[70]

0x03 SERNUM0 70 SERNUM[70]

0x0A SERNUM7 70 SERNUM[70]

0x0B SERNUM8 70 SERNUM[70]

0x0C SERNUM9 70 SERNUM[70]

Reserved

0x20 TEMPSENSE0 70 TEMPSENSE[70]

682 Signature Row Description

6821 Device ID n

Name DEVICEIDnOffset 0x00 + n0x01 [n=02]Reset [Device ID]Property

Bit 7 6 5 4 3 2 1 0 DEVICEID[70]

Access R R R R R R R R Reset 0 0 0 0 0 0 0 0

Bits 70 ndash DEVICEID[70] Byte n of the Device ID

6822 Serial Number Byte n

Name SERNUMnOffset 0x03 + n0x01 [n=09]Reset [device serial number]Property

Bit 7 6 5 4 3 2 1 0 SERNUM[70]

Bits 70 ndash SERNUM[70] Serial Number n [n=09]Each device has an individual serial number representing a unique ID This can be used to identify aspecific device in the field The serial number consists of ten bytes

6823 Temperature Sensor Calibration n

Name TEMPSENSEnOffset 0x20 + n0x01 [n=01]Reset [Temperature sensor calibration value]Property

Bit 7 6 5 4 3 2 1 0 TEMPSENSE[70]

Bits 70 ndash TEMPSENSE[70] Temperature Sensor Calibration ByteTBD

683 Fuse Summary - FUSE

Offset Name Bit Pos

0x00 WDTCFG 70 WINDOW[30] PERIOD[30]

0x01 BODCFG 70 LVL[20] SAMPLFREQ ACTIVE[10] SLEEP[10]

0x02 OSCCFG 70 OSCLOCK FREQSEL[10]

0x03 Reserved

0x04 TCD0CFG 70 CMPD CMPC CMPB CMPA CMPD CMPC CMPB CMPA

0x05 SYSCFG0 70CRCBOOTDI

SCRCAPPDIS RSTPINCFG[10] EESAVE

0x06 SYSCFG1 70 SUT[20]

0x07 APPEND 70 APPEND[70]

0x08 BOOTEND 70 BOOTEND[70]

0x09 Reserved

0x0A LOCKBIT 70 LOCKBIT[70]

684 Fuse Description

6841 Watchdog Configuration

Name WDTCFGOffset 0x00Reset -Property

Bit 7 6 5 4 3 2 1 0 WINDOW[30] PERIOD[30]

Bits 74 ndash WINDOW[30] Watchdog Window Timeout PeriodThis value is loaded into the WINDOW bit field of the Watchdog Control A register (WDTCTRLA) at theend of the startup sequence

Bits 30 ndash PERIOD[30] Watchdog Timeout PeriodThis value is loaded into the PERIOD bit field of the Watchdog Control A register (WDTCTRLA) at theend of the startup sequence

6842 BOD Configuration

Name BODCFGOffset 0x01Reset -Property

Bit 7 6 5 4 3 2 1 0 LVL[20] SAMPLFREQ ACTIVE[10] SLEEP[10]

Bits 75 ndash LVL[20] BOD LevelThis value is loaded into the LVL bit field of the BOD Control B register (BODCTRLB) at the end of thestartup sequence

Bit 4 ndash SAMPLFREQ BOD Sample FrequencyThis value is loaded into the SAMPLEFREQ bit of the BOD Control A register (BODCTRLA) at the end ofthe startup sequence

Value Description0x0 Sample frequency is 1kHz

0x1 Sample frequency is 125Hz

Bits 32 ndash ACTIVE[10] BOD Operation Mode in Active and IdleThis value is loaded into the ACTIVE bit field of the BOD Control A register (BODCTRLA) at the end ofthe startup sequence

Value Description0x0 Disabled

0x1 Enabled

0x2 Sampled

0x3 Enabled with wake-up halted until BOD is ready

Bits 10 ndash SLEEP[10] BOD Operation Mode in SleepThis value is loaded into the SLEEP bit field of the BOD Control A register (BODCTRLA) at the end ofthe startup sequence

0x1 Enabled

0x2 Sampled

0x3 Reserved

6843 Oscillator Configuration

Name OSCCFGOffset 0x02Reset -Property

Bit 7 6 5 4 3 2 1 0 OSCLOCK FREQSEL[10]

Access R R R Reset 0 0 0

Bit 7 ndash OSCLOCK Oscillator LockThis fuse bit is written to LOCKEN in CLKCTRLMCLKLOCK at startup

Value Description0 Calibration registers of the main oscillator are accessible

1 Calibration registers of the main oscillator are locked

Bits 10 ndash FREQSEL[10] Frequency SelectThese bits selects the operation frequency of the 1620MHz internal oscillator (OSC20M) and determinethe respective calibration value to be written to CAL20M in CLKCTRLOSC20MCALIBA

Value Description0x1 Run at 16MHz with corresponding factory calibration

0x2 Run at 20MHz with corresponding factory calibration

Other Reserved

6844 Timer Counter Type D ConfigurationThe bit values of this fuse register are written to the corresponding bits in the TCDFAULTCTRL registerof the TCD0

Name TCD0CFGOffset 0x04Reset -Property

Bit 7 6 5 4 3 2 1 0 CMPD CMPC CMPB CMPA CMPD CMPC CMPB CMPA

Bits 4 5 6 7 ndash CMPA CMPB CMPC CMPD Compare x Enable

Value Description0 Compare x output on Pin is disabled

1 Compare x output on Pin is enabled

Bits 0 1 2 3 ndash CMPA CMPB CMPC CMPD Compare xThis bit selects the default state of Compare x after Reset or when entering debug if FAULTDET is 1

Value Description0 Compare x default state is 0

1 Compare x default state is 1

6845 System Configuration 0

Name SYSCFG0Offset 0x05Reset -Property

Bit 7 6 5 4 3 2 1 0 CRCBOOTDIS CRCAPPDIS RSTPINCFG[10] EESAVE

Access R R R R R Reset 0 0 0 0 0

Bit 7 ndash CRCBOOTDIS CRC of Boot Section in Reset DisableSee CRC description for more information about the functionality

Value Description0 Boot section undergoing a CRC before Reset releases

1 No CRC of the boot section before Reset releases

Bit 6 ndash CRCAPPDIS CRC of Application Code Section in Reset DisableSee CRC description for more information about the functionality

Value Description0 Application code section undergoing a CRC before Reset releases

1 No CRC of the application code section before Reset releases

Bits 32 ndash RSTPINCFG[10] Reset Pin ConfigurationThese bits select the ResetUPDI pin configuration

Value Description0x0 GPIO

0x1 UPDI

0x2 RESET

0x3 Reserved

Bit 0 ndash EESAVE EEPROM Save during chip eraseNote If the device is locked the EEPROM is always erased by a chip erase regardless of this bit

Value Description0 EEPROM erased during chip erase

1 EEPROM not erased under chip erase

Bit 7 6 5 4 3 2 1 0 SUT[20]

Bits 20 ndash SUT[20] Start Up Time SettingThese bits selects the start-up time

Value Description0x0 0ms

0x1 1ms

0x2 2ms

0x3 4ms

0x4 8ms

0x5 16ms

0x6 32ms

0x7 64ms

other Reserved

6847 Application Code End

Name APPENDOffset 0x07Reset -Property

Bit 7 6 5 4 3 2 1 0 APPEND[70]

Bits 70 ndash APPEND[70] Application Code Section EndThese bits set the end of the application code section in blocks of 256 bytes The end of the applicationcode section should be set as BOOT size + application code size A value of 0x00 defines the wholeFlash as application code sectionNote When both FUSEAPPEND and FUSEBOOTEND are 0x00 the entire Flash is application codesection

6848 Boot End

Name BOOTENDOffset 0x08Reset -Property

Bit 7 6 5 4 3 2 1 0 BOOTEND[70]

Bits 70 ndash BOOTEND[70] Boot Section EndThese bits set the end of the boot section in blocks of 256 bytes A value of 0x00 defines the whole Flashas BOOT sectionNote When both FUSEAPPEND and FUSEBOOTEND are 0x00 the entire Flash is application codesection

6849 Lock Bits

Name LOCKBITOffset 0x0AReset -Property

Bit 7 6 5 4 3 2 1 0 LOCKBIT[70]

Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0

Bits 70 ndash LOCKBIT[70] Lock Bits

Value Description0xC5 The device is open

other The device is locked

7 Peripherals and Architecture

71 Peripheral Module Address MapThe address map show the base address for each peripheral For complete register description andsummary for each peripheral module refer to the respective module chapters

Table 7-1 Peripheral Module Address Map

Base Address Name Description

0x0000 VPORTA Virtual Port A

0x0004 VPORTB Virtual Port B

0x0008 VPORTC Virtual Port C

0x001C GPIO General Purpose IO registers

0x0030 CPU CPU

0x0040 RSTCTRL Reset Controller

0x0050 SLPCTRL Sleep Controller

0x0060 CLKCTRL Clock Controller

0x0080 BOD Brown-Out Detector

0x00A0 VREF Voltage Reference

0x0100 WDT Watchdog Timer

0x0110 CPUINT Interrupt Controller

0x0120 CRCSCAN Cyclic Redundancy Check Memory Scan

0x0140 RTC Real Time Counter

0x0180 EVSYS Event System

0x01C0 CCL Configurable Custom Logic

0x0200 PORTMUX Port Multiplexer

0x0400 PORTA Port A Configuration

0x0420 PORTB Port B Configuration

0x0440 PORTC Port C Configuration

0x0600 ADC0 Analog to Digital ConverterPeripheral Touch Controller

0x0670 AC0 Analog Comparator

0x0680 DAC0 Digital to Analog Converter

0x0800 USART0 Universal Synchronous Asynchronous Receiver Transmitter

0x0810 TWI0 Two Wire Interface

0x0820 SPI0 Serial Peripheral Interface

0x0A00 TCA0 TimerCounter Type A

0x0A40 TCB0 TimerCounter Type B 0

0x0A80 TCD0 TimerCounter Type D

0x0F00 SYSCFG System Configuration

0x1000 NVMCTRL Non Volatile Memory Controller

0x1100 SIGROW Signature Row

0x1280 FUSES Device specific fuses

0x1300 USERROW User Row

72 Interrupt Vector MappingEach of the 26 interrupt vectors is connected to one peripheral instance as shown in the table below Aperipheral can have one or more interrupt sources see the Interrupt section in the FunctionalDescription of the respective peripheral for more details on the available interrupt sources

When the interrupt condition occurs an Interrupt Flag (nameIF) is set in the Interrupt Flags register of theperipheral (peripheralINTFLAGS)

An interrupt is enabled or disabled by writing to the corresponding Interrupt Enable bit (nameIE) in theperipherals Interrupt Control register (peripheralINTCTRL)

An interrupt request is generated when the corresponding interrupt is enabled and the Interrupt Flag isset The interrupt request remains active until the Interrupt Flag is cleared See the peripheralsINTFLAGS register for details on how to clear Interrupt Flags

Note Interrupts must be enabled globally for interrupt requests to be generated

Table 7-2 Interrupt Vector Mapping

Vector Number Base Address Peripheral source

0 0x00 RESET

1 0x02 NMI - Non-Maskable Interruptfrom CRC

2 0x04 VLM - Voltage Level Monitor

3 0x06 PORTA - Port A

4 0x08 PORTB - Port B

5 0x0A PORTC - Port C

6 0x0C RTC - Real Time Counter

7 0x0E PIT - Periodic Interrupt Timer (inRTC peripheral)

8 0x10 TCA0 - Timer Counter Type A

13 0x1A TCB0 - Timer Counter Type B

14 0x1C TCD0 - Timer Counter Type D

16 0x20 AC0 ndash Analog Comparator

17 0x22 ADC0 ndash Analog-to-DigitalConverter

19 0x26 TWI0 - Two Wire Interface I2C

21 0x2A SPI0 - Serial Peripheral Interface

22 0x2C USART0 - UniversalAsynchronous Receiver-Transmitter

25 0x32 NVM - Non Volatile Memory

Related LinksNVMCTRL - Non Volatile Memory Controller on page 59PORT - IO Pin Controller on page 140RTC - Real Time Counter on page 312SPI - Serial Peripheral Interface on page 373USART - Universal Synchronous and Asynchronous Receiver and Transmitter on page 336TWI - Two Wire Interface on page 388CRCSCAN - Cyclic Redundancy Check Memory Scan on page 420TCA - 16-bit TimerCounter Type A on page 189TCB - 16-bit TimerCounter Type B on page 238TCD - 12-bit TimerCounter Type D on page 262AC ndash Analog Comparator on page 449ADC - Analog to Digital Converter on page 460

8 SYSCFG - System Configuration

81 OverviewThe System Configuration blocks (SYSCFG) contain various device-specific registers

82 Functional Description

821 External BreakThe External Break feature makes it possible to connect several devices through one PIN on eachdevice and control the debug start and stop (RUN and BREAK) flow from a debugger connected to oneof the parts Enabling this feature is done through writing the ENABLE bit in SYSCFGEXTBRK Note thatwriting this bit is protected and requires setting the correct CPUCCP signature before it can be writtenThe External Break feature can be described from the perspective of a master and slave point of viewmeaning that the master device initiates HALTRESTART commands to another device and a slavereceives HALTRESTART commands from another device

After the ENABLE bit in SYSCFGEXTBRK is written it is possible to send HALT and RESTARTcommands to an external device through the EXTBREAK output It is recommended that all devices thatis part of the debug chain is set up with OCD mode enabled See section on Enabling of KEY ProtectedInterfaces for details on enabling the OCD features To set up a device for slave mode operation with thepossibility to start and stop the CPU based on the External Debug inputs the must be written

Related LinksEnabling of KEY Protected Interfaces on page 517

8211 Sending HALT and RESTART commandsWhen the External Break feature is enabled through EXTBRKENABLE it is possible to HALT (BREAK)and RESTART (RUN) another device through the External Break Pin This operation works as follows

bull The user writes to the HALT bit in SYSCFGEXTBRK This bit is not protected with CCP signatureand can be written at any time This bit can be written independent of the state of the device that ismaster in this operation meaning that the master device can be in RUN mode and request theconnected device to BREAK

bull The CPU of the master device is enabled in OCD mode and hits a breakpoint or is stopped bywriting the OCD_STOP bit in UPDIASI_OCD_CTRLA

Sending the RESTART commands to an external device is done in the same manner as for the HALTcommands

bull The user writes to the RESTART bit in EXTBRK bit This bit is not protected with CCP signatureand can be written at any time

bull The CPU of the master device is in OCD Stopped mode and receives a restart command forinstance by writing the OCD_RUN bit in UPDIASI_OCD_CTRLA

8212 External BREAK ProtocolThe External BREAK output (EXTBREAK) is in the RUN state when it is pulled low If the device does notsupport internal pull-down the line can be actively driven low from the master device or have an externalpull-down resistor connected Figure 8-1 shows the External BREAK output signal level during stop andrestart requests A transition from low to high level on the EXTBREAK output signalizes that either aninternal or external debug stop condition has occurred while a high to low level transition signalizes theoccurrence of an internal or external restart condition

Figure 8-1 External BREAK output signal level on internal stop and restart request

Inte rna l Debug s top reques t

Inte rna l Debug res ta rt reques t

EXTBREAK

A stop request can be sent on the EXTBREAK output by writing to the HALT bit in SYSCFGEXTBRKThis is effectively the same as sending a BREAK command to any connected slave device from themaster Figure 8-2 gives an example of sending a HALT commandFigure 8-2 External BREAK output signal level when sending HALT command

EXTBREAK

A restart request can be sent on the EXTBREAK output by writing a 1 to the RESTART bit inSYSCFGEXTBRK This is the same as sending a RUN command to any connected slave device fromthe master Figure 8-3 shows a combined example where a HALT command is followed by a RESTARTcommandFigure 8-3 External BREAK output signal level when sending HALT followed by RESTART command

EXTBREAK

RESTART

822 Configuration Change ProtectionThis peripheral has registers that are under Configuration Change Protection (CCP) In order to write tothese a certain key must be written to the CPUCCP register first followed by a write access to theprotected bits within four CPU instructions

It is possible to try writing to these registers any time but the values are not altered

The following registers are under CCP

Table 8-1 SYSCFG - Registers under Configuration Change Protection

Register Key

SYSCFGEXTBRK IOREG

List of bitsregisters protected by CCP

bull External Break Enable (ENABLE) in External Break register (SYSCFGEXTBRK)

83 Register Summary - SYSCFG

Offset Name Bit Pos

0x01 REVID 70 REVID[70]

0x02 EXTBRK 70 RESTART HALT ENABLE

84 Register Description

841 Device Revision ID RegisterThis register is read only and give the device revision ID

Name REVIDOffset 0x01Reset [revision ID]Property

Bit 7 6 5 4 3 2 1 0 REVID[70]

Access R R R R R R R R Reset

Bits 70 ndash REVID[70] Revision IDThese bits contain the device revision 0x00 = A 0x01 = B and so on

842 External Break RegisterEnables external break

Name EXTBRKOffset 0x02Reset 0x00Property

Configuration Change Protection

Bit 7 6 5 4 3 2 1 0 RESTART HALT ENABLE

Access W W W Reset 0 0 0

Bit 2 ndash RESTART External Break Restart CommandWill send a restart command to external break pin This bit has no Configuration Change Protection

Bit 1 ndash HALT External Break Halt CommandWill send a halt command to external break pin This bit has no Configuration Change Protection

Bit 0 ndash ENABLE External Break EnableEnables external break

9 AVR CPU

91 OverviewAll Atmel AVR devices use the 8-bit AVR CPU The main function of the CPU is to execute the code andperform all calculations The CPU is able to access memories perform calculations control peripheralsand execute instructions in the program memory Interrupt handling is described in a separate section

Related LinksMemories on page 20NVMCTRL - Non Volatile Memory Controller on page 59CPUINT - CPU Interrupt Controller on page 104

92 Featuresbull 8-bit high-performance Atmel AVR RISC CPU

ndash 135 instructionsndash Hardware multiplier

bull 32x8-bit registers directly connected to the ALUbull Stack in RAMbull Stack pointer accessible in IO memory spacebull Direct addressing of up to 64KB of unified memory

ndash Entire Flash accessible with all LDST instructionsbull True 16-bit access to 16-bit IO registersbull Efficient support for 8- 16- and 32-bit arithmeticbull Configuration Change Protection for system-critical featuresbull Native OCD support

ndash 2 hardware breakpointsndash Change of flow interrupt and software breakpointsndash Runtime readout of Stack Pointer register program counter (PC) and Status registerndash Register file read- and writable in stopped mode

93 ArchitectureIn order to maximize performance and parallelism the AVR CPU uses a Harvard architecture withseparate buses for program and data Instructions in the program memory are executed with single-levelpipelining While one instruction is being executed the next instruction is pre-fetched from the programmemory This enables instructions to be executed on every clock cycle

Figure 9-1 AVR CPU Architecture

The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or between aconstant and a register Single-register operations can also be executed in the ALU After an arithmeticoperation the status register is updated to reflect information about the result of the operation

The ALU is directly connected to the fast-access register file The 32x8-bit general purpose workingregisters all have single clock cycle access time allowing single-cycle arithmetic logic unit operation

between registers or between a register and an immediate Six of the 32 registers can be used as three16-bit address pointers for program and data space addressing enabling efficient address calculations

The program memory bus is connected to Flash and the first program memory Flash address is 0x0000

The data memory space is divided into IO registers SRAM EEPROM and Flash

All IO status and control registers reside in the lowest 4KB addresses of the data memory This isreferred to as the IO memory space The lowest 64 addresses are accessed directly with single cycleINOUT instructions or as the data space locations from 0x00 to 0x3F These addresses can also beaccessed using load (LDLDSLDD) and store (STSTSSTD) instructions The lowest 32 addresses caneven be accessed with single cycle SBICBI instructions and SBISSBIC instructions The rest is theextended IO memory space ranging from 0x0040 to 0x0FFF IO registers here must be accessed asdata space locations using load and store instructions

Data addresses 0x1000 to 0x1800 are reserved for memory mapping of fuses the NVM controller andEEPROM The addresses from 0x1800 to 0x7FFF are reserved for other memories such as SRAM

The Flash is mapped in the data space from 0x8000 and above The Flash can be accessed with all loadand store instructions by using addresses above 0x8000 The LPM instruction accesses the Flash as inthe code space where the Flash starts at address 0x0000

For a summary of all AVR instructions refer to the Instruction Set Summary For details of all AVRinstructions refer to httpwwwatmelcomavr

Related LinksInstruction Set Summary on page 537NVMCTRL - Non Volatile Memory Controller on page 59Memories on page 20

94 ALU - Arithmetic Logic UnitThe Arithmetic Logic Unit supports arithmetic and logic operations between registers or between aconstant and a register Single-register operations can also be executed

The ALU operates in direct connection with all 32 general purpose registers Arithmetic operationsbetween general purpose registers or between a register and an immediate are executed in a single clockcycle and the result is stored in the register file After an arithmetic or logic operation the Status register(CPUSREG) is updated to reflect information about the result of the operation

ALU operations are divided into three main categories ndash arithmetic logical and bit functions Both 8- and16-bit arithmetic is supported and the instruction set allows for efficient implementation of 32-bitarithmetic The hardware multiplier supports signed and unsigned multiplication and fractional format

941 Hardware MultiplierThe multiplier is capable of multiplying two 8-bit numbers into a 16-bit result The hardware multipliersupports different variations of signed and unsigned integer and fractional numbers

bull Multiplication of unsigned integersbull Multiplication of signed integersbull Multiplication of a signed integer with an unsigned integerbull Multiplication of unsigned fractional numbersbull Multiplication of signed fractional numbersbull Multiplication of a signed fractional number with an unsigned one

A multiplication takes two CPU clock cycles

951 Program FlowAfter Reset the CPU starts to execute instructions from the lowest address in the Flash program memory0x0000 The program counter (PC) addresses the next instruction to be fetched

Program flow is provided by conditional and unconditional jump and call instructions capable ofaddressing the whole address space directly Most AVR instructions use a 16-bit word format while alimited number use a 32-bit format

During interrupts and subroutine calls the return address PC is stored on the stack as a word pointerThe stack is allocated in the general data SRAM and consequently the stack size is only limited by thetotal SRAM size and the usage of the SRAM After Reset the stack pointer (SP) points to the highestaddress in the internal SRAM The SP is readwrite accessible in the IO memory space enabling easyimplementation of multiple stacks or stack areas The data SRAM can easily be accessed through the fivedifferent addressing modes supported in the AVR CPU

952 Instruction Execution TimingThe AVR CPU is clocked by the CPU clock CLK_CPU No internal clock division is applied The Figurebelow shows the parallel instruction fetches and instruction executions enabled by the Harvardarchitecture and the fast-access register file concept This is the basic pipelining concept enabling up to1MIPSMHz performance with high efficiency

Figure 9-2 The Parallel Instruction Fetches and Instruction Executions

The following Figure shows the internal timing concept for the register file In a single clock cycle an ALUoperation using two register operands is executed and the result is stored back to the destinationregister

Figure 9-3 Single Cycle ALU Operation

953 Status RegisterThe Status register (CPUSREG) contains information about the result of the most recently executedarithmetic or logic instruction This information can be used for altering program flow in order to performconditional operationsNote CPUSREG is updated after all ALU operations as specified in the Instruction Set Summary

This will in many cases remove the need for using the dedicated compare instructions resulting in fasterand more compact code

CPUSREG is not automatically storedrestored when enteringreturning from an interrupt service routineMaintaining the status register between context switches must therefore be handled by user definedsoftware

CPUSREG is accessible in the IO memory space

Related LinksInstruction Set Summary on page 537

954 Stack and Stack PointerThe Stack is used for storing return addresses after interrupts and subroutine calls It can also be used forstoring temporary data The Stack Pointer (SP) always point to the top of the Stack The SP is defined bythe Stack Pointer bits (SP) in the Stack Pointer register (CPUSP) CPUSP is implemented as two 8-bitregisters that are accessible in the IO memory space

Data is pushed and popped from the Stack using the PUSH and POP instructions The Stack grows fromhigher to lower memory locations This implies that pushing data onto the Stack decreases the SP andpopping data off the Stack increases the SP The Stack Pointer is automatically set to the highest addressof the internal SRAM after Reset If the Stack is changed it must be set to point above address 0x2000and it must be defined before both any subroutine calls are executed and before interrupts are enabled

During interrupts or subroutine calls the return address is automatically pushed on the Stack as a wordpointer The return address consists of two bytes and the least significant byte is pushed on the Stack first(at the higher address) The return address is popped off the Stack when returning from interrupts usingthe RETI instruction and from subroutine calls using the RET instruction The return address is saved onthe Stack as a word pointer As example a byte pointer return address of 0x0006 is saved on the Stackas 0x0003 (shifted one bit to the right) pointing to the fourth 16-bit instruction word in the programmemory

The SP is decremented by 1 when data is pushed on the Stack with the PUSH instruction andincremented by 1 when data is popped off the Stack using the POP instruction

To prevent corruption when updating the Stack pointer from software a write to SPL will automaticallydisable interrupts for up to four instructions or until the next IO memory write

955 Register FileThe register file consists of 32x 8-bit general purpose working registers with single clock cycle accesstime The register file supports the following inputoutput schemes

bull One 8-bit output operand and one 8-bit result inputbull Two 8-bit output operands and one 8-bit result inputbull Two 8-bit output operands and one 16-bit result inputbull One 16-bit output operand and one 16-bit result input

Six of the 32 registers can be used as three 16-bit address register pointers for data space addressingenabling efficient address calculations One of these address pointers can also be used as an addresspointer for lookup tables in Flash program memory

Figure 9-4 AVR CPU General Purpose Working Registers

7 0R0R1R2

R13R14R15R16R17

R26R27R28R29R30R31

Addr0x000x010x02

0x0D0x0E0x0F0x100x11

0x1A0x1B0x1C0x1D0x1E0x1F

X-register Low ByteX-register High ByteY-register Low ByteY-register High ByteZ-register Low ByteZ-register High Byte

The register file is located in a separate address space so the registers are not accessible as datamemory

9551 The X- Y- and Z- RegistersRegisters R26R31 have added functions besides their general-purpose usage

These registers can form 16-bit address pointers for addressing data memory These three addressregisters are called the X-register Y-register and Z-register The Z-register can also be used as anaddress pointer to read from andor write to the Flash program memory signature and user rows fusesand lock bits

Figure 9-5 The X- Y- and Z-registersBit (individually)

X-register

Bit (X-register)

7 0 7 0

15 8 7 0

R27 R26

Bit (individually)

Y-register

Bit (Y-register)

7 0 7 0

15 8 7 0

R29 R28

Bit (individually)

Z-register

Bit (Z-register)

7 0 7 0

15 8 7 0

R31 R30

The lowest register address holds the least-significant byte (LSB) and the highest register address holdsthe most-significant byte (MSB) In the different addressing modes these address registers function asfixed displacement automatic increment and automatic decrement

956 Accessing 16-bit RegistersThe AVR data bus is 8 bits wide and so accessing 16-bit registers requires atomic operations Theseregisters must be byte-accessed using two read or write operations 16-bit registers are connected to the8-bit bus and a temporary register using a 16-bit bus

For a write operation the low byte of the 16-bit register must be written before the high byte The low byteis then written into the temporary register When the high byte of the 16-bit register is written thetemporary register is copied into the low byte of the 16-bit register in the same clock cycle

For a read operation the low byte of the 16-bit register must be read before the high byte When the lowbyte register is read by the CPU the high byte of the 16-bit register is copied into the temporary registerin the same clock cycle as the low byte is read When the high byte is read it is then read from thetemporary register

This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously whenreading or writing the register

Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bitregister during an atomic 16-bit readwrite operation To prevent this interrupts can be disabled whenwriting or reading 16-bit registers

The temporary registers can also be read and written directly from user software

957 CCP - Configuration Change ProtectionSystem critical IO register settings are protected from accidental modification Flash self-programming(via store to NVM controller) is protected from accidental execution This is handled globally by theconfiguration change protection (CCP) register

Changes to the protected IO registers or bits or execution of protected instructions are only possibleafter the CPU writes a signature to the CCP register The different signatures are listed in the descriptionof the CCP register (CPUCCP)

There are two modes of operation one for protected IO registers and one for the protected self-programming

Related Links

Clocks on page 240Interrupts on page 61Events on page 191Debug Operation on page 240

2251 ClocksThis peripheral uses the systems peripheral clock CLK_PER The peripheral has its own local prescaleror can be configured to run off the prescaled clock signal of the Timer Counter type A (TCA)

2255 Debug OperationWhen the CPU is halted in debug mode this peripheral will halt normal operation This peripheral can beforced to continue operation during debugging

2261 Principle of OperationDepending on the mode of operation the countertimer is cleared reloaded incremented or decrementedat each clock tick or Event input

Name Description

22622 InitializationBy default the TCB is in Periodic Interrupt mode Follow these steps to start using it

bull Write a TOP value to the CompareCapture register (TCBCC)bull Enable the counter by writing a 1 to the ENABLE bit in the Control A register (TCBCTRLA)

The counter will start counting clock ticks according to the prescaler setting in the Clock Select bitfield (CLKSEL in TCBCTRLA)

bull The counter value can be read from the Count register (TCBCNT) The peripheral will generate aninterrupt when the CNT value reaches TOP

22623 ModesThe timer can be put in eight different modes which are explained below

Periodic Interrupt ModeIn the periodic interrupt mode the counter counts to the capture value and restarts from zero Interrupt isgenerated when counter is equal to TOP If TOP is updated to a value lower than count the counter willcontinue until MAX and wrap around without generating an interrupt

Figure 22-2 Periodic Interrupt Mode

BOTTOM

Inte rrupt

TOP changed to a va lue lower than CNT

Counte r wraps a round

Related Links

CPUINT - CPU Interrupt Controller on page 104SREG on page 58Interrupts on page 144

2661 Principle of OperationThe SPI is an interface is a high-speed synchronous data transfer interface supporting full duplexcommunication

The SPI peripheral can be configured as either Master controlling all data transactions by pulling aSlaves Select (SS) signal low or Slave controlled by an SPI Master

Data are shifted from Master to Slave on the Master Output Slave Input (MOSI) line and from Slave toMaster on the Master Input Slave Output (MISO) line

MasterSlave synchronization is achieved by SS

26621 InitializationInitialize the SPI to a basic functional state by following these steps

1 Configure the SS pin in the Port peripheral2 Select SPI Master Slave operation by writing the MasterSlave Select bit (MASTER) in the Control

A register (SPICTRLA)3 In Master mode select the clock speed by writing the Prescaler bits (PRESC) and the Clock Double

bit (CLK2X) in SPICTRLA4 Optional Select the data transfer mode by writing to the MODE bits in the Control B register

(SPICTRLB)5 Optional Write the Data Order bit (DORD) in SPICTRLA6 If Hardware SS control is required in Master mode write 1 to the Slave Select Disable bit (SSD) in

SPICTRLB7 Enable the SPI by writing a 1 to the ENABLE bit in SPICTRLA

PORT - IO Pin Controller on page 140

26622 Master Mode OperationIn master mode the SPI interface has no automatic control of the SS line If the SS pin is used it must beconfigured as output and controlled by user software If the bus consists of several SPI slaves andormasters a SPI master can use general purpose IO pins to control the SS line to each of the slaves onthe bus

Writing a byte to the DATA register starts the SPI clock generator and the hardware shifts the eight bitsinto the selected slave After shifting one byte and when there is no pending data the Data RegisterEmpty Interrupt flag (DREIF) in SPIINTFLAGS is set the SPI clock generator stops and the TransferComplete interrupt flag (TXCIF) in SPIINTFLAGS is set

If there is pending data the flag DREIF is cleared the master will continue to shift out the next bytesAfter each byte is shifted out the new data is copied to the shift register and the DREIF flag is set Onlywhen a shift is completed and there is no more pending data the TXCIF flag is set An end-of-transfercan also be signaled by pulling the SS line high The last incoming byte will be kept in the shift register

If the SS pin is not used it can be disabled by writing the Slave Select Disable bit (SSD) in the Control Bregister (SPICTRLB) If not disabled and configured as input the pin must be held high to ensure masteroperation

If the SS pin is set as input and is being driven low the SPI peripheral will interpret this as another mastertrying to take control of the bus To avoid bus contention the master will take the following action

1 The master enters slave mode2 The Slave Select Interrupt Flag (SSIF) in SPIINTFLAGS is set

26623 Slave ModeIn slave mode the SPI peripheral will remain idle with the MISO line tri-stated as long as the SS pin isdriven high In this state software may update the contents of the DATA register but the data will not beshifted out by incoming clock pulses on the SCK pin until the SS pin is driven low If SS is driven low theslave will start to shift out data on the first SCK clock pulse When one byte has been completely shiftedthe SPI Interrupt flag (IF) in SPIINTFLAGS is set The slave may continue placing new data to be sentinto the SDIDATA register before reading the incoming data The last incoming byte will be kept in theregister

When SS is driven high the SPI logic is halted and the SPI slave will not receive any new data Anypartially received packet in the shift register will be lost

As the SS pin is used to signal the start and end of a transfer it is useful for achieving packetbytesynchronization and keeping the slave bit counter synchronized with the master clock generator

To avoid write collisions the SPI peripheral can be configured in buffered mode by writing a 1 to theBuffer Mode Enable bit (BUFEN) in the Control B register (SPICTRLB) Then data is copied from theTransmit Register to the Shift Register only when a receive has been completed This means that afterdata is written to the Transmit Buffer one SPI transfer must be completed before the data is copied intothe shift register

26624 Buffer ModesThere are three buffer modes

bull Unbuffered modeThe default mode is unbuffered in the transmit direction and single buffered in the receive directionThis means that bytes to be transmitted cannot be written to the SPIDATA register before the entireshift cycle is completed When receiving data a received character must be read from the

SPIDATA register before the next character has been completely shifted in Otherwise the firstbyte will be lost

bull Buffered mode with dummy transferThe SPI peripheral is single buffered in the transmit direction and double buffered in the receivedirection A byte written to the transmit register will be copied to the shift register when a fullcharacter has been received When receiving data a received character must be read from theSPIDATA register before the third character has been completely shifted in to avoid losing data

bull Buffered mode without dummy transferThe SPI peripheral is single buffered in the transmit direction and double buffered in the receivedirection A byte written to the transmit register will be copied to the shift register when the SPI isenabled and SS is high

26625 Data ModesThere are four combinations of SCK phase and polarity with respect to serial data The desiredcombination is selected by writing to the MODE bits in the Control B register (SPICTRLB)

The SPI data transfer formats are shown below Data bits are shifted out and latched in on oppositeedges of the SCK signal ensuring sufficient time for data signals to stabilize

Figure 26-2 SPI Data Transfer Modes

0x00 SPI SPI interrupt bull SSI Slave Select Trigger Interruptbull DRE Data Register Empty Interruptbull TXC Transfer Complete Interruptbull RXC Receive Complete Interrupt

Related LinksSREG on page 58CPUINT - CPU Interrupt Controller on page 104

2664 Sleep Mode OperationThe SPI will continue working in Idle sleep mode When entering any deeper sleep mode an activetransaction will be stopped

Related LinksSLPCTRL - Sleep Controller on page 92

Offset Name Bit Pos

0x00 CTRLA 70 DORD MASTER CLK2X PRESC[10] ENABLE

0x01 CTRLB 70 BUFEN BUFWR SSD MODE[10]

0x02 INTCTRL 70 RXCIE TXCIE DREIE SSIE IE

0x03 INTFLAGS 70 RXCIFIFTXCIF

WRCOLDREIF SSIF BUFOVF

0x04 DATA 70 DATA[70]

2681 Control A

Bit 7 6 5 4 3 2 1 0 DORD MASTER CLK2X PRESC[10] ENABLE

Bit 6 ndash DORD Data Order

Value Description0 The MSB of the data word is transmitted first

1 The LSB of the data word is transmitted first

Bit 5 ndash MASTER MasterSlave SelectIf SS is configured as input and driven low while this bit is 1 this bit is cleared and the IF flag inSPIINTFLAGS is set The user has to write MASTER=1 again to re-enable SPI Master mode

This behavior is controlled by the Slave Select Disable bit (SSD) in SPICTRLB

Value Description0 SPI Slave mode selected

1 SPI Master mode selected

Bit 4 ndash CLK2X Clock DoubleWhen this bit is written to 1 the SPI speed (SCK frequency after internal prescaler) is doubled in Mastermode

Value Description0 SPI speed (SCK frequency) is not doubled

1 SPI speed (SCK frequency) is doubled in Master mode

Bits 21 ndash PRESC[10] PrescalerThis bit field controls the SPI clock rate configured in master mode These bits have no effect in slavemode The relationship between SCK and the peripheral clock frequency (CLK_PER) is shown below

Note The output of the SPI prescaler can be doubled by writing the CLK2X bit to 1

Value Name Description0x0 DIV4 CLK_PER4

0x1 DIV16 CLK_PER16

0x2 DIV64 CLK_PER64

0x3 DIV128 CLK_PER128

Bit 0 ndash ENABLE SPI Enable

Value Description0 SPI is disabled

1 SPI is enabled

2682 Control B

Bit 7 6 5 4 3 2 1 0 BUFEN BUFWR SSD MODE[10]

Bit 7 ndash BUFEN Buffer Mode EnableWriting this bit to 1 enables Buffer Mode meaning two buffers in receive direction one buffer in transmitdirection and separate interrupt flags for both transmit complete and receive complete

Bit 6 ndash BUFWR Buffer Mode Wait for ReceiveWhen writing this bit to 0 the first data transferred will be a dummy sample

Value Description0 One SPI transfer must be completed before the data is copied into the shift register

1 When writing to the data register when the SPI is enabled and SS is high the first write willgo directly to the shift register

Bit 2 ndash SSD Slave Select DisableWhen this bit is set and when operating as SPI Master (MASTER=1 in SPICTRLA) SS does not disableMaster Mode

Value Description0 Enable the Slave Select line when operating as SPI Master

1 Disable the Slave Select line when operating as SPI Master

Bits 10 ndash MODE[10] ModeThese bits select the transfer mode The four combinations of SCK phase and polarity with respect to theserial data are shown in the table below These bits decide whether the first edge of a clock cycle (leadingedge) is rising or falling and whether data setup and sample occur on the leading or trailing edge Whenthe leading edge is rising the SCK signal is low when idle and when the leading edge is falling the SCKsignal is high when idle

Value Name Description0x0 0 Leading edge Rising sample

Trailing edge Falling setup

0x1 1 Leading edge Rising setupTrailing edge Falling sample

Value Name Description0x2 2 Leading edge Falling sample

Trailing edge Rising setup

0x3 3 Leading edge Falling setupTrailing edge Rising sample

Bit 7 6 5 4 3 2 1 0 RXCIE TXCIE DREIE SSIE IE

Bit 7 ndash RXCIE Receive Complete Interrupt EnableIn buffer mode this bit enables the receive complete interrupt The enabled interrupt will be triggeredwhen the RXCIF flag in the INTFLAG register is set In non-buffer mode this bit does not have any effect

Bit 6 ndash TXCIE Transfer Complete Interrupt EnableIn buffer mode this bit enables the transfer complete interrupt The enabled interrupt will be triggeredwhen the TXCIF flag in the INTFLAG register is set In non-buffer mode this bit does not have any effect

Bit 5 ndash DREIE Data Register Empty Interrupt EnableIn buffer mode this bit enables the data register empty interrupt The enabled interrupt will be triggeredwhen the DREIF flag in the INTFLAG register is set In non-buffer mode this bit does not have any effect

Bit 4 ndash SSIE Slave Select Trigger Interrupt EnableIn buffer mode this bit enables the Slave Select interrupt The enabled interrupt will be triggered when theSSIF flag in the INTFLAG register is set In non-buffer mode this bit does not have any effect

Bit 0 ndash IE Interrupt EnableThis bit enables the SPI interrupt when the SPI is not in buffer mode The enabled interrupt will betriggered when the corresponding flag is set in the INTFLAG register

Bit 7 6 5 4 3 2 1 0 RXCIFIF TXCIFWRCOL DREIF SSIF BUFOVF

Bit 7 ndash RXCIFIF Receive Complete Interrupt FlagInterrupt FlagRXCIF In buffer mode this flag is set when there is unread data in the receive buffer and cleared whenthe receive buffer is empty (ie does not contain any unread data) In non-buffer mode this bit does nothave any effect

When interrupt-driven data reception is used the receive complete interrupt routine must read thereceived data from DATA in order to clear RXCIF If not a new interrupt will occur directly after the returnfrom the current interrupt This flag can also be cleared by writing a one to its bit location

IF This flag is set when a serial transfer is complete and one byte is completely shifted inout of the DATAregister If SS is configured as input and is driven low when the SPI is in master mode this will also setthis flag IF is cleared by hardware when executing the corresponding interrupt vector Alternatively the IFflag can be cleared by first reading the SPIINTFLAGS register when IF is set and then accessing theDATA register

Bit 6 ndash TXCIFWRCOL Transfer Complete Interrupt FlagWrite Collision FlagTXCIF In buffer mode this flag is set when all the data in the transmit shift register has been shifted outand there are no new data in the transmit buffer (DATA) The flag is cleared by writing a one to its bitlocation In non-buffer mode this bit does not have any effect

WRCOL The WRCOL flag is set if the DATA register is written to during a data transfer This flag iscleared by first reading the SPIINTFLAGS register when WRCOL is set and then accessing the DATAregister

Bit 5 ndash DREIF Data Register Empty Interrupt FlagIn buffer mode this flag indicates whether the transmit buffer (DATA) is ready to receive new data Theflag is one when the transmit buffer is empty and zero when the transmit buffer contains data to betransmitted that has not yet been moved into the shift register DREIF is set after a reset to indicate thatthe transmitter is ready In non-buffer mode this bit does not have any effect

DREIF is cleared by writing DATA When interrupt-driven data transmission is used the data registerempty interrupt routine must either write new data to DATA in order to clear DREIF or disable the dataregister empty interrupt If not a new interrupt will occur directly after the return from the current interrupt

Bit 4 ndash SSIF Slave Select Trigger Interrupt FlagIn buffer mode this flag indicates that the SPI has been in master mode and the SS line has been pulledlow externally so the SPI is now working in slave mode The flag will only be set if the Slave SelectDisable bit (SSD) is not 1 The flag is cleared by writing a one to its bit location In non-buffer mode thisbit does not have any effect

Bit 0 ndash BUFOVF Buffer OverflowThis flag indicates data loss due to a receiver buffer full condition This flag is set if a buffer overflowcondition is detected A buffer overflow occurs when the receive buffer is full (two characters) and a thirdbyte has been received in the shift register If there is no transmit data the buffer overflow will not be setbefore the start of a new serial transfer This flag is valid until the receive buffer (DATA) is read Alwayswrite this bit location to zero when writing the SPIINTFLAGS register

2685 Data

Bit 7 6 5 4 3 2 1 0 DATA[70]

Bits 70 ndash DATA[70] SPI DataThe DATA register is used for sending and receiving data Writing to the register initiates the datatransmission and the byte written to the register will be shifted out on the SPI output line

Reading the register causes the first byte in the buffer FIFO to be read and the following received byteswill move forward in the FIFO

27 TWI - Two Wire Interface

271 OverviewThe Two-Wire Interface (TWI) is a bidirectional two-wire communication interface It is I2C and SystemManagement Bus (SMBus) compatible The only external hardware needed to implement the bus is onepull-up resistor on each bus line

Any device connected to the bus must act as a master or a slave The master initiates a data transactionby addressing a slave on the bus and telling whether it wants to transmit or receive data One bus canhave many slaves and one or several masters that can take control of the bus An arbitration processhandles priority if more than one master tries to transmit data at the same time Mechanisms for resolvingbus contention are inherent in the protocol

The TWI module supports master and slave functionality The master and slave functionality areseparated from each other and can be enabled and configured separately The master module supportsmulti-master bus operation and arbitration It contains the baud rate generator All 100kHz 400kHz and1MHz bus frequencies are supported Quick command and smart mode can be enabled to auto-triggeroperations and reduce software complexity

The slave module implements 7-bit address match and general address call recognition in hardware 10-bit addressing is also supported A dedicated address mask register can act as a second address matchregister or as a register for address range masking The slave continues to operate in all sleep modesincluding power-down mode This enables the slave to wake up the device from all sleep modes on TWIaddress match It is possible to disable the address matching to let this be handled in software instead

The TWI module will detect START and STOP conditions bus collisions and bus errors Arbitration losterrors collision and clock hold on the bus are also detected and indicated in separate status flagsavailable in both master and slave modes

It is possible to disable the TWI drivers in the device and enable a four-wire digital interface forconnecting to an external TWI bus driver This can be used for applications where the device operatesfrom a different VDD voltage than used by the TWI bus It is also possible to enable the bridge mode Inthis case the slave IO pins are selected from an alternative port enabling independent and simultaneousmaster and slave operation

272 Featuresbull Bidirectional two-wire communication interface

ndash Philips I2C compatiblendash System Management Bus (SMBus) compatible

bull Bus master and slave operation supportedndash Slave operationndash Single bus master operationndash Bus master in multi-master bus environmentndash Multi-master arbitration

bull Flexible slave address match functionsndash 7-bit and general call address recognition in hardwarendash 10-bit addressing supportedndash Address mask register for dual address match or address range masking

ndash Optional software address recognition for unlimited number of addressesbull Slave can operate in all sleep modes including power-downbull Slave address match can wake device from all sleep modesbull Up to 1MHz bus frequency supportbull Slew-rate limited output driversbull Input filter for bus noise and spike suppressionbull Support arbitration between startrepeated start and data bit (SMBus)bull Slave arbitration allows support for address resolve protocol (ARP) (SMBus)bull Supports SMBus Layer 1 timeoutsbull Configurable timeout valuesbull Independent timeout counters in master and slave (Bridge mode support)

273 Block DiagramFigure 27-1 TWI Block Diagram

BAUD TxDATA

RxDATA

baud rate generator SCL hold low

shift register

TxDATA

RxDATA

shift register

0 0SCL hold low

ADDRADDRMASK

Master Slave

SCL Serial clock line Digital IO

SDA Serial data line Digital IO

Table 27-1 TWI Product Dependencies

Clocks Yes CLKCTRL

Events No -

Debug Yes UPDI

2751 ClocksThis peripheral requires the system clock (CLK_PER) The relationship between CLK_PER and the TWIbus clock (SCL) is explained in the TWIMBAUD register

Related LinksCLKCTRL - Clock Controller on page 75MBAUD on page 410

Note When the CPU is halted in debug mode an DBGRUN=1 that readingwriting the DATA registerwill neither trigger a bus operation nor cause transmit and clear flags

2761 Principle of OperationThe Two-Wire Interface (TWI) uses two communication lines for data transfer It can either act as masteror slave The master initiates a data transaction by addressing a slave on the bus and telling whether itwants to transmit or receive data

The following sections explain general TWI bus concepts See Basic Operation for the TWIimplementation on this device

27611 General TWI Bus ConceptsThe TWI provides a simple bidirectional two-wire communication bus consisting of a serial clock line(SCL) and a serial data line (SDA) The two lines are open-collector lines (wired-AND) and pull-upresistors (Rp) are the only external components needed to drive the bus The pull-up resistors provide ahigh level on the lines when none of the connected devices are driving the bus

The TWI bus is a simple and efficient method of interconnecting multiple devices on a serial bus A deviceconnected to the bus can be a master or slave where the master controls the bus and all communication

Figure 27-2 illustrates the TWI bus topology

TWIDEVICE 1

TWIDEVICE 2

TWIDEVICE N

Note RS is optional

Figure 27-2 TWI Bus TopologyAn unique address is assigned to all slave devices connected to the bus and the master will use this toaddress a slave and initiate a data transaction

Several masters can be connected to the same bus called a multi-master environment An arbitrationmechanism is provided for resolving bus ownership among masters since only one master device mayown the bus at any given time

A device can contain both master and slave logic and can emulate multiple slave devices by respondingto more than one address

A master indicates the start of a transaction by issuing a START condition (S) on the bus An addresspacket with a slave address (ADDRESS) and an indication whether the master wishes to read or writedata (RW) are then sent After all data packets (DATA) are transferred the master issues a STOPcondition (P) on the bus to end the transaction The receiver must acknowledge (A) or not-acknowledge(A) each byte received

Figure 27-3 shows a TWI transaction

Figure 27-3 Basic TWI Transaction Diagram Topology for a 7-bit Address Bus

PS ADDRESS

RW ACK ACK

DATA ACKNACK

S A AARWADDRESS DATA PA DATA

Address Packet Data Packet 0

Transaction

Data Packet 1

Direction

The slave provides data on the bus

The master provides data on the bus

The master or slave can provide data on the bus

The master provides the clock signal for the transaction but a device connected to the bus is allowed tostretch the low-level period of the clock to decrease the clock speed

START and STOP ConditionsTwo unique bus conditions are used for marking the beginning (START) and end (STOP) of a transactionThe master issues a START condition (S) by indicating a high-to-low transition on the SDA line while theSCL line is kept high The master completes the transaction by issuing a STOP condition (P) indicated bya low-to-high transition on the SDA line while SCL line is kept high

Figure 27-4 START and STOP Conditions

STARTCondition

STOPCondition

Multiple START conditions can be issued during a single transaction A START condition that is notdirectly following a STOP condition is called a repeated START condition (Sr)

Bit TransferAs illustrated by Figure 27-5 a bit transferred on the SDA line must be stable for the entire high period ofthe SCL line Consequently the SDA value can only be changed during the low period of the clock This isensured in hardware by the TWI module

Figure 27-5 Data Validity

DATAValid

ChangeAllowed

Combining bit transfers results in the formation of address and data packets These packets consist ofeight data bits (one byte) with the most-significant bit transferred first plus a single-bit not-acknowledge(NACK) or acknowledge (ACK) response The addressed device signals ACK by pulling the SCL line lowduring the ninth clock cycle and signals NACK by leaving the line SCL high

Address PacketAfter the START condition a 7-bit address followed by a readwrite (RW) bit is sent This is alwaystransmitted by the master A slave recognizing its address will ACK the address by pulling the data linelow for the next SCL cycle while all other slaves should keep the TWI lines released and wait for the nextSTART and address The address RW bit and acknowledge bit combined is the address packet Onlyone address packet for each START condition is allowed also when 10-bit addressing is used

The RW bit specifies the direction of the transaction If the RW bit is low it indicates a master writetransaction and the master will transmit its data after the slave has acknowledged its address If the RWbit is high it indicates a master read transaction and the slave will transmit its data after acknowledgingits address

Data PacketAn address packet is followed by one or more data packets All data packets are nine bits long consistingof one data byte and an acknowledge bit The direction bit in the previous address packet determines thedirection in which the data are transferred

TransactionA transaction is the complete transfer from a START to a STOP condition including any repeated STARTconditions in between The TWI standard defines three fundamental transaction modes Master writemaster read and a combined transaction

Figure 27-6 illustrates the master write transaction The master initiates the transaction by issuing aSTART condition (S) followed by an address packet with the direction bit set to zero (ADDRESS+W)

Figure 27-6 Master Write Transaction

S A A AA PWADDRESS DATA DATA

Address Packet Data PacketTransaction

N data packets

Assuming the slave acknowledges the address the master can start transmitting data (DATA) and theslave will ACK or NACK (AA) each byte If no data packets are to be transmitted the master terminatesthe transaction by issuing a STOP condition (P) directly after the address packet There are no limitationsto the number of data packets that can be transferred If the slave signals a NACK to the data the mastermust assume that the slave cannot receive any more data and terminate the transaction

Figure 27-7 illustrates the master read transaction The master initiates the transaction by issuing aSTART condition followed by an address packet with the direction bit set to one (ADDRESS+R) Theaddressed slave must acknowledge the address for the master to be allowed to continue the transaction

Figure 27-7 Master Read Transaction

S R A A AADDRESS DATA DATA P

TransactionAddress Packet Data Packet

N data packets

Assuming the slave acknowledges the address the master can start receiving data from the slave Thereare no limitations to the number of data packets that can be transferred The slave transmits the datawhile the master signals ACK or NACK after each data byte The master terminates the transfer with aNACK before issuing a STOP condition

Figure 27-8 illustrates a combined transaction A combined transaction consists of several read and writetransactions separated by repeated START conditions (Sr)

Figure 27-8 Combined Transaction

S A SrAARW DATA AA PADDRESS DATA RWADDRESS

TransactionAddress Packet 1 N Data Packets M Data PacketsAddress Packet 2

Direction Direction

Clock and Clock StretchingAll devices connected to the bus are allowed to stretch the low period of the clock to slow down theoverall clock frequency or to insert wait states while processing data A device that needs to stretch theclock can do this by holdingforcing the SCL line low after it detects a low level on the line

Three types of clock stretching can be defined as shown in Figure 27-9

Figure 27-9 Clock Stretching (1)

ACKNACKbit 0bit 7 bit 6

Periodic clock stretching

Random clock stretching

Wakeup clock stretching

Note Clock stretching is not supported by all I2C slaves and masters

If a slave device is in sleep mode and a START condition is detected the clock stretching normally worksduring the wake-up period For AVR devices the clock stretching will be either directly before or after theACKNACK bit as AVR devices do not need to wake up for transactions that are not addressed to it

A slave device can slow down the bus frequency by stretching the clock periodically on a bit level Thisallows the slave to run at a lower system clock frequency However the overall performance of the buswill be reduced accordingly Both the master and slave device can randomly stretch the clock on a bytelevel basis before and after the ACKNACK bit This provides time to process incoming or prepareoutgoing data or perform other time-critical tasks

In the case where the slave is stretching the clock the master will be forced into a wait state until theslave is ready and vice versa

ArbitrationA master can start a bus transaction only if it has detected that the bus is idle As the TWI bus is a multi-master bus it is possible that two devices may initiate a transaction at the same time This results inmultiple masters owning the bus simultaneously This is solved using an arbitration scheme where themaster loses control of the bus if it is not able to transmit a high level on the SDA line The masters wholose arbitration must then wait until the bus becomes idle (ie wait for a STOP condition) beforeattempting to reacquire bus ownership Slave devices are not involved in the arbitration procedure

Figure 27-10 TWI Arbitration

DEVICE1_SDA

SDA(wired-AND)

DEVICE2_SDA

bit 7 bit 6 bit 5 bit 4

DEVICE1 Loses arbitration

Figure 27-10 shows an example where two TWI masters are contending for bus ownership Both devicesare able to issue a START condition but DEVICE1 loses arbitration when attempting to transmit a highlevel (bit 5) while DEVICE2 is transmitting a low level

Arbitration between a repeated START condition and a data bit a STOP condition and a data bit or arepeated START condition and a STOP condition are not allowed and will require special handling bysoftware

SynchronizationA clock synchronization algorithm is necessary for solving situations where more than one master istrying to control the SCL line at the same time The algorithm is based on the same principles used for theclock stretching previously described Figure 27-11shows an example where two masters are competingfor control over the bus clock The SCL line is the wired-AND result of the two masters clock outputs

Figure 27-11 Clock Synchronization

DEVICE1_SCL

SCL(wired-AND)

WaitState

DEVICE2_SCL

High PeriodCount

Low PeriodCount

A high-to-low transition on the SCL line will force the line low for all masters on the bus and they will starttiming their low clock period The timing length of the low clock period can vary among the masters Whena master (DEVICE1 in this case) has completed its low period it releases the SCL line However the SCLline will not go high until all masters have released it Consequently the SCL line will be held low by thedevice with the longest low period (DEVICE2) Devices with shorter low periods must insert a wait stateuntil the clock is released All masters start their high period when the SCL line is released by all devicesand has gone high The device which first completes its high period (DEVICE1) forces the clock line lowand the procedure is then repeated The result is that the device with the shortest clock period determinesthe high period while the low period of the clock is determined by the device with the longest clockperiod

27612 TWI Bus State LogicThe bus state logic continuously monitors the activity on the TWI bus lines when the master is enabled Itcontinues to operate in all sleep modes including power-down

The bus state logic includes START and STOP condition detectors collision detection inactive bustimeout detection and a bit counter These are used to determine the bus state Software can get thecurrent bus state by reading the bus state bits in the master status register The bus state can beunknown idle busy or owner and is determined according to the state diagram shown in Figure 27-12The values of the bus state bits according to state are shown in binary in the figure

Figure 27-12 Bus State State Diagram

P + Timeout

Write ADDRESS

IDLE(0b01)

BUSY(0b11)

UNKNOWN(0b00)

OWNER(0b10)

ArbitrationLost

Command P

WriteADDRESS(Sr)

P + Timeout

After a system reset andor TWI master enable the bus state is unknown The bus state machine can beforced to enter idle by writing to the bus state bits accordingly If no state is set by application softwarethe bus state will become idle when the first STOP condition is detected If the master inactive bustimeout is enabled the bus state will change to idle on the occurrence of a timeout After a known busstate is established only a system reset or disabling of the TWI master will set the state to unknown

When the bus is idle it is ready for a new transaction If a START condition generated externally isdetected the bus becomes busy until a STOP condition is detected The STOP condition will change thebus state to idle If the master inactive bus timeout is enabled the bus state will change from busy to idleon the occurrence of a timeout

If a START condition is generated internally while in idle state the owner state is entered If the completetransaction was performed without interference ie no collisions are detected the master will issue aSTOP condition and the bus state will change back to idle If a collision is detected the arbitration isassumed lost and the bus state becomes busy until a STOP condition is detected A repeated STARTcondition will only change the bus state if arbitration is lost during the issuing of the repeated STARTArbitration during repeated START can be lost only if the arbitration has been ongoing since the firstSTART condition This happens if two masters send the exact same ADDRESS+DATA before one of themasters issues a repeated START (Sr)

27621 Electrical CharacteristicsThe TWI module in AVR devices follows the electrical specifications and timing of I2C bus and SMBusThese specifications are not 100 compliant and so to ensure correct behavior the inactive bus timeoutperiod should be set in TWI master mode Refer to TWI Master Operation for more details

27622 InitializationTo start the TWI as Master write a 1 to the ENABLE bit in the Master Control A register (TWIMCTRLA)followed by writing the slave address to the Master Address (TWIMADDR) register The TWIMADDRregister also has a RW bit which indicates whether the Master is transmitting or receiving The MasterDATA register (TWIMDATA) is written in case master is transmitting data

To enable the TWI as Slave write a 1 to the ENABLE bit in the Slave Control A register (TWISCTRLA)The TWI peripheral will wait to receive a byte addressed to it

27623 TWI Master OperationThe TWI master is byte-oriented with an optional interrupt after each byte There are separate interruptsfor master write and master read Interrupt flags can also be used for polled operation There arededicated status flags for indicating ACKNACK received bus error arbitration lost clock hold and busstate

When an interrupt flag is set the SCL line is forced low This will give the master time to respond orhandle any data and will in most cases require software interaction Figure 27-13 shows the TWI masteroperation The diamond shaped symbols (SW) indicate where software interaction is required Clearingthe interrupt flags releases the SCL line

Figure 27-13 TWI Master Operation

IDLE S BUSYBUSY P

R DATA

ADDRESS

AADATA

Wait for IDLE

APPLICATION

BUSY M4ASW

MASTER READ INTERRUPT + HOLD

MASTER WRITE INTERRUPT + HOLD

BUSYRW

SW Driver software

Slave provides data on the bus

BUSY M4

Bus state

Mn Diagram connections

The number of interrupts generated is kept to a minimum by automatic handling of most conditions Quickcommand and smart mode can be enabled to auto-trigger operations and reduce software complexity

Transmitting Address PacketsAfter issuing a START condition the master starts performing a bus transaction when the master addressregister is written with the 7-bit slave address and direction bit If the bus is busy the TWI master will waituntil the bus becomes idle before issuing the START condition

Depending on arbitration and the RW direction bit one of four distinct cases (M1 to M4) arises followingthe address packet The different cases must be handled in software

Case M1 Arbitration Lost or Bus Error during Address PacketIf arbitration is lost during the sending of the address packet the Master Write Interrupt Flag (WIF inTWIMSTATUS) and Arbitration Lost Flag (ARBLOST in TWIMSTATUS) are both set Serial data outputto the SDA line is disabled and the SCL line is released The master is no longer allowed to perform anyoperation on the bus until the bus state has changed back to idle

A bus error will behave in the same way as an arbitration lost condition but the Bus Error Flag (BUSERRin TWIMSTATUS) is set in addition to the write interrupt and arbitration lost flags

Case M2 Address Packet Transmit Complete - Address not Acknowledged by SlaveIf no slave device responds to the address the Master Write Interrupt Flag (WIF in TWIMSTATUS) andthe Master Received Acknowledge Flag (RXACK in TWIMSTATUS) are set The clock hold is active atthis point preventing further activity on the bus

Case M3 Address Packet Transmit Complete - Direction Bit ClearedIf the master receives an ACK from the slave the Master Write Interrupt Flag (WIF in TWIMSTATUS) isset and the Master Received Acknowledge Flag (RXACK in TWI_MSTATUS) is cleared The clock hold isactive at this point preventing further activity on the bus

Case M4 Address Packet Transmit Complete - Direction Bit SetIf the master receives an ACK from the slave the master proceeds to receive the next byte of data fromthe slave When the first data byte is received the Master Read Interrupt Flag (RIF in TWIMSTATUS) isset and the Master Received Acknowledge Flag (RXACK in TWIMSTATUS) is cleared The clock hold isactive at this point preventing further activity on the bus

Transmitting Data PacketsThe slave will know when an address packet with RW direction bit set has been successfully received Itcan then start sending data by writing to the slave data register When a data packet transmission iscompleted the data interrupt flag is set If the master indicates NACK the slave must stop transmittingdata and expect a STOP or repeated START condition

Receiving Data PacketsThe slave will know when an address packet with RW direction bit cleared has been successfullyreceived After acknowledging this the slave must be ready to receive data When a data packet isreceived the data interrupt flag is set and the slave must indicate ACK or NACK After indicating a NACKthe slave must expect a STOP or repeated START condition

27624 TWI Slave OperationThe TWI slave is byte-oriented with optional interrupts after each byte There are separate slave data andaddressstop interrupts Interrupt flags can also be used for polled operation There are dedicated statusflags for indicating ACKNACK received clock hold collision bus error and readwrite direction

When an interrupt flag is set the SCL line is forced low This will give the slave time to respond or handledata and will in most cases require software interaction Figure 27-14 shows the TWI slave operationThe diamond shapes symbols (SW) indicate where software interaction is required

Figure 27-14 TWI Slave Operation

ADDRESSS2 A

DATA AA

SLAVE ADDRESS INTERRUPT SLAVE DATA INTERRUPT

SWInterrupton STOPConditionEnabled

SW Driversoftware

Sn Diagramconnections

The number of interrupts generated is kept to a minimum by automatic handling of most conditions Quickcommand can be enabled to auto-trigger operations and reduce software complexity

Promiscuous mode can be enabled to allow the slave to respond to all received addresses

Receiving Address PacketsWhen the TWI slave is properly configured it will wait for a START condition to be detected When thishappens the successive address byte will be received and checked by the address match logic and theslave will ACK a correct address and store the address in the DATA register If the received address is nota match the slave will not acknowledge and store address and will wait for a new START condition

The slave addressstop interrupt flag is set when a START condition succeeded by a valid address byte isdetected A general call address will also set the interrupt flag

A START condition immediately followed by a STOP condition is an illegal operation and the bus errorflag is set

The RW direction flag reflects the direction bit received with the address This can be read by software todetermine the type of operation currently in progress

Depending on the RW direction bit and bus condition one of four distinct cases (S1 to S4) arisesfollowing the address packet The different cases must be handled in software

Case S1 Address Packet Accepted - Direction Bit SetIf the RW direction flag is set this indicates a master read operation The SCL line is forced low by theslave stretching the bus clock If ACK is sent by the slave the slave hardware will set the data interruptflag indicating data is needed for transmit Data repeated START or STOP can be received after this IfNACK is sent by the slave the slave will wait for a new START condition and address match

Case S2 Address Packet Accepted - Direction Bit ClearedIf the RW direction flag is cleared this indicates a master write operation The SCL line is forced lowstretching the bus clock If ACK is sent by the slave the slave will wait for data to be received Datarepeated START or STOP can be received after this If NACK is sent the slave will wait for a new STARTcondition and address match

Case S3 CollisionIf the slave is not able to send a high level or NACK the collision flag is set and it will disable the dataand acknowledge output from the slave logic The clock hold is released A START or repeated STARTcondition will be accepted

Case S4 STOP Condition ReceivedWhen the STOP condition is received the slave addressstop flag will be set indicating that a STOPcondition and not an address match occurred

0x00 Slave TWI Slave interrupt bull DIF Data Interrupt Flag in SSTATUS setbull APIF Address or Stop Interrupt Flag in SSTATUS set

0x02 Master TWI Master interrupt bull RIF Read Interrupt Flag in MSTATUS setbull WIF Write Interrupt Flag in MSTATUS set

When an interrupt condition occurs the corresponding Interrupt Flag is set in the Master register(TWIMSTATUS) or Slave Status register (TWISSTATUS)When several interrupt request conditions are supported by an interrupt vector the interrupt requests areORed together into one combined interrupt request to the Interrupt Controller The user must read theperipherals INTFLAGS register to determine which of the interrupt conditions are presentRelated LinksCPUINT - CPU Interrupt Controller on page 104SREG on page 58

2765 Sleep Mode OperationThe bus state logic and Slave continue to operate in all sleep modes including Power Down sleep modeIf a Slave device is in sleep mode and a START condition is detected clock stretching is active during thewake-up period until the system clock is available Master will stop operation in all sleep modes

277 Register Summary - TWI

Offset Name Bit Pos

0x00 CTRLA 70 SDASETUP SDAHOLD[10] FMPEN

0x01 Reserved

0x03 MCTRLA 70 RIEN WIEN QCEN TIMEOUT[10] SMEN ENABLE

0x04 MCTRLB 70 FLUSH ACKACT CMD[10]

0x05 MSTATUS 70 RIF WIF CLKHOLD RXACK ARBLOST BUSERR BUSSTATE[10]

0x06 MBAUD 70 BAUD[70]

0x07 MADDR 70 ADDR[70]

0x08 MDATA 70 DATA[70]

0x09 SCTRLA 70 DIEN APIEN PIEN PMEN SMEN ENABLE

0x0A SCTRLB 70 ACKACT CMD[10]

0x0B SSTATUS 70 DIF APIF CLKHOLD RXACK COLL BUSERR DIR AP

0x0C SADDR 70 ADDR[70]

0x0D SDATA 70 DATA[70]

0x0E SADDRMASK 70 ADDRMASK[60] ADDREN

2781 Control A

Bit 7 6 5 4 3 2 1 0 SDASETUP SDAHOLD[10] FMPEN

Bit 4 ndash SDASETUP SDA Setup TimeBy default there are 4 clock cycles of setup time on SDA out signal while reading from slave part of theTWI module Writing this bit to 1 will change the setup time to 8 clocks

Value Name Description0 4CYC SDA setup time is 4 clock cycles

1 8CYC SDA setup time is 8 clock cycle

Bits 32 ndash SDAHOLD[10] SDA Hold TimeWriting these bits selects the SDA hold time

Table 27-3 SDA Hold Time

SDAHOLD[10] Nominal HoldTime

Hold Time Range acrossAll Corners (ns)

Description

0x0 OFF 0 Hold time off

0x1 50ns 36 - 131 Backward compatible setting

0x2 300ns 180 - 630 Meets SMBus specification undertypical conditions

0x3 500ns 300 - 1050 Meets SMBus specification acrossall corners

Bit 1 ndash FMPEN FM Plus EnableWriting these bits selects the 1MHz bus speed for the TWI in default configuration or for TWI Master inbridge configuration

Value Description0 Fm+ disabled

1 Fm+ enabled

2782 Debug Control

Bit 7 6 5 4 3 2 1 0 DBGRUN

Access RW Reset 0

Bit 0 ndash DBGRUN Debug Run

Value Description0 XOCD_BREAK_REQ is respected

1 XOCD_BREAK_REQ is has no effect

2783 Master Control A

Name MCTRLAOffset 0x03Reset 0x00Property

Bit 7 6 5 4 3 2 1 0 RIEN WIEN QCEN TIMEOUT[10] SMEN ENABLE

Bit 7 ndash RIEN Read Interrupt EnableWriting this bit to 1 enables interrupt on the Master Read Interrupt Flag (RIF) in the Master Statusregister (TWIMSTATUS) A TWI Master read interrupt would be generated only if this bit the RIF and theGlobal Interrupt Flag (I) in CPUSREG are all 1

Bit 6 ndash WIEN Write Interrupt EnableWriting this bit to 1 enables interrupt on the Master Write Interrupt Flag (WIF) in the Master Statusregister (TWIMSTATUS) A TWI Master write interrupt will be generated only if this bit the WIF and theGlobal Interrupt Flag (I) in CPUSREG are all 1

Bit 4 ndash QCEN Quick Command EnableWriting this bit to 1 enables Quick Command When Quick Command is enabled the correspondinginterrupt flag is set immediately after the slave acknowledges the address At this point the software caneither issue a Stop command or a repeated Start by writing either the Command bits (CMD) in the MasterControl B register (TWIMCTRLB) or the Master Address register (TWIMADDR)

Bits 32 ndash TIMEOUT[10] Inactive Bus Timeout

Value Name Description0x0 DISABLED Bus timeout disabled I2C

0x1 50US 50micros - SMBus (assume baud is set to 100kHz)

0x2 100US 100micros (assume baud is set to 100kHz)

Bit 1 ndash SMEN Smart Mode EnableWriting this bit to 1 enables the Master smart mode When smart mode is enabled acknowledge action issent immediate after reading the Master Data (TWIMDATA) register

Bit 0 ndash ENABLE Enable TWI MasterWriting this bit to 1 enables the TWI as Master

2784 Master Control B

Name MCTRLBOffset 0x04Reset 0x00Property

Bit 7 6 5 4 3 2 1 0 FLUSH ACKACT CMD[10]

Bit 3 ndash FLUSH FlushWriting a 1 to this bit generates a strobe for one clock cycle disabling and then enabling the master

Writing 0 has no effect

The purpose is to clear the internal state of master For TWI master to transmit successfully it isrecommended to write the Master Address register (TWIMADDR) first and then the Master Data register(TWIMDATA)

The peripheral will transmit invalid data if TWIMDATA is written before TWIMADDR To avoid this invalidtransmission write 1 to this bit to clear both registers

Bit 2 ndash ACKACT Acknowledge ActionThis bit defines the masterrsquos behavior under certain conditions defined by the bus protocol state andsoftware interaction The acknowledge action is performed when DATA is read or when an executecommand is written to the CMD bits

The ACKACT bit is not a flag or strobe but an ordinary readwrite accessible register bit The defaultACKACT for master read interrupt is ldquoSend ACKrdquo (0) For master write the code will know that noacknowledge should be sent since it is itself sending data

Value Description0 Send ACK

1 Send NACK

Bits 10 ndash CMD[10] CommandNote The master command bits are strobes These bits are always read as zero

Writing to these bits triggers a master operation as defined by the table below

Table 27-4 Command Settings

CMD[10] DIR Description

0x0 X NOACT

0x1 X REPSTART - Execute Acknowledge Action succeeded by repeated Start

0x2 0 RECVTRANS - Execute Acknowledge Action succeeded by a byte read operation

1 Execute Acknowledge Action (no action) succeeded by a byte send operation(1)

0x3 X STOP - Execute Acknowledge Action succeeded by issuing a STOP condition

1 For a master being a sender it will normally wait for new data written to the Master Data Register(TWIMDATA)

Note The acknowledge action bits and command bits can be written at the same time

2785 Master StatusNormal TWI operation dictates that this register is regarded purely as a read-only register Clearing any ofthe status flags is done indirectly by accessing the Master transmits address (TWIMADDR) Master Dataregister (TWIMDATA) or the Command bits (CMD) in the Master Control B register (TWIMCTRLB)

Name MSTATUSOffset 0x05Reset 0x00Property

Bit 7 6 5 4 3 2 1 0 RIF WIF CLKHOLD RXACK ARBLOST BUSERR BUSSTATE[10]

Access RW RW RW R RW RW RW RW Reset 0 0 0 0 0 0 0 0

Bit 7 ndash RIF Read Interrupt FlagThis bit is set to 1 when the master byte read operation is successfully completed ie no arbitration lostor bus error occurred during the operation The read operation is triggered by software reading DATA orwriting to ADDR registers with bit 0 set A slave device must have responded with an ACK to the addressand direction byte transmitted by the master for this flag to be set

Writing a 1 to this bit will clear the RIF However normal use of the TWI does not require the flag to becleared by this method

Clearing the RIF bit will follow the same software interaction as the CLKHOLD flag

The RIF flag can generate a master read interrupt (see description of the RIEN control bit in theTWIMCTRLA register)

Bit 6 ndash WIF Write Interrupt FlagThis bit is set when a master transmit address or byte write is completed regardless of the occurrence ofa bus error or an arbitration lost condition

Writing a 1 to this bit will clear the WIF However normal use of the TWI does not require the flag to becleared by this method

Clearing the WIF bit will follow the same software interaction as the CLKHOLD flag

The WIF flag can generate a master write interrupt (see description of the WIEN control bit in theTWIMCTRLA register)

Bit 5 ndash CLKHOLD Clock HoldIf read as 1 this bit indicates that the master is currently holding the TWI clock (SCL) low stretching theTWI clock period

Writing a 1 to this bit will clear the CLKHOLD flag However normal use of the TWI does not require theCLKHOLD flag to be cleared by this method since the flag is automatically cleared when accessingseveral other TWI registers The CLKHOLD flag can be cleared by

1 Writing a 1 to it2 Writing to the TWIMADDR register3 Writing to the TWIMDATA register4 Reading the TWIDATA register while the ACKACT control bits in TWIMCTRLB are set to either

send ACK or NACK

5 Writing a valid command to the TWIMCTRLB register

Bit 4 ndash RXACK Received AcknowledgeThis bit is read-only and contains to the most recently received acknowledge bit from slave

Bit 3 ndash ARBLOST Arbitration LostIf read as 1 this bit indicates that the master has lost arbitration while transmitting a high data or NACKbit or while issuing a start or repeated start condition (SSr) on the bus

Writing a 1 to it will clear the ARBLOST flag However normal use of the TWI does not require the flag tobe cleared by this method However as for the CLKHOLD flag clearing the ARBLOST flag is not requiredduring normal use of the TWI

Clearing the ARBLOST bit will follow the same software interaction as the CLKHOLD flag

Given the condition where the bus ownership is lost to another master the software must either abortoperation or resend the data packet Either way the next required software interaction is in both cases towrite to the TWIMADDR register A write access to the TWIMADDR register will then clear theARBLOST flag

Bit 2 ndash BUSERR Bus ErrorThe BUSERR flag indicates that an illegal bus condition has occurred An illegal bus condition is detectedif a protocol violating start (S) repeated start (Sr) or stop (P) is detected on the TWI bus lines A startcondition directly followed by a stop condition is one example of protocol violation

Writing a 1 to this bit will clear the BUSERR However normal use of the TWI does not require theBUSERR to be cleared by this method

A robust TWI driver software design will treat the bus error flag similarly to the ARBLOST flag assumingthe bus ownership is lost when the bus error flag is set As for the ARBLOST flag the next softwareoperation of writing the TWIMADDR register will consequently clear the BUSERR flag For bus error tobe detected the bus state logic must be enabled and the system frequency must be 4x the SCLfrequency

Bits 10 ndash BUSSTATE[10] Bus StateThese bits indicate the current TWI bus state as defined in the table below After a System Reset or re-enabling the TWI master bus state will be unknown The change of bus state is dependent on busactivity

Writing 0x1 to the BUSSTATE bits forces the bus state logic into its idle state However the bus statelogic cannot be forced into any other state When the master is disabled the bus-state is unknown

Value Name Description0x0 UNKNOWN Unknown bus state

0x1 IDLE Bus is idle

0x0 OWNER This USART controls the bus

0x0 BUSY The bus is busy

2786 Master Baud Rate

Name MBAUDOffset 0x06Reset 0x00Property

Bit 7 6 5 4 3 2 1 0 BAUD[70]

Bits 70 ndash BAUD[70] Baud RateThis bit field defines the relation between the system clock frequency (fCLK_PER) and the TWI bus clock(SCL) frequency following this equationTWI = CLK_PER2 sdot 5 + BAUDor rearrangedBAUD = CLK_PER2 sdot TWI minus 5The BAUD must be set to a value that results in a TWI bus clock frequency (fTWI) equal or less than100kHz400kHz dependent on the standard used by the application

This bit field should be written while the master is disabled (ENABLE bit in TWIMCTRLA is 0)

2787 Master Address

Name MADDROffset 0x07Reset 0x00Property

Bit 7 6 5 4 3 2 1 0 ADDR[70]

Bits 70 ndash ADDR[70] AddressWhen this bit field is written a START condition and slave address protocol sequence is initiateddependent on the bus state

If the bus state is unknown the Master Write Interrupt Flag (WIF) and bus error flag (BUSERR) in theMaster Status register (TWIMSTATUS) are set and the operation is terminated

If the bus is busy the master awaits further operation until the bus becomes idle When the bus is orbecomes idle the master generates a START condition on the bus copies the ADDR value into the datashift register (TWIMDATA) and performs a byte transmit operation by sending the contents of the dataregister onto the bus The master then receives the response ie the acknowledge bit from the slaveAfter completing the operation the bus clock (SCL) is forced and held low only if arbitration was not lostThe CLKHOLD bit in the Master Setup register (TWIMSETUP) is set accordingly Completing theoperation sets the WIF in the Master Status register (TWIMSTATUS)

If the bus is already owned a repeated start (Sr) sequence is performed In two ways the repeated start(Sr) sequence deviates from the start sequence Firstly since the bus is already owned by the master nowait for idle bus state is necessary Secondly if the previous transaction was a read the acknowledgeaction is sent before the repeated start bus condition is issued on the bus

The master receives one data byte from the slave before the master sets the Master Read Interrupt Flag(RIF) in the Master Status register (TWIMSTATUS) All TWI Master flags are cleared automatically whenthis bit field is written This includes bus error arbitration lost and both master interrupt flags

This register can be read at any time without interfering with ongoing bus activity since a read accessdoes not trigger the master logic to perform any bus protocol related operations

Note The master control logic uses bit 0 of the TWIMADDR register as the bus protocolrsquos readwriteflag (RW)

2788 Master DATA

Name MDATAOffset 0x08Reset 0x00Property

Bit 7 6 5 4 3 2 1 0 DATA[70]

Bits 70 ndash DATA[70] DataThe bit field gives direct access to the masters physical shift register which is used both to shift data outonto the bus (write) and to shift in data received from the bus (read)

The direct access implies that the data register cannot be accessed during byte transmissions Build-inlogic prevents any write access to this register during the shift operations Reading valid data or writingdata to be transmitted can only be successfully done when the bus clock (SCL) is held low by the masterie when the CLKHOLD bit in the Master Status register (TWIMSTATUS) is set However it is notnecessary to check the CLKHOLD bit in software before accessing this register if the software keepstrack of the present protocol state by using interrupts or observing the interrupt flags

Accessing this register assumes that the master clock hold is active auto-triggers bus operationsdependent of the state of the acknowledge action command bit (ACKACT) in TWIMSTATUS and type ofregister access (read or write)

A write access to this register will independent of ACKACT in TWIMSTATUS command the master toperform a byte transmit operation on the bus directly followed by receiving the acknowledge bit from theslave When the acknowledge bit is received the Master Write Interrupt Flag (WIF) in TWIMSTATUS isset regardless of any bus errors or arbitration If operating in a multi-master environment the interrupthandler or application software must check the Arbitration Lost Status Flag (ARBLOST) in TWIMSTATUSbefore continuing from this point If the arbitration was lost the application software must decide to eitherabort or to resend the packet by rewriting this register The entire operation is performed (ie all bits areclocked) regardless of winning or losing arbitration before the write interrupt flag is set When arbitrationis lost only 1s are transmitted for the remainder of the operation followed by a write interrupt withARBLOST flag set

Both TWI master interrupt flags are cleared automatically when this register is written However theMaster Arbitration Lost and Bus Error flags are left unchanged

Reading this register triggers a bus operation dependent on the setting of the acknowledge actioncommand bit (ACKACT) in TWIMSTATUS Normally the ACKACT bit is preset to either ACK or NACKbefore the register read operation If ACK or NACK action is selected the transmission of theacknowledge bit precedes the release of the clock hold The clock is released for one byte allowing theslave to put one byte of data on the bus The Master Read Interrupt flag RIF in TWIMSTATUS is then setif the procedure was successfully executed However if arbitration was lost when sending NACK or abus error occurred during the time of operation the Master Write Interrupt flag (WIF) is set insteadObserve that the two master interrupt flags are mutual exclusive ie both flags will not be setsimultaneously

Both TWI master interrupt flags are cleared automatically if this register is read while ACKACT is set toeither ACK or NACK However arbitration lost and bus error flags are left unchanged

2789 Slave Control A

Name SCTRLAOffset 0x09Reset 0x00Property

Bit 7 6 5 4 3 2 1 0 DIEN APIEN PIEN PMEN SMEN ENABLE

Bit 7 ndash DIEN Data Interrupt EnableWriting this bit to 1 enables interrupt on the Slave Data Interrupt Flag (DIF) in the Slave Status register(TWISSTATUS) A TWI slave data interrupt will be generated only if this bit the DIF and the GlobalInterrupt Flag (I) in CPUSREG are all 1

Bit 6 ndash APIEN Address or Stop Interrupt EnableWriting this bit to 1 enables interrupt on the Slave Address or Stop Interrupt Flag (APIF) in the SlaveStatus register (TWISSTATUS) A TWI slave address or stop interrupt will be generated only if the thisbit APIF PIEN in this register and the Global Interrupt Flag (I) in CPUSREG are all 1

Note The slave stop interrupt shares the interrupt vector with slave address interrupt The AP bitdetermines which caused the interrupt

Bit 5 ndash PIEN Stop Interrupt EnableWriting this bit to 1 enables APIF to be set when a STOP condition occurs To use this feature thesystem frequency must be 4x the SCL frequency

Bit 2 ndash PMEN Address Recognition ModeIf this bit is written to 1 the slave address match logic responds to all received addresses If set to zerothe address match logic uses the slave address register (TWISADDR) to determine which address torecognize as the slaves own address

Bit 1 ndash SMEN Smart Mode EnableWriting this bit to 1 enables the slave smart mode When smart mode is enabled issuing a commandwith CMD or readingwriting DATA resets the interrupt and operation continues If smart mode is disabledthe slave always waits for a CMD command before continuing

Bit 0 ndash ENABLE Enable TWI SlaveWriting this bit to 1 enables the TWI slave

27810 Slave Control B

Name SCTRLBOffset 0x0AReset 0x00Property

Bit 7 6 5 4 3 2 1 0 ACKACT CMD[10]

Bit 2 ndash ACKACT Acknowledge ActionThis bit defines the slaversquos behavior under certain conditions defined by the bus protocol state andsoftware interaction The table below lists the acknowledge procedure performed by the slave if action isinitiated by software The acknowledge action is performed when TWISDATA is read or written or whenan execute command is written to the CMD bits in this register

The ACKACT bit is not a flag or strobe but an ordinary readwrite accessible register bit

Value Name Description0 ACK Send ACK

1 NACK Send NACK

Bits 10 ndash CMD[10] CommandUnlike the acknowledge action bits the slave command bits are strobes These bits always read as zeroWriting to these bits trigger a slave operation as defined in the table below

0x0 - NOACT X No action

0x1 X Reserved

0x2 - COMPTRANS Used to complete a transaction

0 Execute Acknowledge Action succeeded by waiting for any START (SSr)condition

1 Wait for any START (SSr) condition

0x3 - RESPONSE Used in response to an address interrupt (APIF)

0 Execute Acknowledge Action succeeded by reception of next byte

1 Execute Acknowledge Action succeeded by slave data interrupt

Used in response to a data interrupt (DIF)

1 Execute a byte read operation followed by Acknowledge Action

Note that the acknowledge action bits and command bits can be written at the same time

27811 Slave StatusNormal TWI operation dictates that the slave status register should be regarded purely as a read-onlyregister Clearing any of the status flags will indirectly be done when accessing the slave data(TWISDATA) register or the CMD bits in the Slave Control B register (TWISCTRLB)

Name SSTATUSOffset 0x0BReset 0x00Property

Bit 7 6 5 4 3 2 1 0 DIF APIF CLKHOLD RXACK COLL BUSERR DIR AP

Bit 7 ndash DIF Data Interrupt FlagThis flag is set when a slave byte transmit or byte receive operation is successfully completed without anybus error The flag can be set with an unsuccessful transaction in case of collision detection (seedescription of the COLL status bit) Writing a 1 to its bit location will clear the DIF However normal useof the TWI does not require the DIF flag to be cleared by using this method since the flag is automaticallycleared when

1 Writing to the slave DATA register2 Reading the slave DATA register3 Writing a valid command to the CTRLB register

The DIF flag can be used to generate a slave data interrupt (see description of the DIEN control bit inTWICTRLA)

Bit 6 ndash APIF Address or Stop Interrupt FlagThis flag is set when the slave address match logic detects that a valid address has been received or by astop condition Writing a 1 to its bit location will clear the APIF However normal use of the TWI does notrequire the flag to be cleared by this method since the flag is cleared using same software interactions asdescribed for the DIF flag

The APIF flag can be used to generate a slave address or stop interrupt (see description of the AIENcontrol bit in TWICTRLA) Take special note of that the slave stop interrupt shares the interrupt vectorwith slave address interrupt

Bit 5 ndash CLKHOLD Clock HoldIf read as 1 the slave clock hold flag indicates that the slave is currently holding the TWI clock (SCL)low stretching the TWI clock period This is a read only bit that is set when an address or data interrupt isset Resetting the corresponding interrupt will indirectly reset this flag

Bit 4 ndash RXACK Received AcknowledgeThis bit is read only and contains to the most recently received acknowledge bit from the master

Bit 3 ndash COLL CollisionIf read as one the transmit collision flag indicates that the slave has not been able to transmit a high dataor NACK bit If a slave transmit collision is detected the slave will commence its operation as normalexcept no low values will be shifted out onto the SDA line (ie when the COLL flag is set it disables the

data and acknowledge output from the slave logic) DIF flag will be set at the end as a result of internalcompletion of unsuccessful transaction Similarly when collision occurs because slave is not been able totransmit NACK bit it means address match already happened and APIF flag is set as a result APIFDIFflags can only generate interrupt whose handlers can be used to check for the collision Writing a 1 to itsbit location will clear the COLL flag However the flag is automatically cleared if any START condition(SSr) is detected

This flag is intended for systems where address resolution protocol (ARP) is employed However adetected collision in non-ARP situations indicates that there has been a protocol violation and should betreated as a bus error

Bit 2 ndash BUSERR Bus ErrorThe BUSERR flag indicates that an illegal bus condition has occurred An illegal bus condition is detectedif a protocol violating start (S) repeated start (Sr) or stop (P) is detected on the TWI bus lines A startcondition directly followed by a stop condition is one example of protocol violation Writing a one to its bitlocation will clear the BUSERR flag However normal use of the TWI does not require the BUSERR to becleared by this method A robust TWI driver software design will assume that the entire packet of datahas been corrupted and restart by waiting for a new START condition (S) For bus errors to be detectedthe master must be enabled (ENABLE bit in TWIMCTRLA is 1) and the system clock frequency mustbe at least four times the SCL frequency

Bit 1 ndash DIR ReadWrite DirectionThis bit is read only and indicates the current bus direction state The DIR bit reflects the direction bitvalue from the last address packet received from a master TWI device If this bit is read as 1 a masterread operation is in progress Consequently a zero indicates that a master write operation is in progress

Bit 0 ndash AP Address or StopWhen the TWI slave address or stop interrupt flag (APIF) is set this bit determines whether the interruptis due to address detection or a stop condition

Value Name Description0 STOP A stop condition generated the interrupt on APIF

1 ADR Address detection generated the interrupt on APIF

27812 Slave Address

Name SADDROffset 0x0CReset 0x00Property

Bit 7 6 5 4 3 2 1 0 ADDR[70]

Bits 70 ndash ADDR[70] AddressThe slave address register in combination with the slave address mask register (TWISADDRMASK) isused by the slave address match logic to determine if a master TWI device has addressed the TWI slaveThe slave address interrupt flag (APIF) is set to one if the received address is recognized The slaveaddress match logic supports recognition of 7- and 10-bits addresses and general call address

When using 7-bit or 10-bit address recognition mode the upper 7-bits of the address register (ADDR[71])represents the slave address and the least significant bit (ADDR[0]) is used for general call addressrecognition Setting the ADDR[0] bit in this case enables the general call address recognition logic TheTWI slave address match logic only support recognition of the first byte of a 10-bit address ie by settingADDRA[71] = ldquo0b11110aardquo where ldquoaardquo represents bit 9 and 8 or the slave address The second 10-bitaddress byte must be handled by software

27813 Slave Data

Name SDATAOffset 0x0DReset 0x00Property

Bit 7 6 5 4 3 2 1 0 DATA[70]

Bits 70 ndash DATA[70] DataThe slave data register IO location (DATA) provides direct access to the slaves physical shift registerwhich is used both to shift data out onto the bus (transmit) and to shift in data received from the bus(receive) The direct access implies that the data register cannot be accessed during byte transmissionsBuild-in logic prevents any write accesses to the data register during the shift operations Reading validdata or writing data to be transmitted can only be successfully done when the bus clock (SCL) is held lowby the slave ie when the slave CLKHOLD bit is set However it is not necessary to check theCLKHOLD bit in software before accessing the slave DATA register if the software keeps track of thepresent protocol state by using interrupts or observing the interrupt flags Accessing the slave DATAregister assumed that clock hold is active auto-trigger bus operations dependent of the state of the slaveacknowledge action command bits (ACKACT) and type of register access (read or write)

27814 Slave Address Mask

Name SADDRMASKOffset 0x0EReset 0x00Property

Bit 7 6 5 4 3 2 1 0 ADDRMASK[60] ADDREN

Bits 71 ndash ADDRMASK[60] Address MaskThe ADDRMASK register acts as a second address match register or an address mask registerdepending on the ADDREN setting

If ADDREN is written to 0 ADDRMASK can be loaded with a 7-bit Slave Address mask Each of the bitsin ADDRMASK register can mask (disable) the corresponding address bits in the TWI slave AddressRegister (ADDR) If the mask bit is written to 1 then the address match logic ignores the comparebetween the incoming address bit and the corresponding bit in slave ADDR register In other wordsmasked bits will always match

If ADDREN is written to 1 the slave ADDRMASK can be loaded with a second slave address in additionto the ADDR register In this mode the slave will match on 2 unique addresses one in ADDR and theother in ADDRMASK

Bit 0 ndash ADDREN Address Mask EnableIf this bit is written to 1 the slave address match logic responds to the 2 unique addresses in slaveADDR and ADDRMASK

If this bit is 0 the ADDRMASK register acts as a mask to the slave ADDR register

28 CRCSCAN - Cyclic Redundancy Check Memory Scan

281 OverviewA Cyclic Redundancy Check (CRC) takes a data stream of bytes as input and generates a checksumThe CRC peripheral can be used to detect errors in program memory

Typically an n-bit CRC applied to a data block of arbitrary length will detect any single error burst notlonger than n bits (ie any single alteration that spans no more than n bits of the data) and will detect afraction 1-2-n of all longer error bursts

The CRC-generator supports CRC-16-CCITT

Polynomial

bull CRC-16-CCITT x16 + x12 + x5 + 1

The CRC reads in byte by byte of the content of the section(s) it is set up to check starting with byte 0and generates a new checksum per byte The byte is sent through an implementation corresponding to Figure 28-1 starting with the most significant bit If the last two bytes in the section contain the correct 16-bit checksum the CRC will pass See Checksum for how to place the checksum The initial value of thechecksum register is 0xFFFF

Figure 28-1 CRC Implementation Description

Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D

x15 x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0

282 Featuresbull CRC-16 (CRC-CCITT)bull Can check full Flash application code andor boot sectionbull Singlecontinuous background or priority check selectablebull Selectable NMI trigger on failurebull User configurable check during startupbull Paused in all CPU sleep modes

283 Block DiagramFigure 28-2 Cyclic Redundancy Check Block Diagram

CRC-16Memory

CHECKSUMSTATUS

CRC OK

Mode SourceEnable Reset

Non-Maskable

Interrupt

(Boot App Flash)

Table 28-1 CRCSCAN Product Dependencies

Clocks Yes CLKCTRL

Events No -

Debug Yes UPDI

2845 Debug OperationWhenever the debugger accesses the device for instance reading or writing a peripheral or memorylocation the CRCSCAN peripheral will be disabled

If the CRCSCAN is busy when the debugger accesses the device the CRCSCAN will restart the ongoingoperation when the debugger accesses an internal register or when the debugger disconnects

The BUSY bit in the Status register (CRCSCANSTATUS) will read 1 if the CRCSCAN was busy whenthe debugger caused it to disable but it will not actively check any section as long as the debugger keepsit disabled There are synchronized CRC status bits in the debuggers internal register space which canbe read by the debugger without disabling the CRCSCAN Reading the debuggers internal CRC statusbits will make sure that the CRCSCAN is enabled

It is possible to write the CRCSCANSTATUS register directly from the debuggerbull BUSY bit in CRCSCANSTATUS

ndash Writing the BUSY bit to 0 will stop the ongoing CRC operation (so that the CRCSCAN doesnot restart its operation when the debugger allows it)

ndash Writing the BUSY bit to 1 will make the CRC start a single check with the settings in theControl B register (CRCSCANCTRLB) but not until the debugger allows it

As long as the BUSY bit in CRCSCANSTATUS is 1 CRCSCANCRCTRLB and the Non-Maskable Interrupt Enable bit (NMIEN) in the Control A register (CRCSCANCTRLA) cannot bealtered

bull OK bit in CRCSCANSTATUSndash Writing the OK bit to 0 can trigger a non-maskable interrupt (NMI) if the NMIEN bit in

CRCSCANCTRLA is 1 If an NMI has been triggered no writes to the CRCSCAN areallowed

ndash Writing the OK bit to 1 will make the OK bit read as 1 when the BUSY bit inCRCSCANSTATUS is 0

Writes to CRCSCANCTRLA and CRCSCANCTRLB from the debugger are treated in the same way aswrites from the CPU

Related LinksUPDI - Unified Program and Debug Interface on page 502CTRLA on page 426CTRLB on page 427

2851 Principle of OperationThe CRCSCAN peripheral takes data input from the NVM (either entire Flash only Boot section or bothapplication code and Boot section) and generates a checksum based on the data The last location in thesection to check has to contain the correct pre-calculated 16-bit checksum for comparison If thechecksum calculated by the CRCSCAN and the pre-calculated checksums match a status bit in theCRCSCAN is set If they do not match the status register will indicate that it failed The user can chooseto let the CRCSCAN generate an NMI if the checksums do not match

2852 Basic OperationThe CRC can run in these modes

bull Continuous mode in the background the CRC restarts checking from the beginning of the selectedsection The CPU can continue executing code and the CRC fetches data when it can

bull Single mode in the background A single CRC is executed The CPU can continue executing codeand the CRC fetches data when it can

bull Priority mode the CRC peripheral has priority access to the Flash and will stall the CPU untilcompleted

28521 InitializationTo enable a CRC in application (or via the debugger)

1 Write the MODE and Source (SRC) bit fields of the Control B register (CRCSCANCTRLB) to selectthe desired mode and source settings

2 Enable the CRCSCAN by writing a 1 to the ENABLE bit in the Control A register(CRCSCANCTRLA)

The CRCSCAN can be enabled during startup to ensure the Flash is OK before letting the CPU executecode If the CRCSCAN fails during startup the CPU is not allowed to start The full source settings areavailable during startup See the Fuse description for more information

If the CRCSCAN was enabled during startup the CRC Control A and B registers will reflect this afterstartup

bull The ENABLE bit in CRCSCANCTRLA will be 1bull The MODE bit field in CRCSCANCTRLB will be BACKGROUNDbull The SRC bit field in CRCSCANCTRLB will reflect the checked section(s)

28522 ChecksumThe pre-calculated checksum must be present in the last location of the section to be checked If theBOOT section should be checked the 16-bit checksum must be saved in the last two bytes of the BOOTsection and similarly for APPLICATION and entire Flash Table 28-2 shows explicitly how the checksumshould be stored for the different sections Also see CTRLB for how to configure which section to checkand the device fuse description for how to configure the BOOTEND and APPEND fuses

Table 28-2 How to place the pre-calculated 16-bit checksum in Flash

Section to Check CHECKSUM[158] CHECKSUM[70]

BOOT FUSE_BOOTEND256-2 FUSE_BOOTEND256-1

BOOT and APPLICATION FUSE_APPEND256-2 FUSE_APPEND256-1

Full Flash FLASHEND-1 FLASHEND

0x00 NMI Non-Maskable Interrupt Generated on CRC failure

When the interrupt condition occurs the OK flag in the Status register (CRCSCANSTATUS) is cleared to0

An interrupt is enabled by writing a 1 to the respective Enable bit (NMIEN) in the Control A register(CRCSCANCTRLA) but can only be disabled with a system Reset An NMI is generated when the OK

flag in CRCSCANSTATUS is cleared and the NMIEN bit is 1 The NMI request remains active until asystem Reset and can not be disabled

Note A non-maskable interrupt can be triggered even if interrupts are not globally enabled

2854 Sleep Mode OperationIn all CPU sleep modes the CRCSCAN peripheral is halted and will resume operation when the CPUwakes up

It is possible to enter sleep mode after setting up the CRCSCAN to start a PRIORITY check (see CTRLBfor more information) but before the actual check is started If the CPU is able enter sleep mode beforethe check starts and a Priority check was configured the check will start and complete (halting the CPU)immediately after waking up and before entering any interrupt handler

Offset Name Bit Pos

0x00 CTRLA 70 RESET NMIEN ENABLE

0x01 CTRLB 70 MODE[10] SRC[10]

0x02 STATUS 70 OK BUSY

2871 Control AIf an NMI has been triggered this register is not writable

Bit 7 6 5 4 3 2 1 0 RESET NMIEN ENABLE

Bit 7 ndash RESET Reset CRCSCANWriting this bit to 1 resets the CRCSCAN peripheral The CRCSCAN Control registers and Statusregister (CTRLA CTRLB STATUS) will be cleared one clock cycle after the RESET bit was written to 1

If NMIEN is 0 this bit is writable when the CRCSCAN is busy (BUSY bit in CRCSCANSTATUS is 1)and will take effect immediately

If NMIEN is 1 this bit is only writable when the CRCSCAN is not busy (BUSY bit in CRCSCANSTATUSis 0)

The RESET bit is a strobe bit

Bit 1 ndash NMIEN Enable NMI TriggerWhen this bit is written to 1 any CRC failure will trigger an NMI

This can only be cleared by a system Reset - it is not cleared by a write to the RESET bit

This bit can only be written to 1 when the CRCSCAN is not busy (BUSY bit in CRCSCANSTATUS is 0)

Bit 0 ndash ENABLE Enable CRCSCANWriting this bit to 1 enables the CRCSCAN peripheral with the current settings It will stay 1 even after aCRC check has completed but writing it to 1 again will start a new check

Writing the bit to 0 will disable the CRCSCAN after the ongoing check is completed (after reaching theend of the section it is set up to check) This is the preferred way to stop a continuous background checkA failure in the ongoing check will still be detected and can cause an NMI if the NMIEN bit is 1

The CRCSCAN can be enabled during startup to verify Flash sections before letting the CPU start (seedevice datasheet fuse description) If the CRCSCAN is enabled during startup the ENABLE bit will readas 1 after startup

To see whether the CRCSCAN peripheral is busy with an ongoing check poll the Busy bit (BUSY) in theStatus register (CRCSCANSTATUS)

2872 Control BThe CTRLB register contains the mode and source settings for the CRC It is not writable when the CRCis busy or when an NMI has been triggered

Bit 7 6 5 4 3 2 1 0 MODE[10] SRC[10]

Bits 54 ndash MODE[10] CRC Flash Access ModeThe MODE bit field selects the priority of the CRC module in the system when accessing Flash either inthe background or completely stalling the CPU until the CRC is completed It is also possible to select theCONTINUOUS mode which will make the CRC module restart at the beginning of the selected sectionafter finishing a section The CONTINUOUS mode will stop if a failure occurs To otherwise stop aCONTINUOUS mode write the ENABLE or RESET bit in the CRCSCANCTRLA registerThe CRC can be enabled during startup to verify Flash sections before letting the CPU start (see devicedatasheet fuse description) If the CRC is enabled during startup the MODE bit field will read out asBACKGROUND after startup

Table 28-4 Modes of CRC Flash Access

MODE[10] Group Configuration Description

0x0 PRIORITY The CRC module runs a single check with priority to Flash TheCPU is halted until the CRC completes

0x1 Reserved This mode is reserved and should not be selected

0x2 BACKGROUND The CRC module runs a single check with lowest priority to Flash

0x3 CONTINUOUS The CRC module runs continuous checks in the background Aftercompleting a successful check it restarts

Bits 10 ndash SRC[10] CRC SourceThe SRC bit field selects which section of the Flash the CRC module should check To set up sectionsizes please refer to the fuse descriptionThe CRC can be enabled during startup to verify Flash sections before letting the CPU start (see devicedatasheet fuse description) If the CRC is enabled during startup the SRC bit field will read out asFLASH APPLICATION or BOOT after startup (depending on the configuration)

Table 28-5 CRC Sources

SRC[10] Group Configuration Description

0x0 FLASH The CRC is performed on the entire Flash (boot application codeand application data sections)

0x1 APPLICATION The CRC is performed on the boot and application code sections ofFlash

0x2 BOOT The CRC is performed on the boot section of Flash

0x3 Reserved This source configuration is reserved and should not be selected

2873 StatusThe status register contains the busy and OK information It is not writable only readable

Bit 7 6 5 4 3 2 1 0 OK BUSY

Access R R Reset 1 0

Bit 1 ndash OK CRC OKWhen this bit is read as 1 the previous CRC completed successfully The bit is set to 1 from Reset butis cleared to 0 when enabling As long as the CRC module is busy it will be read 0 When runningcontinuously the CRC status must be assumed OK until it fails or is stopped by the user

Bit 0 ndash BUSY CRC BusyWhen this bit is read as 1 the CRC module is busy As long as the module is busy the access to thecontrol registers are limited See CTRLA and CTRLB for more information

29 CCL ndash Configurable Custom Logic

291 OverviewThe Configurable Custom Logic (CCL) is a programmable logic peripheral which can be connected to thedevice pins to events or to other internal peripherals This allows the user to eliminate logic gates forsimple glue logic functions on the PCB

Each Lookup Table (LUT) consists of three inputs a truth table and a filteredge detector Each LUT cangenerate an output as a user programmable logic expression with three inputs Inputs can be individuallymasked

The output can be generated from the inputs combinatorially and can be filtered to remove spikes Anoptional Sequential module can be enabled The inputs to the Sequential module are individuallycontrolled by two independent adjacent LUT (LUT0LUT1) outputs enabling complex waveformgeneration

292 Featuresbull Glue logic for general purpose PCB designbull Up to two Programmable LookUp Tables LUT[10]bull Combinatorial Logic Functions Any logic expression which is a function of up to three inputsbull Sequential Logic Functions

Gated D Flip-Flop JK Flip-Flop gated D Latch RS Latchbull Flexible Lookup Table Inputs Selection

ndash IOsndash Eventsndash Subsequent LUT Outputndash Internal Peripherals

bull Analog Comparatorbull Timersbull Power Stage Controllerbull USARTbull SPI

bull Clocked by system clock or other peripheralsbull Output can be connected to IO pins or Event Systembull Optional synchronizer filter or edge detector available on each LUT output

293 Block DiagramFigure 29-1 Configurable Custom Logic

InternalEvents

IOPeripherals

clkCCL

FilterSynch

Edge Detector

SequentialIN[2]

InternalEvents

IOPeripherals

clkCCL

FilterSynch

Edge Detector

ENABLE

CLKSRC

FILTSEL EDGEDET

CLKSRC

ENABLE

FILTSEL

EDGEDET

SEQSEL

CLK_MUX_OUT

Pin Name Type Description

LUTn-OUT Digital output Output from lookup table

LUTn-IN[20] Digital input Input to lookup table

Refer to IO Multiplexing and Considerations for details on the pin mapping for this peripheral One signalcan be mapped on several pins

Table 29-1 CCL Product Dependencies

Clocks Yes CLKCTRL

Events No EVSYS

Debug Yes UPDI

2951 ClocksBy default the CCL is using the peripheral clock of the device (CLK_PER)

Alternatively the CCL can be clocked by a peripheral input that is available on LUT n input line 2(LUTn_IN[2]) This is configured by writing a 1 to the Clock Source Selection bit (CLKSRC) in the LUTnControl A register (CCLLUTnCTRLA) The sequential block is clocked by the same clock as that of itseven LUT in the LUT pair (SEQnclk = LUT2nclk) It is advised to disable the peripheral by writing a 0 tothe Enable bit (ENABLE) in the Control A register (CCLCTRLA) before configuring the CLKSRC bit inCCLLUTnCTRLA

Alternatively the input line 2 (IN[2]) of a LUT can be used to clock the LUT and the correspondingSequential block This is enabled by writing a 1 to the Clock Source Selection bit (CLKSRC) in the LUTnControl A register (CCLLUTnCTRLA)

Note The CCL must be disabled before changing the LUT clock source write a 0 to the Enable bit(ENABLE) in Control A register (CCLCTRLA)

2952 IO LinesUsing the CCL IO lines requires the IO pins to be configured Refer to PORT - IO Pin Controller fordetails

2954 EventsThe events are connected to the Event System Refer to EVSYS ndash Event System for details on how toconfigure the Event System

2955 Debug OperationWhen the CPU is halted in debug mode the CCL continues normal operation If the CCL is configured in away that requires it to be periodically serviced by the CPU improper operation or data loss may resultduring debugging

2961 Principle of OperationConfigurable Custom Logic (CCL) is a programmable logic block that can use the device port pinsinternal peripherals and the internal Event System as both input and output channels The CCL canserve as glue logic between the device and external devices The CCL can eliminate the need forexternal logic component and can also help the designer overcome challenging real-time constrains bycombining core independent peripherals in clever ways to handle the most time critical parts of theapplication independent of the CPU

29621 InitializationThe following bits are enable-protected meaning that they can only be written when the correspondingeven LUT is disabled (ENABLE=0 in CCLLUTCTRL0A)

bull Sequential Selection (SEQSEL) in Sequential Control 0 register (CCLSEQCTRL0)

The following registers are enable-protected meaning that they can only be written when thecorresponding LUT is disabled (ENABLE=0 in CCLLUTCTRL0A)

bull LUT Control x register except ENABLE bit (CCLLUTCTRLxn)

Enable-protected bits in the CCLLUTCTRLxn registers can be written at the same time as ENABLE inCCLLUTCTRLxA is written to 1 but not at the same time as ENABLE is written to 0

Enable-protection is denoted by the Enable-Protected property in the register description

29622 Enabling Disabling and ResettingThe CCL is enabled by writing a 1 to the ENABLE bit in the Control register (CCLCTRLA) The CCL isdisabled by writing a 0 to that ENABLE bit

Each LUT is enabled by writing a 1 to the LUT Enable bit (ENABLE) in the LUT Control x A register(CCLLUTCTRLxA) Each LUT is disabled by writing a 0 to the ENABLE bit in CCLLUTCTRLxA

29623 Lookup Table LogicThe lookup table in each LUT unit can generate a combinational logic output as a function of up to threeinputs IN[20] Unused inputs can be masked (tied low) The truth table for the combinational logicexpression is defined by the bits in the CCLTRUTHn registers Each combination of the input bits(IN[20]) corresponds to one bit in the TRUTHn register as shown in the table

Table 29-2 Truth Table of LUT

IN[2] IN[1] IN[0] OUT

0 0 0 TRUTH[0]

0 0 1 TRUTH[1]

0 1 0 TRUTH[2]

0 1 1 TRUTH[3]

1 0 0 TRUTH[4]

1 0 1 TRUTH[5]

1 1 0 TRUTH[6]

1 1 1 TRUTH[7]

29624 Truth Table Inputs Selection

Input OverviewThe inputs can be individually

bull Maskedbull Driven by peripherals

ndash Analog comparator output (AC)ndash TimerCounters waveform outputs (TC)ndash Power Stage Controller outputs

bull Driven by internal events from Event Systembull Driven by other CCL sub-modules

The Input Selection for each input y of LUT x is configured by writing the Input y Source Selection bit inthe LUT x Control n=[BC] registers

bull INSEL0 in CCLLUTCTRLxBbull INSEL1 in CCLLUTCTRLxBbull INSEL2 in CCLLUTCTRLxC

Internal Feedback Inputs (FEEDBACK)When selected (INSELy=FEEDBACK in CCLLUTCTRLxn) the Sequential (SEQ) output is used as inputfor the corresponding LUT

The output from an internal sequential module can be used as input source for the LUT see figure belowfor an example for LUT0 and LUT1 The sequential selection for each LUT follows the formulaIN 2N = SEQ IN 2N+1 = SEQ With N representing the sequencer number and i=01 representing the LUT input index

For details refer to Sequential Logic

Figure 29-2 Feedback Input Selection

Linked LUT (LINK)When selecting the LINK input option the next LUTs direct output is used as the LUT input In generalLUT[n+1] is linked to the input of LUT[n] As example LUT1 is the input for LUT0

Figure 29-3 Linked LUT Input Selection

CTRL(ENABLE)

LUT0 SEQ 0

Internal Events Inputs Selection (EVENT)Asynchronous events from the Event System can be used as input to the LUT Two event input lines(EVENT0 and EVENT1) are available and can be selected as LUT input Before selecting the EVENTinput option by writing to the LUT CONTROL A or B register (CCLLUTnCTRLB or LUTnCTRLC) theEvent System must be configured

IO Pin Inputs (IO)When selecting the IO option the LUT input will be connected to its corresponding IO pin Refer to the IOMultiplexing section for more details about where the LUTnINn are located

Figure 29-4 IO Pin Input Selection

PeripheralsThe different peripherals on the three input lines of each LUT are selected by writing to the respectiveLUT n Input x bit fields in the LUT n Control B and C registers

bull INSEL0 in CCLLUTCTRLxB

bull INSEL1 in CCLLUTCTRLxBbull INSEL2 in CCLLUTCTRLxC

29625 FilterBy default the LUT output is a combinational function of the LUT inputs This may cause some shortglitches when the inputs change value These glitches can be removed by clocking through filters ifdemanded by application needs

The Filter Selection bits (FILTSEL) in the LUT Control registers (CCLLUTnCTRLA) define the digital filteroptions When a filter is enabled the output will be delayed by two to five CLK cycles (peripheral clock oralternative clock) One clock cycle after the corresponding LUT is disabled all internal filter logic iscleared

Note Events used as LUT input will also be filtered if the filter is enabled

Figure 29-5 Filter

FILTSEL

CLK_MUX_OUT

29626 Edge DetectorThe edge detector can be used to generate a pulse when detecting a rising edge on its input To detect afalling edge the TRUTH table should be programmed to provide inverted output

The edge detector is enabled by writing 1 to the Edge Selection bit (EDGEDET) in the LUT n Control Aregister (CCLLUTnCTRLA) In order to avoid unpredictable behavior a valid filter option must be enabledas well

Edge detection is disabled by writing a 0 to EDGEDET in CCLLUTnCTRLA After disabling a LUT thecorresponding internal Edge Detector logic is cleared one clock cycle later

Figure 29-6 Edge Detector

CLK_MUX_OUT

29627 Sequential LogicEach LUT pair can be connected to an internal Sequential block A Sequential block can function aseither D flip-flop JK flip-flop gated D-latch or RS-latch The function is selected by writing the SequentialSelection bits (SEQSEL) in Sequential Control register (CCLSEQCTRLn)

The Sequential block receives its input from the either LUT filter or edge detector depending on theconfiguration

The Sequential block is clocked by the same clock as the corresponding LUT which is either theperipheral clock or input line 2 (IN[2]) This is configured by the Clock Source bit (CLKSRC) in the LUT nControl A register (CCLLUTnCTRLA)

When the even LUT (LUT0) is disabled the latch is asynchronously cleared during which the flip-flopreset signal (R) is kept enabled for one clock cycle In all other cases the flip-flop output (OUT) isrefreshed on rising edge of the clock as shown in the respective Characteristics tables

Gated D Flip-Flop (DFF)The D-input is driven by the even LUT output (LUT0) and the G-input is driven by the odd LUT output(LUT1)

Figure 29-7 D Flip-Flop

CLK_MUX_OUT

Table 29-3 DFF Characteristics

R G D OUT

1 X X Clear

0 1 1 Set

0 Clear

0 X Hold state (no change)

JK Flip-Flop (JK)The J-input is driven by the even LUT output (LUT0) and the K-input is driven by the odd LUT output(LUT1)

Figure 29-8 JK Flip-Flop

CLK_MUX_OUT

Table 29-4 JK Characteristics

R J K OUT

1 X X Clear

0 0 0 Hold state (no change)

0 0 1 Clear

0 1 0 Set

0 1 1 Toggle

Gated D-Latch (DLATCH)The D-input is driven by the even LUT output (LUT0) and the G-input is driven by the odd LUT output(LUT1)

Figure 29-9 D-Latch

LUT(2x+1)

Table 29-5 D-Latch Characteristics

G D OUT

1 0 Clear

1 1 Set

RS Latch (RS)The S-input is driven by the even LUT output (LUT0) and the R-input is driven by the odd LUT output(LUT1)

Figure 29-10 RS-LatchRS-latch

LUT(2x+1)

Table 29-6 RS-latch Characteristics

S R OUT

0 0 Hold state (no change)

0 1 Clear

1 0 Set

1 1 Forbidden state

29628 Clock Source SettingsThe Filter Edge Detector and Sequential logic are by default clocked by the system clock (CLK_PER) Itis also possible to use the LUT input 2 (IN[2]) to clock these blocks (CLK_MUX_OUT in figure Figure29-11) This is configured by writing the Clock Source bit (CLKSRC) in the LUT Control A register(CCLLUTnCTRLA) to 1

Figure 29-11 Clock Source Settings

CLK_CCL

Edge Detector

Filter

Sequential logic

CLK_MUX_OUT

CLKSRC

Edge Detector

Filter

CLK_MUX_OUT

CLKSRC

LUT1When the Clock Source bit (CLKSRC) is 1 IN[2] is used to clock the corresponding Filter and EdgeDetector (CLK_MUX_OUT) The Sequential logic is clocked by CLK_MUX_OUT of the even LUT in thepair When CLKSRC bit is 1 IN[2] is treated as MASKed (low) in the TRUTH table

The CCL peripheral must be disabled while changing the clock source to avoid undetermined outputsfrom the peripheral

2963 EventsThe CCL can generate the following output events

bull LUTnOUT Lookup Table Output Value

The CCL can take the following actions on an input event

bull INx The event is used as input for the TRUTH table

2964 Sleep Mode OperationWriting the Run In Standby bit (RUNSTDBY) in the Control A register (CCLCTRLA) to 1 will allow thesystem clock to be enabled in Standby sleep mode

If RUNSTDBY is 0 the system clock will be disabled in Standby sleep mode If the Filter Edge Detectoror Sequential logic are enabled the LUT output will be forced to zero in Standby sleep mode In Idlesleep mode the TRUTH table decoder will continue operation and the LUT output will be refreshedaccordingly regardless of the RUNSTDBY bit

If the Clock Source bit (CLKSRC) in the LUT n Control A register (CCLLUTnCTRLA) is written to 1 theLUT input 2 (IN[2]) will always clock the Filter Edge Detector and Sequential block The availability of theIN[2] clock in sleep modes will depend on the sleep settings of the peripheral employed

297 Register Summary - CCL

Offset Name Bit Pos

0x00 CTRLA 70 RUNSTDBY ENABLE

0x01 SEQCTRL0 70 SEQSEL[30]

Reserved

0x05 LUTCTRLA0 70 EDGEDET CLKSRC FILTSEL[10] OUTEN ENABLE

0x06 LUTCTRLB0 70 INSEL1[30] INSEL0[30]

0x07 LUTCTRLC0 70 INSEL2[30]

0x08 TRUTH0 70 TRUTH[70]

0x0A LUTCTRLB1 70 INSEL1[30] INSEL0[30]

0x0B LUTCTRLC1 70 INSEL2[30]

0x0C TRUTH1 70 TRUTH[70]

2981 Control A

Bit 7 6 5 4 3 2 1 0 RUNSTDBY ENABLE

Bit 6 ndash RUNSTDBY Run in StandbyThis bit indicates if the peripheral clock (CLK_PER) is kept running in Standby sleep mode The setting isignored for configurations where the CLK_PER is not required For details refer to Sleep Mode Operation

Value Description0 System clock is not required in standby sleep mode

1 System clock is required in standby sleep mode

2982 Sequential Control 0

Name SEQCTRL0Offset 0x01Reset 0x00Property

Enable-Protected

Bit 7 6 5 4 3 2 1 0 SEQSEL[30]

Bits 30 ndash SEQSEL[30] Sequential SelectionThese bits select the sequential configuration

Value Name Description0x0 DISABLE Sequential logic is disabled

0x1 DFF D flip flop

0x2 JK JK flip flop

0x3 LATCH D latch

0x4 RS RS latch

Other - Reserved

2983 LUT n Control A

Name LUTCTRLA0 LUTCTRLA1Offset 0x05 + n0x04 [n=01]Reset 0x00Property

Enable-Protected

Bit 7 6 5 4 3 2 1 0 EDGEDET CLKSRC FILTSEL[10] OUTEN ENABLE

Bit 7 ndash EDGEDET Edge Detection

Value Description0 Edge detector is disabled

1 Edge detector is enabled

Bit 6 ndash CLKSRC Clock Source SelectionThis bit selects whether the peripheral clock (CLK_PER) or any input present on input line 2 (IN[2]) isused as clock (CLK_MUX_OUT) for a LUT

The CLK_MUX_OUT of the even LUT is used for clocking the Sequential block of a LUT pair

Value Description0 CLK_PER is clocking the LUT

1 IN[2] is clocking the LUT

Bits 54 ndash FILTSEL[10] Filter SelectionThese bits select the LUT output filter options

Filter Selection

Value Name Description0x0 DISABLE Filter disabled

0x1 SYNCH Synchronizer enabled

0x2 FILTER Filter enabled

0x3 - Reserved

Bit 3 ndash OUTEN Output EnableThis bit enables the LUT output to the LUTnOUT pin When written to 1 the pin configuration of thePORT IO-Controller is overridden

Value Description0 Output to pin disabled

1 Output to pin enabled

Bit 0 ndash ENABLE LUT Enable

Value Description0 The LUT is disabled

1 The LUT is enabled

2984 LUT n Control BNote

bull SPI connections to the CCL work only in master SPI modebull USART connections to the CCL work only in asynchronoussynchronous USART master mode

Name LUTCTRLB0 LUTCTRLB1Offset 0x06 + n0x04 [n=01]Reset 0x00Property

Enable-Protected

Bit 7 6 5 4 3 2 1 0 INSEL1[30] INSEL0[30]

Bits 74 ndash INSEL1[30] LUT n Input 1 Source SelectionThese bits select the source for input 1 of LUT n

Value Name Description0x0 MASK Masked input

0x1 FEEDBACK Feedback input

0x2 LINK Linked other LUT as input source

0x3 EVENT0EVENT1 Event 0 as input source for LUT0 Event 1 as input source for LUT1

0x5 IO IO pin LUTn-IN1 input source

0x6 AC0 ACOUT input source

0x7 TCB0 TCB W0 input source

0x8 TCA0 TCA W1 input source

0x9 TCD0 TCDOUTB input source

0xA USART0 USART TXD input source

0xB SPI0 SPI MOSI input source

Value Name Description0x5 IO IO pin LUTn-IN0 input source

0x9 TCD0 TCDOUTA input source

0xA USART0 USART XCK input source

0xB SPI0 SPI SCK input source

Other - Reserved

2985 LUT n Control C

Name LUTCTRLC0 LUTCTRLC1Offset 0x07 + n0x04 [n=01]Reset 0x00Property

Enable-Protected

Bit 7 6 5 4 3 2 1 0 INSEL2[30]

0x3 EVENT0 Event input source 0

0xA - Reserved

0xB SPI0 SPI MISO input source

other - Reserved

2986 TRUTHn

Name TRUTH0 TRUTH1Offset 0x08 + n0x04 [n=01]Reset 0x00Property

Enable-Protected

Bit 7 6 5 4 3 2 1 0 TRUTH[70]

Bits 70 ndash TRUTH[70] Truth TableThese bits define the value of truth logic as a function of inputs IN[20]

30 AC ndash Analog Comparator

301 OverviewThe Analog Comparator (AC) compares the voltage levels on two inputs and gives a digital output basedon this comparison The AC can be configured to generate interrupt requests andor Events upon severaldifferent combinations of input change

The dynamic behavior of the AC can be adjusted by a hysteresis feature The hysteresis can becustomized to optimize the operation for each application

The input selection includes analog port pins internal references and DAC output The analogcomparator output state can also be output on a pin for use by external devices

302 Featuresbull 50ns response time for supply voltage above 27Vbull Zero-cross detectionbull Selectable hysteresis

ndash Nonendash 10mVndash 25mVndash 50mV

bull Analog comparator output available on pinbull Invert comparator outputbull Flexible input selection

ndash 2 Positive pinsndash 2 Negative pinsndash Output from the DACndash Internal reference voltage

bull Interrupt generation onndash Rising edgendash Falling edgendash Toggle

bull Event generationndash Comparator output

303 Block DiagramFigure 30-1 Analog Comparator

Enable Hysteresis

ControllerLogic

Invert

Event System

ACOUT0

MUXCTRLAAC Controller

N0 Negative Input 0 Analog

P0 Postive Input 0 Analog

P1 Positive Input 1 Analog

ACOUT Comparator Output for AC Digital

Table 30-1 AC Product Dependencies

Clocks Yes CLKCTRL

Events Yes EVSYS

Debug Yes UPDI

Related Links

AC ndash Analog Comparator on page 449ADC - Analog to Digital Converter on page 460

3263 Sleep Mode OperationIf the Run in Standby bit (RUNSTDBY) in the Control A register (DACCTRLA) is written to 1 andCLK_PER is available the DAC will continue to operate in Standby sleep mode If RUNSTDBY bit iszero the DAC will stop the conversion in Standby sleep mode

If conversion is stopped in Standby sleep mode the DAC and the output buffer are disabled to reducepower consumption When the device is exiting Standby sleep mode the DAC and the output buffer (ifconfigured by OUTEN=1 in DACCTRLA) are enabled again Therefore a certain startup time is requiredbefore a new conversion is initiated

In Power Down sleep mode the DAC and output buffer are disabled to reduce power consumption

Offset Name Bit Pos

0x00 CTRLA 70 RUNSTDBY OUTEN ENABLE

3281 Control A

Bit 7 6 5 4 3 2 1 0 RUNSTDBY OUTEN ENABLE

Bit 7 ndash RUNSTDBY Run in Standby ModeIf this bit is written to 1 the DAC or Output Buffer will not automatically be disabled when the device isentering Standby sleep mode

Bit 6 ndash OUTEN Output Buffer EnableWriting a 1 to this bit enables the Output Buffer and sends the DACOUT signal to a pin

Bit 0 ndash ENABLE DAC EnableWriting a 1 to this bit enables the DAC

3282 DATA

Bit 7 6 5 4 3 2 1 0 DATA[70]

Bits 70 ndash DATA[70] DataThese bits contains the digital data which will be converted to an analog voltage

33 PTC - Peripheral Touch Controller

331 OverviewThe Peripheral Touch Controller (PTC) acquires signals in order to detect touch on capacitive sensorsThe external capacitive touch sensor is typically formed on a PCB and the sensor electrodes areconnected to the analog front end of the PTC through the IO pins in the device The PTC supports bothself- and mutual-capacitance sensors

In mutual-capacitance mode sensing is done using capacitive touch matrices in various X-Yconfigurations including indium tin oxide (ITO) sensor grids The PTC requires one pin per X-line and onepin per Y-line

In self-capacitance mode the PTC requires only one pin (Y-line) for each touch sensor

The number of available pins and the assignment of X- and Y-lines is depending on both package typeand device configuration Refer to the Configuration Summary and IO Multiplexing table for details

332 Featuresbull Low-power high-sensitivity environmentally robust capacitive touch buttons sliders wheelsbull Supports wake-up on touch from power-save sleep modebull Supports mutual capacitance and self-capacitance sensing

ndash Mix-and-match mutual-and self-capacitance sensorsbull One pin per electrode ndash no external componentsbull Load compensating charge sensing

ndash Parasitic capacitance compensation and adjustable gain for superior sensitivitybull Zero drift over the temperature and VDD range

ndash Auto calibration and re-calibration of sensorsbull Single-shot and free-running charge measurementbull Hardware noise filtering and noise signal de-synchronization for high conducted immunitybull Driven shield for better noise immunity and moisture tolerancebull Selectable channel change delay allows choosing the settling time on a new channel as requiredbull Acquisition-start triggered by command or through auto-triggering featurebull Low CPU utilization through interrupt on acquisition-completebull Using ADC peripheral for signal conversion and acquisitionbull Supported by the Atmelreg QTouchreg Composer development tools See also Atmel|Start and Atmel

Studio documentation

333 Block DiagramFigure 33-1 PTC Block Diagram Mutual-Capacitance

CompensationCircuit

X Line Driver

InputControl

Result

ADCSystem

ChargeIntegrator

Figure 33-2 PTC Block Diagram Self-Capacitance

CompensationCircuit

X Line Driver

InputControl

IRQADCSystem

ChargeIntegrator

Result

334 Signal DescriptionTable 33-1 Signal Description for PTC

Name Type Description

Y[m0] Analog Y-line (InputOutput)

X[n0] Digital X-line (Output)

DS[10] Digital Driven Shield

Note The number of X and Y lines are device dependent Refer to Configuration Summary for details

335 Product DependenciesIn order to use this Peripheral configure the other components of the system as described in thefollowing sections

3351 IO LinesThe IO lines used for analog X-lines and Y-lines must be connected to external capacitive touch sensorelectrodes External components are not required for normal operation However to improve the EMCperformance a series resistor of 1kΩ or more can be used on X-lines and Y-lines

33511 Mutual-capacitance Sensor ArrangementA mutual-capacitance sensor is formed between two IO lines - an X electrode for transmitting and Yelectrode for receiving The mutual capacitance between the X and Y electrode is measured by thePeripheral Touch Controller

Figure 33-3 Mutual Capacitance Sensor Arrangement

PTCModule

Sensor Capacitance Cxy

Cx0y0 Cx0y1 Cx0ym

Cx1y0 Cx1y1 Cx1ym

Cxny0 Cxny1 Cxnym

PTCModule

33512 Self-capacitance Sensor ArrangementThe self-capacitance sensor is connected to a single pin on the Peripheral Touch Controller through the Yelectrode for receiving the signal The sense electrode capacitance is measured by the Peripheral TouchController

Figure 33-4 Self-capacitance Sensor Arrangement

PTCModule

Sensor Capacitance Cy

For more information about designing the touch sensor refer to Buttons Sliders and Wheels TouchSensor Design Guide on httpwwwatmelcom

3352 ClocksThe PTC is clocked by the CLK_PER clock See the Related Links for details on configuring CLK_PER

3353 Analog-Digital Converter (ADC)The PTC is using the ADC of ATtiny417814816817 for signal conversion and acquisition The ADCmust be enabled and configured appropriatly in order to allow correct behavior of the PTC

Related LinksADC - Analog to Digital Converter on page 460

336 Functional DescriptionIn order to access the PTC the user must use the QTouch Composer tool to configure and link theQTouch Library firmware with the application code QTouch Library can be used to implement buttonssliders wheels in a variety of combinations on a single interface

Figure 33-5 QTouch Library Usage

Custom Code Compiler

Link Application

Atmel QTouchLibrary

For more information about QTouch Library refer to the Atmel QTouch Library Peripheral Touch ControllerUser Guide

34 UPDI - Unified Program and Debug InterfaceRelated LinksDebug Operation on page 106

341 OverviewThe Unified Program and Debug Interface (UPDI) is an Atmel proprietary interface for externalprogramming and on-chip debugging of a device

The UPDI supports programming of nonvolatile memory (NVM) space FLASH EEPROM fuses lockbitsand the user row In addition the UPDI can access the entire IO and data space of the device See theNVM Controller documentation for programming via the NVM controller and executing NVM controllercommands

Programming and debugging is done through the UPDI Physical interface (UPDI PHY) which is bydefault a 1-wire UART based half-duplex interface using the Reset pin for data reception andtransmission Clocking is done by an internal 32MHz oscillator Enabling of the 1-wire interface bydisabling the reset functionality is either done by 12V programming or by setting a Fuse Optionally a 2-wire interface using a GPIO as a separate TX-pin can be enabled with the PDI pin still used for the RX-part of the communication The UPDI Access layer grants access to the system bus matrix with memorymapped access to system blocks such as Memories NVM and peripherals

The Asynchronous System Interface (ASI) is providing direct interface access to On-Chip Debugging(OCD) NVM and System Management features This gives the debugger direct access to systeminformation without accessing though the bus The ASI is also responsible for setting up and executingthe system KEYs

Related LinksNVMCTRL - Non Volatile Memory Controller on page 59Enabling of KEY Protected Interfaces on page 517

342 Featuresbull Programming

ndash External programming through PDI 1-wire (1W) interfacebull Enable programming by 12V or fusebull Uses the RESET pin of the device for programmingbull No GPIO pins occupied during operationbull Asynchronous Half-Duplex UART protocol towards the emulatorbull Optional programming with 2-wire asynchronous mode using one additional GPIO pin

bull Debuggingndash Memory mapped access to device address space (NVM RAM IO)ndash Run-time readout of program counter (PC) Stack Pointer (SP) and CPU Status register

(CPU_SREG) for code profilingndash Non-intrusive run-time chip monitoring without accessing system registers

bull Monitor CRC status and sleep statusndash Support for power-aware Debugging

bull Programming and Debug Interface (PDI)

ndashndash Default 1-wire interface with optional enable of 2-wire asynchronous interface for

programming and debugndash Reset pin used as RXTX-pin in 1-wire mode GPIO pin used as TX-pin in 2-wire modendash Built in error detection with error signature readoutndash Frequency Measurement of internal oscillators using theEvent System

343 Block DiagramFigure 34-1 UPDI Block Diagram

UPDI Phys ica l

UPDI Access

ASI Access

UPDI Controlle r

UPDI PAD (RXTX Data)

UPDI TXPAD (TX Data)

Memories

Periphera ls

ASI Inte rna l Inte rfaces

ontroller

System

Managem

Table 34-1 UPDI Product Dependencies

Clocks Yes CLKCTRL

Interrupts No -

Events Yes EVSYS

Debug Yes UPDI

Related Links

Clocks on page 504IO Lines and Connections on page 504Power Management on page 504Debug Operation on page 505

3441 ClocksThe UPDI and ASI operate on two separate clock domains The UPDI Physical layer clock is derived froman internal 32MHz oscillator and the UPDI access layer clock is the same as the system clock There is asynchronization boundary between the UPDI physical layer and access layer which ensures correctoperation for different clock frequencies on each domain The UPDI clock is prescaled in the ASI and thedefault startup frequency is 4MHz (DIV8 prescaling) after enabling the UPDI The UPDI prescaling ischanged by writing the UPDICLKDIV bits in ASI_CTRLA register

Figure 34-2 UPDI clock domains

UPDI Phys ica l

UPDI Controlle r

~ ~Clk_32Mhz Clk_sys

UPDI Clk Presca le r

ClockControlle r

ClockControlle rClk_UPDI

Clk_sys

CH UPDI

Access layer

3442 IO Lines and ConnectionsTo operate the UPDI the RST Pin must be set to UPDI Mode This is not done through the PORT IO PinController as for regular IO Pins but through setting the correct FUSE_SYSCFG1RSTPINCFG registeras described in UPDI Enable with RESET Pin Override or by following the UPDI 12V enable sequencefrom UPDI Enable by 12V Programming Pull enable input enable and output enable settings areautomatically controlled by the UPDI when active

3445 Power ManagementThe UPDI physical layer continues to operate in any sleep mode and is always accessible for aconnected debugger but readwrite access to the system bus is restricted in sleep modes where the CPUclock is switched off The UPDI can be enabled at any time independent of the system sleep state See Sleep Mode Operation for details on UPDI operation duing sleep modes

3451 Principle of OperationCommunication through the UPDI is based on standard UART communication using a fixed frameformat and automatic baud rate detection for clock and data recovery In addition to the data frame thereare several control frames which are important to the communication The supported frame formats arepresented in Figure 34-3

Figure 34-3 Supported UPDI Frame formats

0 1 2 3 4 5 6 7

SYNCH (0x55)

S t P S 1 S 2

S 1 S 2

Synch PartEnd_synch

ACK (0x40)

S 1 S 2

DataFrame

Consist of 1 start bit (always low) 8 data bits 1 parity bit (even parity) and two stop bits(always high) If the start bit parity bit or stop bits have an incorrect value an error will bedetected and signalized by the UPDI The parity bit check in the UPDI can be disabled bywriting the PARD bit in UPDICTRLA in which case the parity generation from the debuggercan be ignored

IDLEFrame

Special Frame which consist of 12 high bits This is the same as keeping the transmissionline in an IDLE state

BREAK The BREAK frame is used to reset the UPDI back to its default state and is typically used forerror recovery

SYNCH The SYNCH frame (0x55) is used by the baud rate generator to set the baud rate for thecoming transmission A SYNCH character is always expected by the UPDI in front of everynew instruction and after a successful BREAK has been transmitted

ACK The Acknowledge (ACK) character is transmitted from the UPDI whenever a ST or STSinstruction has successfully crossed the synchronization border and have gained bus accessWhen an ACK is received by the debugger the next transmission can start

34511 UPDI UARTAll transmission and reception of serial data on the UPDI is achieved using the UPDI frames presented in Figure 34-3 Communication is initiated from the master (debugger) side and every transmission muststart with a SYNCH character upon which the UPDI can recover the transmission baud rate and storethis setting for the coming data The baud rate set by the SYNCH character will be used for bothreception and transmission for the instruction byte received after the SYNCH See UPDI Instruction Setfor details on when the next SYNCH character is expected in the instruction stream

There is no writable baud rate register in the UPDI so the baud rate sampled from the SYNCH characteris used for data recovery by sampling the start bit and do a majority voting on the middle samples Thisprocess is repeated for all bits in the frame including the parity bit and two stop bits The baud generatoruses 16 samples and the majority voting is done on sample 78 and 9Figure 34-4 UPDI UART Start Bit and DataParityStop bit sampling

1 2 3 4 5 6 700 10 11 12 13 14 15 1698 1 2 3

IDLE BIT 0STARTRxD

Sample

1 2 3 4 5 6 7 10 11 12 13 14 15 1698 1

Sample

The transmission Baud Rate must be set up in relation to the currently used UPDI clock prescaler whichcan be adjusted by UPDICLKDIV in UPDIASI_CTRLA See Table 34-2 for recommended maximum andminimum baud rate settingsTable 34-2 Recommended UART Baud Rate based on UPDICLKDIV setting

UPDICLKDIV[10] MAX Recommended Baud Rate MIN Recommended Baud Rate

0x0 (32MHz) 18Mbps 0600kbps

0x2 (8MHz) 450kbps 0150kbps

0x3 (4MHz) - Default 225kbps 0075kbps

The UPDI baud rate generator utilizes fractional baud counting to minimize the transmission error Withthe fixed frame format used by the UPDI the maximum and recommended receiver transmission errorlimits can be seen in the following table

Table 34-3 Receiver Baud Rate Error

Data + parity bits Rslow Rfast Max Total Error()

Recommendedmax RX error ()

9 9639 10476 +476 -361 +15 -15

34512 BREAK CharacterThe BREAK character is used to reset the internal state of the UPDI to the default setting This is useful ifthe UPDI enters an error state due to communication error or when synchronization between thedebugger and the UPDI is lost

A single BREAK character is enough to reset the UPDI but in some special cases where the BREAKcharacter is sent when the UPDI has not yet entered the error state a double BREAK character might beneeded A double BREAK is guaranteed to reset the UPDI from any state Note that when sending adouble BREAK it is required to have at least one stop bit between the BREAK characters

No SYNCH character is required before the BREAK because the BREAK is used to reset the UPDI fromany state This means that the UPDI will sample the BREAK based on the last stored baud rate settingderived from the last received valid SYNCH character If the communication error was due to incorrectsampling of the SYNCH character the baud rate is unknown to the connected debugger For this reasonthe BREAK character should be transmitted at the slowest recommended baud rate setting for anyparticular UPDI oscillator setting according to Table 34-4Table 34-4 Recommended BREAK Character Duration

UPDICLKDIV[10] Recommended BREAK Character Duration

0x0 (32MHz) 3075ms

0x1 (16MHz) 615ms

0x2 (8MHz) 1230ms

0x3 (MHz) - Default 2460ms

3452 Basic OperationThe UPDI must be enabled before the UART communication can start

bull UPDI Enable by 12V Programmingbull UPDI Enable with RESET Pin Override

34521 UPDI Enable with RESET Pin OverrideWhen the Reset Pin Configuration bits in the System Configuration 0 fuse(FUSE_SYSCFG0RSTPINCFG) are 0x1 the RESET Pin will be overridden by the UPDI Pin during thesystem boot sequence the UPDI will take control of the Pin and configure it as input with pull-up Whenthe pull-up is detected by a connected debugger the initial handshake sequence to enable the UPDI asdepicted below is started

Figure 34-5 UPDI Enable sequence with UPDI PAD Enabled by Fuse

(Ignore)

_RESET St SpD0 D1 D2 D3 D4 D5 D6 D7

SYNC (0x55)(Autobaud)

Hands hake BREAK[10 ndash 200us ]

pditxd Hi-Z 2

pdirxd

debuggerpditxd Hi-Z Hi-Z

Fus e read in Pull-up enabled Ready to rece ive init

2 Internal os c illator ready Communication channel ready

10 ndash 200us

When the pull-up is detected the Emulator initiates the enable sequence by driving the line low for aminimum of 200ns The duration can be longer but the data line should be released from the debuggerbefore the UPDI startup sequence is done

The negative edge is detected by the UPDI which requests the peripheral clock The UPDI will continueto drive the line low until the clock is stable and ready for the UPDI to use The duration of this will varydepending on the status of the oscillator and when the UPDI is enabled relative to the boot sequence Astartup time between 10us and 200us can be expected After this duration the data line will be releasedby the UPDI and pulled-high

When the Debugger detects that the line is high the initial SYNCH character (0x55) must be sent toproperly enable the UPDI for communication If the start bit of the SYNCH character is not sent within13ms the UPDI will disable itself and the startup sequence must be repeated This time is based oncounted cycles on the 4MHz UPDI clock which is default when enabling the UPDI The disable isperformed to avoid the UPDI being enabled unintentionally

After successful SYNCH character transmission the first instruction frame can be transmitted

34522 UPDI Enable by 12V ProgrammingGPIO or Reset functionality on the RESET Pin can be overridden by the UPDI by using 12Vprogramming By applying a 12V pulse to the RESET Pin the pin functionality is switched to UPDIindependent of RSTPINCFG in FUSESYSCFG0 It is recommended to always reset the device beforestarting the 12V enable sequence

After startup the Power-on Reset (POR) must be released before the 12V pulse can be applied Theduration of the pulse is recommended in the range from 100us to 1ms before tri-stating When applyingthe rising edge of the 12V pulse the UPDI will be reset After tri-stating the UPDI will remain in Resetuntil the RESET Pin is driven low by the debugger This will release the UPDI Reset and start the initialhandshake sequence as for UPDI Enable with RESET Pin Override The rest of the enable sequencefollows the same pattern as if UPDI is enabled with RESET Pin Override

The following figure shows the 12V enable sequence The ireset signal is the UPDI internal reset

Figure 34-6 UPDI Enable Sequence by 12V Programming

(Ignore)

(Hi-Z)

_RESET (PDI12V) St SpD0 D1 D2 D3 D4 D5 D6 D7

BREAK Hands hake[10 ndash 200us ]

pditxd Hi-Z 2

pdirxd

debuggerpditxd

Hi-Z Hi-Z

_RESET pin dis abled PDI enabled

debuggerpdio12v

10 ndash 200us

When enabled by 12V only a POR will disable the UPDI configuration on the RESET Pin and restore thedefault setting If issuing a UPDI disable command through the UPDIDIS bit in UPDICTRLB the UPDIwill be reset and the clock request will be canceled but the RESET Pin will remain in UPDI configuration

Output Enable Timer Protection for GPIO ConfigurationWhen the Reset pin Configuration bits in the System Configration 0 fuse (RSTPINCFG inFUSESYSCFG0) are 0x0 the RESET Pin configured as GPIO To avoid the potential conflict betweenthe GPIO actively driving the output and a 12V UPDI enable sequence initiation a timer protection isdisabling the output enable for approximately 10ms after each System ResetNote It is always recommended to issue a System Reset before entering the 12V programmingsequence

34523 UPDI DisableAny programming or debug session should be terminated by writing the UPDIDIS bit in UPDICTRLBWriting this bit will reset the UPDI including any decoded KEYs and disable the oscillator request for themodule If the disable operation is not performed the UPDI will stay enabled and request its oscillatorcausing increased power consumption for the application

During the enable sequence the UPDI can disable itself in case of a faulty enable sequence There aretwo cases which will cause an automatic disable

bull A SYNCH character is not sent within 164ms after the initial enable pulse described in UPDIEnable with RESET Pin Override

bull The first SYNCH character after an initiated enable is too short or too long to register as a validSYNCH character See Table 34-2 for recommended baud rate operating ranges

34524 UPDI Communication Error HandlingThe UPDI contains a comprehensive error detection system to be able to provide information to thedebugger during a potential communication loss The error detection consist of detecting physicaltransmission errors like start bit error parity error contention error and frame error to more high levelerrors like access timeout error See UPDI_STATUSBPESIG for an overview of the available errorsignatures

Whenever the UPDI detects an error it will immediately transfer to an internal error state to avoidunwanted system communication In the error state the UPDI will ignore all incoming data requests

except if a BREAK character is transmitted The following procedure should always be applied whenrecovering from an error condition

bull Send a BREAK character See BREAK Character for recommended BREAK character handlingbull Send a SYNCH character at the desired baud rate for the next data transfer Note that upon

receiving a BREAK the UPDI oscillator setting in UPDIASI_CTRLA is reset to the slowest defaultsetting of 4MHz prescaling This affects the baud rate range of the UPDI according to Table 34-2

bull Do an LDCS to UPDISTATUSB register to read the PESIG field PESIG will give information aboutthe occurred error and the error signature will be cleared when read

bull The UPDI is now recovered from the error state and ready to receive the next SYNCH characterand instruction

34525 Direction ChangeIn order to ensure correct timing for half-duplex UART operation the UPDI has a build in Guard Timemechanism to relax the timing when changing direction from RX mode to TX mode The Guard Time is anumber of IDLE bits inserted before the next start bit is transmitted The number of IDLE bits can beconfigured through GTVAL in UPDICTRLA The duration of each IDLE bit is given by the baud rate usedby the current transmissionNote It is not recommended to use GTVAL setting 0x7 with no additional IDLE bits This can cause theUPDI to not respond correctly for some instructions

Figure 34-7 UPDI Direction Change by inserting IDLE bits

S t RX Data Frame P S 1 S 2 TX Data FrameIDLE bits S t P S 1 S 2

RX Data Frame Dir Change TX Data Frame

Data from debugger to UPDI

Guard Time IDLE bits inserted

Data from UPDI to debugger

The UPDI Guard Time is the minimum IDLE time that the connected debugger will experience whenwaiting for data from the UPDI Because of the asynchronous interface to the system as presented in Clocks the ratio between the UPDI baud rate and the system clock will affect the synchronization timeand how long it takes before the UPDI can transmit data In the cases where the synchronization delay isshorter than the current Guard Time setting the Guard Time will be given by GTVAL directly

3453 UPDI Instruction SetCommunication through the UPDI is based on a small instruction set The instructions are used to accessthe internal UPDI and ASI Control and Status (CS) space as well as the memory mapped system spaceAll instructions are byte instructions and must be preceded by a SYNCH character to determine the baudrate for the communication See UPDI UART for information about setting the baud rate for thetransmission The following Figure gives an overview of the UPDI instruction set

Figure 34-8 UPDI Instruction Set Overview

0 0LDS 0

Size A Size B Opcode

0 1 0STS

1 0 0LDCS

CS Address

1 1 0STCS

1 1 0 0KEY 1

Size C

1 0 0 0 0REPEAT 1

Size B

LD0000

OPCODE

LDCS (LDS ControlS ta tus )

STCS (STS ControlS ta tus )KEY

REPEAT1111

Size B - Data s izeByte

ReservedReserved

Word (2 Bytes )

CS Addres s (CS - ControlStatus reg )0 00 Reg 0

Reg 2Reg 3

Reg 10

0 00 10 10 00 10 1

1 11 1

1 00 0

Size C - Key s ize64 bits (8 Bytes )

Reserved

1128 bits (16 Bytes )

Size A - Addres s s izeByte

ReservedReserved

Word (2 Bytes )

0 0LD 1

Ptr Size AB Opcode

0 1 1ST 0

Ptr - Pointer acces s(ptr)

ptrReserved

(ptr++)

SIB ndash Sys tem Information Block s e lReceive KEY0

1 Send SIB

Reg 4 (ASI CS space)

Reserved

34531 LDS - Load Data from Data Space Using Direct AddressingThe LDS instruction is used to load data form the bus matrix and into the serial shift register for serial readout The LDS instruction is based on direct addressing and the address must be given as an operand tothe instruction for the data transfer to start Maximum supported size for address and data is 16 bit LDSsupports repeated memory access when combined with the REPEAT instruction

The following figure shows the operands of the LDS instruction and a typical transmission example

Figure 34-9 LDS Instruction Operation

0 0LDS 0

Size A Size B OPCODE

0Size A - Addres s s ize

ReservedReserved

Word (2 Bytes )

ReservedReserved

Word (2 Bytes )

Synch (0x55) LDS Adr_0 Adr_n

ADR SIZE

Data_0 Data_nΔGT

34532 STS - Store Data to Data Space Using Direct AddressingThe STS instruction is used to store data that is shifted serially into the PHY layer to the bus matrixaddress space The STS instruction is based on direct addressing where the address is the first set ofoperands and data is the second set The size of the address and data operands are given by the sizefields presented in the Figure below Maximum size for both address and data is 16 bit

STS supports repeated memory access when combined with the REPEAT instruction

Figure 34-10 STS Instruction Operation

0 1STS 0

ReservedReserved

Word (2 Bytes )

ReservedReserved

Word (2 Bytes )

Synch (0x55) STS Adr_0 Adr_n

ADR SIZE

Data_0 Data_n

ACK ACK

DATA SIZE

ΔGT ΔGT

The transfer protocol for an STS instruction is depicted in the Figure as well following this sequence1 The address is sent2 An Acknowledge (ACK) is sent back from the UPDI if the transfer was successful3 The data can is sent4 A new ACK is received after the data is successfully transferred

34533 LD - Load Data from Data Space Using Indirect AddressingThe LD instruction is used to load data form the bus matrix and into the serial shift register for serial readout The LD instruction is based on indirect addressing which means that the address pointer in the UPDIneeds to be written prior to bus matrix access Automatic pointer post increment operation is supportedand is useful when the LD instruction is used with REPEAT It is also possible to do a LD of the UPDIpointer register Maximum supported size for address and data load is 16 bit

Figure 34-11 LD Instruction Operation

Ptr Size AB OPCODE

0 0 1LD 0

ptrReserved

(ptr++)

ReservedReserved

Word (2 Bytes )

ReservedReserved

Word (2 Bytes )

Synch (0x55) LD

Data_0 Data_nΔGT

DATA SIZE

The Figure above shows an example of a typical LD sequence where data is received after the GuardTime period Loading data from the UPDI pointer register follows the same transmission protocol

34534 ST - Store Data from Data Space Using Indirect AddressingThe ST instruction is used to store data that is shifted serially into the PHY layer to the bus matrix addressspace The ST instruction is based on indirect addressing which means that the address pointer in theUPDI needs to be written prior to bus matrix access Automatic pointer post increment operation issupported and is useful when the ST instruction is used with REPEAT ST is also used to store the UPDIaddress pointer into the pointer register Maximum supported size for address and data load is 16 bit

Figure 34-12 ST Instruction Operation

Ptr Size AB OPCODE

0 1 1ST 0

ptrReserved

(ptr++)

ReservedReserved

Word (2 Bytes )

ReservedReserved

Word (2 Bytes )

Synch (0x55) ST Data_0 Data_n

Block SIZE

Synch (0x55) ST ADR_0 ADR_n

ADDRESS_SIZE

ACKΔGT

The Figure above gives an example of ST to the UPDI pointer register and store of regular data Notethat in both cases an Acknowledge (ACK) is sent back by the UPDI if the store was successful

34535 LCDS - Load Data from Control and Status Register SpaceThe LCDS instruction is used to load data from the UPDI and ASI CS-space LCDS is based on directaddressing where the address is part of the instruction opcode The total address space for LCDS is 16byte and can only access the internal UPDI register space This instruction only supports byte accessand data size is not configurable

Figure 34-13 LCDS Instruction Operation

1 0 0LDCS

CS Address CS Addres s (CS - ControlStatus reg )0 00 Reg 0

Reg 2Reg 3

Reg 10

0 00 10 10 00 10 1

Reg 15 (PDI ChipASI)1 11 1

1 00 0

Reg 4 (PDI ChipASI)

OPCODE

Synch (0x55) LDCS

DataΔgt

The Figure above shows a typical example of LCDS data transmission A data byte from the LCDS spaceis transmitted from the UPDI after the Guard-Time is completed

34536 STCS (Store Data to Control and Status register space)The STCS instruction is used to store data to the UPDI and ASI CS-space STCS is based on directaddressing where the address is part of the instruction opcode The total address space for STCS is 16byte and can only access the internal UPDI register space This instruction only supports byte accessand data size is not configurable

Figure 34-14 STCS instruction operation

1 1 0STCS

Reg 2Reg 3

Reg 10

0 00 10 10 00 10 1

1 00 0

Reg 4 (PDI ChipASI)

OPCODE

Synch (0x55) STCS Data

Figure 34-14 shows the data frame transmitted after the SYNCH and instruction frames Note that there isno response generated from the STCS instruction as is the case for ST and STS

34537 REPEAT - Set Instruction Repeat CounterThe REPEAT instruction is used to store the repeat count value into the UPDI repeat counter registerWhen instructions are used with REPEAT protocol overhead for SYNCH- and Instruction Frame can beomitted on all instructions except the first instruction after the REPEAT is issued

The DATA_SIZE opcode field refers to the size of the repeat value Only byte size (up to 255 repeats) issupported The instruction that is loaded directly after the REPEAT instruction will be repeated RPT_0

times The instruction will be issued a total of RPT_0 + 1 times An ongoing repeat can only be abortedby sending a BREAK character

Figure 34-15 REPEAT Instruction Operation

1 0 0 0 0REPEAT 1

Size B Size B - Data s izeByte

ReservedReserved

Reserved

OPCODE

Synch (0x55) REPEAT RPT_0

REPEAT SIZE

Synch (0x55)

ST (ptr++) Data_0 Data_n

DATA_SIZE

DataB_1 DataB_n

ACKΔd Δd ΔdΔd Δd

DATA_SIZE DATA_SIZE

Rpt nr of Blocks of DATA_SIZE

The Figure above gives an example of repeat operation with a ST instruction using pointer post incrementoperation After the REPEAT instruction is sent with RPT_0 = n the first ST instruction is issued withSYNCH- and Instruction frame while the next n ST-instructions are executed by only sending in databytes according to the ST operand DATA_SIZE and maintaining the Acknowledge (ACK) handshakeprotocol

34538 KEY - Set Activation KEYThe KEY instruction is used for communicating KEY bytes to the UPDI opening up for executingprotected features on the device See Table 34-5for an overview over functions that are activated byKEYs For the KEY instruction only 64bit KEY size is supported If the System Information Block (SIB)field of the KEY instruction is set the KEY instruction returns the SIB instead of expecting incoming KEYbytes Maximum supported size for SIB is 256bits

Figure 34-16 KEY Instruction Operation

Reserved

1128 bits (16 Bytes ) (SIB only)

1 1 0 0KEY 1

Size C

SIB ndash Sys tem Information Block s e lSend KEY0

1 Rece ive SIB

Synch (0x55) KEY KEY_0 KEY_n

KEY SIZE

Synch (0x55) KEY

SIB_0 SIB_n

SIB SIZEΔgt

Reserved

The Figure above shows the transmission of a KEY and the reception of a SIB In both cases theSIZE_C field in the opcode determines the number of frames to be sent or received Note that there is noresponse after sending a KEY to the UPDI When requesting the SIB data will be transmitted from theUPDI according to the current Guard Time setting

3454 System Clock Measurement with UPDIIt is possible to use the UPDI to get a accurate measurement of the system clock frequency by using theUPDI event connected to TCB with Input Capture capabilities The next steps gives a recommendedsetup flow for this feature

bull Set up TCBCTRLB with setting CNTMODE=0x3 Input Capture frequency measurement modeSee for details

bull Write CAPTEI=1 in TCBEVCTRL to enable Event Interrupt Keep EDGE = 0 in TCBEVCTRLbull Configure the Event System as described in Eventsbull For the SYNCH character used to generate the UPDI events it is recommended to use a slow baud

frequency in the range of 10 - 50kHz to get a more accurate measurement on the value capturedby the timer between each UPDI event One particular thing to note is that if the capture is set upto trigger an interrupt the first captured value should be ignored It is the second captured valuebased on the input event that should be used for the measurement See Figure 34-17 for anexample using 10kHz UPDI SYNCH character pulses giving a capture window of 200us for theTimer

bull It is possible to read out the captured value directly after the SYNCH character by reading theTCBCC register or the value can be written to memory by the CPU once the capture is done

Figure 34-17 UPDI System Clock Measurement Events

CAPT_1 CAPT_2 CAPT_3

TCB_CC

UPDI_Input

Ignore firs t capture event

3455 Interbyte DelayWhen loading data with the UPDI or reading out the System Information Block the output data willnormally come out with two IDLE bits between each transmitted byte for a multibyte transfer Dependingon the application on the receiver side data might be coming out too fast when there is no extra IDLE bitsbetween each byte By enabling the IBDLY feature in UPDICTRLB two extra stop bits will be insertedbetween each byte to relax the sampling time for the debugger Interbyte delay works in the same way asguard time by inserting extra IDLE bits but only a fixed number of IDLE bits and only for multibytetransfers Note that the first transmitted byte after a direction change will be subject to the regular GuardTime before it is transmitted and the interbyte delay is not added to this time

Figure 34-18 Interbyte Delay exemple with LD and RPT

Too fas t transmiss ion no inte rbyte de lay

RPT CNT LD(ptr) D0 D1

Emula tor Data

SB D2 D3S

BSB D4 D5S

Emula tor Process ing

D1 los t D1 los tD0 D2 D4

RPT CNT LD(ptr)

Emula tor Data

Emula tor Process ing D0 D1 D2

D0 D1 D2 D3SB

SBIB IB IB

Data sampling ok with inte rbyte de lay

In Figure 34-18 GT denotes the Guard Time insertion SB are stop bits and IB is the inserted interbytedelay The rest of the frames are data and instructions

3456 System Information BlockThe System Information Block (SIB) can be read out at any time by setting the SIB bit in the KEYinstruction from KEY - Set Activation KEY The SIB provides a compact form of providing information forthe debugger which is vital in identifying and setting up the proper communication channel with the partThe output of the SIB should be interpreted as ASCII symbols KEY size field should be set to 16bytewhen reading out the complete SIB and 8 byte size can be used to read out only the Device_ID See Figure 34-19 for SIB format description and which data that is available at different readout sizesFigure 34-19 System Information Block format

16 8 [Byte][Bits ] Fie ld NameDevice_IDReserved

NVM_VERSIONOCD_VERSION

RESERVEDDBG_OSC_FREQ

[60] [550][7][70]

[108][230][1311][230]

[14][70][15][70]

3457 Enabling of KEY Protected InterfacesAccess to some internal interfaces and features are protected by the UPDI KEY mechanism To activate aKEY the correct KEY data must be transmitted by using the KEY instruction as described in KEYinstruction Table 34-5 describes the available KEYs and the condition required when doing operationwith the KEY active There is no requirement when shifting in the KEY but you would for instancenormally run a Chiperase before enabling the OCD KEY to unlock the device for debug But if the OCDKEY is shifted in first it will not be reset by shifting in the Chiperase KEY afterwards

Table 34-5 KEY Activation Overview

KEY name Description Requirements foroperation

Chiperase Start NVM ChiperaseClear Lockbits

None UPDI Disable UPDIReset

OCD Activate On Chip Debugfeatures

Lockbits cleared UPDI Disable UPDIReset

NVMPROG Activate NVMProgramming

Lockbits ClearedASI_SYS_STATUSNVMPROG set

Programming Done UPDI Reset

USERROW-Write Program User Row onLocked part

Lockbits SetASI_SYS_STATUSUROWPROG set

Write to KEY status bit UPDI Reset

2-Wire Mode Enable 2-Wire modewith separate TX-pin

UPDI enabled in 1Wmode

UPDI Disable UPDIReset

Table 34-6 gives an overview of the available KEY signatures that must be shifted in to activate theinterfaces

Table 34-6 KEY Activation Signatures

KEY name KEY signature (LSB writtenfirst)

Chiperase 0x4E564D4572617365 64bit

OCD 0x4F43442020202020 64bit

NVMPROG 0x4E564D50726F6720 64bit

USERROW-Write 0x4E564D5573267465 64bit

2-Wire Mode 0x5044493A41325720 64bit

For some KEY protected interfaces special enable sequences must be followed See the NVMdocumentation for details

34571 Chip EraseThe following steps should be followed to issue a Chip Erase

1 Enter the CHIPERASE KEY by using the KEY instruction See Table 34-6 for the CHIPERASEsignature

2 Optional Read the Chip Erase bit in the AS Key Status register (CHIPERASE inUPDIASI_KEY_STATUS) to see that the KEY is successfully activated

3 Write the Reset signature into the UPDIASI_RESET_REQ register This will issue a System Reset4 Write 0x00 to the ASI Reset Request register (UPDIASI_RESET_REQ) to clear the System Reset5 Read the Lock Status bit in the ASI System Status register (LOCKSTATUS in

UPDIASI_SYS_STATUS)6 Chip Erase is done when LOCKSTATUS == 0 in UPDIASI_SYS_STATUS If LOCKSTATUS == 1

go to point 5 again

After a successful Chip Erase the Lockbits will be cleared and the UPDI will have full access to thesystem Until Lockbits are cleared the UPDI cannot access the system bus and only CS-spaceoperations can be performed

Caution During Chip Erase the BOD is forced ON (ACTIVE=0x1 in BODCTRLA) and usesthe BOD Level from the BOD Configuration fuse (LVL in BODCTRLB = LVL inFUSEBODCFG) If the supply voltage VDD is below that threshold level the device isunserviceable until VDD is increased adequately

34572 NVM ProgrammingIf the device is unlocked it is possible to write directly to the NVM Controller by the UPDI - this will lead tounpredictable code execution if the CPU is active during the NVM programming To avoid this thefollowing NVM Programming sequence should be executed

1 Follow the Chiperase procedure as described in Chip Erase If the part is already unlocked thispoint can be skipped

2 Enter the NVMPROG KEY by using the KEY instruction See Table 34-6 for the NVMPROGsignature

3 Optional Read the KEY_STATUSNVMPROG field to see that the KEY has been activated4 Write the Reset signature into the ASI_RESET_REQ register This will issue a System Reset5 Write 0x00 to the Reset signature in ASI_RESET_REQ register to clear the System Reset6 Read ASI_SYS_STATUSNVMPROG7 NVM Programming can start when ASI_SYS_STATUSNVMPROG == 1 If

ASI_SYS_STATUSNVMPROG == 0 go to point 6 again8 Write data to NVM through the UPDI9 Write the Reset signature into the ASI_RESET_REQ register This will issue a System Reset10 Write 0x00 to the Reset signature in ASI_RESET_REQ register to clear the System Reset11 Programming is complete

34573 User Row ProgrammingThe User Row Programming feature allows the user to program new values to the User Row(USERROW) on a locked device even with access to the system bus blocked for the UPDI To programwith this functionality enabled the following sequence should be followed

1 Enter the USERROW-Write KEY located in Table 34-6 by using the KEY instruction See Table 34-6for the UROWWRITE signature

2 Optional Read the UROWWRITE bit field in UPDIASI_KEY_STATUS to see that the KEY hasbeen activated

3 Write the Reset signature into the UPDIASI_RESET_REQ register This will issue a System Reset4 Write 0x00 to the Reset signature in UPDIASI_RESET_REQ register to clear the System Reset5 Read UROWPROG bit in UPDIASI_SYS_STATUS6 User Row Programming can start when UROWPROG == 1 If UROWPROG == 0 go to point 5

again7 The writable area has a size of one EEPROM page byte and it is only possible to write User Row

data to the first 32 byte addresses of the RAM Addressing outside this memory range will result ina non executed write The data will map 11 with the User Row space when the data is copied intothe User Row upon completion of the Programming sequence

8 When all User Row data has been written to the RAM write the UROWWRITEFINAL bit inUPDIASI_SYS_CTRLA

9 Read the UROWPROG bit in UPDIASI_SYS_STATUS10 The User Row Programming is completed when UROWPROG == 0 If UROWPROG == 1 go to

point 9 again11 Write the UROWWRITE bit in UPDIASI_KEY_STATUS12 Write the Reset signature into the UPDIASI_RESET_REQ register This will issue a System Reset13 Write 0x00 to the Reset signature in UPDIASI_RESET_REQ register to clear the System Reset14 User Row Programming is complete

Note It is not possible to read back data from the SRAM in this mode Only writes to the first 32 bytes ofthe SRAM is allowed

34574 Activate OCD FeaturesTo open up for debug features like single stepping and breakpoints the OCD KEY must be correctlydecoded The following steps must be followed to activate OCD features

bull Enter the OCD KEY by using the KEY instruction See Table 34-6 for the OCD signaturebull Optional Read out the OCD bit in the ASI KEY Status register (UPDIASI_KEY_STATUS) to see

that the OCD KEY is successfully activated

After the OCD KEY is successfully decoded the UPDI have full access to OCD featuresNote The device must be unlocked by a successful Chiperase before any debug operations can bedone even with the OCD KEY decoded

34575 Enabling of 2-Wire ModeIn applications where it is desirable to have separate RX and TX Pins the UPDI 2-Wire option can beused This is still half-duplex operation with exactly the same communication protocol as in 1-Wire andthe same speed requirements The following steps must be followed to enable 2-Wire mode

bull Enter the 2-Wire Mode KEY by using the KEY instruction See Table 34-6 for the 2-Wire Modesignature

After the last byte of the KEY is transmitted 2-Wire Mode is enabled and ready to receive the nextinstruction

3458 EventsThe UPDI is connected to the Event System (EVSYS) as described in ASYNCCH0 ASYNCCH1ASYNCCH2 ASYNCCH3

The UPDI can generate the following output events

bull SYNCH Character Positive Edge Event

This Event is set on the UPDI clock for each detected positive edge in the SYNCH character and it is notpossible to disable this event from the UPDI The recommended application for this Event is system clockfrequency measurement through the UPDI Section System Clock Measurement with UPDI provides thedetails on how to setup the system for this operation

3459 Sleep Mode OperationThe UPDI physical layer runs independently of all sleep modes and the UPDI is always accessible for aconnected debugger independent of the device sleep mode If the system enters a sleep mode that turnsoff the CPU clock the UPDI will not be able to access the system bus and read memories and

peripherals Note that the UPDI physical layer clock is unaffected by the sleep mode settings as long asthe UPDI is enabled By reading the INSLEEP bit in UPDIASI_SYS_STATUS it is possible to monitor ifthe system domain is in sleep mode The INSLEEP bit is set if the system is in IDLE sleep mode ordeeper

It is possible to prevent the system clock from stopping when going into sleep mode by writing theCLKREQ bit in UPDIASI_SYS_CTRL to 1 If this bit is set the system sleep mode state is emulated andit is possible for the UPDI to access they system bus and read out peripheral registers even in thedeepest sleep modesNote CLKREQ in UPDIASI_SYS_CTRL is by default 1 which means that default operation is keepingthe system clock on during sleep modes

Offset Name Bit Pos

0x00 STATUSA 70 UPDIREV[30]

0x01 STATUSB 70 PESIG[20]

0x02 CTRLA 70 IBDLY TBEN PARD DTD RSD GTVAL[20]

0x03 CTRLB 70 NACKDIS CCDETDIS UPDIDIS PDRM[10]

0x04 ASI_OCD_CTRLA 70OCD_SOR_DI

SOCD_RUN OCD_STOP

0x05 ASI_OCD_STATUS 70 OCDMVOCD_STOPP

0x06 Reserved

0x07 ASI_KEY_STATUS 70 UROWWRITE NVMPROG CHIPERASE OCD

0x08 ASI_RESET_REQ 70 RSTREQ[70]

0x09 ASI_CTRLA 70 UPDICLKDIV[10]

0x0A ASI_SYS_CTRLA 70UROWWRITE

_FINALCLKREQ

0x0B ASI_SYS_STATUS 70 RSTSYS INSLEEP NVMPROG UROWPROG BOOTDONE LOCKSTATUS

0x0C ASI_CRC_STATUS 70 CRC_STATUS[20]

0x0DASI_OCD_MESSA

GE70 OCDM[70]

347 Register DescriptionThese registers are only readable through the PDI with special instructions and are NOT readablethrough the CPU

Registers at offset addresses 0x00-0x03 are the PDI Physical configuration registers

Registers at offset addresses 0x04-0xD are the ASI (PDI chip) level registers

3471 Status A

Name STATUSAOffset 0x00Reset 0x10Property

Bit 7 6 5 4 3 2 1 0 UPDIREV[30]

Bits 74 ndash UPDIREV[30] UPDI RevisionThese bits are read-only and contain the revision of the current UPDI implementation

3472 Status B

Name STATUSBOffset 0x01Reset 0x00Property

Bit 7 6 5 4 3 2 1 0 PESIG[20]

Bits 20 ndash PESIG[20] PDI Error SignatureThese bits describe the UPDI Error Signature created on any occurred Error The Errors can occur duringa transmission or if a system error occurs while the UPDI is in the IDLE state These bits are set by theUPDI upon any occurred error condition and cleared on read from the emulator

Table 34-7 Valid Error Signatures

PESIG[20] Error Type Error Description

0x0 No error No error detected (Default)

0x1 Parity error Wrong sampling of the parity bit

0x2 Frame error Wrong Sampling of frame stop bits

0x3 Access Layer Timeout Error UPDI can get no data or response from the Access layerExamples of error cases are system domain in sleep orsystem domain reset

0x4 Clock recovery error Wrong sampling of frame start bit

0x5 - Reserved

0x6 Reserved Reserved

0x7 Contention error Signalize Driving Contention on the PDI_DATA line

3473 Control A

Bit 7 6 5 4 3 2 1 0 IBDLY TBEN PARD DTD RSD GTVAL[20]

Bit 7 ndash IBDLY Inter-Byte Delay EnableWriting a 1 to this bit enables a fixed inter-byte delay between each data byte transmitted from the UPDIwhen doing multi-byte LD(S) The fixed length is two IDLE characters Note that before the firsttransmitted byte will use the regular GT delay used for direction change

Bit 6 ndash TBEN Transmit BREAK EnableWhen this bit is written to 1 the PDI can send a BREAK character to the Emulator when the CPUreaches a stop condition (SW Break HW Break) This bit only has effect if running in Power Debug orLive Debug Run on Disable modes set by the PDRM bits in PDICRH

Bit 5 ndash PARD Parity DisableWriting this bit to 1 will disable parity detection in the UPDI by just ignoring the Parity bit This feature isrecommended only during testing

Bit 4 ndash DTD Disable Timeout DetectionSetting this bit disables the timeout detection on the PHY layer which requests a response from the ACClayer within a specified time (65536 UPDI clock cycles)

Bit 3 ndash RSD Response Signature DisableWriting a 1 to this bit will disable any response signatures generated by the UPDI This is to reduce theprotocol overhead to a minimum when writing large blocks of data to the NVM space Note that it is notrecommended to disable this feature unless the UPDI clock and the system clock are the same and onlyduring device testing

Bits 20 ndash GTVAL[20] Guard Time ValueThis bit field selects the Guard Time Value that will be used by the UPDI when the transmission modeswitches from RX to TX The Guard time is equal to the Baud Rate used in 1W or 2W modes

Table 34-8 UPDI Guard Time Settings

GTVAL[20] UPDI Guard Time Cycles

0x0 128 (default value)

0x1 64

0x2 32

0x3 16

0x7 GT off (no extra Idle bits inserted)

3474 Control B

Bit 7 6 5 4 3 2 1 0 NACKDIS CCDETDIS UPDIDIS PDRM[10]

Bit 4 ndash NACKDIS Disable NACK ResponseWriting this bit to 1 disables the NACK signature sent by the UPDI if a System Reset is issued during anongoing LD(S) and ST(S) operation

Bit 3 ndash CCDETDIS Collision and Contention Detection DisableIf this bit is written to 0 contention detection is enabled for 1W mode This means that the PDI candetect a collision in an ongoing 1W transmission Contention detection is permanently disabled for 2Wmode as it has a separate TX-pin

Bit 2 ndash UPDIDIS UPDI DisableWriting a 1 to this bit disables the UPDI PHY interface The clock request from the UPDI is lowered andthe UPDI is reset All UPDI PHY configurations and KEYs will be reset when the UPDI is disabled

Bits 10 ndash PDRM[10] PDI Disable on Run ModeThese bits determine which mode the UPDI should enter when enabled the next time Writing these bitsare required for successfully entering PowerDebug and LiveDebug Modes For regular disable of theUPDI the PowerDebug option is recommended

Table 34-9 PDRM Selections

PDRM[20] PDI Disable on Run Modes

0x0 No-disable operation (default)

0x1 PowerDebug

0x2 LiveDebug

0x3 Reserved

3475 ASI On-Chip Debug Control A

Name ASI_OCD_CTRLAOffset 0x04Reset 0x00Property

Bit 7 6 5 4 3 2 1 0 OCD_SOR_DIS OCD_RUN OCD_STOP

Bit 7 ndash OCD_SOR_DIS OCD Stop on Reset DisableIf this bit is written to 1 the ldquoStop on Resetrdquo feature is disabled ldquoStop on Resetrdquo is used when the OCD isenabled and a System Reset occurs The OCD will then halt the CPU on the first instruction (after runningsystem boot) The cause of the OCD stopping can be read out through the OCD status register in theOCD domain

Bit 1 ndash OCD_RUN On-Chip Debug RunWhen this bit is written to 1 an OCD Run request is sent to the CPU By reading the ASI_OCD_STATUSregister it is possible to know when the CPU enters the RUN state (OCD_STOPPED is low) This bit isalso used during Single Step when the OCD system is set up accordingly

Bit 0 ndash OCD_STOP On-Chip Debug StopWhen this bit is written to 1 an OCD Stop request is sent to the CPU By reading the ASI_OCD_STATUSregister it is possible to know when the CPU reached the STOP state

Note For this field to have any effect Lockbits must be cleared and the system cannot be in active boot

3476 ASI On-Chip Debug Status

Name ASI_OCD_STATUSOffset 0x05Reset 0x00Property

Bit 7 6 5 4 3 2 1 0 OCDMV OCD_STOPPE

Bit 4 ndash OCDMV On-Chip Debug Message ValidIf this bit is written to 1 the message contained in the ASI_OCD_MESSAGE register is valid for theUPDI to read out This bit is cleared when the UPDI reads the ASI_OCD_MESSAGAE register

Bit 0 ndash OCD_STOPPED On-Chip Debug StoppedWhen this bit is written to 1 the CPU is in the stopped state If this bit is cleared the CPU is cleared theCPU is in the RUN state

3477 ASI Key Status

Name ASI_KEY_STATUSOffset 0x07Reset 0x00Property

Bit 7 6 5 4 3 2 1 0 UROWWRITE NVMPROG CHIPERASE OCD

Access R R R R Reset 0 0 0 0

Bit 5 ndash UROWWRITE User Row Write Key StatusThis bit is set to 1 if the UROWWRITE KEY is active Otherwise this bit reads as zero

Bit 4 ndash NVMPROG NVM ProgrammingThis bit is set to 1 if the NVMPROG KEY is active This bit is automatically reset after the programmingsequence is done Otherwise this bit reads as zero

Bit 3 ndash CHIPERASE Chip EraseThis bit is set to 1 if the CHIPERASE KEY is active This bit will automatically be reset when the chiperase sequence is completed Otherwise this bit reads as zero

Bit 1 ndash OCD On-Chip Debug Key StatusThis bit is set to 1 if the OCD KEY is successfully decoded and active Otherwise this bit reads as zero

3478 ASI Reset Request

Name ASI_RESET_REQOffset 0x08Reset 0x00Property

Bit 7 6 5 4 3 2 1 0 RSTREQ[70]

Bits 70 ndash RSTREQ[70] Reset RequestA Reset is signalized to the System when writing the Reset signature 0x59h to this address

Writing any other signature to this register will clear the Reset

Note 1 When reading this register reading bit RSTREQ[0] will tell if the UPDI is holding an active Reset on

the system If this bit is 1 the UPDI has an active Reset request to the system All other bits willread as 0

2 The UPDI will not be reset when issuing a System Reset from this register

3479 ASI Control A

Name ASI_CTRLAOffset 0x09Reset 0x02Property

Bit 7 6 5 4 3 2 1 0 UPDICLKDIV[10]

Bits 10 ndash UPDICLKDIV[10] UPDI Clock Divider SelectWriting these bits selects the prescaler setting for the UPDI internal oscillator (32MHz) Default setting atReset is 4MHz Any other prescaler settings is only recommended when the BOD is at the highest levelAt any other level the 8MHz prescaler should be used

Value Description0x0 No prescaling (32MHz)

0x1 Divide by 2 prescaling (16MHz)

0x3 Divide by 8 prescaling (4MHz) (Default Setting)

34710 ASI System Control A

Name ASI_SYS_CTRLAOffset 0x0AReset 0x00Property

Bit 7 6 5 4 3 2 1 0 UROWWRITE_

FINALCLKREQ

Bit 1 ndash UROWWRITE_FINAL User Row Programming DoneThis bit should be set by the UPDI when the user row programming is done The CPU will continue toprogress in the BOOT code when it detects that this bit is written

Note 1 If this bit is written before the User Row code is written to RAM by the UPDI the CPU will progress

without the written data2 This bit is only writable if the Userrow-write KEY is successfully decoded

Bit 0 ndash CLKREQ Request System ClockIf this bit is written to 1 the ASI is requesting the system clock independent of system sleep modes Thismakes it possible for the UPDI to access the ACC layer also if the system is in sleep mode

Writing a zero to this bit will lower the clock request

This bit will be reset when the UPDI is disabled

Note This bit is set by default when the UPDI is enabled in any mode (Fuse 12V)

34711 ASI System Status

Name ASI_SYS_STATUSOffset 0x0BReset 0x01Property

Bit 7 6 5 4 3 2 1 0 RSTSYS INSLEEP NVMPROG UROWPROG BOOTDONE LOCKSTATUS

Access R R R R R R Reset 0 0 0 0 0 1

Bit 5 ndash RSTSYS System Reset ActiveIf this bit is set there is an active Reset on the system domain If this bit is cleared the system is not inReset

This bit is cleared on read

Note A reset held from the ASI_RESET_REQ register will also affect this bit

Bit 4 ndash INSLEEP System Domain in SleepIf this bit is set the system domain is in IDLE or deeper sleep mode If this bit is cleared the system is notin sleep

Bit 3 ndash NVMPROG Start NVM ProgrammingIf this bit is set the CPU has signalized from the BOOT code that the NVM Programming can start fromthe UPDI

When the UPDI is done it must reset the system through the UPDI Reset Register

Bit 2 ndash UROWPROG Start User Row ProgrammingIf this bit is set the CPU has signalized from the BOOT code that User Row Programming can start fromthe UPDI

When the UPDI is done it must write the UROWWRITE_FINAL bit in ASI_SYS_CTRLA

Bit 1 ndash BOOTDONE Boot Sequence DoneThis bit is set when the CPU is done with the BOOT sequence The UPDI will not have regular access tothe ACC layer until this bit is set

Bit 0 ndash LOCKSTATUS NVM Lock StatusIf this bit is set the device is locked If a Chiperase is done and the Lockbits are cleared this bit will readas zero

34712 ASI CRC Status

Name ASI_CRC_STATUSOffset 0x0CReset 0x00Property

Bit 7 6 5 4 3 2 1 0 CRC_STATUS[20]

Bits 20 ndash CRC_STATUS[20] CRC Execution StatusThese bits signalize the status of the CRC conversion The bits are one-hot encoded

Value Description0x0 Not enabled

0x1 CRC enabled busy

0x2 CRC enabled done with OK signature

0x3 CRC enabled done with FAILED signature

34713 ASI On-Chip Debug Message

Name ASI_OCD_MESSAGEOffset 0x0DReset 0x00Property

Bit 7 6 5 4 3 2 1 0 OCDM[70]

Bits 70 ndash OCDM[70] On-Chip Debug MessageThis register is used for byte-wise communication between the UPDI and CPU It is only readable by theUPDI The UPDI can poll the OCDMV bit in the ASI_OCD_STATUS register to know when the CPU haswritten a new message

35 Instruction Set SummaryMnemonics Operands Description Operation Flags Clocks

Arithmetic and Logic Instructions

ADD Rd Rr Add without Carry Rd larr Rd + Rr ZCNVSH 1

ADC Rd Rr Add with Carry Rd larr Rd + Rr + C ZCNVSH 1

ADIW Rd K Add Immediate to Word Rd larr Rd + 1Rd + K ZCNVS 2

SUB Rd Rr Subtract without Carry Rd larr Rd - Rr ZCNVSH 1

SUBI Rd K Subtract Immediate Rd larr Rd - K ZCNVSH 1

SBC Rd Rr Subtract with Carry Rd larr Rd - Rr - C ZCNVSH 1

SBCI Rd K Subtract Immediatewith Carry

Rd larr Rd - K - C ZCNVSH 1

SBIW Rd K Subtract Immediatefrom Word

Rd + 1Rd larr Rd + 1Rd - K ZCNVS 2

AND Rd Rr Logical AND Rd larr Rd bull Rr ZNVS 1

ANDI Rd K Logical AND withImmediate

Rd larr Rd bull K ZNVS 1

OR Rd Rr Logical OR Rd larr Rd v Rr ZNVS 1

ORI Rd K Logical OR withImmediate

Rd larr Rd v K ZNVS 1

EOR Rd Rr Exclusive OR Rd larr Rd oplus Rr ZNVS 1

COM Rd Onersquos Complement Rd larr $FF - Rd ZCNVS 1

NEG Rd Tworsquos Complement Rd larr $00 - Rd ZCNVSH 1

SBR RdK Set Bit(s) in Register Rd larr Rd v K ZNVS 1

CBR RdK Clear Bit(s) in Register Rd larr Rd bull ($FFh - K) ZNVS 1

INC Rd Increment Rd larr Rd + 1 ZNVS 1

DEC Rd Decrement Rd larr Rd - 1 ZNVS 1

TST Rd Test for Zero or Minus Rd larr Rd bull Rd ZNVS 1

CLR Rd Clear Register Rd larr Rd oplus Rd ZNVS 1

SER Rd Set Register Rd larr $FF None 1

MUL RdRr Multiply Unsigned R1R0 larr Rd x Rr (UU) ZC 2

MULS RdRr Multiply Signed R1R0 larr Rd x Rr (SS) ZC 2

MULSU RdRr Multiply Signed withUnsigned

R1R0 larr Rd x Rr (SU) ZC 2

FMUL RdRr Fractional MultiplyUnsigned

R1R0 larr Rd x Rrltlt1(UU)

Mnemonics Operands Description Operation Flags Clocks

FMULS RdRr Fractional MultiplySigned

R1R0 larr Rd x Rrltlt1(SS)

FMULSU RdRr Fractional MultiplySigned with Unsigned

R1R0 larr Rd x Rrltlt1(SU)

Branch instructions

RJMP k Relative Jump PC larr PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC larrlarr

Z None 2

EIJMP Extended Indirect Jumpto (Z)

PC larrlarr

Z None 2(3)

JMP k Jump PC larr k None 3

RCALL k Relative CallSubroutine

PC larr PC + k + 1 None 2

ICALL Indirect Call to (Z) PC larrlarr

Z None 2

EICALL Extended Indirect Callto (Z)

PC larrlarr

Z None 2(3)

CALL k call Subroutine PC larr k None 3

RET Subroutine Return PC larr STACK None 4

RETI Interrupt Return PC larr STACK I 4

CPSE RdRr Compare Skip if Equal if (Rd = Rr) PC larr PC + 2 or 3 None 1 2 3

CP RdRr Compare Rd - Rr ZCNVSH 1

CPC RdRr Compare with Carry Rd - Rr - C ZCNVSH 1

CPI RdK Compare withImmediate

Rd - K ZCNVSH 1

SBRC Rr b Skip if Bit in RegisterCleared

if (Rr(b) = 0) PC larr PC + 2 or 3 None 1 2 3

SBRS Rr b Skip if Bit in RegisterSet

SBIC A b Skip if Bit in IORegister Cleared

if (IO(Ab) = 0)PC

larr PC + 2 or 3 None 1 2 3

SBIS A b Skip if Bit in IORegister Set

If (IO(Ab) =1)PC

BRBS s k Branch if Status FlagSet

if (SREG(s) = 1)then PC

larr PC + k + 1 None 1 2

BRBC s k Branch if Status FlagCleared

BREQ k Branch if Equal if (Z = 1) then PC larr PC + k + 1 None 1 2

BRNE k Branch if Not Equal if (Z = 0) then PC larr PC + k + 1 None 1 2

BRCS k Branch if Carry Set if (C = 1) thenPC

BRCC k Branch if Carry Cleared if (C = 0) thenPC

BRSH k Branch if Same orHigher

if (C = 0) thenPC

BRLO k Branch if Lower if (C = 1) thenPC

BRMI k Branch if Minus if (N = 1) thenPC

BRPL k Branch if Plus if (N = 0) thenPC

BRGE k Branch if Greater orEqual Signed

if (N oplus V= 0)then PC

BRLT k Branch if Less ThanSigned

BRHS k Branch if Half CarryFlag Set

if (H = 1) thenPC

BRHC k Branch if Half CarryFlag Cleared

if (H = 0) thenPC

BRTS k Branch if T Flag Set if (T = 1) then PC larr PC + k + 1 None 1 2

BRTC k Branch if T FlagCleared

if (T = 0) then PC larr PC + k + 1 None 1 2

BRVS k Branch if Overflow Flagis Set

if (V = 1) thenPC

BRVC k Branch if Overflow Flagis Cleared

if (V = 0) thenPC

BRIE k Branch if InterruptEnabled

if (I = 1) then PC larr PC + k + 1 None 1 2

BRID k Branch if InterruptDisabled

Data transfer instructions

MOV Rd Rr Copy Register Rd larr Rr None 1

MOVW Rd Rr Copy Register Pair Rd+1Rd larr Rr+1Rr None 1

LDI Rd K Load Immediate Rd larr K None 1

LDS Rd k Load Direct from dataspace

Rd larr (k) None 3(1)

LD Rd X Load Indirect Rd larr (X) None 2(1)

LD Rd X+ Load Indirect and Post-Increment

larrlarr

(X)X + 1

None 2(1)

LD Rd -X Load Indirect and Pre-Decrement

X larr X - 1Rd larr (X)

larrlarr

X - 1(X)

None 2(1)

LD Rd Y Load Indirect Rd larr (Y) larr (Y) None 2(1)

LD Rd Y+ Load Indirect and Post-Increment

larrlarr

(Y)Y + 1

None 2(1)

LD Rd -Y Load Indirect and Pre-Decrement

larrlarr

Y - 1(Y)

None 2(1)

LDD Rd Y+q Load Indirect withDisplacement

Rd larr (Y + q) None 2(1)

LD Rd Z Load Indirect Rd larr (Z) None 2(1)

LD Rd Z+ Load Indirect and Post-Increment

larrlarr

(Z)Z+1

None 2(1)

LD Rd -Z Load Indirect and Pre-Decrement

larrlarr

Z - 1(Z)

None 2(1)

LDD Rd Z+q Load Indirect withDisplacement

Rd larr (Z + q) None 2(1)

STS k Rr Store Direct to DataSpace

(k) larr Rd None 2(1)(2)

ST X Rr Store Indirect (X) larr Rr None 1(1)(2)

ST X+ Rr Store Indirect and Post-Increment

larrlarr

RrX + 1

None 1(1)(2)

ST -X Rr Store Indirect and Pre-Decrement

larrlarr

X - 1Rr

None 1(1)(2)

ST Y Rr Store Indirect (Y) larr Rr None 1(1)(2)

ST Y+ Rr Store Indirect and Post-Increment

larrlarr

RrY + 1

None 1(1)(2)

ST -Y Rr Store Indirect and Pre-Decrement

larrlarr

Y - 1Rr

None 1(1)(2)

STD Y+q Rr Store Indirect withDisplacement

(Y + q) larr Rr None 1(1)(2)

ST Z Rr Store Indirect (Z) larr Rr None 1(1)(2)

ST Z+ Rr Store Indirect and Post-Increment

larrlarr

RrZ + 1

None 1(1)(2)

ST -Z Rr Store Indirect and Pre-Decrement

Z larr Z - 1 None 1(1)(2)

STD Z+qRr Store Indirect withDisplacement

(Z + q) larr Rr None 1(1)(2)

LPM Load Program Memory R0 larr (Z) None 2(1)

LPM Rd Z Load Program Memory Rd larr (Z) None 2(1)

LPM Rd Z+ Load Program Memoryand Post-Increment

larrlarr

(Z)Z + 1

None 2(1)

ELPM Extended LoadProgram Memory

R0 larr (Z) None 2(1)(3)

ELPM Rd Z Extended LoadProgram Memory

Rd larr (Z) None 2(1)(3)

ELPM Rd Z+ Extended LoadProgram Memory andPost-Increment

larrlarr

(Z)Z + 1

None 2(1)(3)

IN Rd A In From IO Location Rd larr IO(A) None 1

OUT A Rr Out To IO Location IO(A) larr Rr None 1

PUSH Rr Push Register on Stack STACK larr Rr None 1

POP Rd Pop Register fromStack

Rd larr STACK None 2

Bit and bit-test instructions

LSL Rd Logical Shift Left Rd(n+1)Rd(0)

larrlarrlarr

Rd(n)0Rd(7)

ZCNVH 1

LSR Rd Logical Shift Right Rd(n)Rd(7)

larrlarrlarr

Rd(n+1)0Rd(0)

ZCNV 1

ROL Rd Rotate Left ThroughCarry

Rd(0)Rd(n+1)

larrlarrlarr

CRd(n)Rd(7)

ZCNVH 1

ROR Rd Rotate Right ThroughCarry

Rd(7)Rd(n)

larrlarrlarr

CRd(n+1)Rd(0)

ZCNV 1

ASR Rd Arithmetic Shift Right Rd(n) larr Rd(n+1) n=06 ZCNV 1

SWAP Rd Swap Nibbles Rd(30) harr Rd(74) None 1

BSET s Flag Set SREG(s) larr 1 SREG(s) 1

BCLR s Flag Clear SREG(s) larr 0 SREG(s) 1

SBI A b Set Bit in IO Register IO(A b) larr 1 None 1

CBI A b Clear Bit in IO Register IO(A b) larr 0 None 1

BST Rr b Bit Store from Registerto T

T larr Rr(b) T 1

BLD Rd b Bit load from T toRegister

Rd(b) larr T None 1

SEC Set Carry C larr 1 C 1

CLC Clear Carry C larr 0 C 1

SEN Set Negative Flag N larr 1 N 1

CLN Clear Negative Flag N larr 0 N 1

SEZ Set Zero Flag Z larr 1 Z 1

CLZ Clear Zero Flag Z larr 0 Z 1

SEI Global Interrupt Enable I larr 1 I 1

CLI Global Interrupt Disable I larr 0 I 1

SES Set Signed Test Flag S larr 1 S 1

CLS Clear Signed Test Flag S larr 0 S 1

SEV Set Tworsquos ComplementOverflow

V larr 1 V 1

CLV Clear TworsquosComplement Overflow

V larr 0 V 1

SET Set T in SREG T larr 1 T 1

CLT Clear T in SREG T larr 0 T 1

SEH Set Half Carry Flag inSREG

H larr 1 H 1

CLH Clear Half Carry Flag inSREG

H larr 0 H 1

MCU control instructions

BREAK Break (See specific descr for BREAK) None 1

NOP No Operation None 1

SLEEP Sleep (see specific descr for Sleep) None 1

WDR Watchdog Reset (see specific descr for WDR) None 1

1 Cycle times for data memory accesses assume internal RAM access and are not valid for accessesthrough the NVM controller A minimum of one extra cycle must be added when accessing memorythrough the NVM controller (such as Flash and EEPROM) but depending on simultaneous accesses byother masters or the NVM controller state there may be more than one extra cycle

2 One extra cycle must be added when accessing lower (64 bytes of) IO space

3 Instruction behaviour identical to instruction variant without E prefix

36 Electrical Characteristics

361 DisclaimerAll typical values are measured at T = 25degC unless otherwise specified All minimum and maximumvalues are valid across operating temperature and voltage unless otherwise specified

362 Absolute Maximum RatingsStresses beyond those listed in this section may cause permanent damage to the device This is a stressrating only and functional operation of the device at these or other conditions beyond those indicated inthe operational sections of this specification is not implied Exposure to absolute maximum ratingconditions for extended periods may affect device reliability

Table 36-1 Absolute Maximum Ratings

Symbol Description Conditions

Min Max Units

VDD Power Supply Voltage -05 6 V

IVDD Current into a VDD pin T=-40+85degC

- 200 mA

T=-+85+125degC

- 100 mA

IGND Current out of a GND pin T=-40+85degC

- 200 mA

T=-+85+125degC

- 100 mA

Vrst RESET pin voltage with respect toGND

-05 13 V

VPIN Pin voltage with respect to GND -05 VDD+05V V

IPIN IO pin sinksource current -40 40 mA

Ic IO pin injection current exceptRESET pin

-20 20 mA

Tstorage Storage temperature -65 150 degC

Caution This device is sensitive to electrostatic discharges (ESD) Improper handling maylead to permanent performance degradation or malfunctioningHandle the device following best practice ESD protection rules Be aware that the human bodycan accumulate charges large enough to impair functionality or destroy the device

363 General Operating RatingsThe device must operate within the ratings listed in this section in order for all other electricalcharacteristics and typical characteristics of the device to be validTable 36-2 General Operating Conditions

Symbol Description Condition Min Max Units

VDD Operating Supply Voltage 18(2) 55 V

VRAM Power Supply Voltage to guarantee SRAMretention

09 55 V

T Operating Temperature range Standard temperaturerange(1)

-40 105 degC

Extended temperaturerange(1)

-40 125

Note 1 Please refer to the device ordering code for the device temperature range2 Operation guaranteed down to 18V or VBOD with BODLEVEL=18V whichever is lower

Symbol Description Condition min max Unit

CLKSYS Operating system clock frequency VDD=1855VT=-40105degC(1)

0 5 MHz

VDD=2755VT=-40105degC(2)

VDD=4555VT=-40105degC(3)

VDD=2755VT=-40125degC(2)

VDD=4555VT=-40125C(3)

Note 1 Operation guaranteed down to BOD triggering level VBOD with BODCTRLB LVL=18V2 Operation guaranteed down to BOD triggering level VBOD with BODCTRLB LVL=287V3 Operation guaranteed down to BOD triggering level VBOD with BODCTRLB LVL=43V

The maximum CPU clock frequency depends on VDD As shown in the following figure the MaximumFrequency vs VDD is linear between 18VltVDDlt27V and 27VltVDDlt45V

18V 27V 45V

Safe Operating Area

364 Voltage ProtectionTable 36-3 Power Supply Characteristics

Symbol Description Condition Min Typ Max Unit

SRON Power-on Slope Rate 001 - 100 Vms

Table 36-4 Power On Reset (POR) Characteristics

VPOR POR threshold voltage on VDDfalling

VDD fallsrises at 05Vms or slower 080 - 160 V

POR threshold voltage on VDDrising

140 - 170

Table 36-5 Brownout Detection (BOD) Characteristics

VBOD BOD triggering level (fallingrising)

BODLEVEL7 (430V) 41 - 45 V

BODLEVEL2 (250V) 24 - 29

BODLEVEL0 (180V) 17 - 20

VINT Interrupt level 0 Percentage above to the selectedBOD level

Interrupt level 1 - 15 -

VHYS Hysteresis BODLEVEL7 (43V) - TBD - mV

BODLEVEL2 (25V) - TBD -

TBOD Detection time(1) Continuous - 7 - micros

Sampled 1kHz - 1 - ms

Sampled 125 Hz - 8 -

Tstart Startup time Time from enable to ready - 40 - micros

Note 1 Tfall 1VmicroS 100mV below BOD level

37 Typical Characteristics

371 Power Consumption

ACTIVE Supply CurrentFigure 37-1 ACTIVE SUPPLY CURRENT vs FREQUENCY

1 6 11 16

Frequency [MHz]

Figure 37-2 ACTIVE SUPPLY CURRENT vs VDD INTERNAL RC OSCILLATOR 20MHz

4 42 44 46 48 5 52 54 56

VDD [V]

105degC

85degC

25degC

-20degC

2 25 3 35 4 45 5 55 6I D

VDD [V]

105degC

85degC

25degC

-20degC

0 1 2 3 4 5 6

VDD [V]

105degC

85degC

25degC

-20degC

Figure 37-5 ACTIVE SUPPLY CURRENT vs VDD INTERNAL RC OSCILLATOR 32kHz

15 2 25 3 35 4 45 5 55

VDD [V]

25degC

IDLE Supply CurrentFigure 37-6 IDLE SUPPLY CURRENT vs FREQUENCY

0 5 10 15 20 25

Frequency [MHz]

Figure 37-7 IDLE SUPPLY CURRENT vs VDD INTERNAL RC OSCILLATOR 20MHz

4 42 44 46 48 5 52 54 56

VDD [V]

105degC

85degC

25degC

-20degC

0 1 2 3 4 5 6

VDD [V]

105degC

85degC

25degC

-20degC

POWER-DOWN Supply CurrentFigure 37-9 POWER-DOWN SUPPLY CURRENT vs VDD

0 1 2 3 4 5 6

[microA

VDD [V]

105degC

85degC

25degC

-20degC

Note Watchdog Timer (WDT) disabled

STANDBY Supply CurrentFigure 37-10 STANDBY SUPPLY CURRENT vs VDD

0 1 2 3 4 5 6

[microA

VDD [V]

105degC

85degC

25degC

-20degC

Note All functions off

Figure 37-11 STANDBY SUPPLY CURRENT vs VDD

0 1 2 3 4 5 6

[microA

VDD [V]

105degC

85degC

25degC

-20degC

Note BOD sampled at 125Hz

0 1 2 3 4 5 6

[microA

VDD [V]

105degC

85degC

25degC

-20degC

Note BOD sampled at 1kHz

0 1 2 3 4 5 6

[microA

VDD [V]

105degC

85degC

25degC

-20degC

Note RTC on OSC32K BOD off

38 Package Drawings

381 WARNING

Warning Note that the package types are final but the dimensions might slightly change

382 14-pin SOIC150

TITLE DRAWING NO REV Package Drawing Contactpackagedrawingsatmelcom

14S1 14-lead 0150 Wide Body Plastic GullWing Small Outline Package (SOIC)

14S1 A

Side View

Top View End View

COMMON DIMENSIONS(Unit of Measure = mminches)

SYMBOL MIN NOM MAX NOTE

Notes 1 This drawing is for general information only refer to JEDEC Drawing MS-012 Variation AB for additional information2 Dimension D does not include mold Flash protrusions or gate burrs Mold Flash protrusion and gate burrs shall not

exceed 015 mm (0006) per side 3 Dimension E does not include inter-lead Flash or protrusion Inter-lead f ash and protrusions shall not exceed 025 mm

(0010) per side 4 L is the length of the terminal for soldering to a substrate 5 The lead width B as measured 036 mm (0014) or greater above the seating plane shall not exceed a maximum value

of 061 mm (0024) per side

A 13500532 ndash 17500688

A1 010040 ndash 02500098

b 03300130 ndash 0500200 5

D 85503367 ndash 87403444 2

E 3801497 ndash 39901574 3

H 5802284 ndash 61902440

L 04100160 ndash 12700500 4

e 1270050 BSC

383 20-pin SOIC300

384 20-pin VQFN

385 24-pin QFN

Package Drawing Contactpackagedrawingsatme lcom

ZHA POD_ZHA_05 A

DRAWING NO REVGPC

POD_ZHA_05_QFN_24

O JUNESCH June 26 2016

Top View

Bottom View

7 1213

Side View

Exposed pad 26x26Package QFN_4x4_24L

COMMON DIMENSIONS( Unit of Measure = mm )

A 08 085 09A1 00 0035 005A3 016 021 026D 39 4 41

D2 25 26 27E 39 4 41

E2 25 26 27L 035 04 045b 02 025 03e 05

specifica tionsa ccording to DINtechnica l drawings

39 Datasheet Revision HistoryNote The datasheet revision is independent of the die revision and the device variant (last letter of theordering number)

391 RevA - 092016Initial release

Atmel Corporation 1600 Technology Drive San Jose CA 95110 USA T (+1)(408) 4410311 F (+1)(408) 4364200 | wwwatmelcom

copy 2016 Atmel Corporation Rev Atmel-42721A-ATtiny417814816817_Datasheet_Advance Information-092016

Atmelreg Atmel logo and combinations thereof Enabling Unlimited Possibilitiesreg AVRreg QTouchreg and others are registered trademarks or trademarks of AtmelCorporation in US and other countries Other terms and product names may be trademarks of others

DISCLAIMER The information in this document is provided in connection with Atmel products No license express or implied by estoppel or otherwise to anyintellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN THE ATMEL TERMS ANDCONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIEDOR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITYFITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECTCONSEQUENTIAL PUNITIVE SPECIAL OR INCIDENTAL DAMAGES (INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS AND PROFITS BUSINESSINTERRUPTION OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISEDOF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of thisdocument and reserves the right to make changes to specifications and products descriptions at any time without notice Atmel does not make any commitment toupdate the information contained herein Unless specifically provided otherwise Atmel products are not suitable for and shall not be used in automotiveapplications Atmel products are not intended authorized or warranted for use as components in applications intended to support or sustain life

SAFETY-CRITICAL MILITARY AND AUTOMOTIVE APPLICATIONS DISCLAIMER Atmel products are not designed for and will not be used in connection with anyapplications where the failure of such products would reasonably be expected to result in significant personal injury or death (ldquoSafety-Critical Applicationsrdquo) withoutan Atmel officers specific written consent Safety-Critical Applications include without limitation life support devices and systems equipment or systems for theoperation of nuclear facilities and weapons systems Atmel products are not designed nor intended for use in military or aerospace applications or environmentsunless specifically designated by Atmel as military-grade Atmel products are not designed nor intended for use in automotive applications unless specificallydesignated by Atmel as automotive-grade

Introduction

Features

Table of Contents

1 Configuration Summary

21 ATtiny81x

22 ATtiny41x

3 Block Diagram

4 Pinout

41 24-pin QFN

42 20-pin QFN

43 20-pin SOIC

44 14-pin SOIC


51 Multiplexed Signals

6 Memories

61 Overview

62 Memory Map

63 In-System Reprogrammable Flash Program Memory

64 SRAM Data Memory

65 EEPROM Data Memory

66 User Row

67 IO Memory




6821 Device ID n








6844 Timer Counter Type D Configuration




6848 Boot End

6849 Lock Bits


71 Peripheral Module Address Map

72 Interrupt Vector Mapping


81 Overview


821 External Break

8211 Sending HALT and RESTART commands

8212 External BREAK Protocol




841 Device Revision ID Register

842 External Break Register

9 AVR CPU

91 Overview

92 Features

93 Architecture

94 ALU - Arithmetic Logic Unit

941 Hardware Multiplier


951 Program Flow

952 Instruction Execution Timing

953 Status Register

954 Stack and Stack Pointer

955 Register File

9551 The X- Y- and Z- Registers

956 Accessing 16-bit Registers

957 CCP - Configuration Change Protection

9571 Sequence for Write Operation to Configuration Change Protected IO Registers

9572 Sequence for Execution of Self-Programming

96 Register Summary



972 Stack Pointer

973 Status Register


101 Overview

102 Features

103 Block Diagram

104 Product Dependencies

1041 Clocks

1042 IO Lines and Connections

1043 Interrupts

1044 Events

1045 Debug Operation


1051 FlashEEPROM Memory Organization

1052 User Page

1053 Read

1054 Write Operation

10541 Write Flash

10542 EEPROM Write

1055 Commands

10551 Write Command

10552 Erase Command

10553 Erase-Write Operation

10554 Page Buffer Clear Command

10555 Chip Erase Command

10556 EEPROM Erase Command

10557 Fuse Write Command

1056 Flash Write Protection

1057 Interrupts

1058 Sleep Mode Operation




1071 Control A

1072 Control B

1073 Status



1076 Data

1077 Address


111 Overview

112 Features

113 Block Diagram - CLKCTRL



1151 Principle of Operation


1153 Main Clock Selection and Prescaler


1155 Clock Sources

11551 Internal Oscillators

115511 1620MHz Oscillator (OSC20M)

115512 32KHz Oscillator (OSCULP32K)

11552 External Clock Sources

115521 32768kHz Crystal Oscillator (XOSC32K)

115522 External Clock (EXTCLK)












1179 32768kHz Crystal Oscillator Control A


121 Overview

122 Features

123 Block Diagram


1241 Clocks


1243 Interrupts

1244 Events




1252 Sleep Modes


12531 Initialization

12532 Wake-Up Time




1271 Control A


131 Overview

132 Features

133 Block Diagram






13522 Reset Sources

135221 Power-On Reset (POR)

135222 Brownout Detector (BOD) Reset Source

135223 Software Reset

135224 External Reset

135225 Watchdog Reset

135226 Universal Program Debug Interface (UPDI) Reset





1371 Reset Flag Register



141 Overview

142 Features

143 Block Diagram



1451 Clocks


1453 Interrupts

1454 Events






14622 Enabling Disabling and Resetting

14623 Interrupt Vector Locations

14624 Interrupt Response Time


14631 NMI - Non-Maskable Interrupts

14632 Static Priority

14633 Round-Robin Scheduling

14634 Compact Vector Table

1464 Events





1481 Control A

1482 Status




151 Overview

152 Features

153 Block Diagram



1551 Clocks


1553 Interrupts

1554 Events






15622 Event User Multiplexer Setup

15623 Event System Channel

15624 Event Generators

15625 Software Event

1563 Interrupts


1565 Synchronization











161 Overview




1641 Control A

1642 Control B

1643 Control C

1644 Control D


171 Overview

172 Features

173 Block Diagram



1751 Clocks


1753 Interrupts

1754 Events






17622 Basic Functions

1763 Virtual Ports

1764 Pin Configuration

1765 Interrupts






1781 Data Direction




1785 Output Value




1789 Input Value


17811 Pin n Control




17102 Output Value

17103 Input Value



181 Overview

182 Features

183 Block Diagram


1841 Clocks


1843 Interrupts

1844 Events






1853 Interrupts






1871 Control A

1872 Control B

1873 VLM Control A



1876 VLM Status


191 Overview

192 Features

193 Block Diagram


1941 Principal of Operation





1961 Control A

1962 Control B


201 Overview

202 Features

203 Block Diagram



2051 Clocks


2053 Interrupts

2054 Events






20622 Normal Mode

20623 Window Mode

2063 Configuration Protection and Lock

2064 Events

2065 Interrupts






2081 Control A

2082 Status


211 Overview

212 Features

213 Block Diagram



2151 Clocks


2153 Interrupts

2154 Events





21621 Definitions


21623 Normal Operation

21624 Double Buffering

21625 Changing the Period

21626 Compare Channel

216261 Waveform Generation

216262 Frequency (FRQ) Waveform Generation

216263 Single-Slope PWM Generation

216264 Dual-slope PWM

216265 Port Override for Waveform Generation

21627 TimerCounter Commands


2163 Events

2164 Interrupts





2181 Control A



2184 Control D

2185 Control Register E Clear - Normal Mode

2186 Control Register E Set - Normal Mode

2187 Control Register F Clear

2188 Control Register F Set

2189 Event Control


21811 Interrupt Flag Register - Normal Mode


21813 Temporary bits for 16-bit Access

21814 Counter Register - Normal Mode

21815 Period Register - Normal Mode

21816 Compare n Register - Normal Mode

21817 Period Buffer Register

21818 Compare n Buffer Register



21101 Control A



21104 Control D

21105 Control Register E Clear - Split Mode

21106 Control Register E Set - Split Mode


21108 Interrupt Flag Register - Split Mode


211010 Low-byte Timer Counter Register - Split Mode

211011 High-byte Timer Counter Register - Split Mode

211012 Low-byte Timer Period Register - Split Mode

211013 High-byte Period Register - Split Mode

211014 Compare Register n for low-byte Timer - Split Mode

211015 High-byte Compare Register n - Split Mode


221 Overview

222 Features

223 Block Diagram



2251 Clocks


2253 Interrupts

2254 Events





22621 Definitions


22623 Modes

226231 Periodic Interrupt Mode

226232 Timeout Check Mode

226233 Input Capture on Event

226234 Input Capture Frequency Measurement

226235 Input Capture Pulse Width Measurement

226236 Input Capture Frequency and Pulse Width Measurement

226237 Single-Shot Mode

226238 8-bit PWM Mode

22624 Synchronous Output

22625 Asynchronous Output

22626 Noise Canceller

2263 Synchronized with TCA

2264 Events

2265 Interrupts






2281 Control A

2282 Control B

2283 Event Control



2286 Status

2287 Debug Control

2288 Temporary Value

2289 Count

22810 Capture


231 Overview

232 Features

233 Block Diagram



2351 Clocks


2353 Interrupts

2354 Events





23621 Initialization and Disabling

23622 Register Synchronization Categories

23623 Wave Generation Modes

236231 One Ramp Mode

236232 Two Ramp Mode

236233 Four Ramp Mode

236234 Dual Slope Mode

23624 TCD Inputs

236241 Input Blanking

236242 Digital Filter

236243 Asynchronous Event Detection

236244 Input Modes

2362441 Input Mode 1 Stop Signal Jump to Opposite Dead-Time and Wait

2362442 Input Mode 2 Stop Signal Execute Opposite Dead and on Time and Wait

2362443 Input Mode 3 Stop Signal Execute Opposite Dead Time and On Time while Fault is Active

2362444 Input Mode 4 Deactivate Outputs without Changing Timing

2362445 Input Mode 5 Stop Signal Insert Dead Time

2362446 Input Mode 6 Stop Signal Jump to Next Dead Time and Wait

2362447 Input Mode 7 Stop Signals andTCD Counter Wait for Software Restart

2362448 Input Mode 8 Input Edge RetriggerTCD

2362449 Input Mode 9 Fix Frequency Edge Retrigger

23624410 Input Mode 10 Fixed Frequency Input Deactivate Output

23625 Clock Selection and Prescalers

23626 TCD Dithering

23627 TCD Counter Capture

23628 Output Control

2363 Events

23631 Programmable output events

2364 Interrupts






2381 Control A

2382 Control B

2383 Control C

2384 Control D

2385 Control E




2389 Status


23811 Fault Control

23812 Delay Control

23813 Delay Value


23815 Dither Value

23816 Debug Control

23817 Capture x Low byte

23818 Capture x High byte

23819 Compare x Set Low byte

23820 Compare x Set High byte

23821 Compare x Clear Low byte

23822 Compare x Clear High byte


241 Overview

242 Features

243 Block Diagram



2451 Clocks


2453 Interrupts

2454 Events


246 RTC Functional Description





247 PIT Functional Description





248 Events

249 Interrupts






24141 Control A

24142 Status



24145 Temporary

24146 Debug Control

24147 Clock Control

24148 Count

24149 Top

241410 Compare






25 USART - Universal Synchronous and Asynchronous Receiver and Transmitter

251 Overview

252 Features

253 Block Diagram



2551 Clocks


2553 Interrupts

2554 Events






25622 Clock Generation

256221 Internal Clock Generation - The Fractional Baud Rate Generator

256222 External Clock

256223 Double Speed Operation

256224 Synchronous Clock Operation

256225 Master SPI Mode Clock Generation

25623 Frame Formats

256231 Parity

256232 SPI Frame Formats

25624 Data Transmission - USART Transmitter

256241 Sending Frames

256242 Disabling the Transmitter

25625 Data Reception - USART Receiver

256251 Receiving Frames

256252 Receiver Error Flags

256253 Parity Checker

256254 Disabling the Receiver

256255 Flushing the Receive Buffer

256256 Asynchronous Data Reception

2562561 Asynchronous Clock Recovery

2562562 Asynchronous Data Recovery

256257 Asynchronous Operational Range


25631 USART in Master SPI mode

256311 USART SPI vs SPI

25632 RS485 Mode of Operation

25633 Start Frame Detection

25634 Break Character Detection and Auto-baud

25635 One-wire Mode

25636 Multiprocessor Communication Mode

256361 Using Multiprocessor Communication Mode

25637 IRCOM Mode of Operation

2564 Events

2565 Interrupts




2581 Receiver Data Register Low Byte

2582 Receiver Data Register High Byte

2583 Transmit Data Register Low Byte

2584 Transmit Data Register High Byte


2586 Control A

2587 Control B

2588 Control C

2589 Control C

25810 Baud Register






261 Overview

262 Features

263 Block Diagram



2651 Clocks


2653 Interrupts

2654 Events






26622 Master Mode Operation

26623 Slave Mode

26624 Buffer Modes

26625 Data Modes

2663 Interrupts





2681 Control A

2682 Control B



2685 Data


271 Overview

272 Features

273 Block Diagram



2751 Clocks


2753 Interrupts

2754 Events




27611 General TWI Bus Concepts

276111 START and STOP Conditions

276112 Bit Transfer

276113 Address Packet

276114 Data Packet

276115 Transaction

276116 Clock and Clock Stretching

276117 Arbitration


27612 TWI Bus State Logic




27623 TWI Master Operation

276231 Transmitting Address Packets

2762311 Case M1 Arbitration Lost or Bus Error during Address Packet

2762312 Case M2 Address Packet Transmit Complete - Address not Acknowledged by Slave

2762313 Case M3 Address Packet Transmit Complete - Direction Bit Cleared

2762314 Case M4 Address Packet Transmit Complete - Direction Bit Set

276232 Transmitting Data Packets

276233 Receiving Data Packets

27624 TWI Slave Operation

276241 Receiving Address Packets

2762411 Case S1 Address Packet Accepted - Direction Bit Set

2762412 Case S2 Address Packet Accepted - Direction Bit Cleared

2762413 Case S3 Collision

2762414 Case S4 STOP Condition Received



2763 Events

2764 Interrupts






2781 Control A

2782 Debug Control



2785 Master Status


2787 Master Address

2788 Master DATA



27811 Slave Status

27812 Slave Address

27813 Slave Data



281 Overview

282 Features

283 Block Diagram


2841 Clocks


2843 Interrupts

2844 Events






28522 Checksum

2853 Interrupts





2871 Control A

2872 Control B

2873 Status


291 Overview

292 Features

293 Block Diagram



2951 Clocks

2952 IO Lines

2953 Interrupts

2954 Events







29623 Lookup Table Logic


29625 Filter

29626 Edge Detector

29627 Sequential Logic

29628 Clock Source Settings

2963 Events





2981 Control A



2984 LUT n Control B


2986 TRUTHn


301 Overview

302 Features

303 Block Diagram



3051 Clocks


3053 Interrupts

3054 Events






30622 Input Hysteresis

30623 Input Sources

306231 Pin Inputs

306232 Internal Inputs

30624 Low Speed Mode

3063 Events

3064 Interrupts





3081 Control A

3082 Mux Control A


3084 Status


311 Overview

312 Features

313 Block Diagram



3151 Clocks


3153 Interrupts

3154 Events






31622 Starting a Measurement

31623 Prescaling and Conversion Timing

31624 Changing Channel or Reference Selection

316241 ADC Input Channels

316242 ADC Voltage Reference

316243 Analog Input Circuitry

316244 ADC Accuracy Definitions

31625 ADC Conversion Result

31626 Temperature Measurement

31627 Window Comparator Mode

3163 Events

3164 Interrupts






3181 Control A

3182 Control B

3183 Control C

3184 Control D

3185 Control E

3186 Sample Enable

3187 MUXPOS

3188 Command

3189 Event Control



31812 Debug Run

31813 Temporary

31814 Result

31815 Window Comparator Low Threshold

31816 Window Comparator High Threshold

31817 Calibration


321 Overview

322 Features

323 Block Diagram



3251 Clocks


3253 Events

3254 Interrupts







32623 Starting a Conversion

32624 DAC As Source For Internal Peripherals





3281 Control A

3282 DATA


331 Overview

332 Features

333 Block Diagram



3351 IO Lines

33511 Mutual-capacitance Sensor Arrangement

33512 Self-capacitance Sensor Arrangement

3352 Clocks

3353 Analog-Digital Converter (ADC)


34 UPDI - Unified Program and Debug Interface

341 Overview

342 Features

343 Block Diagram


3441 Clocks


3443 Interrupts

3444 Events

3445 Power Management




34511 UPDI UART

34512 BREAK Character


34521 UPDI Enable with RESET Pin Override

34522 UPDI Enable by 12V Programming

34523 UPDI Disable

34524 UPDI Communication Error Handling

34525 Direction Change

3453 UPDI Instruction Set

34531 LDS - Load Data from Data Space Using Direct Addressing

34532 STS - Store Data to Data Space Using Direct Addressing

34533 LD - Load Data from Data Space Using Indirect Addressing

34534 ST - Store Data from Data Space Using Indirect Addressing

34535 LCDS - Load Data from Control and Status Register Space

34536 STCS (Store Data to Control and Status register space)

34537 REPEAT - Set Instruction Repeat Counter

34538 KEY - Set Activation KEY

3454 System Clock Measurement with UPDI

3455 Interbyte Delay

3456 System Information Block

3457 Enabling of KEY Protected Interfaces

34571 Chip Erase

34572 NVM Programming

34573 User Row Programming

34574 Activate OCD Features

34575 Enabling of 2-Wire Mode

3458 Events




3471 Status A

3472 Status B

3473 Control A

3474 Control B



3477 ASI Key Status


3479 ASI Control A





35 Instruction Set Summary


361 Disclaimer

362 Absolute Maximum Ratings

363 General Operating Ratings

364 Voltage Protection



38 Package Drawings

381 WARNING

382 14-pin SOIC150

383 20-pin SOIC300

384 20-pin VQFN

385 24-pin QFN

39 Datasheet Revision History

391 RevA - 092016