Microprocessing and Microprogramming 38 (1993) 715-722 715 North-Holland

Automatic Test Pattern Generation can be Solved as a Constraint Satisfaction Problem

K. Tilly", L. Surjfm" and G. Romhn"

'Technical University of Budapest, Department of Measurement and Instrumentation Engineering, H-1521. Budapest, Mfiegyetem rkp. 9, Hungary, Tel. & Fax.: (36-1) 166 4938, E-mail: tilly@mmt.bme.hu

In this article we propose constraint based test generation as a new method for Automatic Test Pattern Generation (ATPG) in digital circuits, and describe a framework which makes it possible to uniquely handle a set of problems in currently existing ATPG methods, like the question of functional circuit modelling or the topological parallelization of the ATPG algorithm. The stated constructs (object oriented data-flow networks, tho internal representation of network elements by dynamic binary constraint networks, the use of arc consis- tency algorithms, careful scheduling and a special dependency directed backtracking scheme) result in a high representational power and fast operating speed. Main concepts and reasons for decisions are shown before the details of a system architecture is presented.

1. INTRODUCTION

The purpose of Automatic Test Pattern Generation (ATPG) is to find input combinations (tests) which produce different output combinations in a faulty and a fault-free digital circuit. They can be used for detecting and under certain conditions even for identifying faults, so test sets have high significance in factory level exhaustive quality control of inte- grated circuits, printed circuit boards and other electronic equipment.

Since the mid sixties extensive efforts have been made to create ATPG-algorithms. The main diffi- culty is that on the one hand any ATPG-algorithm must be complete (i.e. it must assure that it finds a test if one exists), on the other hand the problem is proved to be NP-complete [5]. After the first basic algorithm, the D-algorithm was published by Roth [23], several new algorithms have been developed like PODEM, FAN [5] or SOCRATES [15]. Good summaries are given in [11] or [5]. All of them generate test patterns for faults of combinational logic circuits and perform exhaustive heuristic search with backtracking.

Although these algorithms can be very efficient in

practical cases, they are, however, hard to be extended for sequential circuits, are not really suitable for handling higher than gate level functional circuit models, and there are difficulties in increas- ing their performance on distributed multi-processor architectures [9].

In this article an artificial intelligence method (constraint satisfaction) is proposed as an alternative for solving ATPG problems. Since there have been several previous attempts made to use AI methods for ATPG and results in general were not convinc- ing, we give an exact definition of machine intelli- gence that makes it clear why AI methods can (and should) be applied for ATPG.

Our definition is based upon the following intuitive reasons. In everyday life person A is considered more intelligent than person B, if A is able to solve (certain) complicated problems based upon his experiences, expertise, talent etc. much quicker than B. In cases where A is more intelligent than B, B will merely use trials for finding solutions, which nearly always takes a lot more time and results in a worse solution. Simple problems, however (e.g. if we tell both A and B to open a window), are not appropriate to judge the differences of the intelli-

* This work was done on leave at Delft University of Technology, Department of Applied Physics, P.O. Box 5046, 2600 GA Delft, The Netherlands, Tel.: (31-15) 78 14 40, Fax.: (31-15) 78 60 81

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gence of A and B: they will perform the task in the same way and same time.

In regard of computers it is possible to exactly define what "complicated problems" and "much quicker" means using the notions of algorithmic complexity according to Garey [6]:

Definition 1 (hardness): Problem p is hard, if no polynomial algorithm for its solution is known or p is NP-complete or p is not in NP.

(Note, that problems not fulfilling the conditions of Def. 1 are all in P. These are considered as simple problems.)

Definition 2 (machine intelligence): Machine intelligence is the ability of a computer program to solve hard problems in polynomial average time.

We should mention here that there are other definitions of machine intelligence in the literature of AI ( e . g . E . Rich's definition [13]), which defines this abstract term slightly differently.

According to Def.2 any ATPG program that can perform the task in polynomial average time is considered intelligent. The validity of this statement can easily be checked: successful ATPG algorithms incorporate a lot of knowledge and heuristics so they possess (in traditional sense) the most important preconditions of intelligent action.

By Def.2 AI and ATPG both share a common basis, so it's natural to introduce AI methods to solve ATPG problems. However previous experi- ences show, that only those methods can be accepted that offer solutions exactly matching the characteris- tics of ATPG. In the following it is shown that constraint satisfaction fits these requirements.

2. THE ATPG PROBLEM

Any ATPG problem can be characterised by three basic elements: - The ATPG network, which is the model of the

digital circuit for which test patterns have to be generated, is built of junctions (representing network nodes) and functional elements (represent- ing building blocks e.g. logic gates). The ATPG network can be represented as a hypergraph whose vertices are the junctions and whose edges (con- nected to one, two or more vertices representing junctions) are the functional elements. In the following we restrict our attention to gate level

ATPG for combinational logic circuits. - The fault model makes it possible to describe

different kinds of physical defects in the given digital circuit. A good summary of the basic fault modelling techniques is given by Miczo [11]. In this article the simplest single-stuck-at-fault model is used where only one fault is assumed to occur in the network at a time, and the fault can be described by fixing the value of the given junction at 0 (s-a-0 fault) or 1 (s-a-1 fault).

- The ATPG algorithm is based upon the ATPG network and it controls the search for tests. Although there is a very large range of practical differences, essentially all ATPG algorithms per- form three basic steps: - Fault propagation: A path must be found from

the fault site to a primary output through con- nected gates to propagate the fault and make it observable. A fault is propagated through a functional element, if at least at one of its outputs there is a different value for the fault- free and for the faulty network.

- Fault sensitization: A primary input combina- tion must be found that forces the opposite level of the given stuck-at (e.g. 1 must be forced for s-a-0) at the point of the given fault.

- Justification: During the previous two steps a set of internal junctions also get values. These must be recursively "justified" by finding (tracing backwards to the primary inputs) a consistent set of assignments for all the junc- tions which affect these values.

It often occurs that a certain value must be selected from among multiple possible choices, which can lead to global inconsistencies and can only be resolved by backtracking.

3. AUTOMATIC TEST PATTERN GENER- ATION CAN BE REPRESENTED AND SOLVED AS A CONSTRAINT SATISFACTION PROBLEM

Constraint satisfaction problems (CSP-s) can be represented as hypergraphs: their vertices are a set of variables and their hyperarcs (arcs connected to one, two or more variables) are a set of constraints given as unary, binary or in general k-ary relations of the connected variables [12]. If the network

ATPG can be solved as a CSP 717

consists of n variables, the solution for the CSP is searched by assigning values to k initial variables and extending them to the remaining (n-k) variables to achieve a variable set consistent for all the given constraints of the network. Since in ATPG networks discrete value sets are used (as defined by the applied fault model), we can restrict our attention to discrete CSPs, where variables can take values from predefined, finite discrete sets, so called domains.

Based upon the strong analogy between constraint networks and physical systems Stallman [17] used this technique for automated circuit analysis, Davis [2] applied constraints in his structure and behaviour based diagnostic system, and constraints are the basis of qualitative modelling as proposed by de Kleer [8] to only mention some of the most signifi- cant results.

Considering an ATPG problem (as described in section 2.) and a CSP (as described above) it's obvious that they are the same, if functional elements (here gates) are represented as constraints and junctions as variables.

3.1. Constraint Satisfaction Algorithms Can be Used in ATPG Algorithms

Although CSP-s (just like ATPG problems) are generally NP-complete [10], many useful methods and clever considerations were developed for solving them. The main goal is identical with ATPG methods: to avoid backtracking whenever possible (referred here as preprocessing methods), and to increase the efficiency of backtracking (referred here as intelligent backtracking).

Due to their simplicity and proved worst case polynomial complexity, the most significant preprocessing methods are the binary arc and path consistency algorithms proposed by Mackworth [ 10]. If R~ denotes a binary constraint between variable X and Y, arc consistency algorithms exclude all x~ values from the actual domain of X for which no y~ value exists in the current domain of Y, such that R~(x~,yj) is satisfied. Such x~ values can surely not be part of a consistent solution. In path consistency a binary relation ('length 1 path') is compared to a composite relation of a length 2 path, and those values are excluded which are not consistent with the same value for both relations.

Other preprocessing methods are based upon the network topology e.g. by searching for subtrees

(used in ATPG as the easy solvability of recon- vergent fanout-free circuits) or by creating special orderings of variable initialisations and using direc- tional arc and path consistency procedures [3,4]. Other useful heuristics were suggested by Dechter [4] (e.g. searching for separating vertices and decomposing the CSP network into subgraphs or using adaptive consistency algorithms). These methods are somewhat similar to giving high import- ance to primary inputs and using testability measures to select most significant junctions first, like in the PODEM algorithm of Goel [7].

Montanari proposed graph transformation [12], in which CSP networks are repeatedly transformed (using rule sequences - strategies) into networks with equivalent solutions but decreased complexity to achieve a minimal network. The order of rules can be derived by using graph grammars and appropriate parsers.

In cases when preprocessing methods cannot assure backtrack-free search a kind of intelligent backt racking is needed. A remarkab le characterisation of the possibilities is given by Dechter [3]. These methods are based on the topology of the constraint graph or on data depend- encies [6,13] recorded during the constraint satisfac- tion process [ 16]. Another possibility is to search for variable sets (so called cycle-cutsets) which when omitting them from the constraint graph turn it into a tree. The cutset is then initialised and the tree can be solved in polynomial time. If no global consist- ency is achieved, the process is repeated with a new cutset initialisation. Cycle-cutsets can be considered as the analogies of headlines in the FAN algorithm of Fujiwara [5].

3.2. Any ATPG Network can be Described as the Object Oriented Data-Flow Representation of a Constraint Network

There are many known methods to describe constraint networks at the machine level (e.g. algebraic or rule based [17] descriptions ). For ATPG networks, however, we consider the bidirectional object oriented data-flow network representation of Steele [17] as the most advantage- ous. It emphasises the autonomous nature of func- tional elements; object class libraries can be created according to the practice of digital designers who are using catalogues; network topology can easily be

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defined; different levels of functional elements (like gate, IC, printed circuit board) can be well described by object class hierarchies; and finally - since the ATPG network can be topologically distributed among different processors - the overall performance of the system can be increased on multi-processor computer architectures [9].

4. THE ARCHITECTURE OF THE CON- STRAINT BASED ATPG FRAMEWORK

4.1. Basic Concepts According to the single-stuck-at-fault model the

value set (domain) of the junctions is {LOW, HIGH, s-a-0 , s-a-I} for which we use the {0, 1, D, -D} notation respectively [ 14]. The value X (don't care),

A B c -~)-E D

RI:

0 -

I I

D i,D

-D i, -D

Tin:

0 -

I Reducel

D Rz --* R2D -D R 2 -~ RZ- D

Tout :

0 Tin~ Tino

i -

D Tin-~ TinED

-D Tin-~TinE-D -D Error

Tin 0 : TinoD :

0 C o n s . 0 C o n s , i Go on i Go on

D Tin-~TinOD D 0o on

-D TIn-~TInO-D -D Cons

R 2 :

0

i

D

-D

P~D:

0 0 "1 -

D 0,D

-D 0

TinED '.

0 E r r o r

i Go on

D Cons

u t

0

O.D O . - D

R2-D:

0 0 i - D 0

-D 0 , -D

TinE-D: 0 E r r o r 1 Go on D Error

-D Cons

TlnO_D'. 0 Cons,

I Go on

D Cons

-D Go on

Figure 1. The DBCN model of the AND gate

which is traditionally incorporated as a fifth element for expressing that any value of {0,1,D,-D} is acceptable, is covered by the case when each domain elements are allowed, so it can be omitted.

For the internal representatio n of gate constraints we introduce a new concept, the dynamic binary constraint network (DBCN) method (Fig. 1), which keeps the advantages of binary constraint networks while extending their representational power to general n-ary constraints. DBCN models contain variables connected by directed binary relations (e.g. R s and R 2 in Fig. 1). Furthermore there can be a transformation rule associated with any variable (as e.g. T~ or To~ in Fig. 1). Binary relations are represented as simple vectors of 4 elements (in general they contain as many elements as the size of the given variable's domain), and they define the acceptable values of the target variable supposing that the source variable takes a given value. Trans- formation rules can contain instructions that change one or more binary relations or transformation rules in the DBCN, or perform other actions.

There is a common algorithm, the DBCN inter- preter, which assigns values to the variables of the DBCN one by one in the following manner. The interpretation starts from an initial DBCN graph (shown in Fig. 1 for the AND model). Until all variables are passed or a locally consistent state is reached (coded in the DBCN model as a Cons

instruction to the DBCN interpreter) select a yet not examined variable X. Restrict the set of allowed values of X by performing a binary arc consistency algorithm on the actual DBCN graph. If the domain of X gets empty, a contradiction is detected. Other- wise select an allowed value of X, save the actual state of the DBCN model and perform all the actions given in the actual transformation rule of X. The following are some important DBCN instructions. Reducel eliminates a variable, and if this variable is the last input and all previous inputs were assigned 1, the binary relations R t and R 2 are substituted with equality; Error signals a state that cannot happen, so it can only occur because of a system error; and finally Go on signals an acceptable value except for the last input variable assignment.

The applicability of the DBCN method is based upon the simple fact that in any constraint satisfac- tion problem a variable assignment can never loosen the constraints of the remaining network, it can only restrict them, or leaves them unchanged. It can be shown (as in fact it will be done in a subsequent article) that DBCN models have equivalent repre- sentational power to truth table or cubical represen-

ATPG can be solved as a CSP 719

tations, though offer far more flexibility and - especially for more complicated elements - far smaller space complexity and thus much faster operating speed. These statements are well demonst- rated by Fig. 1, which is a general (justification) model for AND gates with arbitrary number of inputs.

There are seven basic gate object classes in our implementation (AND, NAND, OR, NOR, XOR, INVERT, BUFFER), which (where necessary) can be instantiated to any number of input pins based upon general DBCN models. The junctions belong to two classes: internal junctions and ports (which represent primary inputs and outputs) (Figure 3).

The run-time system fetches gate objects from queues [16] and can invoke them with different methods. The gates use their DBCN model and assign values to the neighbouring junctions by activating the DBCN interpreter. If a junction is set, it automatically queues all the gates connected to it (except the one that has set its value).

Fault

[]

f'l Port Precondition Consequence 0 Junction - 0 ' ~ L , ~ -

Funct elem 72>-

Figure 2. The registration of data dependencies in the object oriented data-flow network

To decrease the number of backtrackings arc consistency algorithms and the hesitate agenda is used (see 4.2.1).

The intelligent backtracking method is based upon the data dependencies automatically registered by gates and junctions in their instance variable struc- tures during operation [ 16]. Gates and junctions hold preconditions (identifiers of neighbouring junctions, which initiated the operation of a gate, or gates which set the value of a junction) and consequences (identifiers of neighbouring gates queued by a given junction or junctions which were assigned by a given gate). The same data dependencies are registered

during local propagation and contradiction resolution (see section 4.). The proposed backtracking method performs a procedure which combines dependency directed backtracking with problem space decompo- sition.

4.2. The Run-Time System 4.2.1. Control Data Structures

The run-time system uses three basic data struc- tures to operate the network:

The local propagation queue contains gates queued by a junction whose value was set. The run-time system always tries to start the first gate of this queue. The hesitate agenda is an agenda where (accordingly to the habitual terminology of Rich [13]) the tasks are gates, the justifications of the gates are the precondition junctions and the weights of the gates are computed as follows.

When a gate is started, it autonomously checks the reliability of the new values it could generate (it can be rather simply implemented using the DBCN models and the DBCN interpreter). If it is below a certain level (in the current implementation unique value assignments (implications) are required), the gate begins to "hesitate", and places itself to the hesitate agenda.

The elements of the hesitate agenda are activated when the local propagation queue becomes empty. At that moment the weights are computed and the gate with the highest weight is started. This solution can also be considered as an implicit ordering of value initializations, or as a generalisation of the heuristic "perform every possible unique implica- tions" of the FAN algorithm [5] by using adjustable decision weights during the search.

The D-stack, which plays a similar role to the D- frontier in the D-algorithm of Roth [23], is used for optimal D-path selection in the fault propagation phase. If the contradiction resolution fails, there is another possibility of backtracking: to select a new D-path (i.e. to propagate the fault on another way), reinitialize the rest of the ATPG network and start again. This process can also be very time consum- ing, if we don't consider the exact place of the contradiction. This problem is solved by the regis- tered data dependencies and the D-stack.

4.2.2. The Local Propagation Algorithm The local propagation algorithm is theoretically

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identical to the general path sensitization algorithm described in section 2. The problem of reconvergent fanouts and multiple D-paths is solved by a simple assignment step after the fault injection where the domains of all junctions that can be reached on an input-output directed path from the place of the fault are set to {0,1,D,-D}, while the domains of remain- ing junctions are set to {0,1}. The rest is done by the run-time system and the DBCN interpreter.

4.2.3. The Contradiction Resolution Algorithm The algorithm is started from the gate (referred to

as contradiction) which signals a contradiction and a kind of dependency directed backtracking is performed based on data dependencies registered during the local propagation algorithm. During local propagation the gates generate only one consistent value set for the junctions around them, while during contradiction resolution they can systematically and exhaustively generate all possible consistent value sets upon request of the run-time system. Because of the more complicated operation and so as to be able to continue local propagation after a contradiction is resolved, a backtrack list (for storing retracted gates) and a contradiction context stack (CCS) (which stores backtrack lists and contradiction gates) are used.

The kernel of the contradiction resolution algorithm is given in Figure 6.

Registering data dependencies, is essentially the remembering the order in which junction values were generated, when a contradiction occurs, new values are tried to be assigned by exactly those gates which have originally set the given value. From the aspect of a gate there are two kinds of junctions: premises (which were known to the gate when it was first started) and consequences (which were gener- ated by the given gate). The general idea of the contradiction resolution algorithm is to make changes under the same conditions, which were present, when the original value was assigned to a given junction, when searching for a consistent solution a gate can never alter its premises, but it can retract and change the values of its consequences within a systematically growing area of the ATPG network around the contradiction. This is achieved by the backtrack list and the StepCounter procedure.

Although the algorithm in Fig. 3 guarantees to find a consistent solution, in itself it cannot assure, that

values assigned in a previous successful contradic- tion resolution session will not be retracted, and this can lead to the repeated appearence of the same contradiction, in the worst case in an infinite cycle.

To solve this problem, the basic algorithm can be enhanced by a marking mechanism (the so called engagement level) to extend the basic philosophy of "preserve original conditions" to whole contradiction resolution sessions. It works as follows.

There are three kinds of junctions:free (which can unconditionally be changed by its precondition gate), engaged (which can only be changed by the precond- ition gate, if the engagement level of the junction is the same as the current engagement level) and D- path which can only be changed by selecting a new D-path).

The ATPG network is automatically divided into topological subspaces by the contradiction resolution algorithm. When the first contradiction occurs, all (known) junctions are free but the D-path. If the contradiction is resolvable, all the gates are regis- tered on the backtrack list which have set the value of a free junction, and all the junctions involved in the contradiction resolution as preconditions or consequences are marked as engaged at level 1, the contradiction gate and the elements of the backtrack list are pushed to the CCS and the engagement level is incremented. When the next contradiction occurs, the engagement level is already 2, so in this case free junctions can only be altered. When a solution for a contradiction is found, the subspace is marked with the current engagement level. If no solution has been found in a given subspace, all elements of the subspace are retracted, and the next consistent state of the previous subspace is generated by the basic algorithm in Fig. 3. This can be achieved by de- crementing the engagement level and by restoring the previous contradiction and backtrack list from the CCS. This way the search for consistent sol- utions is limited to subspaces, which in the average are less complex than the whole set of the known junctions.

In this aspect the D-path can be considered as the 0th subspace. If the resolution of contradiction c fails and the CCS is empty, a new D-path must be selected. It can be shown that from the point of resolving c, only those elements of the D-path are effective that are direct or indirect preconditions of c. So a new D-path can be started from the D-path

ATPG can be solved as a CSP 721

ResolveContradiction( c ) { select junction to retract:

J~, ~ J I JE {Pre(c)} or (J E {Pre(b_list)} and J ~ {Cons(b_list)};

if ~]J~, then select a new D-path; else {

G,~t ~- the precondition of J~t; Retract( Gxt, b_list ); append G,~, to the end of b_list;

} while StepCounter(b_list) succeeds do {

if contradiction is resolved then { append in the given order c and

VG i E b_list to the beginning of local_q;

return( success ); }} goto select junction to retract;

Retract( G, b_list ) { if GE b list or GE D-path then return; for VJ, E{Cons(G)} do {

reset the domain of J,; for WGjE {Cons(J,)} do

Retract( Gj,b_list); }}

StepCounter( b_list ) { if b_list is empty then return failure; G ~ the first gate on b list; if G is not exhausted then generate next value set for G; else {

StepCounter( b_list - G ); reset the value generation cycle of G;

} return success;

Figure 6. The contradiction resolution algorithm

gate that is effective and lays the nearest to the current primary output end of the D-path.

5. CORRECTNESS

The local propagation algorithm assures that the fault is spread to an output and solves the problem of reconvergent fanouts and multiple D-paths. When a gate is started, it sets all the junctions around it which have unknown values. This will result in the queuing of other gates. This means that if all the queues are empty and no unresolvable contradiction occurred, then no needed value is missing and all values are consistent, so a test is found.

The correctness of the new D-path selection and the completeness of the stated contradiction resol- ution algorithm can be shown, which will be pub- lished in a following article.

6. CONCLUSIONS

In this article a new ATPG method, constraint based test generation was proposed. Our intention was not to report complete run-time evaluations of an ATPG implementation, rather to point out the stated methods' very good applicability based on common characteristics of CSP and ATPG problems and describe the architecture of a constraint based ATPG framework.

The traditional D-cube representation of Roth [23] for the functional elements applied by any wide- spreadly used ATPG algorithm is exchanged by the DBCN representation, which assures higher flexibil- ity (especially by describing more complicated functional elements), and combines the representa- tional and run-time efficiency of four-valued logic with the increased decisional reliability of "higher- valued" (e.g 10-valued [18]) logics. The number of backtrackings is decreased by the use of binary consistency algorithms and the hesitate agenda. The applied contradiction resolution (backtracking) algorithm is explicitly tailored to the needs of ATPG, and it is highly efficient.

It is also obvious that the stated solutions can be extended for more complex ATPG problems. Object oriented descriptions allow the representation of higher level (IC, printed circuit board etc.) func- tional elements even in a hierarchical manner. The described algorithms are able to handle feedback loops (i.e. sequential circuits), although in this case additional solutions are required for D-path selection

722 K. Tilly et al.

and for the handling of internal states of the net- work. Furthermore, object oriented data-flow net- works offer the possibility of enhancing the operat- ing speed by topologically distributing [9] object in- stances on multi-processor architectures.

Theoretical methods of improving the operating speed are not exhausted in the described implementa- tion, so on certain points the prototype framework is far from being optimal, it has proved however to be surprisingly efficient. We used the ten standard combinational benchmark networks [ 1] to test ATPG programs, and for those circuits (e.g. c432) for we have produced experimental results, the constraint based lest generator runs in times which are approxi- mately the same (or slightly worse) than those produced by highly efficient ATPG systems like SOCRATES [ 15].

Our experiences show that constraint based auto- matic test pattern generation is powerful enough to efficiently solve difficult ATPG problems. Currently we are working on the extensions of this technique in multiple directions. We intend to develop frame- works for ATPG on multi-processor parallel com- puter architectures and we intend to investigate the possibilities of extending it to multi-level functional testing and sequential logic.

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