AVR Microcontrollers (ATMega128) - Hanyangrtcc.hanyang.ac.kr/.../Lecture_08_AVR_Microcontrollers.pdfSince all AVR instructions are 16 or 32 bits wide, the Flash is organized as 64K

Real-Time Computing and Communications Lab., Hanyang Universityhttp://rtcc.hanyang.ac.kr

Real-Time Computing and Communications Lab., Hanyang Universityhttp://rtcc.hanyang.ac.kr

AVR Microcontrollers(ATMega128)

Minsoo Ryu

Department of Computer Science and EngineeringHanyang University

[email protected]

2Real-Time Computing and Communications Lab., Hanyang University

http://rtcc.hanyang.ac.kr 2Real-Time Computing and Communications Lab., Hanyang Universityhttp://rtcc.hanyang.ac.kr

Topics Covered

IntroductionMain Features Architectural OverviewMemory Organization



Atmel AVR

The AVR is a Modified Harvard architecture 8-bit RISC single chip microcontroller (µC) which was developed by Atmel in 1996

The AVR was one of the first microcontroller families to use on-chip flash memory for program storage One-Time Programmable ROM, EPROM, or EEPROM used by

other microcontrollers at the time The AVR allows users to download a program to the board

without a ROM Writer using the ISP (In-System Programming) function



History

It is believed the AVR basic architecture was conceived by two students at the Norwegian Institute of Technology (NTH) Alf-Egil Bogen and Vegard Wollan The original AVR MCU was developed at a local ASIC house

in Trondheim, Norway, where the two founders of Atmel Norway were working as students



Basic Families

Family Description

tinyAVR(The ATtiny series)

- 1~8 kB program memory - 8~32-pin package - Limited peripheral set

megaAVR(The ATmega series)

- 4~256 kB program memory - 28–100-pin package - Extended instruction set (Multiply instructions and instructions for handling larger program memories) - Extensive peripheral set

XMEGA(The ATxmega series)

- 16~384 kB program memory - 44~64~100-pin package (A4, A3, A1) - Extended performance features, such as DMA, "Event System", and cryptography support- Extensive peripheral set with DACs

Application-Specific AVR- megaAVRs with special features not found on the other members of the AVR family, such as LCD controller, USB controller, advanced PWM, CAN etc



Main Features of the ATMega Series (1/2)

Tuned for high level languages Simple addressing mode Every register is an accumulator

Consistent architecture across entire line Small AVR are subsets of larger chips: same hardware and

code works across all chips High performance

Most single clock cycle execution for 133 Instructions – 32 x 8 General Purpose Working Registers + Peripheral

Control Registers Up to 16 MIPS Throughput at 16 MHz

• 0 - 8 MHz ATmega128L• 0 - 16 MHz ATmega128

On-chip 2-cycle Multiplier



Main Features of the ATMega Series (2/2)

JTAG support For on chip debugging

Six software selectable power saving modes The Idle mode stops the CPU while allowing the SRAM,

Timer/Counters, SPI port, and interrupt system to continue functioning

The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset

Others include Power-save mode, ADC Noise Reduction mode, Standby mode, and Extended Standby mode



Pin Configurations



Block Diagram



CPU Core



Architectural Overview

Single level pipelining While one instruction is being executed, the next instruction

is pre-fetched from the program memory This concept enables instructions to be executed in every

clock cycle

The fast-access Register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time This allows single-cycle Arithmetic Logic Unit (ALU)

operation In a typical ALU operation, two operands are output from the

Register file, the operation is executed, and the result is stored back in the Register file – in one clock cycle



Architectural Overview

High-performance ALU The ALU operates in direct connection with all the 32 general

purpose working registers Within a single clock cycle, arithmetic operations between

general purpose registers or between a register and an immediate are executed

The ALU operations are divided into three main categories –arithmetic, logical, and bit-functions

Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format



Status Register (SREG)

I (Global Interrupt Enable) The I-bit is cleared by hardware after an interrupt has occurred,

and is set by the RETI instruction to enable subsequent interrupts

The I-bit can also be set and cleared in software with the SEI and CLI instructions, as described in the instruction set reference

T (Bit Copy Storage) The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore)

use the T-bit as source or destination for the operated bit A bit from a register in the Register file can be copied into T by

the BST instruction, and a bit in T can be copied into a bit in a register in the Register file by the BLD instruction



Status Register (SREG)

H (Half Carry Flag) Holds the carry from bit 3 to bit 4 To support operations on four bits

S (Sign Bit) Is always an exclusive or between the negative flag N and the

two’s complement overflow flag V V (Overflow Flag)

Supports two’s complement arithmetic N (Negative Flag)

Indicates a negative result in an arithmetic or logic operation Z (Zero Flag)

Indicates a zero result in an arithmetic or logic operation C (Carry Flag)

Indicates a carry in an arithmetic or logic operation



32 General Purpose Registers

Each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space



The X-, Y-, and Z-registers

The registers R26 ~ R31 have some added functions to their general purpose usage These registers are 16-bit address pointers for indirect

addressing of the Data Space



Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls

The Stack Pointer Register always points to the top of the Stack Note that the Stack is implemented as growing from higher

memory locations to lower memory locations This implies that a Stack PUSH command decreases the

Stack Pointer The AVR Stack Pointer is implemented as two 8-bit registers

in the I/O space



Flash Program Memory

The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space Flash Program memory SRAM Data Memory

The ATmega128 contains 128K bytes On-chip In-System Reprogrammable Flash memory for program storage The Flash memory has an endurance of at least 10,000

write/erase cycles Since all AVR instructions are 16 or 32 bits wide, the Flash is

organized as 64K x 16 The ATmega128 Program Counter (PC) is 16 bits wide, thus

addressing the 64K program memory locations For software security, the Flash Program memory space is

divided into two sections, Boot Program section and Application Program section



Program Memory Map



SRAM Data Memory

Two configurations

Register file from 0x0000 I/O Registers Extended I/O Registers Internal SRAM External SRAM



SRAM Data Memory



I/O Register Access

All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space

They can also be accessed by the IN and OUT instructions and the I/O addresses $00 - $3F must be used When addressing I/O registers as data space using LD and

ST instructions, $20 must be added to these addresses I/O registers within the address range $00 - $1F are directly

bit-accessible using the SBI and CBI instructions



External SRAM Access

When the addresses accessing the SRAM memory space exceeds the internal data memory locations, the external data SRAM is accessed using the same instructions as for the internal data memory access

Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM This means that the commands LD, ST, LDS, STS, LDD, STD,

PUSH, and POP take one additional clock cycle If the Stack is placed in external SRAM, interrupts, subroutine

calls and returns take three clock cycles extra because the two-byte program counter is pushed and popped, and external memory access does not take advantage of the internal pipe-line memory access



EEPROM Data Memory

The ATmega128 contains 4K bytes of data EEPROM memory It is organized as a separate data space, in which single bytes

can be read and written The EEPROM has an endurance of at least 100,000

write/erase cycles The access between the EEPROM and the CPU can be

performed by specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register



Instruction Set



Instruction Set



Instruction Set



Instruction Set



Instruction Set

Documents

AVR Microcontrollers (ATMega128) - Hanyangrtcc.hanyang.ac.kr/.../Lecture_08_AVR_Microcontrollers.pdfSince all AVR instructions are 16 or 32 bits wide, the Flash is organized as 64K