Upload
peyton-wilshire
View
222
Download
4
Tags:
Embed Size (px)
Citation preview
Figure 1 B4McCollum
Reliability of Antifuse-Based field Programmable Gate Arrays
for Military and Aerospace Applications
John McCollum, Roy Lambertson, Jeewicka Ranweera, Jennifer Moriarta, Jih-Jong Wang,
Frank Hawley, and Arun Kundu
Actel Corporation
Figure 2 B4McCollum
• The Design Engineer (user) and his CAE tools is partially responsible for the content of an FPGA
• Reliability of an FPGA design is therefore a mix of the manufacturer and the user
Figure 3 B4McCollum
Manufacturer Responsibility
• Antifuses are an addition to the base CMOS process
• Reliability of the ONO antifuse
• There are two states that must be reliable– Open– Short
Figure 4 B4McCollum
N+ Polysilicon
N+ Diffusion
OxideNitrideOxide
ONO Antifuse
Figure 5 B4McCollum
ONO Antifuse Photomicrograph
Figure 6 B4McCollum
TDDB (sec)
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+01
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+07
1.0E+08
1.0E+09
1.0E+10
1.0E+11
1.0E+12
1.0E+13
1.0E+14
1.0E+15
1.0E+16
1.0E+17
1.0E+18
1.0E+19
1.0E+20
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
100/E (cm/MV)
Operating Voltage
Age of Universe
Figure 7 B4McCollum
Programmed State of ONO
Figure 8 B4McCollum
Programmed ONO Antifuse Resitance vs Read Current Characteristic
0
200
400
600
800
1000
1200
0 1 2 3 4 5 6 7 8 9 10
Read Current in mA
Res
itan
ce i
n O
hm
s
Note: No Switch off
Programmed at 5mA
Heating of Filament
Figure 9 B4McCollum
ONO Antifuse Switch off Test
Figure 10 B4McCollum
Photomicrograph showing Poly Contact failed not the Antifuse
Figure 11 B4McCollum
RH1020_ONO
3
4
5
6
20 30 40 50 60 70 80 90
LET (MeV-cm2/mg)
Vc
riti
ca
l (v
olt
)SEDR Curve
90A ThicknessTypical is 96A
Figure 12 B4McCollum
• Amorphous-Silicon Antifuse allow higher density(Sea of Modules)
• Higher performance - Lower Capacitance
• Reliability analysis for opens and shorts
Figure 13 B4McCollum
Unprogrammed Antifuse
Antifuse
Metal 3
Via to Metal 4
Figure 14 B4McCollum
TDDB MEC 0.6um Lot P10 and 0.25um P006 @VOT@RMT
-5
0
5
10
15
20
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3
BVG(1ms)/v
Lo
g T
ime
(sec
)
Operating Voltage
Life of the Universe
Data indicates that this line actually turns up
Figure 15 B4McCollum
Programmed Antifuse
Figure 16 B4McCollum
0.25um Time To Fail comparison @ 25C
1.E+00
1.E+02
1.E+04
1.E+06
1.E+08
1.E+10
Current
TT
F (
S)
No Fail Test 1(Product)No Fail Test 2(Product)Fail Test 3(Product)SX_S SafeDesign SpecNo Fail DataArea
Data showing that switch off the metal Antifuse is over designed by at least a factor of 2
Figure 17 B4McCollum
2
3
4
20 30 40 50 60 70 80
LET (MeV-cm2/mg)
Vc
riti
ca
l (v
olt
)
RTSX16_0.6u_3.3V
RHSX16_0.6u_3.3V
ASX16_0.35u_3.3V
RTSX32_0.25u_2.5V
RTSX72_0.25u_2.5V
SEDR of the Metal to Metal Antifuse
SXS shows one failat 2.85Vmax spec is 2.75V
No failure
Figure 18 B4McCollum
• Since BVG (Break Down Voltage) of ONO was lower than gate oxide no antifuses are connected to pins
• ESD thus achieved Class 2 >2000 Volts• Actel however discovered PID (Process Induced
Damage) in Fabs• Implanters and Plasma Etchers could produce 20 volts
on the wafer and destroy the ONO• Actel worked with the Fabs and solved this problem• Additionally Actel voltage stresses each part at Wafer
Sort and Final Test to eliminate all antifuse defects
Figure 19 B4McCollum
Cum Probability of Antifuse BVG with PID
-3
-2
-1
0
1
2
3
0 2 4 6 8 10 12 14 16
BVG
Sig
ma
Nominal BVG
PID tale
Figure 20 B4McCollum
• Most MOS reliability defects are traditionally Gate oxide Failures
• By virtue of the high voltage stresses applied to Actel circuits for programming (even low voltage transistors) there have been very few oxide failures
Figure 21 B4McCollum
Apparent FIT Rate vs Generation
0
20
40
60
80
100
120
ApolloGuidanceComputer
MSI 1976 LSI 1987 1.0u 0.8u 0.6u 0.45u 0.35u RT 0.6u 0.25u 0.22u
Generation
FIT
Apparent turn up is dueto less time to collectlong term data
Figure 22 B4McCollum
# Fails vs Generation
-1
0
1
2
3
4
5
6
7
1.0u 0.8u 0.6u 0.45u 0.35u RT 0.6u 0.25u 0.22u
Generation
# F
ailu
res
Early defects related to via failures
With ten years of production ofMulti-Layer Aluminum the processis very mature even thoughit has been scaled
Figure 23 B4McCollum
FITS/Gate
1.00E-04
1.00E-03
1.00E-02
1.00E-01
1.00E+00
1.00E+01
ApolloGuidanceComputer
MSI 1976 LSI 1987 1.0u 0.8u 0.6u 0.45u 0.35u RT 0.6u 0.25u 0.22u
Generation
FIT
S/G
ate
Due to the high level of integrationmodern ICs are have progresseddramatically
Note: no failures
Figure 24 B4McCollum
• Testing ASIC s with test vectors of less than 100% can lead to unacceptable failure rates
• FPGAs are however 100% tested
•All tracks •All modules•All clocks•All programming circuits•All I/Os •All isolation transistors
•The charge pump•All antifuses in the open state•All antifuses are stressed•A column of circuits is programmed (binning circuit) to verify programming
Figure 25 B4McCollum
PPM FAULTS VERSUS YIELD
1
10
100
1000
10000
100000
1000000
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1
YIELD
PPM
0.70 0.80 0.90 0.95 0.96 0.97 0.98 0.99 0.995 0.999
0.7
0.999
Fault Coverage
Figure 26 B4McCollum
• During programming a small fraction of antifuses will fail to program
• Once the programmer passes a part it is guaranteed to be 100% functional
• Tests are performed to verify the correct antifuse is programmed and is the correct impedance
• Additional tests are done to verify that no other antifuse was erroneously programmed or any circuit damage was done
Figure 27 B4McCollum
• CAE tools are reliable in translating RTL code to a logic design, but may pitfalls await the designer
• Behavior level code would be less prone to bugs, but it will not be very efficient in silicon use or very fast - hence not much demand
• Remember with FPGAs YOU are an IC designer
• Following are few examples of pitfalls
Figure 28 B4McCollum
D
>CLK
Q D
>CLK
Q
High Skew Clock
Without “Preserve” VHDL will delete this buffer
A lot of emphasis needs to be placed of timing analysis!!
Figure 29 B4McCollum
• The designer must know his target FPGA and understand the proper coding style to achieve his design goals
• Improper coding will produce a logically correct circuit, but might use combinatorial logic to clock a register rather than merely enabling the register and using the clock
Figure 30 B4McCollum
• For example, the following Verilog code will synthesize to a two-input AND gate the output of which will clock the register.
module gatedFF(Q, Data, Clock, Enable);
input Clock, Data, Enable;
output Q;
reg Q;
wire GC;
assign = (Clock && Enable);
always @(posedge GC)
begin
Q = Data;
end
endmodule
Figure 31 B4McCollum
• Once you rewrite the Verilog in the following way, the tools are able to infer the Enable-FF.
module enableFF(Q, Data, Clock, Enable);
input Clock, Data, Enable;
output Q;
reg Q;
always @(posedge Clock)
begin
if (Enable)
Q = Data;
end
endmodule
Figure 32 B4McCollum
• In space based applications Register Duplication is to be avoided as SEU can easily create illegal states
• VHDL requires you to instantiate the special CLKINT or CLKBUF
• Synplify has an option to turn register duplication off
Figure 33 B4McCollum
• If SEU is a concern the use of CC Module or TMR techniques are required. Actel tools fully support these techniques in synthesis
• The RTSXS family has self refreshing TMR built into every register. It has proven nearly ion proof, such that SEU upsets do not have to be considered in design
Figure 34 B4McCollum
• RTSXS have new features to make it power-up friendly while the charge pump is turning on – Outputs are tristated – Logic Modules are in standby– Outputs can be programmed to source or sink 50 a– Once Charge pump has reached operating voltage
the modules are activated and the outputs become valid with no glitches
Figure 35 B4McCollum
• Every FPGA manufacturer will tell their customers “use fully synchronous design”
• Yet many designers don’t or manage to avoid fully synchronous design points at critical interfaces
• The successful designer will learn his CAE tools and the target FPGA and follow good design practice
Figure 36 B4McCollum
User Testing
• FLIP FLOPs can remember their last state up to 24 hours
• Set flip flops to the opposite state of the desired power-up state for one hour before power-down followed by the power-up sequence
• Power-on reset signals should not be applied until the power supplies have reached spec.
Figure 37 B4McCollum
Summary
• Devices and CAE tools have improved tremendously in 30 years.
• Very high levels of integration have made systems more reliable
• ICs and CAE tools benefit from multiple users to scrub defects from the circuits
• FPGAs have made the system designer an IC designer - ultimately the system reliability rests with him