BAB09 - The Model Verification Library

8/9/2019 BAB09 - The Model Verification Library

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Introduction to Simulink with Engineering Applications 9−1Copyright © Orchard Publications

Chapter 9

The Model Verification Library

his chapter is an introduction to the Model Verification Library, also referred to as theRun−Time Model Verification Library. This is the eighth library in the Simulink group of libraries and contains the blocks shown below. The blocks in this library are intended to

facilitate creation of self −validating models. We use model verification blocks to check whetherthe signals exceed specified limits during simulation.


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Chapter 9 The Model Verification Library

9−2 Introduction to Simulink with Engineering Applications Copyright © Orchard Publications

9.1 The Check Static Lower Bound Block

The Check Static Lower Bound block performs a check to verify that each element of the inputsignal is greater than or equal to a specified lower bound. The block's parameter dialog box allowsus to specify the value of the lower bound and whether the lower bound is inclusive. If the verifi-cation condition is true, the block takes no action. If not, simulation is halted and an error mes-sage is displayed.

Example 9.1

In the model of Figure 9.1, the amplitude of a sinusoidal signal may vary from its nominal

value of . We will configure this model to display error messages when the lower inclusive

boundary is specified as .

The Signal Generator block is specified for a sine waveform with amplitude , frequency

, and the Check Static Lower Bound block is specified at with the Inclusive boundary

checked, Enable assertion checked, Output assertion signal checked, and icon type graphic. TheConvert block was inserted to convert the Boolean output of the Check Dynamic Gap to doubleas required by the Bus Creator block.

Figure 9.1. Model for Example 9.1

The input and output waveforms are shown in Figure 9.2.

10%±

1 volt

1– volt

1.1 volt

0.3 Hz 1–


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The Check Static Upper Bound Block

Figure 9.2. Input and output waveforms for the model of Figure 9.1

9.2 The Check Static Upper Bound Block

The Check Static Upper Bound block performs a check to verify that each element of the inputsignal is less than or equal to a specified lower bound. The block's parameter dialog box allows usto specify the value of the upper bound and whether the bound is inclusive. If the verification

condition is true, the block takes no action. If not, simulation is halted and an error message isdisplayed.

Example 9.2


value of . We will configure this model to display error messages when the lower boundary

inclusive boundary is specified as .


, and the Check Static Upper Bound block is specified at with the Inclusive boundarychecked, Enable assertion checked, Output assertion signal checked, and icon type graphic. TheConvert block was inserted to convert the Boolean output of the Check Dynamic Gap to doubleas required by the Bus Creator block.


10%±

1 volt

1– volt

1.1 volt

0.3 Hz +1


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9.3 The Check Static Range Block

The Check Static Range block performs checks to verify that each element of the input signalfalls inside the same range of amplitudes. The block's parameter dialog box allows us to specify theupper and lower bounds of the valid amplitude range and whether the range includes the bounds.If the verification condition is true, the block takes no action. If not, simulation is halted and anerror message is displayed.

Example 9.3


value of . We will configure this model to convert a sine waveform of amplitude 1 to a pulse

waveform of the same amplitude and frequency.

10%±

1 volt


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The Check Static Gap Block


, and the Check Static Range block is specified as with the Inclusive upper bound

checked, as with the Inclusive lower bound checked, Enable assertion checked, Output asser-

tion signal checked, and icon type graphic. The Convert block was inserted to convert the Bool-ean output of the Check Dynamic Gap to double as required by the Bus Creator block.




9.4 The Check Static Gap Block

The Check Static Gap block performs a check to verify that each element of the input signal isless than or equal to a static lower bound, or greater than or equal to a static upper bound. If theverification condition is true, the block takes no action. If not, simulation is halted and an errormessage is displayed.

1 volt

0.3 Hz 1.0

0


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Example 9.4

We will configure the model of Figure 9.7 whose input is a sawtooth waveform to display error

messages when the upper bound is specified at or greater and the lower bound is specified as

or less.

The Signal Generator block is specified for a sawtooth waveform with amplitude , frequency

, and the Check Static Gap block is specified at with the Inclusive upper bound

checked, at with the Inclusive lower bound checked, Enable assertion checked, Output

assertion signal checked, and icon type graphic. The Convert block was inserted to convert theBoolean output of the Check Dynamic Gap to double as required by the Bus Creator block. Theinput and output waveforms are shown in Figure 9.8.



9.5 The Check Dynamic Lower Bound Block

0.5

0.5–

1 volt

0.5 Hz 0.5

0.5–


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The Check Dynamic Lower Bound Block

The Check Dynamic Lower Bound block performs a check to verify that the amplitude of a testsignal is less than the amplitude of a reference signal at the current time step. The test signal is thesignal connected to the input labeled sig. If the verification condition is true, the block takes noaction. If not, simulation is halted and an error message is displayed.

Example 9.5

For the model of Figure 9.9 the amplitude of a sinusoidal signal may vary from its nominal

value of . We will configure the model to display error messages when the amplitude

exceeds .

The Signal Generator block has been specified as a sine waveform with the amplitude set at 1.1,frequency at 0.1 Hz, Constant blocks with the values shown, in the Check Dynamic Lower Boundblock the Enable assertion and Output assertion signal are checked, and the icon type is selected

as graphic. The Convert block was inserted to convert the Boolean output of the Lower Boundblock to double as required by the Bus Creator block. The input and output waveforms are shownin Figure 9.10.



10%±

1 volt

1– volt


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9.6 The Check Dynamic Upper Bound Block

The Check Dynamic Upper Bound block performs checks to verify that the amplitude of a testsignal is greater than the amplitude of a reference signal. The test signal is the signal connected tothe input labeled sig. If the verification condition is true, the block takes no action. If not, simula-tion is halted and an error message is displayed.

Example 9.6

For the model of Figure 9.11 the amplitude of a sinusoidal signal may vary from its nominalvalue of . We will configure the model to display error messages when the amplitude

exceeds .

The Signal Generator block has been selected as a sine waveform with the amplitude set at 1.1,frequency at 0.1 Hz, Constant blocks at the values shown, in the Check Dynamic Upper Boundblock the Enable assertion and Output assertion signal are checked, and the icon type is selectedas graphic. The Convert block was inserted to convert the Boolean output of the Check DynamicUpper Bound block to double as required by the Bus Creator block. The input and output wave-forms are shown in Figure 9.12.


10%±1 volt

+1 volt


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The Check Dynamic Range Block


9.7 The Check Dynamic Range Block

The Check Dynamic Range block performs a check to verify that a test signal falls within a rangeof amplitudes. The width of the range can vary from time step to time step. The input labeled sigis the test signal, and the inputs labeled min and max are the lower and upper bounds respectively

of the valid range. If the verification condition is true, the block takes no action. If not, simulationis halted and an error message is displayed.

Example 9.7

The amplitude of a random waveform may vary from its nominal value of . We will

create a model using a Check Dynamic Range block to display error messages when the amplitude

exceeds .

In Figure 9.13 the Signal Generator block has been selected as a random waveform with ampli-

tude specified at 1.2, frequency at 1 Hz, Constant blocks with the values as indicated, in theCheck Dynamic Range block the Enable assertion and Output assertion signal are checked, andthe icon type is selected as graphic. The Convert block was inserted to convert the Boolean out-put of the Check Dynamic Range block to double as required by the Bus Creator block. The inputand output waveforms are shown in Figure 9.14.

20%± 1 volt

1± volt


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As stated above this block performs a check to verify that a signal falls inside a range of ampli-tudes that varies from time step to time step.

9.8 The Check Dynamic Gap Block

The Check Dynamic Gap block performs checks to determine whether a gap of possibly varyingwidth occurs in the range of a signal's amplitudes. The test signal is the signal connected to theinput labeled sig, and the inputs labeled min and max specify the lower and upper bounds respec-tively of the dynamic gap. If the verification condition is true, the block takes no action. If not,simulation is halted and an error message is displayed.


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The Check Dynamic Gap Block

Example 9.8

The amplitude of a sinusoidal signal may vary from its nominal value of . We will cre-

ate a model using a Check Dynamic Gap block to display error messages when the amplitude

exceeds .

In Figure 9.15, the Signal Generator block has been selected as a sine waveform with amplitudeset at 1.1, frequency at 0.1 Hz, Constant blocks with the values shown, in the Check DynamicGap block the Enable assertion and Output assertion signal are checked, and the icon type isselected as graphic. The Convert block was inserted to convert the Boolean output of the CheckDynamic Gap block to double as required by the Bus Creator block. The input and output wave-forms are shown in Figure 9.16.



The Assertion warnings are listed in MATLAB’s Command Window.

10%± 1 volt

1 volt±


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9.9 The Assertion Block

The Assertion block verifies that the elements of the signal at its input have a non−zero value. If all elements are non−zero, the block takes no action. If any element is zero, the block halts thesimulation and displays an error message. The block's parameter dialog box allows us to specifythat the block should display an error message when the assertion fails but allows the simulationto continue.

Example 9.9

In the model of Figure 9.17, the Signal Generator block was specified for a square waveform, inad-vertently the amplitude was specified as 0, and thus the Scope block displayed 0 also. To thismodel we will add an Assertion block to display an error message.

Figure 9.17. Model for Example 9.9 without Assertion block

The model with the addition of an Assertion block is shown in Figure 9.18 where after the simula-tion command is executed, the following message is displayed:

Assertion detected in ‘Figure_9_18/Assertion’ at time 0.000000

Figure 9.18. Model for Example 9.9 with Assertion block


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The Check Discrete Gradient Block

9.10 The Check Discrete Gradient Block

The Check Discrete Gradient block performs a check to determine whether the absolute valueof the difference between successive samples of the element is less than an upper bound. Theblock's parameter dialog box allows us to specify the value of the upper bound whose default valueis unity. If the verification condition is true, the block takes no action. Otherwise, the block haltsthe simulation and displays an error message in the Simulation Diagnostics Viewer.

Example 9.10

In Figure 9.19, the Digital Clock block has been set for Sample time 1 as shown on the Scopeblock and thus the difference between successive samples is 1. We will add a Check Discrete Gra-dient block specifying that the value of the upper bound is unity (the default) to determinewhether an error message will be displayed.

Figure 9.19. Model for Example 9.10 without a Check Discrete Gradient block

The model with the addition of a Check Discrete Gradient block where the value of the upperbound is specified as 1 (default), is shown in Figure 9.20. After the simulation command is exe-

cuted, the following message is displayed:Assertion detected in ‘Figure_9_20/Check Discrete Gradient’ at time

1.000000.

However, if the Digital Clock block is specified for Sample time less than 1, no error message willbe displayed.


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Figure 9.20. Model for Example 9.2 with a Check Discrete Gradient block

9.11 The Check Input Resolution Block

The Check Input Resolution block performs a check to determine whether the input signal has a

specified scalar or vector resolution.* If the resolution is a scalar, the input signal must be a multi-

ple of the resolution within a tolerance. If the resolution is a vector, the input signal must

equal an element of the resolution vector. If the verification condition is true, the block takes noaction. If not, simulation is halted and an error message is displayed.

In general, the resolution of an analog-to-digital (A/D) converter that spans an input volt-age of volts is given by where is the number of bit. For instance, an A/D con-

verter with a range of 0 to 12 volts, with the range is divided to so the

resolution is .

Example 9.11

In the model of Figure 9.21, the resolution for both Check Input Resolution blocks is specified asthe row vector

* Accuracy and resolution have different meaning. Accuracy is the degree with which an instrument measures avariable in terms of an accepted standard value or true value; usually measured in terms of inaccuracy butexpressed as accuracy; often expressed as a percentage of full-scale range. Resolution is the smallest change inthe parameter being measured that causes a detectable change in the output of the instrument. For a detailed dis-cussion on accuracy and resolution, please refer to Electronic Devices and Amplifier Circuits with MATLAB

Applications, ISBN 0-9709511-7-5.

103–

n bit –

X X 2n

1–( ) ⁄ n

n 8= 12 255 ⁄ 47.1 mV≈

47.1 mV


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The Check Input Resolution Block

and the Enable assertion and Output assertion signal is checked. The values 1 (true) and 0 (false)in the Display blocks are justified as follows:

Since the resolution specified in the Check Input Resolution blocks is a vector, the input signalmust be equal to an element of the resolution vector. The resolution specified in the Constant 1block is an element of the resolution vector and thus the output is 1 indicating a True condition.However, the resolution specified in the Constant 2 block is not an element of the resolution vec-tor and thus the output is 0 indicating a False condition.


121

27 1–( )-------------------

1

28 1–( )-------------------

1

29 1–( )-------------------

1

210 1–( )---------------------

1

211 1–( )---------------------×


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9.12 Summary

The blocks in the Model Verification library are intended to facilitate creation of self −validatingmodels. For instance, we can use model verification blocks to verify that signals do not exceedspecified limits during simulation. When we are satisfied that a model is correct, we can turn error

checking off by disabling the verification blocks. We need not to physically remove them from themodel.

• The Check Static Lower Bound block performs a check to verify that each element of theinput signal is greater than (or optionally equal to) a specified lower bound at the current timestep. The block's parameter dialog box allows us to specify the value of the lower bound andwhether the lower bound is inclusive. If the verification condition is true, the block takes noaction. If not, the block halts the simulation and displays an error message.

• The Check Static Upper Bound block performs a check to verify that each element of theinput signal is less than (or optionally equal to) a specified lower bound at the current time

step. The block's parameter dialog box allows us to specify the value of the upper bound andwhether the bound is inclusive. If the verification condition is true, the block takes no action.If not, the block halts the simulation and displays an error message.

• The Check Static Range block performs a check to ascertain that each element of the inputsignal falls inside the same range of amplitudes at each time step. The block's parameter dialogbox allows us to specify the upper and lower bounds of the valid amplitude range and whetherthe range includes the bounds. If the verification condition is true, the block takes no action. If not, the block halts the simulation and displays an error message.

• The Check Static Gap block performs a check to verify that each element of the input signalis less than (or optionally equal to) a static lower bound or greater than (or optionally equalto) a static upper bound at the current time step. If the verification condition is true, the blocktakes no action. If not, the block halts the simulation and displays an error message.

• The Check Dynamic Lower Bound block performs a check to verify that the amplitude of atest signal is less than the amplitude of a reference signal at the current time step. The test sig-nal is the signal connected to the input labeled sig. If the verification condition is true, theblock takes no action. If not, the block halts the simulation and displays an error message.

• The Check Dynamic Upper Bound block performs a check to verify that the amplitude of a

test signal is greater than the amplitude of a reference signal at the current time step. The testsignal is the signal connected to the input labeled sig. If the verification condition is true, theblock takes no action. If not, the block halts the simulation and displays an error message.

• The Check Dynamic Range block performs a check to verify that a test signal falls inside arange of amplitudes at each time step. The width of the range can vary from time step to timestep. The input labeled sig is the test signal. The inputs labeled min and max are the lower and


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Summary

upper bounds of the valid range at the current time step. If the verification condition is true,the block takes no action. If not, the block halts the simulation and displays an error message.

• The Check Dynamic Gap block performs checks to determine whether a gap of possibly vary-ing width occurs in the range of a signal's amplitudes. The test signal is the signal connected tothe input labeled sig. The inputs labeled min and max specify the lower and upper bounds of the dynamic gap, respectively. If the verification condition is true, the block takes no action. If not, the block halts the simulation and displays an error message.

• The Assertion block verifies that the elements of the signal at its input have a non-zero value.If all elements are non-zero, the block takes no action. If any element is zero, the block haltsthe simulation, by default, and displays an error message. The block's parameter dialog boxallows us to specify that the block should display an error message when the assertion fails butallows the simulation to continue.

• The Check Discrete Gradient block performs a check to determine whether the absolute

value of the difference between successive samples of the element is less than an upper bound.The block's parameter dialog box allows us to specify the value of the upper bound (1 bydefault). If the verification condition is true, the block takes no action. Otherwise, the blockhalts the simulation and displays an error message in the Simulation Diagnostics Viewer.

• The Check Input Resolution block performs a check to determine whether the input signalhas a specified scalar or vector resolution. If the resolution is a scalar, the input signal must be

a multiple of the resolution within a tolerance. If the resolution is a vector, the input sig-

nal must equal an element of the resolution vector. If the verification condition is true, theblock takes no action. If not, the block halts the simulation and displays an error message.

10 3–


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9.13 Exercises

1. Consider the model shown below where the inputs and outputs of the Signal Generator blockare also shown, and in the parameters for the Assertion block the Enable Assertion is checkedand the Stop simulation when assertion fails is unchecked. The Signal Generator block has

been specified for a sine waveform of amplitude 1 and frequency 0.25 Hz to accept an externalsignal, i.e., the Clock block. Under those conditions will the Assertion block produce a warn-ing?

2. It is known that noise voltages generated within the circuitry of an analog−to−digital converter

are . Create a model using a Check Dynamic Gap block to display error mes-

sages when the amplitude exceeds this range.

3. For the models shown below, the resolution in both Check Input Resolution blocks 1 and 2 has

been specified as

with . What is the maximum value that can be specified in Constant block 1 to cause

the Display 1 block to display 0 (False), and what is the minimum value that will cause theDisplay 2 block to display 1 (True)?

0.75 mv 10%±

12

2n 1–( )-------------------

n 9=


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Solutions to End−of −Chapter Exercises

9.14 Solutions to End−of −Chapter Exercises

1.The Assertion block detects a 0 value at the start of the simulation time, in this case 10 sec-onds as shown by the Clock block, and thus in MATLAB’s Command Window it outputs themessage:

Assertion detected in 'Exercise_9_1/Assertion' at time 0.000000.

However, the simulation continues for 10 seconds since the Stop simulation when assertionfails is unchecked.

2.The model and input and output waveforms are shown below. Since voltage noise occurs in

random, we set the Signal Generator block for Random waveform with amplitude and

frequency at . To allow for the tolerance from the nominal value, we set

the Constant blocks for and .

The output waveform is logic 0 (False) whenever assertions are detected, and jumps to 1(True) when no assertions are detected. The precise times when assertions are detected aredisplayed in MATLAB’s Command Window.

0.01

0.1 Hz 10%± 0.75 mv

+0.0085 0.0085–


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9 20 Introduction to Simulink with Engineering Applications

3.Since the resolution specified in both Check Input Resolution blocks is the scalar

the input signal must be a multiple of this resolution within a tolerance. Since,

any value equal of greater than will cause a display 1 (True), and any value less than

will cause a display of 0 (False) as shown in the models below.

Upon execution of the Simulation command, MATLAB’s Command Window displays Asser-tions detected in the Check Input Resolution block 1 from 0 to 10 in steps of 0.2.

12

29 1–( )-------------------

10 3–

12

29 1–( )------------------- 0.0235=

0.0235

0.0235

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BAB09 - The Model Verification Library