Bai 006 Thuchanh Cpld Adc Dac

PHAN 1 ADC

PHAN 2 DAC

PHAN 3: IEU KHIEN LED MA TRAN 2 MAU 88

PHAN 4: GIAO TIEP BO NH

PHAN 5: IEU KHIEN ONG C

Quy c: cac bai thc hanh eu phai mo phong.

Sau khi chay mo phong ung th tien hanh khai gan chan va chay thc.

Lam bao cao bang file word cho cac bai a thc hanh cua bai 6 va nop lai sau khi thc hanh

xong.

Ten cua kien truc la ten cua Sinh vien thc hanh. Trong bao cao co trnh bay:

Chng trnh VHDL

Ket qua bien dch co ay u cac thong tin ngay thang

Co dang song mo phong chup lai bang snagit.

Chu y: trong cac chng trnh khong in phan khai bao th vien nh mac nhien phai co.

Bai so 6. Mach ieu khien. Tai lieu thc hanh PLD

104 Nguyen nh Phu BMTCN SPKT TPHCM.

I. PHAN 1: ADC

1. Bai mau 1:

Hay viet chng trnh mo ta CPLD ieu khien ADC 0809 e chuyen oi kenh th 1 hien

th gia tr so nh phan tren 8 led n.

Bc 1: Tm hieu ADC trong bo th nghiem:

Khoi ADC cua bo th nghiem dung IC 0809 vi cac tn hieu ieu khien bao gom:

a. A2A1A0: la 3 ng a ch chon kenh, ALE la ieu khien chot a ch.

b. START: ieu khien bat au qua trnh chuyen oi.

c. OE: cho phep xuat d lieu a noi trang thai cho phep.

d. EOC: bao cho biet qua trnh chuyen oi ket thuc.

e. D7-D0: la 8 ng d lieu ra cua ADC.

f. Ngo vao cung cap xung clock e ADC chuyen oi c lay t mach dao ong

dung IC 74HC14 a co tren mach.

Hnh 6-1. S o chan va s o khoi ADC 0809.

Bang 6-1. Bang chon kenh.

Bc 2: Phan tch dang song ieu khien ADC 0809:


Nguyen nh Phu BMCNVT HSPKT TPHCM. 105

Dang song ieu khien ADC 0809 nh hnh sau:

Hnh 6-2. Dang song ieu khien ADC 0809.

Bc 3: S o khoi giao tiep CPLD vi ADC0809:

Xung clk (chan 38) noi vi mach dao ong co tren bo th nghiem tan so 10kHz, clr noi vi

SW(chan 39). Ngo ra so D7-D0 cua ADC ket noi trc tiep vi 8 led n.

clk

clr

addr

CPLD

startale

ADC 0809

addr

startale

8 LED

ND0-D7

(38)

(39)

Hnh 6-3. S o khoi CPLD ieu khien ADC 0809.

Bc 4: Chng trnh CPLD ieu khien ADC0809:

entity ADC_LEDDON is

Port ( CLR : in STD_LOGIC;

CLK : in STD_LOGIC;

ALE : out STD_LOGIC;

START : out STD_LOGIC;

ADDR : out STD_LOGIC_VECTOR (2 downto 0));



end ADC_LEDDON;

architecture Behavioral of ADC_LEDDON is

TYPE STATES IS (ST0,ST1,ST2);

SIGNAL PR_STATE,NX_STATE: STATES;

SIGNAL DEM1,DEM2: INTEGER RANGE 0 TO 1000;

begin

PROCESS(CLR,CLK)

BEGIN

IF CLR ='0' THEN PR_STATE



clk

clr

addr

CPLD

startale

ADC 0809

addr

startale

D0-D7

(38)

(39)

D0-D7

an0an1

clkclr

sseg

an2an3BCD0

BCD1

BCD2

BCD3

Vcc

Hnh 6-4. S o khoi CPLD ieu khien ADC 0809 hien th tren led 7 oan.

Bc 2: Chng trnh CPLD ieu khien ADC0809:

Chng trnh nay dung 2 component HEXTOBCD va DIS_MUX4. Xem hnh 6-5.

Hnh 6-5. Chng trnh CPLD ieu khien ADC 0809.

Chng trnh chnh:

entity ADC_7DOAN is

Port ( CLR : in STD_LOGIC;

CLK : in STD_LOGIC;



DI : in STD_LOGIC_VECTOR (7 downto 0);

ALE : out STD_LOGIC;

START : out STD_LOGIC;

ADDR : out STD_LOGIC_VECTOR (2 downto 0);

SSEG : OUT STD_LOGIC_VECTOR (7 downto 0);

AN : out STD_LOGIC_VECTOR (3 downto 0));

end ADC_7DOAN;

architecture Behavioral of ADC_7DOAN is

TYPE STATES IS (ST0,ST1,ST2);

SIGNAL PR_STATE,NX_STATE: STATES;

SIGNAL DEM1,DEM2: INTEGER RANGE 0 TO 1000;

SIGNAL BCD0,BCD1,BCD2: STD_LOGIC_VECTOR (3 DOWNTO 0);

begin

DISPLAY: ENTITY WORK.DIS_MUX4

PORT MAP (CLK => CLK, CLR=> CLR, AN => AN, SSEG => SSEG,

BCD0=> BCD0, BCD1=>BCD1, BCD2=>BCD2, BCD3

=>"1111");

HEXBCD: ENTITY WORK.HEXTOBCD

PORT MAP (HEXIN => DI, BCDDV => BCD0, BCDCH => BCD1,BCDTR =>

BCD2 );

PROCESS(CLR,CLK)

BEGIN

IF CLR ='0' THEN PR_STATE



Port ( CLK : in STD_LOGIC;

CLR : in STD_LOGIC;

BCD0,BCD1,BCD2,BCD3: IN STD_LOGIC_VECTOR (3 downto 0);

AN : out STD_LOGIC_VECTOR (3 downto 0);

SSEG : out STD_LOGIC_VECTOR (7 downto 0));

end DIS_MUX4;

architecture Behavioral of DIS_MUX4 is

CONSTANT N: INTEGER := 5;

SIGNAL PR_S,NX_S: UNSIGNED (N-1 DOWNTO 0);

SIGNAL SEL: STD_LOGIC_VECTOR(1 DOWNTO 0);

SIGNAL BCD:STD_LOGIC_VECTOR (3 downto 0);

begin

PROCESS(CLK,CLR)

BEGIN

IF CLR ='0' THEN PR_S '0');

ELSIF RISING_EDGE(CLK) THEN PR_S



Chng trnh HEXTOBCD: co chnh lai cac kieu d lieu cho phu hp.

entity HEXTOBCD is

Port ( HEXIN : in STD_LOGIC_VECTOR (7 downto 0);

BCDDV,BCDCH,BCDTR : out STD_LOGIC_VECTOR (3 downto 0));

end HEXTOBCD;

architecture Behavioral of HEXTOBCD is

begin

PROCESS(HEXIN)

VARIABLE QT: STD_LOGIC_VECTOR(19 DOWNTO 0);

BEGIN

QT:= (OTHERS =>'0');

QT(7 DOWNTO 0):= HEXIN;

FOR I IN 0 TO 6

LOOP

QT := QT(18 DOWNTO 0) & QT(19);

IF QT(11 DOWNTO 8) >= "0101" THEN QT(11 DOWNTO 8):=

QT(11 DOWNTO 8) + "0011";

ELSIF QT(15 DOWNTO 12) >= "0101" THEN QT(15 DOWNTO 12):=

QT(15 DOWNTO 12) + "0011";

END IF;

END LOOP;

QT := QT(18 DOWNTO 0) & QT(19);

BCDTR



1. Hay viet chng trnh mo ta mach ieu khien led ma tran sang ch A mau xanh.

2. Hay viet chng trnh mo ta mach ieu khien led ma tran sang ch A mau o.

3. Hay viet chng trnh mo ta mach ieu khien led ma tran sang ch A mau xanh 1 giay va

sau o sang mau o 1 giay roi lap lai.

4. Hay viet chng trnh mo ta mach ieu khien led ma tran sang ch A mau xanh dch

chuyen.

IV. PHAN 4: GIAO TIEP BO NH

1. Hay viet chng trnh mo ta mach ieu khien oc d lieu trong bo nh EEPROM xuat ra

8 led n.

2. Hay viet chng trnh mo ta mach ieu khien d lieu trong bo nh EEPROM xuat ra 8 led

n ong thi cat vao bo nh RAM.

3. Hay viet chng trnh mo ta mach ieu khien oc d lieu trong bo nh EEPROM xuat ra

ieu khien led 7 oan mot chuoi d lieu dch chuyen.

V. PHAN 5: IEU KHIEN ONG C

1. Hay viet chng trnh mo ta mach ieu khien ong c bc quay thuan.

2. Hay viet chng trnh mo ta mach ieu khien ong c bc quay thuan thuan co 2 nut

ieu khien start, stop.

3. Hay viet chng trnh mo ta mach ieu khien ong c bc co 3 nut ieu khien start, stop,

va ao chieu. Khi nhan start th mac nhien ong c quan thuan, khi nhan ao chieu th

ong c se ao chieu.

4. Hay viet chng trnh mo ta mach ieu khien ong c DC co 3 nut ieu khien start, stop,

va ao chieu. Khi nhan start th mac nhien ong c quan thuan, khi nhan ao chieu th

ong c se ao chieu.



THIET KE CHNG TRNH VHDL DANG TOP-

LEVEL

Yeu cau: Viet chng trnh mo ta mach chia xung, em va hien th.

Bc 1: tao chng trnh khai bao port

Chung ta can xay dng module VHDL dang top level cho 3 khoi: clock_divide, counter va

display_drive.

Divide clock

count

Display_drive

Clock_osc Clock_div

clockdirect

resetPause_design

cout_out

count_in led

Direct_extReset_extPause_Design

Clock_ext

Led_out

Clock_div_sig

cout_out_sig

Clock_div_sig

cout_out_sig

Hnh 6-6. S o khoi he thong.

Bc 2: tao chng trnh chnh khai bao port

Vao Project -> New source e xay dng module VHDL mi va at ten la top. Tat ca cac port

phai khai bao trong module nay. Trong thiet ke minh hoa nay chung ta co 4 port ten la clock_ext,

reset_ext, direction_ext va pause_design va port ngo ra la Led_out.

Ma cho chng trnh sau khi khai bao cac tn hieu vao ra nh sau:



Hnh 6-7. Chng trnh chnh khai bao cac port.

Bc 3: - khai bao components trong phan kien truc cua chng trnh chnh

Do chung ta se dung 3 mo hnh clock_divide, counter va display_drive nh la cac thanh phan

trong thiet ke top level nen chung ta phai khai bao chung nh la cac thanh phan component nam

gia hang kien truc architecture va begin nh sau:

architecture Behavioral of top is

Component clock_divide

Port ( clock_osc: in std_logic;

Clock_div: out std_logic);

End component;

Component counter

Port ( clock: in std_logic;

reset: in std_logic;

direction: in std_logic;

pause_design: in std_logic;

count_out: out std_logic_vector(3 downto 0));

End component;

Component display_drive

Port ( count_in: in std_logic_vector(3 downto 0);

Led: out std_logic_vector(6 downto 0));

End component;

Ket qua nh hnh sau:



Hnh 6-8. Chng trnh chnh khai bao cac components.

Bc 4: mo ta cac thanh phan lien ket vi nhau trong than chng trnh nam di begin

en ay th cac thanh phan component a c khai bao, chung ta phai khai bao s hien dien cua

chung trong thiet ke. Hay nhap cac dong ma lenh sau vao gia begin va end nh sau:

begin

U1: clock_divide

Port map (clock_osc => clock_ext,

Clock_div => clock_div_sig);

U2: counter

Port map (clock => Clock_div_sig,

Reset => Reset_ext,

Direction => Direction_ext,

pause_design => pause_design,

count_out => count_in_sig);

U3: display_drive

Port map (count_in => count_in_sig,

Led => led_out);

end Behavioral;

Ket qua nh hnh sau:



Hnh 6-9. Chng trnh chnh khai bao ten cac chng trnh cua components. Chu y cac port cua cac thanh phan phai noi vi cac port nam trong phan khai bao thiet ke

(clock_ext, reset_ext, direction_ext hoac Led_out) hoac cac tn hieu nam ben trong (clock_div_sig

hoac count_in_sig).

Bc 5: Khai bao them tn hieu lien lac gia cac component

Chung ta phai khai bao them 2 tn hieu ma chung ta se dung. Sau khi khai bao het cac thanh phan

th ta khai bao 2 tn hieu nam trc begin nh sau

Signal count_in_sig: std_logic_vector (3 downto 0);

Signal clock_div_sig: std_logic;

Hnh 6-10. Chng trnh chnh khai bao them tn hieu signal.



Bc 6: xuat hien cac thanh phan component trong ca so source

Lu file. en ay chung ta thay trong ca so Project Navigator Source nh hnh sau:

Hnh 6-11. Chng trnh chnh xuat hien ten cua cac components U1, U2, U3.

Bc 7: Chon thanh phan component U1 e viet source

Chon thanh phan U1 clock divide ca s source va chon create new source ca s Processes:

Hnh 6-12. Xay dng chng trnh cho components U1.

at ten file la clock_divide:

Chu y: ten phai trung vi ten trong ca so source.



Hnh 6-13. at ten file cho components U1.

Bam next va khai bao 2 tn hieu la clock_osc va clock_div

Hnh 6-14. Khai bao cac tn hieu cho components U1.

roi anh cac lenh vao nh hnh sau:



Hnh 6-15. Ket qua bien soan va kiem tra thanh cong chng trnh cua components U1.


Chon thanh phan U2 count source va chon create new source:

at ten file la count va khai bao tn hieu va anh cac lenh vao nh hnh sau:





Chon thanh phan U3-display_drive source va chon create new source:

at ten file la display_drive, va khai bao 2 tn hieu la count_in va led roi anh cac lenh vao nh

hnh sau:


Xem lai Cac chng trnh sau khi a viet

Chng trnh chnh TOP.VHD

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top is

Port ( clock_ext : in STD_LOGIC;

reset_ext : in STD_LOGIC;

direction_ext : in STD_LOGIC;

pause_design : in STD_LOGIC;

led_out : out STD_LOGIC_VECTOR (6 downto 0));

end top;



architecture Behavioral of top is

Component clock_divide

Port (clock_osc: in std_logic;

Clock_div: out std_logic);

End component;

Component counter

Port (clock: in std_logic;

reset: in std_logic;

direction: in std_logic;

pause_design: in std_logic;

count_out: out std_logic_vector(3 downto 0));

End component;

Component display_drive

Port (count_in: in std_logic_vector(3 downto 0);

Led: out std_logic_vector(6 downto 0));

End component;

Signal count_in_sig: std_logic_vector (3 downto 0);

Signal clock_div_sig: std_logic;

begin

U1: clock_divide

Port map (clock_osc => clock_ext,

Clock_div => clock_div_sig);

U2: counter

Port map (clock => Clock_div_sig,

Reset => Reset_ext,

Direction => Direction_ext,

pause_design => pause_design,

count_out => count_in_sig);

U3: display_drive

Port map(count_in => count_in_sig,

Led => led_out);

end Behavioral;

Chng trnh component: CLOCK_DIVIDE.VHD

library IEEE;




entity clock_divide is

Port ( clock_osc : in STD_LOGIC;



clock_div : out STD_LOGIC);

end clock_divide;

architecture Behavioral of clock_divide is

Signal count: std_logic_vector(3 downto 0):= "0000";

begin

process(clock_osc)

begin

if clock_osc = '1' and clock_osc'event

then count



Chng trnh component: DISPLAY_DRIVE.VHD

library IEEE;




entity display_drive is

Port ( count_in : in STD_LOGIC_VECTOR (3 downto 0);

led : out STD_LOGIC_VECTOR (6 downto 0));

end display_drive;

architecture Behavioral of display_drive is

begin

with count_in select

led



Hnh 6-18. Ket qua bien dch chng trnh chnh thanh cong.

Sau khi bien dch thanh cong th tien hanh mo phong:

Sau khi at ten mo phong xong th cac file mo phong gom chng trnh chnh va mo phong

tng chng trnh con. Nen chon lan lt tng chng trnh con mo phong trc va sau o mo

phong chng trnh chnh.

Bc 10: Mo phong

Chon chng trnh chia xung clock_divide e mo phong:

Hnh 6-19. Chon clock_divide e mo phong.

Dang song trc khi mo phong:



Hnh 6-20. Dang song trc khi mo phong.

Dang song sau khi mo phong, tn hieu ngo ra clock_div co tan so bang tan so ngo vao chia cho 16:

Hnh 2-21. Dang song sau khi mo phong.

Chon chng trnh em counter e mo phong:

Hnh 6-22. Chon COUNTER e mo phong.



Dang song sau khi mo phong, tn hieu ngo ra COUNT_OUT co gia tr em tang dan phu thuoc vao

tn hieu ieu khien reset, direction, pause:




Chon chng trnh top e mo phong:

Hnh 6-25. Chon top e mo phong.



Dang song sau khi mo phong, tn hieu ngo ra LED_OUT la ma 7 oan:


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Bai 006 Thuchanh Cpld Adc Dac