Basics of Digital Systems Dept. of ECE · 2019-10-01 · Basics of Digital Systems Dept. of ECE KL University, Guntur Multiplexers: Multiplexing means transmitting a large number

Basics of Digital Systems Dept. of ECE

KL University, Guntur

Multiplexers:

Multiplexing means transmitting a large number of information units over a smaller number

of channels or lines. A digital multiplexer is a combinational circuit that selects binary

information from any of many input lines and directs it to a single output line. The selection

of a particular input lie is controlled by a set of selection lines. Generally, there are input

lines and selection lines whose bit combinations determine which input is selected.

Multiplexer:

A Multiplexer shown, consists of four input lines to , two select lines

Multiplexer with Enable:

Y

0 0

0 1

1 0

1 1



Multiplexers usually have an ENABLE input that can be used to control the multiplexing

function. When this input is enabled, that is, when it is in logic ‘1’ or logic ‘0’ state,

depending upon whether the ENABLE input is active HIGH or active LOW respectively, the

output is enabled. The multiplexer functions normally. When the ENABLE input is inactive,

the output is disabled and permanently goes to either logic ‘0’ or logic ‘1’ state, depending

upon whether the output is un-complemented or complemented.

Cascading of Multiplexers:

Implement an Multiplexer using two multiplexers.

Combinational Logic Implementation:



One of the most common applications of a multiplexer is its use for implementation of

combinational logic Boolean functions. The simplest technique for doing so is to employ a

2n-to-1 MUX to implement an n-variable Boolean function. The input lines corresponding to

each of the minterms present in the Boolean function are made equal to logic ‘1’ state. The

remaining minterms that are absent in the Boolean function are disabled by making their

corresponding input lines equal to logic ‘0’.

1. Implement ∑ using a Multiplexer.

2. Implement ∑ using a Multiplexer.

List the inputs of the multiplexer and under them list all the minterms in two rows. The first

row lists all those minterms where is complemented, and the second row all the minterms



with uncomplemented. Circle all the minterms of the function and inspect each column

separately.

If the two minterms in a column are not circled, apply 0 to the corresponding multiplexer

input. If the two minterms are circled, apply 1 to the corresponding multiplexer input. If the

bottom minterm is circled and the top is not circled, apply A to the corresponding multiplexer

input. If the top minterm is circled and the bottom is not circled, apply A’ to the

corresponding multiplexer input.

Demultiplexer:

A demultiplexer is a circuit that receives information on a single line and transmits this

information on one of 2n possible output lines. The selection of a specific output line is

controlled by the bit values of n selection lines.

:

0 0 0 0 0 0 0

0 0 1 0 0 0

0 1 0 0 0 0

0 1 0 1 0 0

1 0 0 0 0 0 0

1 0 1 0 0 1 0

1 1 0 0 0 0 0

1 1 1 0 0 0 1

,

,



Code Converters:

A code converter is a combinational logic circuit that changes data presented in one type of

binary code to another type of binary code.

Binary to Gray Code Converter:

4 bit Binary to Gray code converter is a logic circuit which converts 4 bit Binary code to

corresponding Gray code.

By simplifying the above expressions using K maps, we get

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0



Gray to Binary Code Converter:

4 bit Gray to Binary code converter is a logic circuit which converts 4 bit Gray code to

corresponding Binary code.

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

0 1 0 0 0 1 1 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 1 1 0 1 0

1 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 1 1



BCD to Excess-3 Code Converter:



Parity Generator and Checker:

When digital data is transmitted from one location to another, it is necessary to know at the

receiving end, whether the received data is free of error. To help make the transmission

accurate, special error detection methods are used. To detect errors, we must keep a constant

check on the data being transmitted. To check accuracy we can generate and transmit an extra

bit along with the message (data). This extra bit is known as the parity bit and it decides

whether the data transmitted is error free or not. There are two types of parity bits, namely,

even parity and odd parity.

The circuit that generates the parity bit in the transmitter is called a parity generator. The

circuit that checks the parity in the receiver is called a parity checker.

Even Parity Generator:

Even Parity Checker:

X Y Z P

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1



BCD Adder:

A BCD adder is a combinational circuit that adds two BCD digits in parallel and produces a

sum digit which is also in BCD.

Add two 4-bit BCD numbers using straight binary addition. If the four bit sum is equal to or

less than 9, the sum is in proper BCD form. If the four bit sum is greater than 9 or if a carry is

generated from the sum, the sum is not in BCD form. In this case a correction is required that

is obtained by adding the digit 6 (0110) to the sum produced by binary adder.



BCD Subtractor:

In BCD subtraction, minuend is added with 9’s complement of subtrahend. The 9’s

complement is obtained by using

When minuend is added with 9’s complement of subtrahend, if there is a carry out, it must be

added as an end around carry (EAC) and the result is a positive number. If there is no carry,

the result is a negative number and hence 9’s complement of the result is formed to get the

magnitude.



BCD Adder/Subtractor:

When , the circuit acts an adder and when , the circuit acts as a Subtractor.



Carry Look-ahead adder:

The addition of two binary numbers in parallel implies that all the bits of the augend and the

addend are available for computation at the same time. The total propagation time is equal to

the propagation delay of a typical gate times the number of gate levels in the circuit. The

longest delay time in a parallel adder is the time it takes the carry to propagate through the

full-adders, known as carry propagation time.

Consider the circuit of the full-adder and we define two new binary variables:

;

The output sum and carry can be expressed as

;

is called a carry generate and it produces an output carry when both are one,

regardless of the input carry. is called a carry propagate because it is the term associated

with the propagation of the carry from to



Look-ahead carry generator:

The three Boolean functions for and are implemented in the look-ahead carry

generator. does not have to wait for and to propagate; and it is propagated at the

same time as .

The carry look-ahead adder circuit with look-ahead carry generator is as shown.



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Basics of Digital Systems Dept. of ECE · 2019-10-01 · Basics of Digital Systems Dept. of ECE KL University, Guntur Multiplexers: Multiplexing means transmitting a large number