PROJECT BASED LAB REPORT

On

Design a logic circuit for 4-bit arithmetic circuit using Multiplexers, Full-Adders

Submitted in partial fulfilment of the

Requirements for the award of the Degree of

Bachelor of Technology

In

Electronics & Communication Engineering

By

K.BHANUSINDUSH-14004445

A.SARITHA-14004446

D.KRANTHIVEER-14004447

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

(DST-FIST Sponsored Department)

K L UniversityGreen Fields, Vaddeswaram, Guntur District-522 502

2015-16

1

K L UniversityDEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

(DST-FIST Sponsored Department)

This is to certify that this project based lab report entitled “Design a logic circuit for

4-bit arithmetic circuit using Multiplexers, Full-Adders” is a bonafide work done by

A.Saritha(14004446)in partial fulfilment of the requirement for the award of degree in

BACHELOR OF TECHNOLOGY in Electronics and Communication Engineering

during the academic year 2015-2016.

Faculty In Charge Head of the Department

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CERTIFICATE

K L UniversityDEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

(DST-FIST Sponsored Department)

3

We hereby declare that this project based lab report entitled “Design a logic circuit for 4-

bit arithmetic circuit using Multiplexers, Full-Adders” has been prepared by us in partial

fulfilment of the requirement for the award of degree “BACHELOR OF TECHNOLOGY in

ELECTRONICS AND COMMUNICATION ENGINEERING” during the academic year

2015-2016. I also declare that this project based lab report is of our own effort and it has not been

submitted to any other university for the award of any degree.

Date: 21-4-2016 K.BHANUSINDUSH(14004445)

Place: KLUNIVERSITY A.SARITHA(14004446)

D.KRANTHIVEER(14004447)

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DECLARATION

ACKNOWLEDGEMENT

My sincere thanks to K.PHANISREENIVAS in the Lab for their outstanding support

throughout the project for the successful completion of the work

We express our gratitude to DR.A.S.C.S. SASTRY, Head of the Department for

Electronics and Communication Engineering for providing us with adequate facilities,

ways and means by which we are able to complete this term paper work.

We would like to place on record the deep sense of gratitude to the honourable Vice

Chancellor, K L University for providing the necessary facilities to carry the concluded

term paper work.

Last but not the least, we thank all Teaching and Non-Teaching Staff of our department

and especially my classmates and my friends for their support in the completion of our

term paper work.

K.Bhanusindush(14004445)

A.Saritha(14004446)

D.Kranthiveer(14004447)

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CONTENTSContent PG.NO

1. ABSTRACT 6

2. DESCRIPTION 7-9

3. MODULES

3.1 Analyze the concepts of Multiplexers and Full-adder 9-11

3.2 Understand the design of an arithmetic circuit 12

3.3 Design a 4-bit Arithmetic circuit using combinational circuits

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3. DESIGN 14

4. PROJECT DESCRIPTION 15

5. SNAPSHOTS OF OUTPUT 16

6. REFERENCES 17

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ABSTRACT

In digital circuit theory, combinational logic is a type of digital logic which is implemented by Boolean circuits, where the output is a pure function of the present input only. This is in contrast to sequential logic, in which the output depends not only on the present input but also on the history of the input. In other words, sequential logic has memory while combinational logic does not.

Combinational logic is used in computer circuits to perform Boolean algebra on input signals and on stored data. Practical computer circuits normally contain a mixture of combinational and sequential logic. For example, the part of an arithmetic logic unit, or ALU, that does mathematical calculations is constructed using combinational logic. Other circuits used in computers, such as half adders, full adders, halfsubtractor , full subtractors, multiplexers, demultiplexers, encoders and decoders are also made by using combinational logic.

Adders are essential building blocks for digital systems. There are many different adder architectures that all compute the same result, but they get to the results in different ways. Different adder architectures also differ in area, speed, and power, and there is no architecture that dominates all other adders in all the areas .Therefore hardware designers choose adders based on system area, speed, and power constraints.

In electronics, a multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output.[2] Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth. A multiplexer is also called a data selector.An electronic multiplexer makes it possible for several signals to share one device or resource, for example one A/D converter or one communication line, instead of having one device per input signal.

KEYWORDS:

ALU, Adder, Stores Information, Multiplexers, Combinational.

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DESCRIPTION

An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and

logic operations. It represents the fundamental building block of the central processing

unit (CPU) of a computer. Modern CPUs contain very powerful and complex ALUs. In

addition to ALUs, modern CPUs contain a control unit (CU).

Most of the operations of a CPU are performed by one or more ALUs, which load data

from input registers. A register is a small amount of storage available as part of a CPU.

The control unit tells the ALU what operation to perform on that data and the ALU stores

the result in an output register. The control unit moves the data between these registers,

the ALU, and memory.

Arithmetic Logical Unit is the very important subsystem in the digital system design. An

Arithmetic logic Unit (ALU) is an integral part of a computer processor. It is a

combinational logic unit that performs its arithmetic and logic operations. ALUs of

various bit-widths are frequently required in very large-scale integrated circuits (VLSI)

from processors to application specific integrated circuits (ASICs). ALU is getting

smaller and more complex nowadays to enable the development of a more powerful but

smaller computer.

The demand for low power & high speed processing has been increasing as a result of

expanding computer and signal processing applications. Higher throughput arithmetic

operations are important to achieve the desired performance in many real-time signal and

image processing applications. The key arithmetic operations in such applications are

multiplication, addition, division and subtraction.

Fig 1.1: ARTHEMETIC LOGIC UNIT

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FEATURES OF ALU:

Low-power CMOS Process Technology

1. Total 16 arithmetic operations (add, subtract, plus, shift, plus 12 others)

2.Total 16 logic operations (XOR, AND, NAND, NOR, OR, plus 11 others)

3. Capable of active-high and active-low operation.

4. Full carry look-ahead for high-speed arithmetic operation.

5. Arithmetic operations expressed in 2s complement notation.

6. 4 selection lines are to perform the operations on two 4 bit inputs in both the units.

7. The 5th select line is used to select either one of the units.

A 4-bit high-speed parallel Arithmetic Logic Unit (ALU). Controlled by the four

Function Select inputs (S0–S3) and the Mode Control input (M), it can perform all the 16

possible logic operations or 16 different arithmetic operations on active-HIGH or active-

LOW operands. The Function Table lists these operations.

When the Mode Control input (M) is HIGH, all internal carries are inhibited and the

device performs logic operations on the individual bits as listed. When the Mode Control

input is LOW, the carries are enabled and the device performs arithmetic operations on

the two 4-bit words. The device incorporates full internal carry look ahead and provides

for either ripple carry between devices using the Cn+4 output, or for carry look-ahead

between packages using the signals P (Carry Propagate) and G (Carry Generate). In the

Add mode, P indicates that F is 15 or more, while G indicates that F is 16 or more. In the

Subtract mode, P indicates that F is zero or less, while G indicates that F is less than zero.

P and G are not affected by carry in. When speed requirements are not stringent, it can

be used in a simple Ripple Carry mode by connecting the Carry output (Cn+4) signal to

the Carry input (Cn) of the next unit. For high-speed operation the device is used in

conjunction with a carry look ahead circuit. One carry look ahead package is required for

each group of four F181 devices. Carry look ahead can be provided at various levels and

offers high-speed capability over extremely long word lengths.

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COMBINATIONAL CIRCUIT

In  digital circuit theory, combinational logic (sometimes also referred to as time-independent logic[1] ) is a type of digital logic which is implemented by Boolean circuits, where the output is a pure function of the present input only. This is in contrast to sequential logic, in which the output depends not only on the present input but also on the history of the input. In other words, sequential logic has memory while combinational logic does not.

Combinational logic is used in computer circuits to perform Boolean algebra on input

signals and on stored data. Practical computer circuits normally contain a mixture of

combinational and sequential logic. For example, the part of an arithmetic logic unit, or

ALU, that does mathematical calculations is constructed using combinational logic. Other

circuitsusedincomputers,suchas halfadders, fulladders, multiplexers, demultiplexers, enco

ders and decoders are also made by using combinational logic.

An alternate term is combinatorial logic,

Fig 1.2: COMBINATIONAL CIRCUIT

Design of a combinational circuit begins with a behavioral specification and selection of

the implementation technique. These are then followed by simplification, hardware

synthesis, and verification. Combinational circuits can be specified via Boolean logic

expressions, structural descriptions, or truth tables. Various implementation techniques,

using fixed and programmable components, are outlined in the rest of this article.

Combinational circuits implemented with fixed logic tend to be more expensive in terms

of design effort and hardware cost, but they are often both faster and denser and consume

less power. They are thus suitable for high-speed circuits and/or high-volume production.

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Analyze the concepts of Multiplexers and Full-adders

MULTIPLEXER

In electronics, a multiplexer (or mux) is a device that selects one of

several analog or digital input signals and forwards the selected input into a single line.[1] A multiplexer of 2n inputs has n select lines, which are used to select which input line

to send to the output.[2] Multiplexers are mainly used to increase the amount of data that

can be sent over the network within a certain amount of time and bandwidth.[1] A

multiplexer is also called a data selector.

An electronic multiplexer makes it possible for several signals to share one device or

resource, for example one A/D converter or one communication line, instead of having

one device per input signal.

Conversely, a demultiplexer (or demux) is a device taking a single input signal and

selecting one of many data-output-lines, which is connected to the single input. A

multiplexer is often used with a complementary demultiplexer on the receiving end.

An electronic multiplexer can be considered as a multiple-input, single-output switch, and

a demultiplexer as a single-input, multiple-output switch. The schematic symbol for a

multiplexer is an isosceles trapezoid with the longer parallel side containing the input pins

and the short parallel side containing the output pin. The schematic on the right shows a

2-to-1 multiplexer on the left and an equivalent switch on the right. The   wire

connects the desired input to the output

ADDER:

In electronics, an adder or summer is a digital logic circuit that

performs addition of numbers. In many computers and other kinds of processors, adders

are used not only in the arithmetic logic units, but also in other parts of the processor,

where they are used to calculate addresses, table indices, increment and decrement

operators, and similar operations.

Although adders can be constructed for many numerical representations, such as binary-

coded decimal or excess-3, the most common adders operate on binary numbers. In cases

where two's complement or ones' complement is being used to represent negative

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numbers, it is trivial to modify an adder into an adder–subtractor. Other signed number

representations require a more complex adder

Fig1.4: 1 BIT ADDER

A  adder adds binary numbers and accounts for values carried in as well as out. A

one-bit full adder adds three one-bit numbers, often written as A, B, and Cin; A and B are

the operands, and Cin is a bit carried in from the previous less significant stage.The full

adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. bit binary

numbers. The circuit produces a two-bit output, output carry and sum typically

represented by the signals Cout and S,

A full adder can be implemented in many different ways such as with a

custom transistor-level circuit or composed of other gates. One example implementation

with   and  .

In this implementation, the final OR gate before the carry-out output may be replaced by

an XOR gate without altering the resulting logic. Using only two types of gates is

convenient if the circuit is being implemented using simple IC chips which contain only

one gate type per chip.

A full adder can be constructed from two half adders by connecting A and B to the input

of one half adder, connecting the sum from that to an input to the second adder,

connecting Ci to the other input and OR the two carry outputs. The critical path of a full

adder runs through both XOR-gates and ends at the sum bit  . Assumed that an XOR-gate

takes 3 delays to complete, the delay imposed by the critical path of a full adder is equal

to

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The carry-block subcomponent consists of 2 gates and therefore has a delay of

UNDERSTAND THE DESIGN OF ARTHEMETIC CIRCUIT

ARTHEMETIC CIRCUIT COMLEXITY:

In computational complexity theory, arithmetic circuits are the standard model

for computing polynomials. Informally, an arithmetic circuit takes as inputs either

variables or numbers, and is allowed to either add or multiply two expressions it already

computed. Arithmetic circuits give us a formal way for understanding the complexity of

computing polynomials. The basic type of question in this line of research is `what is the

most efficient way for computing a given polynomial f?

FigE1.5: ARTHEMETIC CIRCUIT COMPLEXITY

An arithmetic circuit C over the field F and the set of variables x1,...,xn is a directed

acyclic graph as follows. Every node in it with in degree zero is called an input gate and is labeled

by either a variable xi or a field element in F. Every other gate is labeled by either + or ; in the

first case it is a sum gate and in the second a product gate. An arithmetic formula is a circuit in

which every gate has outdegree one (and so the underlying graph is a directed tree).

A circuit has two complexity measures associated with it: size and depth. The size of a

circuit is the number of gates in it, and thedepth of a circuit is the length of the longest

directed path in it. For example, the circuit in the figure has size six and depth two.

An arithmetic circuit computes a polynomial in the following natural way. An input gate

computes the polynomial it is labeled by. A sum gate v computes the sum of the

polynomials computed by its children (a gate u is a child of v if the directed edge (u,v) is

in the graph). A product gate computes the product of the polynomials computed by its

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children. Consider the circuit in the figure, for example: the input gates compute (from

left to right) x1,x2 and 1, the sum gates compute x1 + x2 and x2 + 1, and the product gate

computes (x1 + x2)x2(x2 + 1).

Design a 4-bit Arithmetic circuit using combinational circuits The project is designed to implement 4-bit arthemetic circuit using multiplexers

and full adder.The project consists of following ic pin diagrams,the project consists of

two ic pins 74153,7483

Fig1.6: IC PIN DIAGRAM OF 74153

Fig 1.7:IC PIN DIAGRAM FOR 7483

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CIRCUIT DIAGRAM FOR 4-BIT ARTHEMETIC CIRCUIT

USING MULTIPLEXER’S AND FULL-ADDERS

`

Fig 1.8:CIRCUIT DIAGRAM OF ARTHEMETIC LOGIC CIRCUIT

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OUTPUT USING MULTISIM:

Fig 1.9:OUPUT USING MULTISIM

PROJECT DESCREPTION:

If two selected lines are given at low level and also carry(input) also given at low

level then ADD operation is performed

If two selected lines are given at low level and also carry(input) is given at high

level

Then the ADD WITH CARRY operation is performed

if two selected lines one of the given is low level and another one is given as high

level and carry(input) is also given low level then SUBTRACT WITH

BORROW operation is performed

if two selected lines one of the given is low level and another one is given as high

level and carry(input) is also given high level then SUBTRACT operation is

performed

if two selected lines one of the given is low level and another one is given as high

level and carry(input) is also given low level then only A values are obtained

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if two selected lines one of the given is low level and another one is given as high

level and carry(input) is also given high level then INCREMENT operation is

performed

if two selected lines one of the given is high level and another one is given as

high level and carry(input) is also given low level then DECREMENT operation is performed

if two selected lines one of the given is high level and another one is given as

high level and carry(input) is also given high level then the A values are obtained

RESULTS:

Fig 1.11: FINAL OUTPUT

CONCLUSION: To stay competitive in today’s market, engineers must take a design from

engineering through manufacturing with shorter design cycles and faster time to market.

To be successful, we need a set of powerful, intuitive, and integrated tools that work

seamlessly across the entire design flow.

We have studied well about arithmetic & logic unit. Here we have implemented 4-bit

arithmetic logic unit successfully. The full integrated circuit is designed and simulated in

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standard 350 nm CMOS technology. Here the RTL coding is done first using a Verilog

HDL and simulation is done by using MultiSim 6.2. The experimental waveforms, power

measurements have also been presented

REFERENCES:

1.Budd, T. (1997b), An Introduction to Object-Oriented Programming, 2nd edn,

Addison-Wesley.

2.Ghezzi, C., Jayazeri, M. & Mandrioli, D. (1998), Fundamentals of Software

Engineering, 2nd edn,Prentice-Hall.

3.K. Appel and W. Haken. (1976), Every Planar Map is 4-colorable, Bull. Amer. Math.

Soc., vol. 82, pp. 711-712

.

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