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BEE3 Updates June 13 th , 2007. Chuck Thacker, John Davis Microsoft Research Chen Chang UC Berkeley. BEE3 Overview. 4 Xilinx FPGA: (FF1136) Virtex-5 LX110T or SX95T 16 DIMMs 2 DDR2-400/533/667 channels per FPGA Up to two 4GB DIMMs per channel 8 10GBase-CX4 interfaces - PowerPoint PPT Presentation
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BEE3 UpdatesBEE3 UpdatesJune 13June 13thth, 2007, 2007
Chuck Thacker, John DavisMicrosoft Research
Chen ChangUC Berkeley
BEE3 OverviewBEE3 Overview
4 Xilinx FPGA: (FF1136)◦ Virtex-5 LX110T or SX95T
16 DIMMs◦ 2 DDR2-400/533/667
channels per FPGA◦ Up to two 4GB DIMMs per
channel 8 10GBase-CX4
interfaces 4 PCI-E x8 slots
(endpoints) 4 QSH-DP (40 LVDS pairs)
daughter card & cable connectors
4 GE RJ45 interfaces 2U chassis ATX12V/EPS2U 500W
power supply
4 G
B D
DR
2-66
7 D
RA
M4
GB
DD
R2-
667
DR
AM
4 G
B D
DR
2-66
7 D
RA
M4
GB
DD
R2-
667
DR
AM
5VLXTFF1136
4 G
B D
DR
2-66
7 D
RA
M4
GB
DD
R2-
667
DR
AM
4 G
B D
DR
2-66
7 D
RA
M4
GB
DD
R2-
667
DR
AM
5VLXTFF1136
24 pin AT
X P
WR
Fujitsu 2x2 CX4
Fujitsu 2x2 CX4
PC
I-Expre
ss 8x 50 pin 2m
m H
eader12V8-pin
PC
I-Expre
ss 8x
PC
I-Expre
ss 8x
PC
I-Expre
ss 8x
4 GB
DD
R2-667 D
RA
M4 G
B D
DR
2-667 DR
AM
4 GB
DD
R2-667 D
RA
M4 G
B D
DR
2-667 DR
AM
5VLXTFF1136
4 GB
DD
R2-667 D
RA
M4 G
B D
DR
2-667 DR
AM
4 GB
DD
R2-667 D
RA
M4 G
B D
DR
2-667 DR
AM
5VLXTFF1136
1.0V
1.8V
1.0V
1.8V
2.5V
RJ45 RJ45
1.8V
1.8V
JTA
G
QS
H-D
P-0
40
QS
H-D
P-0
40
QS
H-D
P-0
40
12V4-pin
305.00
380.00
20.00
30.00
25.00
105.00
25.00
105.00
15.00
70.00
40.00
QS
H-D
P-0
40
78.00
150.00
60.00
100.00
18.00
102.00
23.00
107.00
35.00
65.00
180.00
40.00
10.00
180.00
21.00
29.00
June 2007 RAMP Tutorial
BEE3 PackageBEE3 Package
ATXPWR
FPGA
PCIe Cards
I/Om
odul
es
BEE3 Package Front ViewBEE3 Package Front View Data I/Os:
◦ 4 PCIe slots◦ 8 CX4 connectors◦ 4 RJ45◦ 4 FPGA done LEDs◦ 4 FPGA user LEDs
June 2007 RAMP Tutorial
Control I/O Panel:◦ 4 RS232(RJ45)◦ 4 SD card slots◦ 1 CF card (SystemACE)◦ 1 Xilinx USB-JTAG◦ 2 SMA clock input◦ 1 Power reset◦ 1 FPGA soft reset
FPGA I/O InterfacesFPGA I/O Interfaces
COTS PCI-Express over Cable COTS PCI-Express over Cable Solution from One Stop Solution from One Stop SystemsSystems
HIB2 x8 Host
HIB2 x8 Target
PCIe x8 cableUp to 7 meters
Peak I/O Bandwidths (per-Peak I/O Bandwidths (per-FPGA)FPGA)(estimates for XC5VLX110T-1 part)(estimates for XC5VLX110T-1 part)DDR2 Memory
◦ 400 MT/s * 8B/T * 2 channels: 6.4 GB/sRing
◦ 400 MT/s * 8 B/T * 2 channels: 6.4 GB/sQSH
◦ 400 MT/s * 4 B/T: 1.6 GB/sEthernet
◦ 125 MB/sCX4
◦ 1.25 GB/s * full duplex * 2 channels: 5GB/sPCI Express x8
◦ 2GB/s * full duplex: 4GB/s
June 2007 RAMP Tutorial
June 2007 RAMP Tutorial
ScheduleScheduleGenerate Specification – DoneSchematic Entry – DoneBoard Layout – StartedThermal modeling, heat sink design –
StartedChassis design -- StartedSignal Integrity – ImminentPrototypes: Late Summer – Bring-up
startsProduction: Start early 2008
