Beyond Transistor Scaling:New Devices for Ultra‐Low‐Energy

Information Processing

Prof. Tsu‐Jae King Liu

Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA 94720

April 28, 2009

6th US‐Korea Nano Forum (Las Vegas, NV, USA)

The CMOS Power Crisis

The CMOS Power Crisis• Due to off‐state leakage, VTH cannot be scaled down

aggressively. Thus, the supply voltage (VDD) has not been scaled down in proportion to the MOSFET channel length.

CMOS power density has increased with transistor scaling!

Source: P. Packan (Intel), 2007 IEDM Short Course

VDD

VDD – VTH

VTH Pow

er D

ensi

ty (

W/c

m2 )

1E-05

1E-04

1E-03

1E-02

1E-01

1E+00

1E+01

1E+02

1E+03

0.01 0.1 1Gate Length (μm)

Passive Power Density

Active Power Density

Source: B. Meyerson (IBM) Semico Conf., January 2004

Power Density with CMOS ScalingCMOS Voltage Scaling

3

• Parallelism is the main technique to improve system performance under a power budget.

100 101 102 103 1040

20

40

60

80

100

Nor

mal

ized

Ene

rgy/

op1/throughput (ps/op)

Operate at a lower energy point

Run in parallel to recoup performance

400480088080

8085

8086

286386486

Pentium® procP6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Pow

er D

ensi

ty (

W/c

m2

)

Hot Plate

Nuclear Reactor

Rocket NozzleSun’s Surface

uP‐Chip Power DensityTrend

Core 2

Source: S. Borkar (Intel)

4

Parallelism

Minimizing Operation Energy

• Edynamic + Eleakage = αLdCVdd2 + LdIOFFVddtdelay

• tdelay = LdCVdd/(2ION)

CMOS has a fundamental lower limit in energy per operation, due to subthreshold leakage.

CMOS Energy per Operation

Etotal

EdynamicEleakage

101

102

103

104

105

0

20

40

60

80

100

Nor

mal

ized

Ene

rgy/

op

1/throughput (ps/op)

CMOS Energy vs. Delay

5

The Need for a New Switch

• When each core operates at the minimum energy, increasing performance requires more power.

Today: Parallelism lowers E/op

Future: Parallelism doesn’t help

CMOS Energy vs. Delay(normalized)

Delay

6

New Switching Devices

MOSFET Subthreshold Swing

• In the subthreshold region (VGS < VTH),

S≥ 60mV/dec at room temperature

log ID

VG

IOFF

VDD

ION

S

8

Electron Energy Band Profile

incr

easi

ng E

distance

∝nkTqVI GS

D exp

• S must be reduced in order to achieve the desired ION/IOFFwith smaller VDD

n(E)∝exp(‐E/kT)

Substrate

Gate

Source Drain

MOSFETStructure:

Tunnel FET (TFET)

Structure:

Energy‐bandDiagrams:

9

Gate Voltage (V)0.0 0.2 0.4 0.6 0.8 1.0

Dra

in C

urre

nt (A

/ µm

)

10-10

10-9

10-8

10-7

10-6

10-5

SS = 52.8 mV/decT = 300 KLG = 70 nmtox = 2 nmtSOI = 70 nmW = 10 µm

VD =1 V

VD = 0.1 V

Si TFET I‐V CharacteristicsW. Y. Choi et al. (Seoul Nat’l U. & UC Berkeley)IEEE‐EDL vol. 28, pp. 743‐745, 2007

Substrate

Gate

p+ Source n+ Drain

OFF STATE:

ON STATE:

EC

EV

EC

EVtunneling current

bandgap (Eg)

3/*

/*

g

g

ox

tunnelGS

Emb

EmAa

TVV

∝

∝

+=

κξ

)/exp( ξξ baID −=

Energy‐Performance Comparison

• Si TFETs appear promising for sub‐1GHz applications

10

1.E-18

1.E-17

1.E-16

1.E-15

1.E-02 1.E-01 1.E+00 1.E+01

Energy [J]

Performance (GHz)

CMOS

TFET

30-stage 65nm CMOS inverter chain (transition probability=0.01, capacitance per stage=2.4fF)

H. Kam et al. (UCB, Stanford U.), 2008 IEDM

TFET Technology Challenges

• Increased ION to expand range of applications– Advanced semiconductor materials to achieve smaller

effective Eg

• VTH control

• TFET‐based integrated‐circuit design

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MOSFET‐Inspired Relay

• The mechanical gate is electrostatically actuated by a voltage applied between the gate and body electrode, to bring the channel into contact with the source and drain electrodes.

ON‐state|VGB| ≥ VTH

OFF‐state|VGB| < VTH

12

L

Plan‐View Micrograph

F. Chen et al. (MIT, UCB, UCLA), 2008 ICCAD

1.E-14

1.E-10

1.E-6

1.E-2

0 5 10 15 20VGB(V)

I DS

(A)

Measured I‐V

VBody=0VVDS = 0.5V

Gate: W =2µm L=20µm H =200nm

actuation gap = 400nm

• Ideal switching behavior:– Zero off‐state leakage

– Abrupt turn‐on

→ low VTH (and VDD) possible!

Relay Scaling

• Scaling has similar benefits for relays as for MOSFETs.

Pull‐in Voltage with Beam Scaling

• Measured pull‐in voltages scale linearly{W,L,tgap} = {90nm,2.3um,10nm}

Vpi = 200mV

• Mechanical delay also scales linearly (~10ns @ 90nm)

13

F. Chen et al. (MIT, UCB, UCLA), 2008 ICCAD

Relay‐Based Circuit Design• Relays have small RC delay but large mechanical delay

Complete all logic in a single complex (pass transistor) gate

14

F. Chen et al. (MIT, UCB, UCLA), 2008 ICCAD

10x reduction

CMOS fundamental limit: • A relay adder can be

~10x more energy efficient at the same delay as a CMOS adder.

Energy vs. Delay Comparison:(32‐bit adders,

90nm technology)

Example of CMOS to RelayLogic Mapping:

Relay Technology Challenges

• Surface adhesion force

• Mechanical contact resistance

• Reliability

Relay I-V Characteristic

IDS

VGSVpiVrel

hysteresis due to surface force

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Summary

Summary

• Due to subthreshold leakage, CMOS technology has a fundamental limit in energy efficiency.

• New switching devices with steeper switching behavior are needed to achieve lower energy per operation. – Examples: tunnel FET, relay

– Note: Such devices may have very different characteristics than the MOSFET. Thus, they will require new circuit and system architectures to fully realize their potential energy‐efficiency (and hence performance) benefits.

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Acknowledgements• Collaborators:

– Faculty: Elad Alon (UCB), Dejan Markovic (UCLA), Vladimir Stojanovic (MIT)

– Students: Hei Kam, Fred Chen (MIT)

• Research funding:» DARPA STEEP Program

» DARPA/MARCO Focus Center Research Program:• Center for Circuits and Systems Solutions (C2S2)• Center for Materials, Structures, and Devices (MSD)

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• UC Berkeley Microfabrication Laboratory