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BIO POTENTIAL SIMULATOR

Instructor: Evgeniy KuksinPreformed by: Ziv Landesberg

Duration: 1 semester

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Introduction

Bio potential detector measures the electric potentials on the surface of living tissue . Bio potential detection is useful in many medical application such as ECG, EMG, AND EEG MONITORS.

Therefore is also useful to have the ability to test the Bio potential detector by a bio potential simulator.

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Project goal

The project goal is to implement a controller of a bio exponential simulator. The controller should control the signal at the output of the simulator.

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System description

Host FPGA

Material resemblingliving tissue

BIO potential Simulator

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Project Block Diagram

FPGAHOST

Multi-ChannelVoltage

Generator128ch@14bit

40KSps

Sub-LSBCalibration

System

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In detailed block diagram

NIFPGA

DAC32ch@14bit

DAC32ch@14bit

DAC32ch@14bit

DAC32ch@14bit

128ch

Data/Control

Data/Control

Data/Control

Data/Control

Sync

CalibrationADC

4ch@16bit

Data/Control

Return Current PS Isolation

X4*

*For Analog crosstalk reduction

5v

Ultra Precision Vref0.02% accuracy

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FPGA code structure

The code on the FPGA is divided to two main parts.

The first part is the calibration of the DACs m and c registers. This registers should allow to digitally set the slope to 1 and to eliminate the bias. (Did not supply with enough precision)

The second stage is the normal running of the system, which continuously read values from the DRAM and sending them to the D/As.

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Reg,addres(always changed at same time)

data

Wr’

ldac

Wait to host

DACs timings at calibration

value

value

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sdout

din

sck

cnv

Start new cycle at host command

ADC timings at calibration

read

write

clock

read

write

clock

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Reg,addres(always changed at same time)

data

Wr’

ldac

Wait to busy

Repeat 32 times

Wait for output stabelize/wanted freq(optional)

Dacs timings at normal runing

value

value

readRead next 32Values from dram

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FPGA VI- hierarchy

top

Fill dram

adcSingle write

Dac control

Read 32

dram

Rapid write

Black-active during calibration

Red-active during normal run

Purple-active all the time

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Fill DRAM

Fill the dram bank given by the host, always. Each block in dram (64 bit) represents the values of single

address on the 4 DAC’s. The DAC address of a block is cyclic and can be calculated

as DAC address=(dram_add-2)mod32 . The Fill dram can fill a dram bank during the normal

running , as long it is not being read at the same time!. Each bank lasts for 16,777,184 /(32*40000)=13.106[sec]

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Rapid-write

Loads all 128 DACs with a sample voltage.

Has 3 states: Wait, Pre-write, Write1. “Wait” wait for begin of writing cycle/

until values from memory are read.2. “Pre-write” set the values of the data to

be written at DACs’ input(wr’ is down)3. “Write” write the data(wr’ is up)

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Read 32 dram

Read 32 blocks from the dram(128 values). Reads the values to be written at the next cycle of rapid write.

Has 2 main states : 1- wait for beginning of new writing cycle. 2- read next 32 blocks from given address and

dram bank

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Dac control

Control all the operation of the DACS in normal writing. Has 5 states: “pre dram read” pre dram read- waiting for end of

calibration. Once ends the state never reappear “busy/reading from dram” wait for busy signal and until end of

reading values from dram “pre wrote ” before writing, set the next dram

address and the dram bank. “writing” writing to all DACS outputs “ldac down-putting ” down ldac begin update of analog

output.

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Graphs of timing at normal runTiming at dram bank

switch

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Zoom on graph from previous slide

5.38 u sec per cycle

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ADC

Control the adc- sends samples from wanted channel to host. Responsible for all of the ADC outputs.

Has 2 main states- 1-reading serial data from the sdout output of the ADC. 2- waiting until ADC ready to make another sample.

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Single write

Write values to one output channel. The values and the channel are set directly by the host.

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Calibration timing

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Zoom on previous graph(5 u sec per cycle)

Calibration ADC readout

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Creation of Labview socketed clip

The creation of a socketed clip in labview is done by 2 simple stages .

The first one is to wire the I/O signals on the FPGA (agpio) according to the schematics of the project.

The second stage is to fill a XML file that declares names of the signals that can be used by labview.

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The entity(base.vhd) of the VHDL part

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Second part of entity

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Xml file(myclip)

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Image of clip in project

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Calibration method

The calibration we chose use 4th order polynomial fit(software calibration), due to the fact that increasing the order did not improve the error we achieved(as will be shown in next slide).

The ADC uses external reference voltage with value of 5[volt] and accuracy of about 1[mV].

After calibration DAC output error is less then 1mVFS is 5v maximal error 0.02% (as accurate as ADC) Before calibration DAC output error is around 10mVFS is 5v error 0. 2%

AccuracyImprovement

x10

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4th order calibration-channel 0

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.002

0.004

0.006

0.008

0.01

0.012

0.014

absolute error with-out calib-voltsabsolute error with calib-volts

input[volts]

error[volts] absolute errors graph

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5th order calibration-channel 0

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.002

0.004

0.006

0.008

0.01

0.012

absolute error without calib-volts

absolute error with calib-volts

input[volts]

error[volts] absolute errors graph

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DAC0-channel 15

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.002

0.004

0.006

0.008

0.01

0.012

0.014

absolute error without calib-volts

absolute error with calib-volts

Input[volts]

error[volts] absolute errors graph

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DAC0-channel 31

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.002

0.004

0.006

0.008

0.01

0.012

0.014

absolute error without calib-volts

absolute error with calib-volts

Input[volts]

error[volts] absolute errors graph

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DAC1-channel 0

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.002

0.004

0.006

0.008

0.01

0.012

0.014

absolute error without calib-volts

absolute error with calib-volts

Input[volts]

error[volts] absolute errors graph

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DAC1-channel 15

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.002

0.004

0.006

0.008

0.01

0.012

0.014

absolute error without calib-volts

absolute error with calib-volts

Input[volts]

error[volts] absolute errors graph

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DAC1-channel 31

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.002

0.004

0.006

0.008

0.01

0.012

0.014

absolute error without calib-volts

absolute error with calib-volts

Input[volts]

error[volts] absolute errors graph

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DAC2 channel 0

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.002

0.004

0.006

0.008

0.01

0.012

absolute error without calib-volts

absolute error with calib-volts

Input[volts]

error[volts] absolute errors graph

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DAC3 –channel 31

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.001

0.002

0.003

0.004

0.005

0.006

0.007

absolute error without calib-volts

absolute error with calib-volts

Input[volts]

error[volts] absolute errors graph

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Writing to dram while board is running

It is possible to write to the FPGA dram while it is writing values to the DAC. Is done by control active_dac2_host which says from which bank the fpga currentely taking is values(it is not possible to write to that bank) .

by the control dram_host, which says to which bank you want to write.

And by the fifo from_host, simply by inserting the data you want to write.

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Code for previous slide

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Writing to dram while board is running

-6.00E+00 -4.00E+00 -2.00E+00 0.00E+00 2.00E+00 4.00E+00 6.00E+00

-1.00E+00

0.00E+00

1.00E+00

2.00E+00

3.00E+00

4.00E+00

5.00E+00

6.00E+00

Sawtooth run when writing to the dram

bank0

bank1

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Activating 2 FPGA’s At the last part of the project we inserted second

FPGA (also connected to a board) and activated both of them at the same time through PXI backplane triggers.

PXI

PXI backplaneWith global triggers for

nsec synchronization

NI FP

GA

NI FP

GA

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Step signal from 2 FPGA’swithout syncronization

-5.00E-05 -3.00E-05 -1.00E-05 1.00E-05 3.00E-05 5.00E-05

-1.00E+00

0.00E+00

1.00E+00

2.00E+00

3.00E+00

4.00E+00

5.00E+00

6.00E+00

fpga2 fpga1

Time[sec]

value[volt]

One DAC Sample

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Signal with synchronization

-0.0001 0.0000 0.0001-1.0000

0.0000

1.0000

2.0000

3.0000

4.0000

5.0000

6.0000

Single sample

board1board2

Time[sec]

Volt

age[v

olt

s]

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System Expansion

By expanding and adding more FPGA and DAC boards we can easily get system with above 2000 Analog outputs.

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Conclusion-summary 128 channels analog outputs was successfully implemented. PCB was manufactured and assembled in china. PCB-PXI FPGA edge connector appeared 100% correct. Analog

Outputs VHDC connector was designed correctly. Calibration of all analog outputs was implemented and gave wanted

0.02% accuracy. Slight PCB issues was found, corrected by local wire soldering. Electrical Parameters Achieved:

128 channels All channels synchronized 0-5v dynamic full scale range Resolution – 14bit Sample rate – 40KHz Accuracy of 1mV (0.02%) Synchronization of different boards is done by PXI triggers.

FW supports cyclic data transfer from Host to internal 512MB RAM.RAM bank switching allows unlimited data generation.

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Test for data Generation

See VIDEO for ECG signals generation. Data was taken from MIT ECG Arrhythmia

Database. Data is 20sec length. Data was divided

into several chunks and was cyclically written to RAM banks.