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Bit-Line Leakage Cancellation: Design and Test Automation. Sudhanshu Khanna. Deliverables. Bit-Line Leakage Cancellation Schematic Layout On-Chip High Speed Testing Memory BIST. BOTTOM – UP DESIGN. TOP – DOWN DESIGN. Goals & Constraints: L1 Cache design. Achieve High Density - PowerPoint PPT Presentation
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April 22, 2010 1
Bit-Line Leakage Cancellation: Design and Test Automation
Sudhanshu Khanna
April 22, 2010 2
Deliverables
Bit-Line Leakage Cancellation Schematic Layout
On-Chip High Speed Testing Memory BIST
BOTTOM – UP DESIGN
TOP – DOWN DESIGN
April 22, 2010 3
Goals & Constraints: L1 Cache design
Achieve High Density How: More Bit-Cells, Less Periphery
Achieve High Speed How: Lower Read Time
L1 bit-cells use Low-Vt transistors
Memory-Vdd must be same as Core-Vdd => Can’t use Multi-Vdd to increase performance
April 22, 2010 4
Why is Bit-Line Leakage an Issue
Challenges (Scaling issues) Lower Iread
Higher Ileakage
Only solution: Reduce # cells on a bit-line => Lower Density
April 22, 2010 5
Why is Bit-Line Leakage an Issue
SA differential = V(BL) – V(BLB)
If BL leaks, differential lowers (data-dependent too)
More time needed to generate same differential => Lower Speed
April 22, 2010 6
Where is Bit-line leakage an issue?
Advanced technology nodes Issue: High Vt variation, high leakage Result: Impact on performance
Sub-threshold memory Issue: Low Ion/Ioff
Result: Energy penalty due to higher required BL swing
High Temperature Compliant Memories
Alternative memories
April 22, 2010 7
Bit-line Leakage Cancellation
Sense leakage value during pre-charge
Inject opposite current during read
Drawbacks: V -> I conversion inaccuracies Pre-charge to VDD – Vt required
Agawa et al, 2001
April 22, 2010 8
High Speed Testing Issues
TESTER
~ 20 MHz
1 GHz InverterOUTPUT PAD
~ 200 MHz
Signal Analyzer
~ 100 MHz
You can make a FAST inverter, but you cant see it work
Memory BISTMemory BIST
BIST BIST modemode
High Speed ClockHigh Speed Clock External Tester (Slow Testing)External Tester (Slow Testing)
Address generatorAddress generatorAddress generatorAddress generatorFFSSMM
FFSSMM
Data generatorData generatorData generatorData generator
Control generatorControl generatorControl generatorControl generator
StartStart DoneDone
FailFail
MemoryMemory
April 22, 2010 10
M-BIST Design Flow
Algorithm
Behavioral Verilog: NC-Verilog
Structural Verilog: RTL Compiler
Place and Route: Encounter
Integration with Custom Memory: Virtuoso
April 22, 2010 11
Top-Down Flow Issues Faced
RTL Complier Assign Statements Unused Nets connect to VDD, VSS
Inputs of standard blocks e.g. Carry-In of Adder Unused bus signals: e.g. Z[4] of a bus Z[11:0]
Encounter < > vs [ ]
Virtuoso: Global Signals
April 22, 2010 12
Thanks for your time !