Bit Matrix Implementation for 40GE and 100GE Block Muxing · Bit Matrix Transpose ... OPU/ODU. HUAWEI TECHNOLOGIES Co., Ltd. ... • Bit matrix adapts to different optical modules

HUAWEI TECHNOLOGIES Co., Ltd.IEEE 802.3ba Task Force, 2008

Bit Matrix Implementation for 40GE and 100GE Block Muxing

Zeng Li, Min Ye, and WB Jiang

HUAWEI TECHNOLOGIES Co., Ltd.

Page 2

IEEE 802.3ba Task Force, 2008

Outline

• High Speed Ethernet (40GE and 100GE) PBL Model• Bit Matrix Implementation for PBL• PBL Applications with Bit Matrix


Page 3


PBL Model Overview

Block Generator

x（64＋4）bit

Block Distributor 64B/66B

encoder64B/66Bencoder

64B/66Bencoder

66bitLane1

Lane2

Lane10

CTBI

VCSEL Array

CGMII

BlockProcess

x（64＋4）bit

Block Alignment

64B/66Bdecoder64B/66Bdecoder

64B/66Bdecoder

66bitLane1

Lane2

Lane10

Alignment BlockGenerator

Alignment BlockDetector

PIN

PIN

PIN

PCS PMA/PMDMAC/RS

Buffer

Bit Matrix

Bit Matrix


Page 4


PBL Model Overview• Receive data from MAC layer and generate 64bit Blocks• Transmit the Blocks through CGMII bus• Distribute to multi-lanes based on Blocks with alignment

words inserted to each lane following the distributor• Encode the Blocks within each lane (64B/66B encoding &

scrambling)• Bit matrix will adapt CTBI to different physical lanes• Keep Block format in every physical Lane (Block interleave

to the Multi-lanes)


Page 5


Bit Matrix Introduction

• Bit Matrix is used for keeping Blocks running in PHY lanes• Bit Matrix has two modes:

–Pass-through

–Transpose

• Bit Matrix can be implemented with Memory


Page 6


Bit Matrix Implementations – Two Modes

• With the same input and output data buses, implementing similar building blocks may share development resource for lower R&D cost

• Bit matrix is a configurable memory to support either a 10x10 or a 4x10 optical module.

Data input

Data output

(640+40)@[email protected]

(4-lanes)

[email protected]

[email protected]

Distributionand

Encode&Scramble

Distributionand

Encode&Scramble

Matrix for 10:10(Pass-through)

Matrix for 4:10(Transpose)

SerDes for CTBI

10bit

[email protected]

CGMII

[email protected](10 lanes)

Skew


Page 7


Bit Matrix Implementations – Two Modes

1

CGMII

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

(640+40)@156.25MHz 1

10

1

(64+4)bit

10

66bit @156.25MHz

Matrix for 10:10(Pass Through)

1

5

9

13

17

9 170bit

4

8

12

16

20

12

1

513

17 9

9 165bit @156.25MHz

Matrix for 4:10(Transpose)

4

816

20 12

12

[email protected]

[email protected]

Block DistributionBlock Generator

Encode & Scramble per lane

[email protected] Serializer

11

64bit block

4bit block type66bit block


Page 8


Bit Matrix Details

•Bit Matrix is a (n x m) memory, n is the # of distributed physical lanes (optical module channel count); m is the # of CTBI signal (m=10)•When connected to a 10x10G optical module, 10-lane data will pass through bit by bit, and physical lanes keep block running in order•When connected to a 4x25G optical module, 4-lane data will be transposed to adapt to the 10bit CTBI interface. In the optical module, anti-transpose matrix will recover the blocks for running in each physical lane.

……

……

……

……

……Input N

lane

Transpose mode:output M lane

Pass-through mode:output N lane

Block

Bit


Page 9


Bit Matrix Pass-through (10:10) Mode

• Optical module ID instructs PCS to configure the pass-through mode• 10x10 bit matrix will be deployed• It will adapt to CTBI and keep block running in all 10 lanes (Block muxing in PHY lanes)• No gearbox (bit matrix) in the VCSEL optical module, skew line idle (not needed)

Bit Matrix

CTBI:10x10.3125G

……

……

10x10G VCSEL Optical Module

……

PL1

PL2

PL10

PL3

MDI:10x10.3125G

Module ID


Page 10


Bit Matrix Transpose (4:10) Mode

• For a 4x25G optical module, the module ID instructs PCS to configure transpose mode, adapt to 10bit electrical interface.

• Blocks are distributed to 4 Physical Lanes• The anti-transpose Matrix (gearbox) is needed in the 4x25G optical module

to recover block data (keep blocks running in all four optical lanes)

SFI-S:(10+1)10.3125G

PL1

PL4

PL2PL3

4X25G Skew Line4X25G xWDM

Optical Module

Module ID


Page 11


Transpose Matrix Implementation

• Use two matrixes with “ping-pong” operation to implement transpose function• Use wr_en and rd_en to control two matrixes’ read and write

– When writing data into Matrix0(wr_en is available to Matrix0), data is read from Matrix1– When writing data into Matrix1(wr_en is available to Matrix1), data is read from Matrix0

Matrix0 Matrix1

control

Data input

wr_en

Data output

rd_en

Skew output


Page 12


Transpose Matrix Implementation with Memory

•In each lane, 160bits of data is written to 10 RAMs. Every RAM is 16-bit wide * 2-bit deep.•Data are read by column. In each column, 64bits are read from 4 RAMs in order, and serialized by SERDES

[email protected]

[email protected]

[email protected]

16bits width *2 depth16b16b16b

64:1 SERDES

64:1 SERDES

64:1 SERDES

64:1 SERDES

64:1 SERDES

64:1 SERDES

64:1 SERDES

64:1 SERDES

64:1 SERDES

64:1 SERDES

[email protected]

64:1 SERDES

Skew line

16b 16b 16b 16b 16b 16b

10x10.3125G

10*[email protected] [email protected]


Page 13


Transpose Matrix Implementation with Memory

• There are 40 RAMs in a sub-Matrix, and 80RAMs in total by “ping-pong”matrixes

• Skew line is introduced for bit alignment.• Resource needed for the matrix (when input data is [email protected])

–Bit Matrix RAM: 16 bits *2 *40 *2 = 2560 bits

–Skew line generator: Logic resource implementation per even-parity element and

odd-parity element – Next page


Page 14


Skew Line Implementation per SFI-S

• Skew line to keep bit alignment in the module• In the optical module, anti-transpose bit matrix recovers blocks from

aligned bits• Skew line adopts SFI-S protocol defined by OIF (oif2007.304.01)

Even Parity Element Even Parity Element Odd Parity Element

D9,0 D8,1 D7,2 D6,3 Pevn D5,5 D4,6 D3,7 D2,8 Pevn D1,10 D0,11 D9,12 D8,13 Podd D9,15 D8,16 D7,17 D6,18 Pevn

Data [3]Data [2]Data [1]Data [0] D0,0 D0,1 D0,2 D0,3 D0,4 D0,5 D0,6 D0,7 D0,8 D0,9 D0,10 D0,11 D0,12 D0,13 D0,14 D0,15 D0,16 D0,17 D0,18 D0,19

D1,0 D1,1 D1,2 D1,3 D1,4 D1,5 D1,6 D1,7 D1,8 D1,9 D1,10 D1,11 D1,12 D1,13 D1,14 D1,15 D1,16 D1,17 D1,18 D1,19D2,0 D2,1 D2,2 D2,3 D2,4 D2,5 D2,6 D2,7 D2,8 D2,9 D2,10 D2,11 D2,12 D2,13 D2,14 D2,15 D2,16 D2,17 D2,18 D2,19D3,0 D3,1 D3,2 D3,3 D3,4 D3,5 D3,6 D3,7 D3,8 D3,9 D3,10 D3,11 D3,12 D3,13 D3,14 D3,15 D3,16 D3,17 D3,18 D3,19

Deskew

Data [7]Data [6]Data [5]Data [4] D4,0 D4,1 D4,2 D4,3 D4,4 D4,5 D4,6 D4,7 D4,8 D4,9 D4,10 D4,11 D4,12 D4,13 D4,14 D4,15 D4,16 D4,17 D4,18 D4,19

D5,0 D5,1 D5,2 D5,3 D5,4 D5,5 D5,6 D5,7 D5,8 D5,9 D5,10 D5,11 D5,12 D5,13 D5,14 D5,15 D5,16 D5,17 D5,18 D5,19D6,0 D6,1 D6,2 D6,3 D6,4 D6,5 D6,6 D6,7 D6,8 D6,9 D6,10 D6,11 D6,12 D6,13 D6,14 D6,15 D6,16 D6,17 D6,18 D6,19D7,0 D7,1 D7,2 D7,3 D7,4 D7,5 D7,6 D7,7 D7,8 D7,9 D7,10 D7,11 D7,12 D7,13 D7,14 D7,15 D7,16 D7,17 D7,18 D7,19

Data [9]Data [8] D8,0 D8,1 D8,2 D8,3 D8,4 D8,5 D8,6 D8,7 D8,8 D8,9 D8,10 D8,11 D8,12 D8,13 D8,14 D8,15 D8,16 D8,17 D8,18 D8,19

D9,0 D9,1 D9,2 D9,3 D9,4 D9,5 D9,6 D9,7 D9,8 D9,9 D9,10 D9,11 D9,12 D9,13 D9,14 D9,15 D9,16 D9,17 D9,18 D9,19


Page 15


Anti-Transpose Matrix in 4x25G xWDM Optical Module

• SFI-S-like inteterface is used as a common electrical interface for optical modules• The aligned bits are recovered in blocks in the physical lanes by anti-transpose bit matrix method• Implementation is the similar to the PCS, but reversing the rows and columns

– 2.56k memory– 10x10G (161.133MHz bus) Serdes with CTBI– 4x25G (161.133MHz bus) Serdes with 4x25G xWDM PMD

CDR

CDR

CDR

CDR

bit0

bit8

bit9

Bit skew

FIFO&

Deskew Circuit

SFI-Sbit0

bit94 Lanes

GearboxSFI-S

Bit Matrix

(10:4)Anti-transpose


Page 16


Common Optical Module Interface for Ethernet & OTN

• SFI-S is introduced as a common interface for the 100G optical module• Similar chip design due to similar function blocks may be shared

Distributor&

encode

VCSELArray

10X10G

Bit matrix10:10

Pass through10bit interface

1bit no use

Distributor&

encode

Bit matrix4:10

transpose

SFI-S (10+1)

10x10G Transceiver

Bit matrix10:4

Anti-transpose

Deskew

Skew Line

Laser

WD

M

Gearbox

Bit matrix10:4

Deskew

Modulator

Gearbox

DQPSK&

Precoder

SFI-SInterface

SFI-S (10+1)

Skew Line

4x25G Transceiver

OTN4 Framer

100G Transponder

MA

CM

AC

MAC & PHY Chip

MAC & PHY Chip

100GE Module10x10G

100GE Module4x25G

100G Module100G

Ethernet packet

Ethernet packet

OPU/ODU


Page 17


Conclusions of Bit Matrix Method

• Bit matrix method provides a solution to keeping data blocks running in the physical lanes

• Bit matrix adapts to different optical modules with the same electrical interface–Support both 10x10G and 4x25G modules

–Select operation mode (pass-through or transpose) by diagnosing module

type

• SFI-S is introduced to interface between PHY and optical modules–SFI-S is defined by OIF

–Skew line keeps the bits aligned in transpose mode

–SFI-S allows common interfaces for both 100GE and ODU-4 optical

modules


Page 18


Appendix – PBL Applications


Page 19


PBL Application– Flexible OTN Mapping

•PBL supports both Aggregation and Independent Mapping into OTN•Blocks in an independent lane allows for mapping into OTN by transcode

512b/513btranscodeMAC frames

40/100GigE Transport

100m MMF

64/66b code blocksIndependent Mapping

Aggregation Mapping40G/100G MAC

RS

PBL

PCSPMAPMD

PCSPMAPMD

Mux/DemuxDualFiber

CGMII

MDI λ MDI λ

40G/100G MACRS

PBL

PCSPMAPMD

PCSPMAPMD

Mux/DemuxDualFiber

CGMII

λ

PCS40/100GbE

OPU4/100GbE

OPU4

Optical Mux/DemuxDualFiber

10Gbt

10Gbt

10Gbt

10Gbt

OPU4

n*OPU2(OPU4)/100GbE

Optical Mux/DemuxDualFiber

λ λ

10km SMF40km SMF

10Gb/Block

10Gb/Block

10Gb/Block

10Gb/Block


Page 20


PBL Application – PHY Management

• PBL distributes blocks to each lane (block muxing), which is similar to traditional Ethernet format good for management and maintenance

LaneMonitor

40G/100G MACRS

PBL

PCSPMAPMD

PCSPMAPMD

Mux/DemuxDualFiber

CGMII

MDI λ

40G/100G MACRS

PBL

PCSPMAPMD

PCSPMAPMD

Mux/DemuxDualFiber

CGMII

λλ λ

LaneMonitor


Page 21


PBL Application – FEC Support

•PBL distributes blocks to each lane (block muxing) and support FEC function for applications not only in backplane but also in transport over extended distances

40G/100G MACRS

PBL

PCS

PMAPMD

PCS

PMAPMD

Mux/DemuxDualFiber

CGMII

MDI λ

40G/100G MACRS

PBL

PCS

PMAPMD

PCS

PMAPMD

Mux/DemuxDualFiber

CGMII

λλ λ

FEC FEC FEC FEC

10km SMF (Base-L)40km SMF (Base-E)~40km SMF (Base-Z)


Page 22


PBL with Bit Matrix

• Physical Lane Bundling (PBL) with block muxingretains tradition Ethernet technology–Beneficial to many applications

•OTN mapping•PHY management•FEC

• PBL with Bit-Matrix–Provide a common electrical interface solution to

accommodating both 10x10G and 4x25G optical modules–Allow a single 100G optical module design for both 100GE

and ODU-4

HUAWEI TECHNOLOGIES Co., Ltd.IEEE 802.3ba Task Force, 2008

Thank You

Documents

Bit Matrix Implementation for 40GE and 100GE Block Muxing · Bit Matrix Transpose ... OPU/ODU. HUAWEI TECHNOLOGIES Co., Ltd. ... • Bit matrix adapts to different optical modules