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BK5823 Datasheet ETC OBU SOC
© 2012 Beken Corporation Proprietary and Confidential Page 1 of 31
BK5823 Datasheet
5.8-GHz ETC OBU Transceiver IC (OBU)
V2.0.3
Beken Corporation Suite No.3A, 1278 keyuan Rd, Shanghai 201204, China PHONE: (86)21 51066811 FAX: (86)21 6160 9679 This document contains information that may be proprietary to, and/or secrets of, Beken Corporation. The contents of this document should not be disclosed outside the companies without specific written permission. Disclaimer: Descriptions of specific implementations are for illustrative purpose only, actual hardware implementation may differ.
BK5823 Datasheet ETC OBU SOC
© 2012 Beken Corporation Proprietary and Confidential Page 2 of 31
Content 1 General Description .................................................................................................... 3 2 Application .................................................................................................................. 3 3 Features ....................................................................................................................... 3 4 Package ....................................................................................................................... 3 5 Block Diagram ............................................................................................................ 3 6 Pin Information ........................................................................................................... 4 7 Electric Specification .................................................................................................. 5 8 Maximum rate ............................................................................................................. 6 9 Function Description ................................................................................................... 6
9.1 Receiver ................................................................................................................ 6 9.1.1 Receiver Description ...................................................................................... 6 9.1.2 Receiver AGC setting ..................................................................................... 7 9.1.3 Receiver CRC setting ..................................................................................... 8 9.1.4 RX RSSI .......................................................................................................... 8 9.1.5 BER Test Mode .............................................................................................. 8
9.2 Transmitter ............................................................................................................ 9 9.2.1 Transmitter description .................................................................................. 9 9.2.2 Transmitter CRC setting .............................................................................. 10 9.2.3 Transmitter Power setting............................................................................ 10 9.2.4 Single Carrier setting ................................................................................... 10 9.2.5 PN9 Modulation Signal setting .................................................................... 10
9.3 Wake-up Circuit .................................................................................................. 10 9.3.1 Wakeup mode ............................................................................................... 10 9.3.2 Wakeup Band Pass Filter ............................................................................. 11 9.3.3 Wakeup Auto Calibration Mode .................................................................. 11 9.3.4 No Response Mode ....................................................................................... 11
9.4 State Machine...................................................................................................... 12 10 Control Interface ....................................................................................................... 13
10.1 Basic Function ................................................................................................. 13 10.2 Operation and Timing ..................................................................................... 13 10.3 Data FIFO ........................................................................................................ 15 10.4 TX Ramping Control ....................................................................................... 15
11 Register Map ............................................................................................................. 16 12 Test Result ................................................................................................................ 29 13 Application Schematic .............................................................................................. 30 14 PCB Layout Reference Design ................................................................................. 30 15 Package ..................................................................................................................... 31 16 Order Information ..................................................................................................... 31
BK5823 Datasheet ETC OBU SOC
© 2012 Beken Corporation Proprietary and Confidential Page 3 of 31
1 General Description The BK5823 is the CMOS SOC for
electronic toll collection compliant with GB/T 20851.1 -2007 and GB/T 20851.2-2007, which can be used at OBU with ASK modulation and demodulation.
The BK5823 is integrated with wake-up circuit, complete RF transceiver and ASK modulator. The embedded packet processing engine enables its full operation with a very simple MCU as an OBU system.
The BK5823 needs very few external components. The low power design and high sensitivity make it very suitable for low-cost application and fast time to market.
The BK5823 can receive the 1st BST without MCU control after wakeup. The sleep current is 5uA with no signal input.
2 Application Electronic Toll Collection 5.8GHz Short Range Communication
3 Features Full both uplink and downlink band:
5.7 GHz - 5.85 GHz
Data Rate: Uplink 512 kbps/256kbps option and Downlink 256 kbps/512kbps option.
Output power: Up to 2 dBm Sensitivity: RX: -71 dBm, wakeup: -
47dBm Fast AGC to accommodate up to 71
dB dynamic range RF input Integrated wake-up circuit with 4.5uA
sleep current. Integrated wake-up baseband circuit
to select the wakeup frequency(the frequency can be controlled).
On-chip auto calibration for wake-up base band frequency range.
ON chip low current (10uA) counter to forbid wakeup again in the setting time (1s->20s).
Receiving the 1st BST without MCU control
The sending CRC seed can auto adjust according to receiving CRC seed
On-chip temperature compensation for TX power.
2.6 V ~ 3.6 V supply 45mA TX mode current 26mA RX mode current 4-wires SPI interface up to 8 MHz
4 Package 28-pin 5x5 mm QFN
5 Block Diagram
Figure 1 Block Diagram
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6 Pin Information
Figure 2 Pin Definition
Table 1 BK5823 Pin List
No. Sym. I/O Function Description 1 PAEN O Analog External PA enable, “1” enable 2 TXSW O Analog TX switch control, “1” enable 3 RFOP O RF Positive RF output 4 RFON O RF Negative RF output5 RFIN I RF RF signal input 6 RXSW O Analog RX switch control, “1” enable7 VDD I Power 2.6V~3.6V power supply input 8 WEC I Analog Wakeup external capacitor, this pin must be
connected with VDD through 6.8nF capacitor. 9 IREF O Analog Connected with GND through external 62Kohm
resistor.,If Reg4.rbsel is “1” ,this pin should be floating.
10 VDD I Power 2.6V~3.6V power supply input 11 CBG O Analog Connected with GND through external 2.7nF
capacitor. 12 VSS GND 0 V 13 CDVDD O Analog Connected with GND through external 1uF
capacitance 14 WKO O Analog Wake-up signal detector output, which will generate
a rising edge after the setting cycles of 14 kHz
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square wave. 15 IRQ O Interrupt Interrupt for packet TX and RX 16 CE I Digital Chip enable, active high .Ce=0, The chip current is
lower than 0.1uA, if Ce=0, the BK5823 should be initialed again when ce=1.
17 CSN I Digital SPI enable input, active low 18 SCK I Digital SPI clock input 19 MISO O Digital SPI data output 20 MOSI I Digital SPI data input21 VDD I Power 2.6 V~3.6 V power supply 22 DCKO O Digital Bit clock output23 DIO I/O Digital The TRX Data stream input/output, the I/O is
control by reg14:gpio_e, “1” input, “0” output. This pin can output Fm0 data or decoded Fm0 data , which is depended on the reg4: Diooutsel.
24 VDD I Power 2.6V~3.6V power supply 25 VSS GND 0V 26 XTALP I Analog 32.768 MHz Crystal (+/-20ppm) 27 XTALN O Analog 32.768 MHz Crystal (+/-20ppm) 28 VDD I Power 2.6V~3.6V power supply input
7 Electric Specification Condition: VDD = +3.3 V, VSS = 0 V, TA = - 40 ºC to + 85 ºC Table 2 Electric Specification
Symbol Parameter Min. Typ. Max. Unit Operating ConditionVDD Voltage 2.6 3.3 3.6 V TEMP Temperature -40 +27 +85 ºC Digital Input Pin VIH High level 0.7VDD VDD 3.6 V VIL Low input VSS 0.3VDD V Digital Output Pin VOH High level (IOH=-0.25 mA) VDD-0.3 VDD V VOL Low level (IOL=0.25 mA) VSS 0.3 V RF/Analog FLO Frequency 5770 5850 MHz FXTAL Crystal 32.768 MHz M ASK modem depth 0 94 % Transmitter PRF Output power 0 3 dBm PRFC Output power range 15 dB PRFCR Output power accuracy ±3 dB PRF
30~1000 MHz -36 dBm/100kHz 2400~2483 MHz -40 dBm/1MHz 3400~3530 MHz -40 dBm/1MHz
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5725 MHz~5850 MHz -37 -33 dBm/100kHz Otherwise 1 GHz~20 GHz -30 dBm/1MHz
IVDDMAX TX Current (MAX. output power) 45 mA TXDR TX Data Rate 512 Kbps OBW Occupied Bandwidth 2.3 4.5 MHz ACPR Adjacent channel power rejection -47 dB Receiver RXMAX Maximum input (10-5 BER) 0 dBm RXSEN Sensitivity (10-5 BER) -71 dBm IVDD RX current 26 mA TLO LO settling time 40 100 us FDR RX data rate 253 256 259 Kbps PCO Co-channel selectivity 12 dBc PAC Adjacent selectivity 8 dBc Block Block interference -30 dBc Wake-up RXSEW Sensitivity -47 -45 dBm Isleep Sleep Current with no signal input 4 4.5 uA TWK Wake-up time 0.2 ms Idle Iidle Idle Current 2.8 mA ShutDown Isd Shut down current(Ce=0) 0.1 uA SPI FSCK SPI clock frequency 8 MHz
8 Maximum and Minimum rate Symbol Parameter(condition) range Unit VDDR VDD input range -0.3~3.6 V Tj Junction temperature 150 oC Tsd Solder temperature(10s) 260 oC Tst Storage temperature -50~150 oC
9 Function Description
9.1 Receiver
9.1.1 Receiver Description Figure3 is the block diagram of receiver. The receiver of BK5823 uses low-IF architecture and there is a 2-order 7.5MHz LPF behind mixer.
BK5823 Datasheet ETC OBU SOC
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Figure 3 Receiver Block Diagram
If set LO frequency to 5.835GHz, BK5823 will detect both 5.83 GHz and 5.84 GHz channel simultaneously, and automatically select the channel with high quality. The RX LO should be set with setting below: Ncal_rx<7:0>=59h, N_rx<18:0>=2B2B2h, If set LO frequency 5.825GHz, BK5823 will only receive the 5.83GHz channel(set reg9<14> lpf_en=1), if set LO frequency 5.845GHz, BK5823 will only receive the 5.84GHz channel(set reg9<14> lpf_en=1). For 5.825GHz LO, Ncal_rx<7:0>=59h, N_rx<18:0>=2B183h, for 5.845GHz LO, Ncal_rx<7:0>=5Ah, N_rx<18:0>=2B3E1h.
To enter RX mode, the MCU should write REG9 rx_en=1. At RX mode, the
BK5823 will automatically issue an interrupt and return to idle mode after receiving a packet. It will go back to RX mode after FIFO is read empty or interrupt flag is cleared. If BK5823 doesn’t receive a whole packet, it will still be RX mode. If user want BK5823 enter idle mode, user should set rx_en in REG15 to 0. BK5823 would enter into idle mode, if BK5823 doesn’t received packet end 2ms behind the packet header arrives. If user want BK5823 enter idle mode from sleep mode, CE pin and pwr_up in REG9 should be set to 1.
BK5823 can enter into RX model from sleep mode automatically too, if the Reg9<31> is set to “1”, in this mode, BK5823 would enter into RX model automatically after the wakeup signal is detected. If set the Reg9<10>=”1”,. the BK5823 will return back the sleep mode, but you should set the Reg9<10>=“0” again in order to active the automatic wakeup mode again.
The BK5823 integrated a clock recover circuit. This circuit make BK5823 could endure ±1% data rate shift. In Rx mode, the pin rxsw will be set to “1” automatically.
We regard as the manual RX mode as RX1, the automatic RX mode as RX2. In RX2 mode, BK5823 would return back sleep mode automatically if 7Eh hadn’t
been received in 2ms. BK5823 would go into idle mode if a packet is received, if the user want to return back RX2 mode, the Reg15<1>rx_en should set “1”, BK5823 would stay at RX2 mode until a packet is received.
9.1.2 Receiver AGC setting To extend the dynamic range of BK5823’s receiver, BK5823 integrated an AGC. There is two method AGC, one is fast mode, the other is slow mode, which is determined by
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Reg9<18:17> AGC_method. In fast mode, BK5823 would set the AGC very quickly in the short time; in slow mode, BK5823 will change the AGC slowly, you can set the threshold value under this mode, if the received signal is smaller than the threshold value, BK5823 will regard this signal as the noise, so AGC would not change, the threshold is set through the REG10<24:11>, the suggested value of the threshold value is “200h”. in fast mode, the threshold isn’t useful. Gain_rf_delay in REG11 is used to set the delay time of AGC adjust. The suggested value is “1h”
9.1.3 Receiver CRC setting Crc_enable in REG15 is used to enable CRC checksum in TX and RX. If set 0 to
crc_en, BK5823 will not do CRC check sum. Crc_seed is used to set the initial value of CRC. If set 1 to crc_rx_opt, BK5823 will do checksum by using 2 initial value “0” and “1” simultaneously.
9.1.4 RX RSSI RSSI in REG3 indicates the received signal strength. User can get the RSSI information according to the value of RSSI and gain_rf in REG2, the unit of RSSI is dB.. The table below indicates the relationship between the value of AGC gain_rf and actual RF gain.
9.1.5 BER Test Mode A continue time PN9 BER test is integrated in BK5823, Reg19 show the received bit number, Reg20 show the received error bit number, BER=reg20/reg19. In RX1 mode, set Reg9<30>ber_en as “1”, Reg9<29> ber_hold=”0”, and toggle Reg15<0>trx_rst(“1”->”0”->”1”) BK5823 begin to receive the PN9, the received bit number is show in Reg19, the error bit is show in Reg20. If Reg9<29>ber_hold=”1”, BK5823 stop the PN9 receiver process, the number in Reg19 and Reg20 would not change any more. If the user want to begin the above process again, the Reg15<0>trx_rstn show be toggled before the above process.
Gain_rf Gain(dB) Gain_rf Gain(dB) Gain_rf Gain(dB)
75H 71 52H 51 40H 31
74H 67 50H 47 8H 27
72H 63 4AH 43 2H 23
56H 59 48H 39 0H 19
54H 55 42H 35
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9.2 Transmitter
9.2.1 Transmitter description Figure 4 is the block diagram of BK5823’s transmitter. Ramp DAC controls the
range of output carrier. To change output power and modulation depth, user can change the value of Ramp register. The ratio of maximum and minimum value of Ramp register decides modulation depth. Tx power temperature compensation is integrated, the power will be controlled in the range 4dB from -40oC to 85oC.
The MCU should write the TX data to the FIFO, and pull CSN pin to high after one packet is filled. The BK5823 will begin transmission after detecting the rising edge of CSN and the delay time is passed ,which is set in reg9<8:7>TX_PLL_DELAY. and issue an interrupt and return to idle mode after FIFO is empty.
Figure 4 Transmitter Block Diagram
The transmit power can be set through REG9<3:1>rf_pwr control word, which can achieve 8 steps adjustment with up to 15 dB dynamic range. The transmit carrier frequency is set with setting below. 5.8 GHz: Ncal_tx<7:0>=ECh, N_tx<18:0>=1D801h, 5.79GHz: Ncal_tx<7:0>=ECh,N_tx<18:0>=1D731h, The BK5823 transmits the data in the FIFO with ASK modulation, whose modulation depth can be programmable with REG18.
kplowrampkphighrampkplowrampkphighrampA
_0_7_0_7
+−
=
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© 2012 Beken Corporation Proprietary and Confidential Page 10 of 31
The definition of ramp7_kphigh and ramp0_kplow is in the description of 9.4 ramping registers. By setting value of ramp7_kphigh and ramp0_kplow, the modulation depth of TX can be adjusted. test_mode in REG15 controls the transmit mode of transmitter. 2’b00 means normal data frame transmit mode. 2’b01 means random data transmit mode (need set pwd_tx in REG4 to 0). 2’b10 means all 0 data transmit mode (need set pwd_tx in REG4 to 0).2’b11 means transmit the data stream inputted from DO pin (need set pwd_tx in REG4 to 0, and set data_oen in REG15 to 1).
9.2.2 Transmitter CRC setting If the reg15<18> CRC_RX_OPT is set to “1”, the sending CRC will be set automatically according to the received CRC value, otherwise the sending CRC would be set according to the reg15<5> CRC_Seed.
If the reg15<4> CRC_en is set “0” , no CRC will be added to the sending packet.
9.2.3 Transmitter Power setting The transmitter power can be set through Reg9<3:1>rf_power.
9.2.4 Single Carrier setting BK5823 enter into single carry transmitter mode through setting: reg4<1>pwd_tx=0, reg9<0>pwr_up=1, reg15<3:2>=01, reg18<87:0>=FFFFFFFFFFFFFFFFFFFFFFh.
9.2.5 PN9 Modulation Signal setting BK5823 enter into PN9 modulation mode through setting: reg4<1>pwd_tx=0, reg9<0>pwr_up=1, reg15<3:2>=01.
9.3 Wake-up Circuit The wake-up circuit will output a high level at WKO pin after detecting setting cycles
of 14 kHz square wave. The number of cycles is set by reg6<25:22>wkpn, the wake-up circuit can be reset by reg6<31>rstwkdig.
9.3.1 Wakeup mode There exist two wakeup modes for BK5823, model 1 is automatic wakeup mode,
model 2 is MCU Control model. For model 1, the BK5823 will enter into RX mode automatically if the wakeup signal is detected; for model 2 the BK5823 will output wko signal in pin wko if the wakup signal is detected, then MCU would detect the WKO output, then MCU is waked up, then MCU will control the BK5823 to receive the packet. the mode is set by reg9<31>
In mode 1, BK5823 will enter into RX mode automatically if the wakeup signal is detected, the user should set reg9<10>softwakeup_end to “1”, BK5823 will exit from the
BK5823 Datasheet ETC OBU SOC
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RX mode, then the user should set the reg9<10>softwakeup_end to “0” again, BK5823 will enter the automatic wakeup mode again.
In mode 1, two wakeup signal can be selected as the MCU wakeup signal, one is the 14KHz wakeup, the other is 7E, which is depended on the reg6<1>wk_sel. If wk_sel is “0”, Dwko pin will output “1” after 14KHz is detected , if wk_sel is “1” , Dwko pin will output “1” after 7Eh is detected.
In mode 2, when MCU detects high level on WKO, MCU can set registers through SPI in order to power up BK5823. After powered up, BK5823 will receive the data package transmitted by RSU.
9.3.2 Wakeup Band Pass Filter In the baseband block of wake-up circuit, there is a BPF frequency discriminator. Only when the frequency of square wave is between Low limiter frequency and high limiter frequency , the square wave will be considered as wake-up wave. The low limiter and high limiter frequency can be set through the reg6<12:10>wlfsel and reg6<15:13>whfsel separately. The frequency of BPF needs calibration. The calibration process is below: 1. Set 1 to awcalen in REG6<21>; 2. Set 1 to wu_cal in REG15<28> when BK5823 is under the idle mode; 3. After the 5ms, the calibration is done. The frequency can be set manually If the Reg6<21>awcalen is set to “0” through the reg6<20:16>spirosc.
9.3.3 Wakeup Auto Calibration Mode The lower limiter and high limiter frequency of BPF will be changed with the temperature, if the wakeup signal frequency is out of the range of BPF, the BK5823 will begin the calibration again automatically. This mode would work after the reg6<0>acalen set to “1”.
9.3.4 No Response Mode The wakeup circuit would not response to the wakeup signal during the period of the setting time. In this mode, the current of BK5823 is about 7uA. The entrance into this mode is reg6<29>wkfibts, toggling this reg between “1” and “0”, BK5823 will enter this mode. The no response time can be set through reg6<28:26>wkfibtset. The maximum time is 21.5s for 3’h111, the step is 3s, the minimum time is 0.7s.
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9.4 State Machine
Figure 5 The BK5823 Manual wakeup Mode State Machine
Figure 6 The BK5823 Automatic Wakeup Mode State Machine
BK5823 Datasheet ETC OBU SOC
© 2012 Beken Corporation Proprietary and Confidential Page 13 of 31
RX
CR
C c
orre
ct/e
rror
inte
rrup
t
End
Flag
Det
ectio
n Er
ror
/Tim
e Ou
t int
erru
pt
Figure 7 RX State Machine
10 Control Interface
10.1 Basic Function The control interface consists of one interrupt pin and a 4-pins SPI interface and the maximum frequency on SCK is 8MHz.
IRQ: interrupt signal, low level valid CSN: SPI chip select signal SCK: SPI clock signal MOSI: Master Out Slave In, SPI data input signal MISO: Master In Slave Out, SPI data output signal
10.2 Operation and Timing The SPI interface always transmits 8 bit command word firstly and then data bytes. Abbr. Description Cn SPI command word Sn State Register Bit Out Dn Data Bit (Note: Analog register is MSByte first, Digital and state
control register is LSByte first. All bytes in every registers is MSBit first)
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Operation (c7-c0) Description Read 000AAAAA AAAAA is the register address (MSB first) Write 001AAAAA AAAAA is the register address (MSB first)
Figure 3 SPI Digital Register Read Timing
Figure 4 SPI Digital Register Write Timing
Figure 5 SPI Interface Timing
Symbol Parameters Min Max UnitsTdc Data to SCK Setup 2 ns Tdh SCK to Data Hold 2 ns
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Tcsd CSN to Data Valid 38 ns Tcd SCK to Data Valid 55 ns Tcl SCK Low Time 40 ns Tch SCK High Time 40 ns Fsck SCK Frequency 0 8 MHz Tr,Tf SCK Rise and Fall 100 ns Tcc CSN to SCK Setup 2 ns Tcch SCK to CSN Hold 2 ns Tcwh CSN Inactive time 50 ns Tcdz CSN to Output High Z 38 ns
10.3 Data FIFO There is a 256-bytes FIFO in BK5823, which is used to store data packages to be sent or data packages received. Accessing data FIFO is accessing multi-bytes register virtually.
10.4 TX Ramping Control The TX ramping curve is controlled by an 11 bytes ramping FIFO. Table 3 TX Ramping FIFO Definition
Addr. (12h) Symbol Definition Suggested Value 87:84 Reserved 83:78 Ramp13_fall1 Ramping Down 1 3F 77:72 Ramp12_fall2 Ramping Down 1 4 71:66 Ramp11_fall3 Ramping Down 1 4 65:60 Ramp10_fall4 Ramping Down 1 4 59:54 Ramp9_fall5 Ramping Down 1 10 53:48 Ramp8_fall6 Ramping Down 1 20 47:42 Ramp7_Kphigh Amplitude of “1” 3F 41:36 Ramp6_rise6 Ramping up 6 20 35:30 Ramp5_rise5 Ramping up 5 10 29:24 Ramp4_rise4 Ramping up 4 10 23:18 Ramp3_rise3 Ramping up 3 8 17:12 Ramp2_rise2 Ramping up 2 8 11:6 Ramp1_rise1 Ramping up 1 8 5:0 Ramp0_Kplow Amplitude of “0” 0
Register18 defines the envelope of TX as the figure below:
Kphigh
Kplow Rise1
Rise2 Rise3
Rise4 Rise5
Rise6 Fall6
Fall5 Fall4
Fall3 Fall2
Fall1 Kplow
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Modulation depth is defined by the expression below:
kplowrampkphighrampkplowrampkphighrampA
_0_7_0_7
+−
=
According to this expression, if set Kphigh as “Fh”, the value of Kplow can be calculated when we know the modulation depth.
11 Register Map Table 4 Register map table
Address(DEC)
R/W
Blocks Bits Symbol Description
00 – 08
00 W RF/Analog
31:24 Ncal_rx<7:0> RXLO,
5.825GHz:”59h”
5.835GHz:”59h”
5.845GHz:”5Ah”
23:5 N_rx<18:0> LO frequency control
5.825GHz=”2B183h”
5.835GHz=”2B2B2h”
5.845GHz=”3B3E1h”
4 Reserved “0h”
3:2 Reserved “0h”
1:0 Reserved “2h” 00 R Digital 31:8 Reserved
7:0 ChipID Chip ID 01 W RF/Anal
og 31:24 Ncal_tx<7:0> TX Carrier Setting
5.79GHz: “ECh”
5.8GHz: “ECh”
23:5 N_tx<18:0> TX Carrier Setting
5.79GHz: “1D731h”
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5.8GHz: “1D801h”
4 Reserved “0h”
3 Reserved “0h”
2 Reserved “0h”
1 Reserved “0h”
0 Spi_reset_enable “0h” select the spi to reset SDM and A/B control value load
01 R Digital 31:0 Reserved
02 W RF/Analog
31:30 Cp<1:0> Charge pump current control. “02h”
29:28 Ioffset<1:0> Charge pump current offset control “0h”
27 cpfine Bias current control of charge pump “1h”
26:25 Reserved “0h”
24:20 Bandm<4:0> Vco band manual setting
“1Fh”
19:15 NC “0h”
14:10 Reserved “0h”
9:4 Resrved “2h”
3 Calmanual Vco calibration mode set
“1” manual “0” automatic.
Suggest “0h”
2:0 Reserved “0h”
02 R Digital 31:8 Reserved
7 Reserved
6:0 Gain_agc<6:0> AGC setting
03 W RF/Analog
31 Reserved “0h”
30 Int_mode “0h”
29 Reserved “1h”
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28 Resrved “1h”
27:25 Reserved “0h”
24:22 Reserved “5h”
21:14 Reserved “0h”
13 Reserved “1h”
12:9 Loopresc<3:0> Pll loop bandwidth:”Fh”
8 Errdt_spien “1h”
7:5 Dnorvcm<2:0> “3h”
4 Dckref “0h”
3 Downcal_t_tx “0h”
2 Upcal_t_tx “0h”
1:0 Ivref<1:0> “0h”
03 R Digital 31:6 Reserved 5:0 Rssi_dB Rssi data , Unit:dB
04 W RF/Analog
31:30 Reserved “0h”
29:27 Resered “7h”
26:24 Reserved “0h”
23:21 Reserved “0h”
20 Diooutsel Control the pin 22 data output type.”1” output decoded data, “0” output fm0 data.
19 agcen RX agc enable. “1h” enable, “0h” disenable
Suggest “1h”
18:12 Man_ifg<6:0> if agcen is “0h”, the gain of rx is set by this register. “0h”
11:8 Reserved “Fh”
7 Reserved “0h”
6 Rbsel Bias resistor select,.
“1” internal bias resistor, the pin9 IREF should be
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floating,
“0” external bias resistor, the pin9 IREF should be connected with gnd with a 60Kohm resistor.
5 Txbiassel Tx power temperature compensation enable.
“1” enable, “0” disenable
4 pwdxtal xtal enable
“1h” normal mode
“0h” enable the xtal block
3 NC
2 pwdcb Central bias enable:
“1h” normal mode
“0h” enable the central bias
1 Pwd_tx TX Enable.
“1h”: Normal
“0h”: Used CW mode
0 Pwd_rx “1h”: Normal package receiving
“0h”: receive data stream output from pin23 DIO
04 R Digital 31:0 Reserved
05 W RF/Analog
31 Reserved “0h”
30:28 Xtal_amp<2:0> Xtal amplitude control
“0h”
27 Spi_rxpllcal “0h”
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26 Spi_txpllcal “0h”
25 Pll_autocal “1h”
24:23 Vregtx<1:0> Tx ldo output voltage control:
“00” 1.7V
“01” 1.8V
“10” 1.9V
“11” 2V
22:16 Reserved “72h”
15 Reserved ”1h”
14:12 txlobuf_gain<2:0>
Output power control
“0h”: Min.
“7h”: Max.
Default “5h”
11:8 NC
7:6 Reserved “0h”
5:4 Divictrl “3h”
3:0 Reserved “0h” 05 R Digital 31:8 NC
7:0 Buf_cont<7:0> Number of bytes in RX FIFO
06 W RF/Analog
31 rstwk Reset the wakeup circuit
“1h” reset
“0h” normal
30 NC
29 wkfibts wakeup no response mode enable. 0->1->0
28:26 Wkfibtset<2:0> wakeup no response time setting: 3’h111:21.5s, 3s/step
25:22 Wkpn<3:0> Wakeup pulse number setting
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© 2012 Beken Corporation Proprietary and Confidential Page 21 of 31
21 awcalen Wakeup ring oscillator frequency control selection.
“1” normal mode
“0” manual mode
20:16 Spirosc<4:0> If awcalen is set to “0”, this register set the control value.
15:13 Wkhfsel<2:0> Wakeup BPF high limiter frequency setting.
3’h111:22KHz Step :1KHz
Range:15->22KHz
12:10 Wklfsel<2:0> Wakeup BPF low limiter frequency setting.
3’h111:13KHz Step :0.5KHz
Range:10->13KHz
9:6 Wkibc<3::0> Wakeup bias current setting.
“Fh” is suggested.
5:4 Wkhy<1:0> Wake up sensitivity control:
“1h” is suggested.
1.5dB/Step 1h->3h
3 Reserved “0h”
2 NC
1 wksel WKO signal selection:
“1h” select the packet header as the WKO signal.
“0h” select the 14KHz signal as the WKO signal.
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© 2012 Beken Corporation Proprietary and Confidential Page 22 of 31
0 acalen Auto calibration enable
“1h” enable
06 R Digital 31:8 NC
7 Rbuf_rdy “0h”: RX FIFO is empty
6 Nrbuf_rdy Inverse of Rbuf_rdy
5 Tbuf_rdy “0h”: TX FIFO is empty
4 Ntbuf_rdy Inverse of Tbuf_rdy
3 Osc_table “1h” oscillator stable
2 Rx_error_irt RX error
1 Rx_end_irt RX packet end flag is received
0 Tx_end_irt TX packet is finished
07 W RF/Analog
31:29 roscid<2:0> “3h”
28 reserved “1h”
27:26 Wkgset<1:0> “0h” low gain
“3h” high gain
Which can control the wakeup sensitivity
“3h” is suggested
25 Iwkbias Wakeup bias selection,
“1” low current.
“0” high current.
“1” is suggested.
24:23 Vregrx<1:0> Rx LDO output voltage setting.
“00” 1.8V
“01” 1.66V
“10” 2V
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© 2012 Beken Corporation Proprietary and Confidential Page 23 of 31
“11” 1.8V
22:0 NC
07 R Digital 31:8 Reserved
7:0 Wk_calvalue<4:0>
Wakeup calibration value If the awcalen is set to “1h”, this value will be work.
08 R Digital 31:0 Reserved
09 – 18 Digital Digital Control R/W
09 W/R
31 Wakeup_mode Wake mode selection:
“1h” auto mode
“0h” manual mode
30 Ber_en RX bit error rate test enable
“1h” enable
“0h” disenable
29 Ber_hold RX bit error rate test hold
“1h” hold
28 Time_recov_opt Clock Recovery Enable
“0h”: disenable
“1h”: enable
27 Reserved “1h”
26:19 Reserved “0h”
18:17 AGC_Rate AGC speed control
“2’b00”: reserved
“2’b01”: slow AGC
“2’b10”: fast AGC
“2’b11”: reserved
Suggest to use fast AGC
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16 Reserved “0h”
15 Reserved “0h”
14 Lpf_en Digital RX chain low pass filter enable
“1h” enable
“0h” disenable
13 Hpf_en Digital RX chan high pass filter enable
“1h” enable
“0h” disenable
12 Dc_del “1h”
11 Reserved “0h”
10 Soft_wakeupend Return back the sleep mode from idle mode under auto wakeup mode. 1->0
9 Reserved “0h”
8:7 Tx_delay TX delay
“00” 40us
“01” 60us
“10” 80us
“11” 100us
6:5 Rx_delay RX delay
“00” 40us
“01” 60us
“10” 80us
“11” 100us
4 NC
3:1 rf_pwr<2:0> PA output power
“0h”: Min.
“7h”: Max.
0 Pwr_up Mode
“0h”: Sleep
BK5823 Datasheet ETC OBU SOC
© 2012 Beken Corporation Proprietary and Confidential Page 25 of 31
“1h”: Idle
10 W/R
31:25 Reserved “0h”
24:11 Hd_threshold<13:0>
Noise threshold:
If AGC_Rate is “2’b01”, set 200h;
If AGC_Rate is “2’b10”, set 000h.
10:0 Reserved “1FFh”
11 W/R
31:8 Reserved “0h”
7:2 Gain_rf_delay AGC settling time control
“0h”: Min.
“3Fh”: Max
“1h” is suggested
1:0 Reserved “0h”
12 W/R
31:20 Gt_points1<11:0>
“400h” slow agc point setting.
19:10 High_limiter1<9:0>
“60h” slow agc threshold setting value
9:0 Low_limiter1<9:0>
“10h” slow agc threshold setting value
13 W/R
31:20 Gt_points2<11:0>
“800h” fast agc point setting.
19:10 high_limit2<9:0>
“80h” fast agc threshold setting value
9:0 low_limit2<9:0> “20h” fast agc threshold setting value
14 W/R
31:0 Match_pattern As the packet receiver
Set as: “55554CCDh”
As the PN9 receiver:
BK5823 Datasheet ETC OBU SOC
© 2012 Beken Corporation Proprietary and Confidential Page 26 of 31
Set as: 4CAAACD4h
15 W/R
31:29 NC
28 wu_cal Wake-up calibration
Software set, hardware clear
27 Irq_clr[3] Clear xtal start interrupt
26 irq_clr[2] Clear RX error interrupt
25 irq_clr[1] Clear RX interrupt
24 irq_clr[0] Clear TX interrupt
23 Iqr_ena[3] Enable xtal start interrupt
22 irq_ena[2] Enable RX error interrupt
21 irq_ena[1] Enable RX interrupt
20 irq_ena[0] Enable TX interrupt
19 Reserved “0h”
18 crc_rx_opt “1”: use 0 and 1 to do CRC simultaneously
“0”: only use the value of crc_seed to do CRC
If “1” is set, the TX CRC will be set according to the received packet’s CRC.
17 fm0_rx_err_opt “1”: if received fm0 code is wrong, discard the data and receive again
16 fm0_tx_opt When transmit fm0, invert 0 and 1
15 Data_oen Pin22 DIO output enable
“0h”: DIO output
BK5823 Datasheet ETC OBU SOC
© 2012 Beken Corporation Proprietary and Confidential Page 27 of 31
data
“1h”: DIO input data
14 Reserved ”0h”
13 Rxdatatrate Rx date rate selection
“1h” 512K
“0h” 256K
12:11 Txdata_rate TX Data Rate
“00”: 256K
“01”: 125K
“10”: 512K
“11”: NA
10 sqw14_en TX 14KHz square wave
“0h”: Disable
“1h”: Enable
9:6 Pack_pre Number of symbol 1 between square wave and preamble
5 crc_seed CRC seed
4 crc_enable CRC enable
“0h”: Disable
“1h”: enable
3:2 test_mode<1:0> TX test mode
“00”: Normal
“01”: Random bit
“10”: Transmit all 0 data
“11”: transmit data inputted from DIO
1 rx_en RX Enable
“1h”: Enable
“0h”: Disable
0 Trx_rstn Reset TX and RX
BK5823 Datasheet ETC OBU SOC
© 2012 Beken Corporation Proprietary and Confidential Page 28 of 31
“0h”: Reset
“1h”: Work
16 W/R
31:8 NC
7:0 FIFO TX and RX FIFO
17 W/R
111:105 Reserved “56h”
104:98 Reserved “56h”
97:91 Reserved “56h”
90:84 Reserved “56h”
83:77 Reserved “54h”
76:70 Reserved “52h”
69:63 Reserved “50h”
62:56 Reserved “4Ah”
55:49 Reserved “48h”
48:42 Reserved “42h”
41:35 Reserved “40h”
34:28 Reserved “8h”
27:21 Reserved “2h”
20:14 Reserved “0h”
13:7 Reserved “0h”
6:0 Reserved “0h”
18 W/R
88:0 Ramp FIFO TX ramping FIFO
19 R 31:0 BER_RBNUM The number of received bits under BER test mode
20 R 31:0 BER_ERR The number of error bits under BER test mode
BK5823 Datasheet ETC OBU SOC
© 2012 Beken Corporation Proprietary and Confidential Page 29 of 31
12
13 Test Result
BK5823 Datasheet ETC OBU SOC
© 2012 Beken Corporation Proprietary and Confidential Page 30 of 31
14 Application Schematic
15 PCB Layout Reference Design Top layer
Bottom Layer
BK5823 Datasheet ETC OBU SOC
© 2012 Beken Corporation Proprietary and Confidential Page 31 of 31
16 Package
17 Order Information